Bias circuit and amplifier circuit

Abstract

An objective of the present invention is to reduce the distortion of a bias applied to an amplifier while suppressing an increase in the power consumption of the amplifier.　A bias circuit according to the present invention includes: a first differential circuit that uses, as a differential input, a bias signal in which first offset voltages of opposite polarities are superimposed; a second differential circuit that uses, as a differential input, a bias signal in which second offset voltages of opposite polarities are superimposed; and a comparison circuit that outputs a bias signal on the basis of the result of a comparison between the output of the first differential circuit and the output of the second differential circuit. The relationship between the voltage value of the first offset voltage and the voltage value of the second offset voltage is set as M:N (M and N are different positive real numbers), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set as N:M.

Description

Bias and Amplification Circuits

[0001] The present technology relates to a bias circuit and an amplifier circuit. More specifically, the present technology relates to a bias circuit capable of generating a bias for an amplifier and an amplifier circuit to which the bias is applied.

[0002] In amplifiers, a bias may be applied to reduce signal distortion. For example, a feedback circuit has been proposed that senses a DC current signal generated by a bias transistor and reduces this DC current signal to zero (see, for example, Patent Document 1).

[0003] JP 2010-50982 A

[0004] However, in the above-mentioned conventional technology, the transistor is biased in the proportional operation region, which may result in increased power consumption.

[0005] The present technology was developed in light of these circumstances, and aims to reduce distortion in the bias applied to the amplifier while suppressing an increase in the power consumption of the amplifier.

[0006] The present technology has been made to solve the above-mentioned problems, and a first aspect thereof is a bias circuit including: a first differential circuit having as its differential input bias signals superimposed with first offset voltages of opposite polarities, a second differential circuit having as its differential input the bias signals superimposed with second offset voltages of opposite polarities, and a comparison circuit that outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage values ​​of the first offset voltage and the second offset voltage is set to M:N (M and N are positive real numbers that are different from each other), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M. This brings about an effect of setting a bias in a region where even-order distortion and odd-order distortion of a difference between the output of the first differential circuit and the output of the second differential circuit disappear.

[0007] In the first aspect, the bias signal may be set in a perfect square-law region, thereby providing an effect of biasing in a region where IIP3 (Third Order Input Intercept Point) is favorable.

[0008] In a first aspect, the first differential circuit includes a first voltage source that generates the first offset voltage of positive polarity, a second voltage source that generates the first offset voltage of negative polarity, a first transistor to which the bias signal is input via the first voltage source, a second transistor to which the bias signal is input via the second voltage source and that can form a differential pair with the first transistor, a first difference current detection circuit that detects a difference current between an output of the first transistor and an output of the second transistor, and a first amplifier that multiplies the output of the first difference current detection circuit by N; a third voltage source generating the second offset voltage of negative polarity, a third transistor receiving the bias signal via the third voltage source, a fourth transistor receiving the bias signal via the fourth voltage source and capable of forming a differential pair with the third transistor, a second difference current detection circuit detecting a difference current between an output of the third transistor and an output of the fourth transistor, and a second amplifier multiplying the output of the second difference current detection circuit by M, wherein the driving power of each of the first to fourth transistors is equal to one another and the driving power of each of the first and second difference current detection circuits is equal to one another. This provides the effect that the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M based on the amplification factor of the amplifier downstream of the difference current detection circuit.

[0009] In addition, in a first aspect, the first difference current detection circuit may include a fifth transistor connected in series with the first transistor, a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor, and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, wherein a first input of the first operational amplifier is connected to a drain of the first transistor and a second input of the first operational amplifier is connected to a first bias source; the second difference current detection circuit may include a seventh transistor connected in series with the third transistor, an eighth transistor connected in series with the fourth transistor and capable of forming a differential pair with the seventh transistor, and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, wherein a first input of the second operational amplifier is connected to the drain of the third transistor and a second input of the second operational amplifier is connected to a second bias source; and the fifth to eighth transistors may have equal driving strengths. This makes it possible to detect the difference between the differential outputs of the first differential circuit and the second differential circuit, while setting the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit to N:M.

[0010] In a first aspect, the first differential circuit includes a first voltage source that generates the first offset voltage of positive polarity, a second voltage source that generates the first offset voltage of negative polarity, a first transistor to which the bias signal is input via the first voltage source, a second transistor to which the bias signal is input via the second voltage source and capable of forming a differential pair with the first transistor, a first difference current detection circuit that detects a difference current between an output of the first transistor and an output of the second transistor, and a first amplifier that amplifies an output of the first difference current detection circuit, and the second differential circuit includes a third voltage source that generates the second offset voltage of positive polarity, a fourth voltage source that generates the second offset voltage of negative polarity, and a third transistor to which the bias signal is input via the third voltage source. the bias signal is input via the fourth voltage source, the fourth transistor being capable of forming a differential pair with the third transistor, a second difference current detection circuit detecting a difference current between an output of the third transistor and an output of the fourth transistor, and a second amplifier amplifying an output of the second difference current detection circuit, wherein the driving strengths of the first and second transistors are equal to each other, the driving strengths of the third and fourth transistors are equal to each other, the driving strengths of the third and fourth transistors are set to N times the driving strengths of the first and second transistors, the driving strength of the first difference current detection circuit is set to N times the driving strength of the second difference current detection circuit, and the gains of the first and second amplifiers are equal to each other. This provides the effect that the relationship between the gain of the first differential circuit and the gain of the second differential circuit is set to N:M based on the driving strengths of the differential pair and the difference current detection circuit.

[0011] In a first aspect, the first difference current detection circuit includes a fifth transistor connected in series with the first transistor, a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor, and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, a first input of the first operational amplifier being connected to a drain of the first transistor and a second input of the first operational amplifier being connected to a first bias source, and the second difference current detection circuit includes a seventh transistor connected in series with the third transistor and a sixth transistor connected in series with the fourth transistor. and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, wherein a first input of the second operational amplifier is connected to the drain of the third transistor, a second input of the second operational amplifier is connected to a second bias source, the fifth and sixth transistors have equal driving strengths, the seventh and eighth transistors have equal driving strengths, and the fifth and sixth transistors have equal driving strengths, and the fifth and sixth transistors have equal driving strengths, and the fifth and sixth transistors have driving strengths set to N times the driving strengths of the seventh and eighth transistors. This brings about an effect that the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M, while making it possible to detect the difference between the differential outputs of the first differential circuit and the second differential circuit.

[0012] According to a second aspect, there is provided a bias circuit that generates a bias signal, and an amplifier to which the bias signal is applied, the bias circuit including a first differential circuit that receives as its differential input the bias signals on which first offset voltages of opposite polarities are superimposed, a second differential circuit that receives as its differential input the bias signals on which second offset voltages of opposite polarities are superimposed, and a comparison circuit that outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage values ​​of the first offset voltage and the second offset voltage may be set to M:N (M and N are positive real numbers that are different from each other), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit may be set to N:M. This provides the effect of robustly biasing the amplifier to a sweet spot that obeys the perfect square law.

[0013] In the second aspect, the amplifier may further include a resonant circuit connected as a load to the amplifier, thereby improving the resonant characteristics of the resonant circuit.

[0014] FIG. 1 is a diagram showing a configuration example of a bias circuit according to a first embodiment; FIG. 2 is a diagram showing the relationship between the gate voltage and drain current of a field effect transistor according to the first embodiment; FIG. 3 is a diagram showing the relationship between the gate voltage and transconductance of a field effect transistor according to the first embodiment; FIG. 4 is a diagram showing the relationship between the gate voltage and IIP3 of a field effect transistor according to the first embodiment; FIG. 5 is a diagram showing the relationship between the temperature and IIP3 of a field effect transistor according to the first embodiment; FIG. 6 is a diagram showing the relationship between the temperature and gate voltage of a field effect transistor according to the first embodiment; FIG. 7 is a diagram showing a configuration example of a bias circuit according to a second embodiment; FIG. 8 is a diagram showing a configuration example of a bias circuit according to a third embodiment; FIG. 9 is a diagram showing a configuration example of an amplifier circuit according to a fourth embodiment; and FIG. 10 is a diagram showing a configuration example of a bias circuit according to a fifth embodiment.

[0015] Hereinafter, modes for implementing the present technology (hereinafter referred to as embodiments) will be described. The description will be made in the following order: 1. First embodiment (an example in which the ratio of offset voltages of each differential circuit is set to 1:N, and the ratio of amplification factors is set to N:1) 2. Second embodiment (an example in which the ratio of amplification factors of amplifiers in the subsequent stages of a differential current detection circuit is set to N:1) 3. Third embodiment (an example in which the ratio of driving powers of a differential pair and a differential current detection circuit is set to N:1) 4. Fourth embodiment (an example in which a resonant circuit is connected as a load of an amplifier) ​​5. Fifth embodiment (an example in which the ratio of voltages of each offset of a differential circuit is set to N:M, and the ratio of amplification factors is set to M:N)

[0016] 1. First Embodiment FIG. 1 is a diagram showing an example of the configuration of a bias circuit according to a first embodiment.

[0017] In the figure, a bias circuit 10 generates a bias signal VBS for an amplifier transistor 133. The bias circuit 10 can set the bias signal VBS in a perfect square-law region of the amplifier transistor 133. At this time, the bias circuit 10 can set the bias in a region where even-order distortion and odd-order distortion of the difference between the outputs of a pseudo differential pair to which a differential signal is input disappear.

[0018] The bias circuit 10 includes differential circuits 100 and 110 and an operational amplifier 121. The differential circuit 100 receives a bias signal VBS, on which offset voltages V and −V, each of which has an opposite polarity, as a differential input, and outputs the difference between the differential outputs multiplied by N. The differential circuit 110 receives a bias signal VBS, on which offset voltages N·V and −N·V, each of which has an opposite polarity, as a differential input, and outputs the difference between the differential outputs multiplied by 1. The operational amplifier 121 outputs the bias signal VBS based on the comparison result between the outputs of the differential circuits 100 and 110. The operational amplifier 121 is an example of a comparison circuit as defined in the claims.

[0019] The differential circuit 100 includes a differential current detection circuit 101, an amplifier 102, field effect transistors 103 and 104, and voltage sources 105 and 106.

[0020] Voltage source 105 generates an offset voltage −V. Voltage source 105 is connected between the output of operational amplifier 121 and the gate of field effect transistor 103. Voltage source 106 generates an offset voltage V. Voltage source 106 is connected between the output of operational amplifier 121 and the gate of field effect transistor 104.

[0021] Field effect transistors 103 and 104 can form a differential pair. A bias signal VBS is input to the gate of field effect transistor 103 via voltage source 105. At this time, the gate voltage of field effect transistor 103 can be given as VBS-V. A bias signal VBS is input to the gate of field effect transistor 104 via voltage source 106. At this time, the gate voltage of field effect transistor 104 can be given as VBS+V.

[0022] The differential current detection circuit 101 detects the differential current between the output of the field effect transistor 103 and the output of the field effect transistor 104, and inputs the detection result to the amplifier 102. The amplifier 102 amplifies the output of the differential current detection circuit 101 by N times and inputs the amplified output to the operational amplifier 121.

[0023] The differential circuit 110 includes a differential current detection circuit 111, an amplifier 112, field effect transistors 113 and 114, and voltage sources 115 and .

[0024] Voltage source 115 generates an offset voltage −N·V. Voltage source 115 is connected between the output of operational amplifier 121 and the gate of field effect transistor 113. Voltage source 116 generates an offset voltage N·V. Voltage source 116 is connected between the output of operational amplifier 121 and the gate of field effect transistor 114.

[0025] Field effect transistors 113 and 114 can form a differential pair. A bias signal VBS is input to the gate of field effect transistor 113 via voltage source 115. At this time, the gate voltage of field effect transistor 113 can be given as VBS-N·V. A bias signal VBS is input to the gate of field effect transistor 114 via voltage source 116. At this time, the gate voltage of field effect transistor 114 can be given as VBS+N·V.

[0026] The differential current detection circuit 111 detects the differential current between the output of the field effect transistor 113 and the output of the field effect transistor 114, and inputs the detection result to the amplifier 112. The amplifier 112 multiplies the output of the differential current detection circuit 111 by 1 and inputs the result to the operational amplifier 121.

[0027] N-channel field effect transistors may be used as the field effect transistors 103, 104, 113, and 114. The voltage sources 105, 106, 115, and 116 may be configured as resistor voltage divider circuits or batteries.

[0028] The output of the operational amplifier 121 is applied to the gate of the amplifier transistor 133 via a resistor 131. An input signal IN is also input to the gate of the amplifier transistor 133 via a capacitor 132. The amplifier transistor 133 can be used for high-frequency amplification in, for example, a communication circuit. The amplifier transistor 133 may be an N-channel field-effect transistor.

[0029] Here, the operational amplifier 121 compares the outputs of the amplifiers 102 and 112 and sets the bias signal VBS so that the outputs of the amplifiers 102 and 112 are equal to each other. When a differential input is applied to the differential pair, even-order distortion in the differential current output from the differential pair disappears. Furthermore, when the bias signal VBS is set to a perfect square-law region, odd-order distortion also disappears. If neither even-order nor odd-order distortion is present, the outputs of the differential current detection circuits 101 and 111 are proportional to each other. Here, the offset of the differential inputs of the differential circuits 100 and 110 is 1:N, while the amplification factor of the amplifiers 102 and 112 is N:1. Therefore, by setting the bias signal VBS so that the outputs of the amplifiers 102 and 112 are equal to each other, the outputs of the differential current detection circuits 101 and 111 can be biased to be proportional to each other.

[0030] FIG. 2 is a diagram showing the relationship between the gate voltage and the drain current of the field effect transistor according to the first embodiment.

[0031] In the figure, when the gate voltage VGS is below the threshold voltage, the field-effect transistor operates in the subthreshold region, and almost no drain current IDS flows. When the gate voltage VGS exceeds the threshold voltage, the transistor enters the saturation region, and the drain current IDS increases as the gate voltage VGS increases.

[0032] FIG. 3 is a diagram showing the relationship between the gate voltage and the transconductance of the field effect transistor according to the first embodiment.

[0033] In the figure, when the gate voltage VGS is equal to or less than the threshold voltage, the field-effect transistor operates in the subthreshold region, and the mutual conductance gm is almost 0. When the gate voltage VGS exceeds the threshold voltage, the transistor enters the saturation region, and the mutual conductance gm increases, saturates, and then decreases.

[0034] FIG. 4 is a diagram showing the relationship between the gate voltage and IIP3 of the field effect transistor according to the first embodiment.

[0035] In the figure, a field-effect transistor has a perfect square-law region RA between the subthreshold region and the saturation region. The perfect square-law region RA exists almost exactly. The perfect square-law region RA has extremely good third-order distortion. The bias circuit 10 can bias to the sweet spot of the perfect square-law region RA without depending on modeling accuracy and variation.

[0036] FIG. 5 is a diagram showing the results of a simulation of the relationship between the temperature and IIP3 of the field-effect transistor according to the first embodiment.

[0037] In the figure, the optimum value of IIP3 exists at a certain temperature with a constant current bias P11, while the bias P12 provided by the bias circuit 10 allows IIP3 to approach the optimum value P13 over a wide temperature range.

[0038] FIG. 6 is a diagram showing the relationship between the temperature and the gate voltage of the field effect transistor according to the first embodiment.

[0039] In the figure, at constant current bias P11, the temperature of the field effect transistor and the gate voltage VGS have a proportional relationship E11. At bias P12 by bias circuit 10, the relationship E12 between the temperature of the field effect transistor and the gate voltage VGS has a curvature. At room temperature or higher, the gate voltage VGS decreases below the proportional relationship E11.

[0040] As described above, in the first embodiment, the ratio of the offset voltages of the differential circuits 100 and 110 is set to 1:N, and the ratio of the amplification factors is set to N:1. This allows the bias circuit 10 to robustly bias the amplifier transistor 133 to the sweet spot that follows the perfect square law. This makes it possible to reduce distortion in the bias applied to the amplifier transistor 133 while suppressing an increase in the power consumption of the amplifier transistor 133.

[0041] 2. Second Embodiment In the first embodiment described above, the ratio of the offset voltages of the differential circuits 100 and 110 is set to 1:N, and the amplification factor is set to N:1. In this second embodiment, the ratio of the amplification factors of the amplifiers 102 and 112 subsequent to the differential current detection circuits 101 and 111 is set to N:1.

[0042] FIG. 7 is a diagram illustrating an example of the configuration of a bias circuit according to the second embodiment.

[0043] In the bias circuit 20 shown in the figure, the differential current detection circuit 101 includes field effect transistors 201 and 202, an operational amplifier 203, and a bias source 204. The differential current detection circuit 111 includes field effect transistors 211 and 212, an operational amplifier 213, and a bias source 214. The amplifier 102 includes an operational amplifier 205 and a resistor 206. The amplifier 112 includes an operational amplifier 215 and a resistor 216. Other configurations of the bias circuit 20 of the second embodiment are similar to those of the bias circuit 10 of the first embodiment described above.

[0044] The field effect transistors 201 and 202 can form a differential pair. The field effect transistor 201 is connected in series to the field effect transistor 103. The field effect transistor 202 is connected in series to the field effect transistor 104. The output of the operational amplifier 203 is connected to the gates of the field effect transistors 201 and 202.

[0045] The inverting input of the operational amplifier 203 is connected to the drain of the field effect transistor 201. The non-inverting input of the operational amplifier 203 is connected to a bias source 204. The bias source 204 supplies a bias voltage VC to the operational amplifier 203. The bias voltage VC can be set so that the operational amplifier 203 is operable.

[0046] The output of the operational amplifier 205 is fed back to the inverting input of the operational amplifier 205 via a resistor 206, and is also applied to the inverting input of the operational amplifier 121. The inverting input of the operational amplifier 205 is connected to the drain of the field-effect transistor 202. The non-inverting input of the operational amplifier 205 is connected to the non-inverting input of the operational amplifier 203.

[0047] The field effect transistors 211 and 212 can form a differential pair. The field effect transistor 211 is connected in series to the field effect transistor 113. The field effect transistor 212 is connected in series to the field effect transistor 114. The output of the operational amplifier 213 is connected to the gates of the field effect transistors 211 and 212.

[0048] The inverting input of the operational amplifier 213 is connected to the drain of the field effect transistor 211. The non-inverting input of the operational amplifier 213 is connected to a bias source 214. The bias source 214 supplies the operational amplifier 213 with a bias voltage VC.

[0049] The output of the operational amplifier 215 is fed back to the inverting input of the operational amplifier 215 via a resistor 216, and is also applied to the non-inverting input of the operational amplifier 121. The inverting input of the operational amplifier 215 is connected to the drain of the field-effect transistor 212. The non-inverting input of the operational amplifier 215 is connected to the non-inverting input of the operational amplifier 213.

[0050] Here, the driving forces of the field-effect transistors 103, 104, 113, and 114 can be made equal to one another. For example, the size of each of the field-effect transistors 103, 104, 113, and 114 can be set to Wn / Ln, where Wn is the gate width of each of the field-effect transistors 103, 104, 113, and 114, and Ln is the gate length of each of the field-effect transistors 103, 104, 113, and 114.

[0051] Furthermore, the driving forces of the differential current detection circuits 101 and 111 can be made equal to each other. At this time, the driving forces of the field effect transistors 201, 202, 211, and 212 can be made equal to each other. For example, the size of each field effect transistor 201, 202, 211, and 212 can be set to Wp / Ln, where Wp is the gate width of each field effect transistor 201, 202, 211, and 212. Furthermore, the ratio of the resistance values ​​of the resistors 206 and 216 can be set to N:1.

[0052] The field effect transistors 201, 202, 211, and 212 may be P-channel field effect transistors. The bias sources 204 and 214 may be configured with a resistor voltage divider circuit or a battery.

[0053] In this way, in the second embodiment described above, the ratio of the amplification factors of the amplifiers 102, 112 subsequent to the differential current detection circuits 101, 111 is set to N:1. This makes it possible to detect the difference between the differential outputs of the differential circuits 100 and 110, while also setting the relationship between the amplification factors of the differential circuits 100 and 110 to N:1.

[0054] 3. Third Embodiment In the second embodiment described above, the ratio of the amplification factors of the amplifiers 102, 112 subsequent to each difference current detection circuit 101, 111 is set to N:1. In this third embodiment, the ratio of the driving power of the differential pairs connected in series to each difference current detection circuit 101, 111 and each difference current detection circuit 101, 111 is set to N:1.

[0055] FIG. 8 is a diagram illustrating an example of the configuration of a bias circuit according to the third embodiment.

[0056] In the figure, the bias circuit 30 includes field effect transistors 303 and 304, a difference current detection circuit 301, and an amplifier 302 instead of the field effect transistors 103 and 104, the difference current detection circuit 101, and the amplifier 102 of the second embodiment described above. The other configurations of the bias circuit 30 of the third embodiment are the same as the configurations of the bias circuit 20 of the second embodiment described above.

[0057] Field effect transistors 303 and 304 can form a differential pair. A bias signal VBS is input to the gate of field effect transistor 303 via voltage source 105. At this time, the gate voltage of field effect transistor 303 can be given as VBS-V. A bias signal VBS is input to the gate of field effect transistor 304 via voltage source 106. At this time, the gate voltage of field effect transistor 304 can be given as VBS+V.

[0058] The field effect transistors 401 and 402 can form a differential pair. The field effect transistor 401 is connected in series to the field effect transistor 303. The field effect transistor 402 is connected in series to the field effect transistor 304. The output of the operational amplifier 203 is connected to the gate of each of the field effect transistors 401 and 402. The drain of the field effect transistor 401 is connected to the inverting input of the operational amplifier 203. The output of the operational amplifier 205 is fed back to the inverting input of the operational amplifier 205 via a resistor 406, and is also applied to the inverting input of the operational amplifier 121.

[0059] Here, the driving power of each field effect transistor 303, 304 can be made equal to each other. The ratio of the driving power of each field effect transistor 303, 304 to the driving power of each field effect transistor 113, 114 can be set to N:1. For example, the size of each field effect transistor 303, 304 can be set to N·Wn / Ln.

[0060] Furthermore, the ratio between the driving force of the differential current detection circuit 101 and the driving force of the differential current detection circuit 111 can be set to N:1. In this case, the driving forces of the field effect transistors 401 and 402 can be made equal to each other. The ratio between the driving force of the field effect transistors 401 and 402 and the driving force of the field effect transistors 211 and 212 can be set to N:1. For example, the size of the field effect transistors 401 and 402 can be set to N·Wp / Ln. Furthermore, the ratio between the resistance values ​​of the resistors 406 and 216 can be set to 1:1.

[0061] The field effect transistors 303 and 304 may be N-channel field effect transistors, and the field effect transistors 401 and 402 may be P-channel field effect transistors.

[0062] In this way, in the third embodiment described above, the differential pairs connected in series to the respective difference current detection circuits 101, 111 and the driving forces of the respective difference current detection circuits 101, 111 are set to N:1. This makes it possible to detect the difference between the differential outputs of the differential circuits 100 and 110, while also setting the relationship between the amplification factors of the differential circuits 100 and 110 to N:1.

[0063] 4. Fourth Embodiment In the above-described first embodiment, the bias signal generated by the bias circuit 10 is input to the amplifier transistor 133. In this fourth embodiment, a resonant circuit 40 is connected as a load of the amplifier transistor 133 to which the bias signal VBS generated by the bias circuit 10 is input.

[0064] FIG. 9 is a diagram illustrating an example of the configuration of an amplifier circuit according to the fourth embodiment.

[0065] In the drawing, the amplifier circuit is connected to a resonant circuit 40 as a load of an amplifier transistor 133. A field effect transistor 401 is connected between the amplifier transistor 133 and the resonant circuit 40.

[0066] A bias source 402 is connected to the gate of the field effect transistor 401. The bias source 402 supplies a bias voltage to the field effect transistor 401.

[0067] The resonant circuit 40 includes an inductor 411 and a capacitor 412. The inductor 411 and the capacitor 412 are connected in parallel. In this case, the resonant circuit 40 is driven via the amplifier transistor 133, and can resonate based on the input signal IN input to the amplifier transistor 133.

[0068] As described above, in the fourth embodiment, the resonant circuit 40 is connected as a load of the amplifying transistor 133 to which the bias signal VBS generated by the bias circuit 10 is input. This improves the out-of-band rejection effect of the resonant circuit 40, thereby improving the resonance characteristics.

[0069] 5. Fifth Embodiment In the first embodiment described above, the ratio of the offset voltages of the differential circuits 100 and 110 is set to 1:N, and the ratio of the amplification factors is set to N:1. In this fifth embodiment, the ratio of the offset voltages of the differential circuits is set to M:N (M and N are different positive real numbers), and the ratio of the amplification factors is set to N:M.

[0070] FIG. 10 is a diagram illustrating an example of the configuration of a bias circuit according to the fifth embodiment.

[0071] In the figure, a bias circuit 50 includes differential circuits 500 and 510 instead of the differential circuits 100 and 110 of the first embodiment described above. The other configurations of the bias circuit 50 of the fifth embodiment are similar to the configurations of the bias circuit 10 of the first embodiment described above.

[0072] Differential circuit 500 receives as its differential input a bias signal VBS on which offset voltages M·V and −M·V, each of which has opposite polarity, are superimposed, and outputs the difference between the differential outputs multiplied by N. Differential circuit 510 receives as its differential input a bias signal VBS on which offset voltages N·V and −N·V, each of which has opposite polarity, are superimposed, and outputs the difference between the differential outputs multiplied by M.

[0073] The differential circuit 500 includes voltage sources 505 and 506 instead of the voltage sources 105 and 106 of the first embodiment described above. The remaining configuration of the differential circuit 500 of the fifth embodiment is similar to the configuration of the differential circuit 100 of the first embodiment described above.

[0074] The differential circuit 510 includes an amplifier 512 instead of the amplifier 112 of the first embodiment described above. Other configurations of the differential circuit 510 of the fifth embodiment are similar to the configurations of the differential circuit 110 of the first embodiment described above.

[0075] The voltage source 505 generates an offset voltage −M·V. The voltage source 505 is connected between the output of the operational amplifier 121 and the gate of the field effect transistor 103. At this time, a bias signal VBS is input to the gate of the field effect transistor 103 via the voltage source 505.

[0076] The voltage source 506 generates an offset voltage M·V. The voltage source 506 is connected between the output of the operational amplifier 121 and the gate of the field effect transistor 104. At this time, a bias signal VBS is input to the gate of the field effect transistor 104 via the voltage source 506.

[0077] The amplifier 512 multiplies the output of the differential current detection circuit 111 by M and inputs the multiplied output to the operational amplifier 121 .

[0078] Here, the operational amplifier 121 compares the outputs of the amplifiers 102 and 512 and sets the bias signal VBS so that the outputs of the amplifiers 102 and 512 are equal to each other. When a differential input is applied to the differential pair, even-order distortion in the differential current output from the differential pair disappears. Furthermore, when the bias signal VBS is set to a perfect square-law region, odd-order distortion also disappears. If neither even-order nor odd-order distortion is present, the outputs of the differential current detection circuits 101 and 111 are proportional to each other. Here, the offset of the differential inputs of the differential circuits 500 and 510 is M:N, while the amplification factor of the amplifiers 102 and 512 is N:M. Therefore, by setting the bias signal VBS so that the outputs of the amplifiers 102 and 512 are equal to each other, the outputs of the differential current detection circuits 101 and 111 can be biased to be proportional to each other.

[0079] As described above, in the fifth embodiment, the ratio of the offset voltages of the differential circuits 500 and 510 is set to M:N, and the ratio of the amplification factors is set to N:M. This allows the bias circuit 50 to robustly bias the amplification transistor 133 to the sweet spot that follows the perfect square law while improving the flexibility of parameter setting.

[0080] Note that the above-described embodiment shows an example for realizing the present technology, and the matters in the embodiment and the matters specifying the invention in the claims correspond to each other. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present technology with the same title correspond to each other. However, the present technology is not limited to the embodiment, and can be realized by applying various modifications to the embodiment within the scope of the gist. Furthermore, the effects described in this specification are merely examples and are not limited, and other effects may also be present.

[0081] The present technology may also be configured as follows: (1) A bias circuit including: a first differential circuit having bias signals superimposed with first offset voltages of opposite polarities as differential inputs; a second differential circuit having the bias signals superimposed with second offset voltages of opposite polarities as differential inputs; and a comparison circuit that outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage value of the first offset voltage and the voltage value of the second offset voltage is set to M:N (M and N are positive real numbers that are different from each other), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M. (2) The bias circuit according to (1), wherein the bias signal is set in a perfect square-law region. (3) The first differential circuit comprises: a first voltage source that generates the first offset voltage of positive polarity; a second voltage source that generates the first offset voltage of negative polarity; a first transistor to which the bias signal is input via the first voltage source; a second transistor to which the bias signal is input via the second voltage source and capable of forming a differential pair with the first transistor; a first difference current detection circuit that detects a difference current between an output of the first transistor and an output of the second transistor; and a first amplifier that multiplies the output of the first difference current detection circuit by N; and the second differential circuit comprises: a third voltage source that generates the second offset voltage of positive polarity; a fourth voltage source that generates the second offset voltage of negative polarity; a third transistor to which the bias signal is input via the third voltage source; a fourth transistor to which the bias signal is input via the fourth voltage source and capable of forming a differential pair with the third transistor; a second difference current detection circuit that detects a difference current between the output of the third transistor and the output of the fourth transistor; and a second amplifier that multiplies the output of the second difference current detection circuit by M; The bias circuit according to (1) or (2), wherein the driving powers of the first to fourth transistors are equal to each other, and the driving powers of the first and second difference current detection circuits are equal to each other.(4) The bias circuit according to (3), wherein the first differential current detection circuit comprises: a fifth transistor connected in series with the first transistor; a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor; and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, wherein a first input of the first operational amplifier is connected to a drain of the first transistor, and a second input of the first operational amplifier is connected to a first bias source; the second differential current detection circuit comprises: a seventh transistor connected in series with the third transistor; an eighth transistor connected in series with the fourth transistor and capable of forming a differential pair with the seventh transistor; and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, wherein a first input of the second operational amplifier is connected to the drain of the third transistor, and a second input of the second operational amplifier is connected to a second bias source; and the fifth to eighth transistors have equal driving powers.(5) The first differential circuit comprises: a first voltage source that generates the first offset voltage of positive polarity; a second voltage source that generates the first offset voltage of negative polarity; a first transistor to which the bias signal is input via the first voltage source; a second transistor to which the bias signal is input via the second voltage source and capable of forming a differential pair with the first transistor; a first difference current detection circuit that detects a difference current between an output of the first transistor and an output of the second transistor; and a first amplifier that amplifies the output of the first difference current detection circuit; and the second differential circuit comprises: a third voltage source that generates the second offset voltage of positive polarity; a fourth voltage source that generates the second offset voltage of negative polarity; a third transistor to which the bias signal is input via the third voltage source; a fourth transistor to which the bias signal is input via the fourth voltage source and capable of forming a differential pair with the third transistor; a second difference current detection circuit that detects a difference current between the output of the third transistor and the output of the fourth transistor; and a second amplifier that amplifies the output of the second difference current detection circuit. The bias circuit according to (1) or (2), wherein the driving strengths of the first and second transistors are equal to each other, the driving strengths of the third and fourth transistors are equal to each other, the driving strengths of the third and fourth transistors are set to N times the driving strengths of the first and second transistors, the driving strength of the first differential current detection circuit is set to N times the driving strength of the second differential current detection circuit, and the amplification factors of the first and second amplifiers are equal to each other.(6) The first differential current detection circuit comprises: a fifth transistor connected in series with the first transistor; a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor; and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, a first input of the first operational amplifier being connected to a drain of the first transistor, and a second input of the first operational amplifier being connected to a first bias source; the second differential current detection circuit comprises: a seventh transistor connected in series with the third transistor; an eighth transistor connected in series with the fourth transistor and capable of forming a differential pair with the seventh transistor; and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, a first input of the second operational amplifier being connected to the drain of the third transistor, and a second input of the second operational amplifier being connected to a second bias source; the fifth and sixth transistors have equal driving strengths; the seventh and eighth transistors have equal driving strengths; the driving power of each of the fifth and sixth transistors is set to N times the driving power of each of the seventh and eighth transistors. (7) The bias circuit according to (5), further comprising: a bias circuit that generates a bias signal; and an amplifier to which the bias signal is applied, the bias circuit comprising: a first differential circuit that receives as its differential input the bias signals superimposed with first offset voltages of opposite polarities; a second differential circuit that receives as its differential input the bias signals superimposed with second offset voltages of opposite polarities; and a comparison circuit that outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage value of the first offset voltage and the voltage value of the second offset voltage is set to M:N (M and N are positive real numbers that are different from each other), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M. (8) The amplifier circuit according to (7), further comprising: a resonant circuit connected as a load of the amplifier.

[0082] 10 Bias circuit 100, 110 Differential circuit 101, 111 Differential current detection circuit 102, 112 Amplifier 103, 104, 113, 114 Field effect transistor 105, 106, 115, 116 Voltage source 121 Operational amplifier 131 Resistor 132 Capacitor 133 Amplifying transistor

Claims

1. A bias circuit comprising: a first differential circuit having as its differential input bias signals superimposed with first offset voltages of opposite polarities; a second differential circuit having as its differential input the bias signals superimposed with second offset voltages of opposite polarities; and a comparison circuit which outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage value of the first offset voltage and the voltage value of the second offset voltage is set to M:N (M and N are mutually different positive real numbers), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M.

2. The bias circuit according to claim 1, wherein the bias signal is set in a perfect square law region.

3. The first differential circuit comprises: a first voltage source which generates the first offset voltage of positive polarity; a second voltage source which generates the first offset voltage of negative polarity; a first transistor to which the bias signal is input via the first voltage source; a second transistor to which the bias signal is input via the second voltage source and which can form a differential pair with the first transistor; a first difference current detection circuit which detects a difference current between an output of the first transistor and an output of the second transistor; and a first amplifier which multiplies the output of the first difference current detection circuit by N; and the second differential circuit comprises: a third voltage source which generates the second offset voltage of positive polarity; a fourth voltage source which generates the second offset voltage of negative polarity; a third transistor to which the bias signal is input via the third voltage source; a fourth transistor to which the bias signal is input via the fourth voltage source and which can form a differential pair with the third transistor; a second difference current detection circuit which detects a difference current between the output of the third transistor and the output of the fourth transistor; and a second amplifier which multiplies the output of the second difference current detection circuit by M; 2. The bias circuit according to claim 1, wherein the driving strengths of the first to fourth transistors are equal to each other, and the driving strengths of the first and second difference current detection circuits are equal to each other.

4. The bias circuit according to claim 3, wherein the first differential current detection circuit comprises: a fifth transistor connected in series with the first transistor; a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor; and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, a first input of the first operational amplifier being connected to a drain of the first transistor, and a second input of the first operational amplifier being connected to a first bias source; the second differential current detection circuit comprises: a seventh transistor connected in series with the third transistor; an eighth transistor connected in series with the fourth transistor and capable of forming a differential pair with the seventh transistor; and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, a first input of the second operational amplifier being connected to the drain of the third transistor, and a second input of the second operational amplifier being connected to a second bias source; and the driving strengths of the fifth to eighth transistors are equal to each other.

5. The first differential circuit comprises: a first voltage source which generates the first offset voltage of positive polarity; a second voltage source which generates the first offset voltage of negative polarity; a first transistor to which the bias signal is input via the first voltage source; a second transistor to which the bias signal is input via the second voltage source and which can form a differential pair with the first transistor; a first difference current detection circuit which detects a difference current between an output of the first transistor and an output of the second transistor; and a first amplifier which amplifies an output of the first difference current detection circuit; and the second differential circuit comprises: a third voltage source which generates the second offset voltage of positive polarity; a fourth voltage source which generates the second offset voltage of negative polarity; a third transistor to which the bias signal is input via the third voltage source; a fourth transistor to which the bias signal is input via the fourth voltage source and which can form a differential pair with the third transistor; a second difference current detection circuit which detects a difference current between the output of the third transistor and the output of the fourth transistor; and a second amplifier which amplifies an output of the second difference current detection circuit; 2. The bias circuit of claim 1, wherein the driving strengths of the first and second transistors are equal to each other, the driving strengths of the third and fourth transistors are equal to each other, the driving strengths of the third and fourth transistors are set to N times the driving strengths of the first and second transistors, the driving strength of the first difference current detection circuit is set to N times the driving strength of the second difference current detection circuit, and the amplification factors of the first and second amplifiers are equal to each other.

6. The first difference current detection circuit comprises: a fifth transistor connected in series with the first transistor; a sixth transistor connected in series with the second transistor and capable of forming a differential pair with the fifth transistor; and a first operational amplifier having an output connected to a gate of the fifth transistor and a gate of the sixth transistor, a first input of the first operational amplifier being connected to a drain of the first transistor, and a second input of the first operational amplifier being connected to a first bias source; the second difference current detection circuit comprises: a seventh transistor connected in series with the third transistor; an eighth transistor connected in series with the fourth transistor and capable of forming a differential pair with the seventh transistor; and a second operational amplifier having an output connected to a gate of the seventh transistor and a gate of the eighth transistor, a first input of the second operational amplifier being connected to the drain of the third transistor, and a second input of the second operational amplifier being connected to a second bias source; the fifth and sixth transistors have equal driving strengths; the seventh and eighth transistors have equal driving strengths; 6. The bias circuit according to claim 5, wherein the driving strength of each of the fifth and sixth transistors is set to N times the driving strength of each of the seventh and eighth transistors.

7. An amplifier circuit comprising: a bias circuit that generates a bias signal; and an amplifier to which the bias signal is applied, the bias circuit comprising: a first differential circuit having as its differential input the bias signals superimposed with first offset voltages of opposite polarities; a second differential circuit having as its differential input the bias signals superimposed with second offset voltages of opposite polarities; and a comparison circuit that outputs the bias signal based on a comparison result between an output of the first differential circuit and an output of the second differential circuit, wherein the relationship between the voltage value of the first offset voltage and the voltage value of the second offset voltage is set to M:N (M and N are positive real numbers which are different from each other), and the relationship between the amplification factor of the first differential circuit and the amplification factor of the second differential circuit is set to N:M.

8. The amplifier circuit of claim 7, further comprising a resonant circuit connected as a load to the amplifier.

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