Programmable sequencer, and system-on chip device using same

Abstract

The present invention relates to: a programmable sequencer capable of changing a power up / down sequence for power control of a power domain; and a system-on chip device using same. The programmable sequencer according to the present invention comprises: a processing unit, which receives, from a central processing unit, a command related to power control of at least one object to be controlled, accesses a memory in which at least one instruction for performing the command is stored, and executes the at least one instruction stored in the memory; and a register bank of which at least one register field value is changed by the processing unit so that a power control signal is transmitted to the object to be controlled, wherein the memory stores the at least one instruction for performing the command by the central processing unit.

Description

Programmable sequencer and system-on-chip device using the same

[0001] The present invention relates to power control of a system-on-chip device, and more particularly, to a programmable sequencer capable of changing a power up / down sequence for power control of a power domain, and a system-on-chip device using the same.

[0002] A system-on-chip (SoC) is a technology that integrates various functional blocks, such as a central processing unit (CPU), memory, interfaces, digital signal processing circuits, and analog signal processing circuits, into a single semiconductor integrated circuit to implement a computer system or other electronic system, or an integrated circuit (IC) integrated according to that technology. SoCs are evolving into increasingly complex systems that include various functional blocks, such as processors, multimedia, graphics, interfaces, and security.

[0003] The SoC requires a power management unit to appropriately manage the power consumed by the SoC, and this power management unit may include a power controller that outputs a power up / down sequence for each power domain.

[0004] Conventional power controllers are designed as fixed-sequencers, outputting predetermined sequences based on state machines. While state machines offer the advantages of simplicity and speed, they also suffer from limited flexibility, as they only execute a predetermined sequence.

[0005] As SoCs have become increasingly complex, the power up / down sequences for each power domain have become increasingly complex. This can lead to various abnormal cases when the SoC is designed and fabricated into actual silicon chips. These abnormal cases require modifications to the power up / down sequence, but conventional state machines designed to operate with fixed sequencers are unable to flexibly handle these various abnormal cases.

[0006] Accordingly, there is a recent trend to design power controllers using microprocessing units (MCUs), and power controllers are mainly designed using Cortex-M, a commercial MCU developed by ARM Holdings. Since these commercial MCUs are expensive, arranging individual power controllers for each individual power domain greatly increases the price of the system-on-chip device. Therefore, a single microprocessing unit is designed to perform power up / down sequences for multiple power domains. Although the microprocessing unit has high flexibility in adapting to abnormal cases after fab out, since a single microprocessing unit sequentially controls power for multiple power domains one power domain at a time, the operation delay time is long, and it takes a long time for the microprocessing unit to enter an idle state, which increases the power consumption of the system-on-chip device.

[0007] [Prior patent literature]

[0008] (Patent Document 001) Republic of Korea Patent No. 10-1861743

[0009] (Patent Document 002) Republic of Korea Patent No. 10-1835615

[0010] The purpose of the present invention is to implement a power controller for power control in a power domain as a programmable sequencer capable of changing a power up / down sequence.

[0011] Another object of the present invention is to provide a system-on-chip device capable of changing the power up / down sequence of a programmable sequencer.

[0012] A programmable sequencer according to the present invention includes a processing unit that receives a command related to power control of at least one control target from a central processing unit, accesses a memory in which at least one command for executing the command is stored, and executes the at least one command stored in the memory, and a register bank in which at least one register field value is changed by the processing unit so that a power control signal is transmitted to the control target, and the memory stores at least one command for executing the command by the central processing unit.

[0013] More specifically, the programmable sequencer according to the present invention further includes a power management interface unit that receives a signal from a control target and changes a value of a specific register field of a register bank.

[0014] More specifically, the control target is one power domain, and the command includes at least one of a domain power up command and a domain power down command.

[0015] More specifically, the control object is the central processing unit.

[0016] More specifically, the control target is at least one domain power manager, and the command includes at least one of a system power up command and a system power down command.

[0017] More specifically, the instructions include instructions that change the values ​​of specific register fields in a register bank.

[0018] More specifically, the instruction further includes an instruction to wait until the value of a specific register field in a register bank changes.

[0019] More specifically, the instruction further includes an instruction that waits for a specific cycle of time.

[0020] More specifically, the instruction further includes at least one of an instruction for writing an internal register value of a processing unit to a specific register field of a register bank, an instruction for writing a specific register field value of a register bank to an internal register of the processing unit, and an instruction for writing a user input constant value to an internal register of the processing unit.

[0021] More specifically, the instruction further includes instructions that determine the execution order of instructions stored in memory.

[0022] A system-on-chip device according to the present invention includes a memory storing at least one command for executing a command related to power control of at least one control target, a central processing unit storing at least one command for executing the command in the memory and outputting the command, and a programmable sequencer receiving a command from the central processing unit, accessing the memory to execute at least one command, and transmitting a power control signal to the control target. The programmable sequencer includes a processing unit receiving a command from the central processing unit, accessing the memory to execute at least one command, and a register bank in which at least one register field value is changed by the processing unit to transmit a power control signal to the control target.

[0023] More specifically, the programmable sequencer further includes a power management interface unit that receives signals from a controlled object and changes values ​​of specific register fields of a register bank.

[0024] More specifically, it comprises at least two programmable sequencers for sending power control signals to different control targets, and the memory stores at least one instruction for the at least two programmable sequencers to perform.

[0025] More specifically, the control target is one power domain, and the command includes at least one of a domain power up command and a domain power down command.

[0026] More specifically, the control object is the central processing unit.

[0027] More specifically, the control target is at least one domain power manager, and the command includes at least one of a system power up command and a system power down command.

[0028] More specifically, the instructions include instructions that change the values ​​of specific register fields in a register bank.

[0029] More specifically, the instruction further includes an instruction to wait until the value of a specific register field in a register bank changes.

[0030] More specifically, the instruction further includes an instruction that waits for a specific cycle of time.

[0031] More specifically, the instruction further includes at least one of an instruction for writing an internal register value of a processing unit to a specific register field of a register bank, an instruction for writing a specific register field value of a register bank to an internal register of the processing unit, and an instruction for writing a user input constant value to an internal register of the processing unit.

[0032] More specifically, the instruction further includes instructions that determine the execution order of instructions stored in memory.

[0033] According to the present invention, the following effects are achieved.

[0034] The present invention implements a power controller for power control of a power domain as a programmable sequencer capable of changing a power up / down sequence, thereby enabling flexible response to defects after fab-out.

[0035] The present invention implements a power controller for power control of a domain power manager as a programmable sequencer capable of changing the power up / down sequence, thereby enabling flexible response to defects after fab-out.

[0036] The present invention can reduce the operation delay time of the power domain and the idle state entry time of the programmable sequencer by implementing a programmable sequencer using a microprocessing unit, thereby increasing the speed of the system-on-chip device and reducing power consumption.

[0037] The present invention performs power control using a programmable sequencer individually designed for each power domain, thereby enabling efficient and fast control for each power domain.

[0038] The present invention configures a programmable sequencer for power control of an upper central processing unit (CPU) that controls a power management unit, thereby enabling power up / down of the central processing unit (CPU), thereby drastically reducing the power consumption of the SoC.

[0039] The effects of the present invention are not limited to the effects mentioned above, and other effects not mentioned can be clearly understood by a person having ordinary knowledge in the technical field to which the present invention belongs (referred to as “one of ordinary skill in the art”) from the description of the claims.

[0040] Embodiments of the present invention will be described below with reference to the accompanying drawings, wherein like reference numerals represent similar elements, but are not limited thereto.

[0041] FIG. 1 is a configuration diagram of a system-on-chip device (100) according to one embodiment of the present invention.

[0042] FIG. 2 is a configuration diagram of a domain power manager (210) according to one embodiment of the present invention.

[0043] Figure 3 illustrates a power state transition diagram of the power domain of the present invention.

[0044] FIG. 4 is a diagram illustrating an example of a power-up sequence and a power-down sequence performed in a domain power manager of the present invention.

[0045] Figure 5 illustrates a changed power state transition diagram of the power domain of the present invention.

[0046] FIG. 6 is a diagram illustrating an example of a modified power-up sequence and a power-down sequence performed by a domain power manager.

[0047] FIG. 7 is a configuration diagram of a root power manager (710) according to one embodiment of the present invention.

[0048] Embodiments of the present invention will be described below with reference to the accompanying drawings, wherein like reference numerals represent similar elements, but are not limited thereto.

[0049] [Explanation of symbols]

[0050] 100: System-on-Chip (SoC)

[0051] 110: Power Management Unit (PMU)

[0052] 120: Central Processing Unit (CPU)

[0053] 130, 140: Power Domain (PD)

[0054] 111: Power Management for Root (PMR)

[0055] 112, 113, 114: Power Management for Domain (PMD)

[0056] 115: Memory

[0057] 116: Internal bus

[0058] Hereinafter, specific details for implementing the present invention will be described in detail with reference to the attached drawings. However, in the following description, specific descriptions of widely known functions or configurations will be omitted if they may unnecessarily obscure the gist of the present invention.

[0059] In the attached drawings, identical or corresponding components are assigned the same reference numerals. Furthermore, in the description of the embodiments below, duplicate descriptions of identical or corresponding components may be omitted. However, even if a description of a component is omitted, it is not intended that such component is not included in any embodiment.

[0060] The advantages and features of the embodiments disclosed herein, and the methods for achieving them, will become clearer with reference to the embodiments described below, along with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various different forms. These embodiments are provided solely to fully inform those skilled in the art of the scope of the invention.

[0061] Unless otherwise defined, all terms (including technical and scientific terms) used herein may be used in their common sense to those of ordinary skill in the art to which the present invention pertains. Furthermore, terms defined in commonly used dictionaries are not to be interpreted ideally or excessively unless explicitly and specifically defined otherwise.

[0062] For example, the term "technology" may refer to systems, methods, computer-readable instructions, modules, algorithms, hardware logic, and / or operations as permitted by the context described above and throughout the document.

[0063] In this specification, singular expressions include plural expressions unless the context clearly indicates otherwise. Furthermore, plural expressions include singular expressions unless the context clearly indicates otherwise. When a part of the specification is said to include a component, this does not exclude other components, but rather implies that other components may be included, unless otherwise specifically stated.

[0064] In the present invention, terms such as “comprise”, “comprising”, etc. may indicate the presence of features, steps, operations, elements, and / or components, but such terms do not exclude the addition of one or more other functions, steps, operations, elements, components, and / or combinations thereof.

[0065] In the present invention, when a specific component is referred to as being "coupled," "combined," "connected," "associated," or "reacting" with any other component, the specific component may be directly coupled, combined, connected, and / or associated with, or reacting with, the other component, but is not limited thereto. For example, one or more intermediate components may exist between the specific component and the other component. Furthermore, in the present invention, "and / or" may include each of one or more listed items or a combination of at least some of one or more items.

[0066] In the present invention, terms such as "first," "second," etc. are used to distinguish specific components from other components, and these terms do not limit the components described above. For example, the term "first" component may be used to refer to an element having the same or similar form as the "second" component.

[0067] FIG. 1 is a configuration diagram of a system-on-chip device (100) according to one embodiment of the present invention.

[0068] The system-on-chip device (100) according to the present invention is a product and system that are fully driven in one integrated circuit, and can be implemented as a chip, module, or system.

[0069] A system-on-chip device (100) according to the present invention may include a power management unit (PMU) (110), a central processing unit (CPU) (120) that controls the power management unit (110) with software, and at least one power domain (PD) (130, 140).

[0070] The central processing unit (120) controls the power management unit (110) and may be one power domain (120) constituting the system-on-chip device. That is, in the present invention, the central processing unit (120) and the power domain (120) may be the same component. In this specification, when the reference number 120 performs the function of controlling the power management unit (110), it is named as the central processing unit (120), and when it is referred to as a power domain, it is named as the power domain (120).

[0071] The power management unit (110) can provide a power up / down sequence corresponding to at least one power domain (120, 130, 140), respectively. Each power domain (120, 130, 140) can process the power up / down sequence to enter a power up state or a power down state. The system-on-chip device can include at least one power management unit (110).

[0072] A power domain may include a core domain including a central processing unit (120), a memory domain including a memory subsystem such as a main memory or a cache memory, a graphics and video domain including multimedia elements such as a graphics processing unit or a video encoding / decoding unit, and an input / output domain including input / output interface elements for communication with the outside. Each power domain may include lower sub-power domains.

[0073] The power management unit (110) corresponds to each power domain (120, 130, 140) and may include at least one domain power manager (PMD; Power Management for Domain) (112, 113, 114) that controls the corresponding power domain, a root power manager (PMR; Power Management for Root) (111) that manages at least one domain power manager (112, 113, 114), and a memory (115) that stores a program that operates the root power manager (111) and at least one domain power manager (112, 113, 114). The at least one domain power manager (112, 113, 114), the root power manager (111), and the memory (115) may be interconnected by an internal bus (116). The program stored in the memory (115) may include instructions and data.

[0074] The root power manager (111) can receive a system power up / down command from the central processing unit (120). The system power up / down command can include a power up / down command for a system-on-chip device or a power up / down command for a subsystem composed of one or more power domains. In the present invention, the power up / down command for the system-on-chip device and the power up / down command for the subsystem are collectively referred to as a system power up / down command. The root power manager (111) can perform booting of the system-on-chip device (100) by operating at least one domain power manager (112, 113, 114) based on commands and data for performing booting at the time of booting. In addition, when a system power up / down command is received from a central processing unit (120), at least one domain power manager (112, 113, 114) is operated based on the command and data for performing the command, thereby powering on / off a system-on-chip device (100) or a subsystem composed of multiple power domains.

[0075] In addition, when at least one domain power manager (112, 113, 114) receives a domain power up / down command for power control of a power domain from a central processing unit (120), it performs power up / down sequence control on the corresponding power domain based on the command and data for performing the command.

[0076] The first domain power manager (112) outputs a power control signal to the power domain (120), which is the central processing unit (120), and performs a power up / down sequence, the second domain power manager (113) outputs a power control signal to the first power domain (130) and performs a power up / down sequence, and the third domain power manager (114) outputs a power control signal to the second power domain (140) and performs a power up / down sequence.

[0077] In the present invention, the power consumption of a system-on-chip device can be reduced by including a first domain power manager (112) for power control of a central processing unit (120) so that the central processing unit (120) can be put into a power-down state. In addition, since separate domain power managers (112, 113, 114) are matched for each power domain (120, 130, 140), power control of each power domain (120, 130, 140) can be performed in parallel, enabling efficient and fast processing.

[0078] The root power manager (111), the first domain power manager (112), the second domain power manager (113), and the third domain power manager (114) can each be implemented as a programmable sequencer of the present invention.

[0079] The memory (115) can store both commands and data for the root power manager (111) to perform a system power up / down command, and commands and data for each domain power manager (112, 113, 114) to perform a domain power up / down command. At this time, the memory can be divided into sections according to addresses, and an independent address area can be allocated to each manager (111, 112, 113, 114). Meanwhile, if a program that must be run in at least two of the multiple managers (111, 112, 113, 114) is the same, the same address area can be shared by multiple managers.

[0080] In this embodiment, a system-on-chip device composed of three power domains and three domain power managers is exemplified, but the present invention is not limited thereto, and the number of power domains may be designed to be a different number depending on the complexity of the system-on-chip device, and the number of domain power managers may be changed depending on the number of power domains.

[0081] The root power manager (111) and each domain power manager (112, 113, 114) may be a programmable sequencer implemented as a microprocessing unit (MCU). A commercial product of a microprocessing unit (MCU) mainly used in system-on-chip devices is the cortex-M developed by ARM Holdings, and such commercial MCUs are manufactured to be used generally. The programmable sequencer of the present invention may also be implemented using a general-purpose MCU. However, such a general-purpose MCU includes unnecessary components for operating as a programmable sequencer, such as a cache, an interrupt handler, an arithmetic unit, a debugger interface, and a breakpoint unit, and has the disadvantage of being large in size and slow in operating speed due to these unnecessary components.

[0082] In the present invention, a programmable sequencer of the present invention is configured by designing a specialized MCU necessary to operate as a programmable sequencer, rather than using a general-purpose MCU.

[0083] FIG. 2 is a configuration diagram of a domain power manager (210) according to one embodiment of the present invention.

[0084] The domain power manager (210) may be an embodiment of a programmable sequencer.

[0085] The domain power manager (210) transmits power control signals to the power domain (220) and performs a power up / down sequence of the power domain (220) to proceed from a power up state to a power down state or from a power down state to a power up state. The power control signals for performing the power up / down sequence may include a reset signal (Reset), an isolation signal (Isolation), a switch control signal (Switch Control), a retention signal (Retention), etc. These power control signals may be added / deleted / changed according to the specifications of the power domain (220).

[0086] The domain power manager (210) of FIG. 2 may be one of the first domain power manager (112), the second domain power manager (113), and the third domain power manager (114) of FIG. 1. The power domain (220) of FIG. 2 may be one of the power domains (120, 130, 140) of FIG. 1. The central processing unit (120) may store a program including commands and data to be executed by the domain power manager (210) in the memory (115). The central processing unit (120) may change and store the commands and data stored in the memory (115). Accordingly, the contents and order of commands executed by the domain power manager (210) may be changed, and thus the domain power manager (210) may become a programmable sequencer. The central processing unit (120) outputs a domain power up command or domain power down command for power control of a power domain (220) to the domain power manager (210). When the domain power up command or domain power down command is received, the domain power manager (210) performs power control on the corresponding power domain (220), transmits power control signals to the power domain (220), and performs a power up sequence or a power down sequence. Through this, the power domain (220) is put into a power up state or a power down state.

[0087] The domain power manager (210) includes a processing unit (211) that receives a domain power up / down command related to power control of a power domain (220) from a central processing unit (120), accesses a memory (115) in which instructions for performing the command are stored, and executes the instructions stored in the memory (115), and a register bank (212) that changes at least one field value by the processing unit (211) and transmits power control signals to the power domain (220).

[0088] The register bank (212) includes a plurality of register fields corresponding to each power control signal, and the values ​​recorded in the register fields are transmitted to the power domain (220) as the corresponding power control signals. For example, the register bank (212) includes a register field corresponding to a reset signal, a register field corresponding to an isolation signal, a register field corresponding to a switch control signal, and a register field corresponding to a retention signal, and the corresponding signal is transmitted as 0 or 1 depending on the corresponding register field value (0 or 1).

[0089] The command stored in the memory (115) includes a command to write a specific register field value of the register bank (212) as 0 and a command to write a specific field value of the register bank (212) as 1. The processing unit (211) can execute the command to change the specific register field value of the register bank (212) to 0 or 1. Then, the value of the corresponding power control signal is changed to 0 or 1 and transmitted to the power domain (220).

[0090] The domain power manager (210) may further include a power management interface unit (213) that receives a signal from the power domain (220) and transmits it to at least one of the processing unit (211) and the register bank (212).

[0091] Among the power control signals, there are many signals that are composed of a handshake. For example, after transmitting a power switch enable signal, a corresponding feedback signal must be received. At this time, the feedback signal output from the power domain is recorded as a specific register field value of the register bank (212) through the power management interface unit (213), and the processing unit (211) waits until the corresponding register field value is recorded as the specific value.

[0092] To this end, the instructions stored in the memory (115) may include an instruction to wait until a specific register field value of the register bank (212) becomes 0, and an instruction to wait until a specific register field value of the register bank (212) becomes 1.

[0093] Additionally, among the power control signals, after transmitting one signal, it may be necessary to wait for a certain period of time before performing the next operation. For example, when the power domain (220) is reset and released, it is necessary to wait until the power domain (220) is reset and returns to normal operation.

[0094] To this end, the instruction stored in the memory (115) may include an instruction that waits for a specific cycle time, and the waiting time information may be stored in a specific register field of the register bank (212), or a constant value input by the user may be stored in an internal register of the processing unit.

[0095] In addition, the instructions stored in the memory (115) may include an instruction for writing an internal register value of the processing unit (211) to a specific register field of the register bank (212), an instruction for writing a specific register field value of the register bank (212) to an internal register of the processing unit (211), and an instruction for writing a user input constant value to an internal register of the processing unit (211).

[0096] In addition, the instructions stored in the memory (115) may include instructions that determine the execution order of the instructions stored in the memory (115), and these instructions may include instructions for jumping to a specific address, instructions for returning to a previous address, instructions for moving to a specific address according to the result of executing the instructions, etc.

[0097] Figure 3 illustrates a power state transition diagram of the power domain of the present invention.

[0098] When the power domain (220) is in a power-up state, if the reset signal transitions from 1 to 0, the isolation signal transitions from 0 to 1, and the switch control signal transitions from 0 to 1, it is assumed that the power domain is in a power-down state. The power control signals that cause the power domain (220) to be in a power-up state and to be in a power-down state are referred to as a power-down sequence. In addition, it is assumed that the power domain (220) is in a power-down state, if the switch control signal transitions from 1 to 0, the isolation signal transitions from 1 to 0, and the reset signal transitions from 0 to 1, it is assumed that the power domain (220) is in a power-up state and to be in a power-up state. The power control signals that cause the power domain (220) to be in a power-up state and to be in a power-up state are referred to as a power-up sequence.

[0099] FIG. 4 is a diagram illustrating an example of a power-up sequence and a power-down sequence performed in a domain power manager of the present invention.

[0100] The domain power manager (210) performs a power up sequence and a power down sequence for the power domain (220), and the power domain (220) can transition to a power up state and a power down state by executing the power up sequence and the power down sequence.

[0101] The central processing unit (120) stores commands for the domain power manager (210) to control power of the power domain (220) in the memory (115) and sends a domain power up command or domain power down command to the domain power manager (210).

[0102] When a domain power down command is received from the central processing unit (120), the domain power manager (210) reads and executes commands for performing a power down sequence in the power domain (220) from the memory (115). These commands include commands for setting a specific register field value of the register bank (212) to 0 or 1, and through execution of these commands, a power down sequence can be performed in the power domain (220) as illustrated in FIG. 4.

[0103] Meanwhile, when a domain power-up command is received from the central processing unit (120), the domain power manager (210) reads and executes commands for performing a power-up sequence in the power domain (220) from the memory (115), thereby allowing the power-up sequence to be performed in the power domain (220) as illustrated in FIG. 4.

[0104] If at least a part of the power down sequence and the power up sequence is changed, the central processing unit (120) can change the execution order and data of the commands stored in the memory (115). If the execution order and data of the commands stored in the memory (115) are changed in this way, the domain power manager (210) that receives a subsequent domain power up command or domain power down command performs the power up / down sequence by reflecting the changed command execution order and data. In this way, the domain power manager (210) operates as a programmable sequence.

[0105] FIG. 5 illustrates a changed power state transition diagram of the power domain of the present invention, and FIG. 6 is a diagram illustrating an example of a changed power up sequence and a power down sequence performed by a domain power manager.

[0106] The power down sequence that causes the power domain (220) to go from a power up state to a power down state is the same as in FIG. 3, but the power up sequence that causes the power domain (220) to go from a power down state to a power up state is assumed to have changed. That is, the power up sequence is assumed to have changed such that the switch control signal transitions from 1 to 0, the isolation signal sequentially transitions from 1 to 0, from 0 to 1, and from 1 to 0 again, and the reset signal transitions from 0 to 1.

[0107] In the present invention, when a situation arises where the power-down sequence or power-up sequence needs to be changed, the central processing unit (120) simply changes the execution order and data of the commands stored in the memory (115). Therefore, according to the present invention, various abnormal cases can be flexibly dealt with after fab out.

[0108] FIG. 7 is a configuration diagram of a root power manager (710) according to one embodiment of the present invention.

[0109] The root power manager (710) may be another embodiment of a programmable sequencer.

[0110] The root power manager (710) may be the root power manager (PMR: Power Management for Root) of FIG. 1.

[0111] The central processing unit (120) can store a program including commands and data to be performed by the root power manager (710) in the memory (115). The central processing unit (120) can change and store the program including commands and data stored in the memory (115). Accordingly, the content and order of commands performed by the root power manager (710) can be changed, and for this reason, the root power manager (710) can operate as a programmable sequencer. The central processing unit (120) can output a system power up / down command to the root power manager (710). The system power up / down command can include a power up / down command for the system-on-chip device (100) or a power up / down command for an arbitrary subsystem composed of multiple power domains.

[0112] The root power manager (710) includes a processing unit (711) that receives a system power up / down command from a central processing unit (120), accesses a memory (115) in which instructions for performing the command are stored, and executes the instructions stored in the memory (115), and a register bank (712) that changes at least one field value by the processing unit (711) and transmits a power control signal to at least one domain power manager (721, 722). The root power manager (710) may further include a power management interface unit (not shown) that receives a signal from at least one domain power manager (721, 722) and transmits the signal to at least one of the processing unit (711) and the register bank (712).

[0113] The memory (115) stores commands that the root power manager (710) must perform according to the command. When a system power up / down command is received from the central processing unit (120), the root power manager (710) performs the commands stored in the memory (115) and transmits a power control signal to at least one domain power manager (721, 722) to control power.

[0114] That is, when a system power up / down command is received from a central processing unit (120), the root power manager (710) can operate at least one domain power manager (112, 113, 114) based on instructions and data for performing the command, thereby powering on / off a system-on-chip device (100) or a subsystem composed of multiple power domains.

[0115] After fab-out, situations may arise where the power-up order of the domain power manager or the power-down order during power-off must be changed. In such cases, the central processing unit (120) can change the execution order of the instructions and data stored in the memory (115). Then, the root power manager (710) can execute the power-on / off order of the system-on-chip device (100) or a subsystem comprised of multiple power domains in the changed order. Therefore, according to the present invention, various abnormal cases can be flexibly dealt with after fab-out.

[0116] Any routine description, element, or block of a flowchart described herein and / or depicted in the accompanying drawings should be understood to potentially represent code, modules, segments, or portions that contain one or more executable instructions for implementing a particular logical function or element. Routine. Alternative examples are included within the scope of the examples described herein, and elements or functions may be deleted or executed in the order shown or discussed, substantially synchronously or in reverse order, depending on the functionality understood herein.

[0117] Many variations and modifications can be made to the above-described embodiments, and it should be understood that the elements are just one of the permissible examples. All such variations and modifications are intended to be included within the scope of the present disclosure and protected by the following claims. The embodiments according to the present invention described above may be implemented in the form of program instructions that can be executed by various computer components and recorded on a computer-readable recording medium. The computer-readable recording medium may include program instructions, data files, data structures, etc., either singly or in combination. The program instructions recorded on the computer-readable recording medium may be those specially designed and configured for the present invention, or may be known and available to those skilled in the art of computer software. Examples of the computer-readable recording medium include magnetic media such as hard disks, floppy disks, and magnetic tapes; optical recording media such as CD-ROMs and DVDs; magneto-optical media such as floptical disks; and hardware devices specially configured to store and execute program instructions such as ROMs, RAMs, and flash memories. Examples of program instructions include not only machine language codes, such as those generated by a compiler, but also high-level language codes that can be executed by a computer using an interpreter or the like. The hardware device may be configured to operate as one or more software modules to perform processing according to the present invention, and vice versa.

[0118] Although the present invention has been described above with specific details such as specific components and limited examples and drawings, these are provided only to help a more general understanding of the present invention, and the present invention is not limited to the above examples, and those with ordinary knowledge in the technical field to which the present invention pertains can make various modifications and variations from this description.

[0119] Therefore, the idea of ​​the present invention should not be limited to the embodiments described above, and all things that are modified equally or equivalently to the following claims as well as the claims are considered to fall within the scope of the idea of ​​the present invention.

Claims

1. A processing unit that receives a command related to power control of at least one control target from a central processing unit, accesses a memory in which at least one command for performing the command is stored, and executes at least one command stored in the memory; A register bank is included so that at least one register field value is changed by the processing unit to transmit a power control signal to the control target, The above memory stores at least one command for executing the command by the central processing unit. Programmable sequencer.

2. In paragraph 1, Further comprising a power management interface unit that receives a signal from the control target and changes a specific register field value of the register bank. Programmable sequencer.

3. In the second paragraph, the control target is one power domain, The above command includes at least one of a domain power up command and a domain power down command. Programmable sequencer.

4. In the third paragraph, the control target is the central processing unit. Programmable sequencer.

5. In the second paragraph, the control target is at least one domain power manager, The above command includes at least one of a system power up command and a system power down command. Programmable sequencer.

6. In paragraph 2, The above command includes a command that changes the value of a specific register field of the register bank. Programmable sequencer.

7. In paragraph 6, The above instruction further includes an instruction to wait until the value of a specific register field of the register bank changes. Programmable sequencer.

8. In paragraph 6, The above command further includes a command to wait for a specific cycle time, Programmable sequencer.

9. In paragraph 6, The command further includes at least one of a command for writing an internal register value of the processing unit to a specific register field of the register bank, a command for writing a specific register field value of the register bank to an internal register of the processing unit, and a command for writing a user input constant value to an internal register of the processing unit. Programmable sequencer.

10. In paragraph 6, The above command further includes a command that determines the execution order of the commands stored in the memory. Programmable sequencer.

11. A memory storing at least one command for performing a command related to power control of at least one control target, A central processing unit that stores at least one command for performing the above command in the memory and outputs the command, and A programmable sequencer that receives the command from the central processing unit, accesses the memory, executes the at least one instruction, and transmits a power control signal to the control target, The programmable sequencer comprises a processing unit that receives the command from the central processing unit, accesses the memory, and executes the at least one instruction; A register bank including at least one register field value changed by the processing unit to transmit a power control signal to the control target. System on a chip device.

12. In paragraph 11, The programmable sequencer further includes a power management interface unit that receives a signal from the control target and changes a specific register field value of the register bank. System on a chip device.

13. In the 11th paragraph, at least two programmable sequencers each transmitting a power control signal to a different control target are included, The above memory stores at least one instruction for each of the at least two programmable sequencers to be performed. System on a chip device.

14. In paragraph 12, the control target is one power domain, The above command includes at least one of a domain power up command and a domain power down command. System on a chip device.

15. In paragraph 14, the control target is the central processing unit. System on a chip device.

16. In paragraph 12, the control target is at least one domain power manager, The above command includes at least one of a system power up command and a system power down command. System on a chip device.

17. In paragraph 12, The above command includes a command that changes the value of a specific register field of the register bank. System on a chip device.

18. In paragraph 17, The above instruction further includes an instruction to wait until the value of a specific register field of the register bank changes. System on a chip device.

19. In paragraph 17, The above command further includes a command to wait for a specific cycle time, System on a chip device.

20. In paragraph 17, The command further includes at least one of a command for writing an internal register value of the processing unit to a specific register field of the register bank, a command for writing a specific register field value of the register bank to an internal register of the processing unit, and a command for writing a user input constant value to an internal register of the processing unit. System on a chip device.

21. In paragraph 17, The above command further includes a command that determines the execution order of the commands stored in the memory. System on a chip device.

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