Display device and manufacturing method therefor

Abstract

This display device comprises: a substrate: a first transistor including a first bottom gate electrode disposed on the substrate, a first active layer disposed on the first bottom gate electrode and including a first channel region, a first drain region, and a first source region, and a first top gate electrode disposed on a portion of the first active layer in which the first channel region is included; a first insulating layer disposed between the first bottom gate electrode and the first active layer; and a second insulating layer disposed between the first active layer and the first top gate electrode. The second insulating layer includes a first portion having a first thickness and disposed on the portion of the first active layer in which the first channel region is included, and a second portion having a second thickness smaller than the first thickness and disposed on the remainder of the first active layer.

Description

Display device and method for manufacturing the same

[0001] Embodiments of the present invention relate to a display device and a method for manufacturing the same.

[0002] Display devices are becoming increasingly important with the development of multimedia. In response, various display devices, such as liquid crystal displays (LCDs) and light-emitting display devices (LEDs), are being developed.

[0003] The problem to be solved by the present invention is to provide a display device and a manufacturing method thereof that can improve the operating characteristics of a transistor.

[0004] The tasks of the present invention are not limited to the technical tasks mentioned above, and other technical tasks not mentioned will be clearly understood by those skilled in the art from the description below.

[0005] According to one embodiment, a display device includes: a substrate; a first transistor including a first bottom gate electrode disposed on the substrate; a first active layer disposed on the first bottom gate electrode and including a first channel region, a first drain region, and a first source region; a first top gate electrode disposed on a portion of the first active layer including the first channel region; a first insulating layer disposed between the first bottom gate electrode and the first active layer; and a second insulating layer disposed between the first active layer and the first top gate electrode. The second insulating layer may include a first portion disposed on a portion of the first active layer including the first channel region and having a first thickness, and a second portion disposed on a remaining portion of the first active layer and having a second thickness smaller than the first thickness.

[0006] In one embodiment, the first channel region may include a lower portion adjacent to the first bottom gate electrode and having a first length, and an upper portion adjacent to the first top gate electrode and having a second length longer than the first length.

[0007] In one embodiment, on the cross-section of the first active layer, the first channel region may have a shape of an inverted trapezoid whose length increases from the lower layer to the upper layer.

[0008] In one embodiment, the first channel region includes a lower portion adjacent to the first bottom gate electrode and an upper portion adjacent to the first top gate electrode, wherein the lower portion of the first channel region can have a higher carrier concentration than the upper portion of the first channel region.

[0009] In one embodiment, the second insulating layer includes an upper portion in contact with the first top gate electrode, and the upper portion of the second insulating layer and the first top gate electrode may have the same pattern shape.

[0010] In one embodiment, the second insulating layer includes an upper portion in contact with the first top gate electrode, and the upper portion of the second insulating layer and the first top gate electrode may have the same area.

[0011] In one embodiment, the side surface of the first top gate electrode and the side surface of the second insulating layer may have a continuously connected inclined surface.

[0012] In one embodiment, the second insulating layer may have a step-shaped difference at the boundary between the first portion and the second portion.

[0013] In one embodiment, the display device may further include a third insulating layer covering the second insulating layer and the first top gate electrode.

[0014] In one embodiment, the display device may further include at least one of a first drain electrode disposed on the third insulating layer and connected to the first drain region by a first contact hole penetrating the second insulating layer and the third insulating layer; and a first source electrode disposed on the third insulating layer and connected to the first source region by a second contact hole penetrating the second insulating layer and the third insulating layer. The second insulating layer may entirely cover the first active layer except for a portion where at least one of the first contact hole and the second contact hole is formed.

[0015] In one embodiment, the first bottom gate electrode may be electrically connected to the first top gate electrode.

[0016] In one embodiment, the display device may further include a pixel including the first transistor.

[0017] In one embodiment, the pixel may further include a second transistor. The second transistor may include: a second bottom gate electrode disposed on the substrate; a second active layer disposed on the first insulating layer, the second active layer including a second channel region, a second drain region, and a second source region; and a second top gate electrode disposed on the second insulating layer, the second active layer including the second channel region.

[0018] In one embodiment, the second insulating layer may cover the second active layer and have the first thickness and the second thickness, respectively, on a portion of the second active layer including the second channel region and the remaining portion of the second active layer.

[0019] In one embodiment, the first active layer and the second active layer may include the same oxide semiconductor.

[0020] In one embodiment, the display device may further include a driver connected to the pixel, and a driver transistor included in the driver. The driver transistor may include: a third bottom gate electrode disposed on the substrate; a third active layer disposed on the first insulating layer and including a third channel region, a third drain region, and a third source region; and a third top gate electrode disposed on the second insulating layer and on a portion of the third active layer including the third channel region.

[0021] In one embodiment, the second insulating layer may cover the third active layer and have the first thickness and the second thickness, respectively, on a portion of the third active layer including the third channel region and the remaining portion of the third active layer.

[0022] In one embodiment, the first active layer and the third active layer may include the same oxide semiconductor.

[0023] A method for manufacturing a display device according to one embodiment includes the steps of: forming a first insulating layer on a substrate; forming an active layer on the first insulating layer; forming a second insulating layer covering the active layer on the substrate; forming a conductive film on the second insulating layer; etching the conductive film to form a top gate electrode overlapping a portion of the active layer; and forming a third insulating layer on the second insulating layer and the top gate electrode, and prior to forming the third insulating layer, the method may further include the step of etching a portion of the second insulating layer that does not overlap the top gate electrode by a certain thickness using a mask identical to a mask used for etching the conductive film or using the top gate electrode as a mask.

[0024] In one embodiment, the method for manufacturing the display device further includes a step of forming a bottom gate electrode on the substrate prior to forming the first insulating layer, wherein the active layer can be formed on the first insulating layer so as to overlap at least a portion of the bottom gate electrode.

[0025] Specific details of other embodiments are included in the detailed description and drawings.

[0026] A display device according to embodiments includes a transistor including a bottom gate electrode, an active layer, and a top gate electrode, and an insulating layer disposed between the active layer and the top gate electrode of the transistor. The insulating layer may have a first thickness on a portion of the active layer including a channel region, and a second thickness smaller than the first thickness on a remaining portion of the active layer.

[0027] According to the display device and the manufacturing method thereof according to the embodiments, in the manufacturing process of the display device including the transistor, the source region and the drain region of the active layer can be appropriately and / or easily made conductive, while reducing the amount of hydrogen flowing into or penetrating the active layer, thereby expanding or securing the effective channel length of the transistor. Accordingly, the threshold voltage roll-off (Vth roll-off) of the transistor can be prevented, and the operating characteristics of the transistor can be improved and / or stabilized. For example, even if the size of the transistor (e.g., channel length) is reduced in a high-resolution display device, etc., the operating characteristics of the transistor can be improved by appropriately and / or easily securing the length of the effective channel of the transistor.

[0028] The effects according to the embodiments are not limited to those exemplified above, and more diverse effects are included in this specification.

[0029] FIG. 1 is a plan view showing a display device according to one embodiment.

[0030] Figure 2 is a plan view showing the display panel of Figure 1.

[0031] Figure 3 is an equivalent circuit diagram showing a pixel according to one embodiment.

[0032] Figure 4 is an equivalent circuit diagram showing a pixel according to one embodiment.

[0033] FIG. 5 is a cross-sectional view showing a display panel according to one embodiment.

[0034] FIG. 6 is a cross-sectional view showing a display panel according to one embodiment.

[0035] Fig. 7 is a cross-sectional view showing a display panel according to one embodiment.

[0036] Figures 8a and 8b are graphs showing the effective channel length of a channel region formed in a transistor depending on the etching degree of the gate insulating layer.

[0037] Figures 9a and 9b are graphs showing changes in the characteristics of a transistor according to the degree of etching of the gate insulating layer.

[0038] FIGS. 10 to 16 are cross-sectional views showing a method of manufacturing a display device according to one embodiment.

[0039] The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms. These embodiments are provided solely to ensure that the disclosure of the present invention is complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined solely by the scope of the claims.

[0040] When elements or layers are referred to as being "on" another element or layer, this includes both cases where the other element or layer is directly on top of the other element or layer, or where the other layer or layer is interposed therebetween. Like reference numerals refer to like elements throughout the specification. The shapes, sizes, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments are illustrative and therefore the present invention is not limited to the matters illustrated.

[0041] The individual features of the various embodiments of the present invention can be partially or fully combined or combined with one another, enabling various technically feasible interconnections and operations. Each embodiment may be implemented independently of the others, or may be implemented together in a related manner.

[0042] Specific embodiments are described below with reference to the attached drawings.

[0043] Fig. 1 is a plan view showing a display device (100) according to one embodiment. Fig. 2 is a plan view showing a display panel (110) of Fig. 1.

[0044] Referring to FIGS. 1 and 2, the display device (100) is a device that displays a moving image or a still image, and can be used as a display screen for various products such as portable electronic devices such as mobile phones, smart phones, tablet personal computers (PCs), smart watches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable multimedia players (PMPs), navigation devices, and Ultra Mobile PCs (UMPCs), as well as televisions, laptops, monitors, billboards, and Internet of Things (IOT). These are presented only as examples, and the display device (100) can also be employed in other electronic devices.

[0045] In one embodiment, the display device (100) may be a light-emitting display device such as an organic light-emitting display device including an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or an ultra-small light-emitting display device using an ultra-small light-emitting diode such as a micro or nano light emitting diode (micro LED or nano LED), but is not limited thereto. For example, the display device (100) may be a type of display device other than a light-emitting display device. Hereinafter, embodiments in which the display device (100) is an organic light-emitting display device are disclosed.

[0046] The display device (100) may include a display panel (110) including pixels (PX), and a first driving unit (120) and a second driving unit (130) that supply driving signals to the pixels (PX). The display device (100) may further include additional components. For example, the display device (100) may further include a power supply unit for supplying power voltages to the pixels (PX), the first driving unit (120) and the second driving unit (130), and a timing control unit for controlling the operations of the first driving unit (120) and the second driving unit (130).

[0047] The display panel (110) may include a display area (DA) and a non-display area (NDA) (also referred to as a "bezel area"). The display area (DA) may be an area that displays an image by including pixels (PX). The non-display area (NDA) is an area excluding the display area (DA), and an image may not be displayed in the non-display area (NDA). In one embodiment, the non-display area (NDA) may be located around the display area (DA) and may surround the display area (DA).

[0048] In FIGS. 1 and 2, a first direction (D1), a second direction (D2), and a third direction (D3) are defined. In one embodiment, the first direction (D1) and the second direction (D2) may be perpendicular to each other, the first direction (D1) and the third direction (D3) may be perpendicular to each other, and the second direction (D2) and the third direction (D3) may be perpendicular to each other. For example, the first direction (D1) may be a horizontal direction of the display panel (110) (e.g., a row direction or an X-axis direction), the second direction (D2) may be a vertical direction of the display panel (110) (e.g., a column direction or a Y-axis direction). The third direction (D3) may be a thickness direction of the display panel (110) (e.g., a height direction or a Z-axis direction).

[0049] In one embodiment, the display panel (110) may be formed in a rectangular shape on a plane. For example, the display panel (110) may include two first sides extending in a first direction (D1) and two second sides extending in a second direction (D2) intersecting the first direction (D1). In FIGS. 1 and 2 , the display panel (110) is illustrated in which the first side in the horizontal direction is longer than the second side in the vertical direction, but the shape of the display panel (110) is not limited thereto. For example, the display panel (110) may have a shape in which the second side in the vertical direction is longer than the first side in the horizontal direction, or may have a shape in which the lengths of the first side and the second side are substantially the same.

[0050] In one embodiment, the display panel (110) may include, but is not limited to, an angled corner where the first side and the second side meet. For example, the display panel (110) may also include a rounded corner where the first side and the second side meet.

[0051] The planar shape of the display panel (110) is not limited to the rectangular shape illustrated, and may be applied in other shapes. For example, the display panel (110) may have a planar square shape, a non-square polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes.

[0052] In one embodiment, the display panel (110) may be substantially flat on a plane defined by the first direction (D1) and the second direction (D2), and may have a uniform thickness in the third direction (D3). In another embodiment, the display panel (110) may be provided in a three-dimensional shape having a curved surface, etc.

[0053] The display panel (110) may be provided as a panel having rigid characteristics so as not to be substantially deformed, or may be provided as a panel having flexible characteristics so as to be deformed in a form such as by folding, bending, or rolling at least in one portion. The display panel (110) may be provided to the display device (100) in an unbent state, or may be provided to the display device (100) in a bent state in some sections.

[0054] A display panel (110) may include a substrate (SUB) and pixels (PX) arranged on the substrate (SUB). The pixels (PX) may be arranged in a display area (DA) on the substrate (SUB).

[0055] The substrate (SUB) is a base member for manufacturing or providing a display panel (110) and may constitute a base surface of the display panel (110). The substrate (SUB) may include a display area (DA) and a non-display area (NDA) located around the display area (DA).

[0056] The display area (DA) may have various shapes depending on the embodiments. For example, the display area (DA) may have a rectangular shape, a non-rectangular polygonal shape, a circular shape, an oval shape, an irregular shape, or other shapes. In one embodiment, the display area (DA) may have a shape that matches (or corresponds to) the shape of the display panel (110), but is not limited thereto.

[0057] The display area (DA) may include pixel areas in which pixels (PX) are provided and / or arranged. For example, each pixel (PX) may be arranged in a respective pixel area located in the display area (DA). In one embodiment, the display device (100) may be a light-emitting display device, and each pixel (PX) may include a light-emitting element located in each light-emitting area and a pixel circuit connected to the light-emitting element. In describing the embodiments, “connection” may include the meaning of electrical connection and / or physical connection.

[0058] Each pixel area may include a light-emitting area where the light-emitting element of the corresponding pixel is positioned and the pixel emits light, and a pixel circuit area where circuit elements constituting the pixel circuit of the corresponding pixel are positioned. In one embodiment, the light-emitting area and the pixel circuit area of ​​each pixel (PX) may overlap each other, but are not limited thereto.

[0059] Pixels (PX) can be arranged in a display area (DA). For example, pixels (PX) can be arranged in a stripe structure, a delta structure, or a pentile structure. TM The structure or other array structure may be arranged in the display area (DA).

[0060] A non-display area (NDA) may include a driving circuit area located at least on one side of a display area (DA) and a pad area (PA) where pads (PD) are arranged. At least one driving unit, pads (PD), and / or wiring may be arranged in the non-display area (NDA).

[0061] At least one driving unit, or a portion of the driving unit, for driving pixels (PX) may be disposed in the driving circuit area. For example, circuit elements constituting the first driving unit (120) may be disposed in the driving circuit area on the substrate (SUB). In one embodiment, the circuit elements of the first driving unit (120) may be formed on the display panel (110) together with the pixels (PX).

[0062] Pads (PD) may be arranged in the pad area (PA). At least one circuit board (140) may be arranged and / or bonded on the pad area (PA). In one embodiment, a plurality of circuit boards (140) connected to different pads (PD) may be arranged on the pad area (PA). The pads (PD) may include signal pads and power pads for transmitting driving signals and power voltages required for driving the pixels (PX) and / or the first driving unit (120) to the inside of the display panel (110).

[0063] The first driving unit (120) and the second driving unit (130) can generate driving signals for controlling the operation timing and brightness of the pixels (PX) and supply the driving signals to the pixels (PX). For example, the first driving unit (120) can be a gate driving unit including a scan driving unit and can be connected to the pixels (PX) through respective gate lines. The first driving unit (120) can supply respective gate signals (for example, driving signals for controlling the operation timing of the pixels (PX) including the first gate signal (GW) of FIG. 3) to the pixels (PX). The second driving unit (130) can be a data driving unit including source driving circuits and can be connected to the pixels (PX) through respective data lines. The second driving unit (130) can supply respective data signals to the pixels (PX).

[0064] In one embodiment, at least one of the first driving unit (120) and the second driving unit (130), or a portion of the at least one driving unit, may be built into the display panel (110). For example, the first driving unit (120) or a portion of the first driving unit (120) may be disposed on the substrate (SUB) of the display panel (110) and may be disposed and / or formed in a non-display area (NDA).

[0065] In Fig. 1, the first driving unit (120) is exemplified as being formed on one side of the display area (DA) (for example, the non-display area (NDA) on the right side of the display area (DA), but the embodiments are not limited thereto. For example, the first driving unit (120) may be positioned only on the other side of the display area (DA) (for example, the non-display area (NDA) on the left side of the display area (DA)) or on both sides of the display area (DA) (for example, the non-display areas (NDA) on the left and right sides of the display area (DA). Alternatively, a part of the first driving unit (120) (for example, some of the circuit elements constituting the first driving unit (120)) may be located in a non-display area (NDA), and another part of the first driving unit (120) (for example, the remaining circuit elements constituting the first driving unit (120)) may be located in a non-emitting area (for example, an area between the emitting areas of the pixels (PX)) within the display area (DA).

[0066] In one embodiment, the other of the first driving unit (120) and the second driving unit (130), or a part of the other driving unit, may be disposed or formed outside the display panel (110) and electrically connected to the display panel (110). For example, the second driving unit (130) or a part of the second driving unit (130) may be implemented with a plurality of integrated circuit chips and may be disposed on a circuit board (140) electrically connected to the pixels (PX) of the display panel (110). In one embodiment, the second driving unit (130) may be integrated with the timing controller as a separate integrated circuit chip, or may be integrated with the timing controller as a separate integrated circuit chip. The second driving unit (130) may also be implemented with at least one integrated circuit chip and mounted on a non-display area (NDA) of the display panel (110).

[0067] The circuit board (140) may be connected to the display panel (110) via pads (PD). In one embodiment, the circuit board (140) may be, but is not limited to, a flexible film such as a flexible printed circuit board (FPCB), a printed circuit board (PCB), or a chip on film (COF). In one embodiment, the circuit board (140) may be connected to a timing control unit and / or a power supply unit via another circuit board or a connector.

[0068] Fig. 3 is an equivalent circuit diagram showing a pixel (PX) according to one embodiment. The pixel (PX) of Fig. 3 is presented as only one embodiment, and the structure and type of the pixel (PX) may be varied in various ways depending on the embodiments.

[0069] In addition to FIGS. 1 and 2, referring to FIG. 3, a pixel (PX) may include a light-emitting element (ED) and a pixel circuit (PC) connected to the light-emitting element (ED). The light-emitting element (ED) is a light source of the pixel (PX), and may be, for example, an organic light-emitting diode, but is not limited thereto. The pixel circuit (PC) may control the light-emitting timing and brightness of the light-emitting element (ED).

[0070] The pixel circuit (PC) may include pixel transistors (Tpx) and at least one pixel capacitor (Cpx). For example, the pixel circuit (PC) may include first to fifth transistors (T1 to T5), and first and second capacitors (C1, C2). The structure of the pixel circuit (PC) or the types of circuit elements constituting the pixel circuit (PC) may vary depending on embodiments. Although FIG. 3 exemplifies an embodiment in which all pixel transistors (Tpx) are N-type transistors, the types of pixel transistors (Tpx) are not limited thereto. For example, at least one pixel transistor (Tpx) may be formed as a P-type transistor.

[0071] The pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to driving signals supplied from the first driving unit (120) and the second driving unit (130). For example, the pixel circuit (PC) can supply a driving current (Id) to the light-emitting element (ED) in response to each of the gate signals (GS) supplied from the first driving unit (120) through each of the gate lines (GL) and the data signal (DATA) supplied from the second driving unit (130) through the data line (DL).

[0072] The second transistor (T2) may be a driving transistor of a pixel (PX), in which the magnitude of the drain-source current (e.g., driving current (Id)) is determined according to the gate-source voltage. The first, third, fourth, and fifth transistors (T1, T3, T4, and T5) may be switching transistors that are turned on or off according to their respective gate-source voltages (substantially, their respective gate voltages). Depending on the type (e.g., P-type or N-type transistor) and / or operating conditions of each of the first to fifth transistors (T1 to T5), the first electrode of each of the first to fifth transistors (T1 to T5) may be a drain electrode (or a drain region) or a source electrode (or a source region), and the second electrode may be an electrode different from the first electrode. For example, when the first electrode is a drain electrode, the second electrode may be a source electrode.

[0073] A pixel (PX) may be connected to a first gate line (GWL) that transmits a first gate signal (GW) (e.g., a scan signal), a second gate line (GIL) that transmits a second gate signal (GI), a third gate line (GRL) that transmits a third gate signal (GR), an emission control line (ECL) that transmits an emission control signal (EM), and a data line (DL) that transmits a data signal (DATA). In addition, the pixel (PX) may be connected to a first pixel power line (VDL) that transmits a first pixel voltage (ELVDD) (also referred to as a “first pixel power voltage”), and a second pixel power line (VSL) that transmits a second pixel voltage (ELVSS) (also referred to as a “second pixel power voltage”). In one embodiment, the pixel (PX) may be further connected to an initialization power line (VIL) that carries an initialization voltage (VINT) (also referred to as a "third pixel power voltage") and a reference power line (VRL) that carries a reference voltage (VREF) (also referred to as a "fourth pixel power voltage").

[0074] In one embodiment, the first to fifth transistors (T1 to T5) may be positioned in respective pixel areas (for example, a pixel area (PXA) of a pixel (PX) provided in a display area (DA) of FIG. 6) and may be oxide transistors (also referred to as “oxide semiconductor transistors”) including an oxide semiconductor (for example, an oxide semiconductor material). For example, the active layer (also referred to as an “active pattern” or a “semiconductor pattern”) of each of the first to fifth transistors (T1 to T5) may be formed of an oxide semiconductor. However, the embodiments are not limited thereto. For example, at least one pixel transistor (Tpx) may be formed of a semiconductor material other than an oxide semiconductor (for example, amorphous silicon or polysilicon).

[0075] Oxide semiconductors have high carrier mobility (for example, high electron mobility in the case of an N-type transistor) and low leakage current, and thus, even if the driving time of the oxide transistor is long, a large voltage drop may not occur. For example, in the case of a pixel (PX) including an oxide transistor, since the brightness and / or color of the image does not change significantly due to the voltage drop even when driven at a low frequency, the pixel can be driven at a low frequency. In the case of a display device (100) in which the first to fifth pixel transistors (T1 to T5) include an oxide semiconductor, the leakage current of the pixel (PX) can be reduced or prevented and power consumption can be reduced.

[0076] Oxide semiconductors are sensitive to light, and thus, the amount of current, etc., may vary depending on external light. In one embodiment, a light-shielding pattern or a lower electrode (e.g., a bottom gate electrode) may be disposed below an active layer constituting at least one pixel transistor (Tpx) (e.g., at least one transistor among the first to fifth pixel transistors (T1 to T5)). Accordingly, the amount of current of the pixel transistor (Tpx) may be prevented or reduced due to light, and the operating characteristics of the pixel transistor (Tpx) may be stabilized.

[0077] A first transistor (T1) (also referred to as a “first pixel transistor”) may include a gate electrode connected to a first gate line (GWL), a first electrode connected to a data line (DL), and a second electrode connected to a first node (N1). The first transistor (T1) may be turned on by a first gate signal (GW) transmitted to the first gate line (GWL) (for example, a first gate signal (GW) of a gate-on voltage) to connect the data line (DL) and the first node (N1). Accordingly, a data signal (DATA) transmitted to the data line (DL) may be transmitted to the first node (N1).

[0078] A second transistor (T2) (also referred to as a “second pixel transistor”) may include a gate electrode connected to a first node (N1) (or gate node), a first electrode (e.g., a drain electrode or a drain region) connected to a second node (N2), and a second electrode (e.g., a source electrode or a source region) connected to a third node (N3). The first electrode of the second transistor (T2) may be connected to the first pixel power line (VDL) via a fifth transistor (T5), and the second electrode may be connected to the light-emitting element (ED). The second transistor (T2) may function as a driving transistor of the pixel (PX), and may control the size (e.g., the amount of current) of a driving current (Id) flowing to the light-emitting element (ED) in response to a data signal (DATA) transmitted according to a switching operation of the first transistor (T1).

[0079] In one embodiment, the second transistor (T2) may further include a bottom gate electrode (BG) (also referred to as a “back-gate electrode of the second transistor (T2)” or a “second bottom gate electrode”) connected to a third node (N3). When the bottom gate electrode (BG) of the second transistor (T2) is connected to a third node (N3) to which the second electrode (e.g., a source electrode) of the second transistor (T2) is connected, thereby forming the second transistor (T2) into a double-gate structured transistor (e.g., a double-gate transistor having a source-sink structure), the operating characteristics of the second transistor (T2) can be improved.

[0080] A third transistor (T3) (also referred to as a “third pixel transistor”) may include a gate electrode connected to a third gate line (GRL), a first electrode connected to a reference power line (VRL), and a second electrode connected to a first node (N1). The third transistor (T3) may be turned on by a third gate signal (GR) transmitted to the third gate line (GRL) and may transmit a reference voltage (VREF) transmitted to the reference power line (VRL) to the first node (N1).

[0081] A fourth transistor (T4) (also referred to as a “fourth pixel transistor”) may include a gate electrode connected to a second gate line (GIL), a first electrode connected to a third node (N3), and a second electrode connected to an initialization power line (VIL). The fourth transistor (T4) may be turned on by a second gate signal (GI) transmitted to the second gate line (GIL) and may transmit an initialization voltage (VINT) transmitted to the initialization power line (VIL) to the third node (N3).

[0082] A fifth transistor (T5) (also referred to as a “fifth pixel transistor”) may include a gate electrode connected to a light emission control line (ECL), a first electrode connected to a first pixel power line (VDL), and a second electrode connected to a second node (or, a first electrode of a second transistor (T2)). The fifth transistor (T5) may be turned on by a light emission control signal (EM) transmitted to the light emission control line (ECL) (for example, a light emission control signal (EM) of a gate-on voltage), thereby controlling a light emission timing of the pixel (PX).

[0083] The first capacitor (C1) may be connected between the first node (N1) and the third node (N3). For example, the first capacitor (C1) may be connected between the gate electrode and the second electrode of the second transistor (T2). The first capacitor (C1) may serve as a storage capacitor of the pixel (PX) and may store a voltage corresponding to the threshold voltage of the second transistor (T2) and a data signal (DATA) (e.g., a data voltage).

[0084] A second capacitor (C2) may be connected between the first pixel power line (VDL) and the third node (N3). In one embodiment, the capacitance of the second capacitor (C2) may be smaller than the capacitance of the first capacitor (C1).

[0085] The light emitting element (ED) may be connected between the third node (N3) and the second pixel power line (VSL). For example, the light emitting element (ED) may include a first electrode (e.g., an anode electrode or a pixel electrode) connected to the third node (N3), a second electrode (e.g., a cathode electrode or a counter electrode) facing the first electrode and connected to the second pixel power line (VSL), and a light emitting layer interposed between the first electrode and the second electrode. In one embodiment, the first electrode of the light emitting element (ED) may be an individual electrode individually provided to each pixel (PX), and the second electrode of the light emitting element (ED) may be a common electrode shared by a plurality of pixels (PX). The light emitting element (ED) may emit light with a brightness corresponding to the driving current (Id) during a period in which the driving current (Id) is supplied from the pixel circuit (PC).

[0086] Fig. 4 is an equivalent circuit diagram showing a pixel (PX) according to one embodiment. For example, Fig. 4 shows an additional embodiment related to switching transistors among the pixel transistors (Tpx) of Fig. 3.

[0087] In addition to FIGS. 1 to 3, referring to FIG. 4, at least one of the switching transistors provided in the pixel (PX) may include a bottom gate electrode (BG) (or back-gate electrode) facing a gate electrode (e.g., a top gate electrode) with an active layer therebetween. For example, at least one of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may include a bottom gate electrode (BG).

[0088] In Fig. 4, an embodiment is disclosed in which bottom gate electrodes (BG) are provided to each of the pixel transistors (Tpx), and reference numerals are given only to the bottom gate electrode (BG) provided to one pixel transistor (Tpx) (e.g., the second transistor (T2)). However, the embodiments are not limited thereto. For example, at least one pixel transistor (Tpx) may not include a bottom gate electrode (BG), and / or may not be formed in a gate-sync structure or a source-sync structure.

[0089] In one embodiment, the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may each include bottom gate electrodes (BG). In one embodiment, the bottom gate electrode (BG) of each of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may be connected to the gate electrode of the corresponding pixel transistor (Tpx). For example, each of the first, third, fourth, and fifth transistors (T1, T3, T4, T5) may be formed as a double gate transistor having a gate-sync structure.

[0090] By providing bottom gate electrodes (BG) to the first, third, fourth and fifth transistors (T1, T3, T4, T5), respectively, current fluctuations of the first, third, fourth and fifth transistors (T1, T3, T4, T5) due to light can be prevented or reduced. In addition, when the bottom gate electrodes (BG) of the first, third, fourth and fifth transistors (T1, T3, T4, T5) are connected to the gate electrodes (also referred to as “top gate electrodes”) of the first, third, fourth and fifth transistors (T1, T3, T4, T5), the operating characteristics (e.g., switching characteristics) of the first, third, fourth and fifth transistors (T1, T3, T4, T5) can be improved and / or stabilized. For example, by forming at least one switching transistor with a double gate structure of a gate-sink structure, the off characteristics and switching speed of the switching transistor can be improved, an additional voltage tolerance range can be secured, leakage current can be reduced, and voltage stability can be improved. For example, by forming a small-sized switching transistor formed with an oxide transistor having a short channel length with a double gate structure such as a gate-sink structure, the operating characteristics of the switching transistor can be improved.

[0091] Fig. 5 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 6 is a cross-sectional view showing a display panel (110) according to one embodiment. Fig. 5 shows a portion of a display area (DA) of a display panel (110) including a connection electrode (CNE) and a second passivation layer (PSV2), and Fig. 6 shows a portion of a display area (DA) of a display panel (110) not including a connection electrode (CNE) and a second passivation layer (PSV2).

[0092] FIGS. 5 and 6 illustrate a first transistor (T1) and a second transistor (T2) arranged in one pixel area (PXA) as examples of circuit elements that may be provided or arranged in a panel circuit layer (PCL) of a display panel (110). In addition, FIGS. 5 and 6 illustrate a light-emitting display panel including a light-emitting element (ED) (for example, an organic light-emitting diode) as an example of a display panel (110) to which embodiments may be applied. However, the type and / or structure of the display panel (110) according to the embodiments is not limited thereto. For example, the display panel (110) may include a light-emitting element of a different type and / or structure, or may be a display panel of a different type and / or structure other than a light-emitting display panel.

[0093] In addition to FIGS. 1 to 4, referring to FIGS. 5 and 6, the display panel (110) may include a substrate SUB (also referred to as a “base member” or “base layer”), a panel circuit layer PCL, a light emitting element layer LEL, and an encapsulation layer ENL. The panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be arranged or provided on the substrate SUB to overlap each other. For example, with respect to the display area DA, the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be sequentially arranged or formed on the substrate SUB along a third direction D3. However, the embodiments are not limited thereto, and the mutual positions of the panel circuit layer PCL, the light emitting element layer LEL, and the encapsulation layer ENL may be changed. For example, the panel circuit layer (PCL) and the light emitting element layer (LEL) may be integrated with each other, or the light emitting element layer (LEL) may be placed on top of the panel circuit layer (PCL).

[0094] In one embodiment, the display panel (110) may further include additional elements provided on top and / or bottom of the encapsulation layer (ENL). For example, the display panel (110) may further include at least one of a sensor layer (e.g., a touch sensor layer), an optical layer (e.g., a color filter layer and / or a wavelength conversion layer), and a protective layer (e.g., a protective film, an insulating layer, an upper substrate, and / or a window). Each of the sensor layer, the optical layer, and / or the protective layer may be provided on top of the encapsulation layer (ENL) or between the light emitting element layer (LEL) and the encapsulation layer (ENL). In one embodiment, the sensor layer, the optical layer, and / or the protective layer may be provided on the display panel (110). For example, the sensor layer, the optical layer, and / or the protective layer may be manufactured integrally with the display panel (110). In another embodiment, the sensor layer, optical layer, and / or protective layer may be manufactured separately from the display panel (110) and attached to the display panel (110) via an adhesive layer or the like.

[0095] The substrate (SUB) is a base member for forming the display panel (110), and may be a substrate (or film) having rigid or flexible characteristics. In one embodiment, the substrate (SUB) may be a substrate having rigid characteristics including an insulating material such as glass, and may not be bent. In another embodiment, the substrate (SUB) may be a flexible substrate including polyimide or another insulating material, and may be deformable by bending, folding, rolling, etc., and may or may not be bent. The type and / or material of the substrate (SUB) may vary depending on the embodiments.

[0096] The substrate (SUB) may include at least a display area (DA). In one embodiment, the display area (DA) may include pixel areas (PXA) corresponding to each pixel (PX). For example, the display area (DA) may define respective pixel areas (PXA) in which each pixel (PX) is arranged.

[0097] In one embodiment, a barrier layer (BRL) may be provided on the substrate (SUB). For example, the display panel (110) may further include a barrier layer (BRL) disposed between the substrate (SUB) and the panel circuit layer (PCL). In another embodiment, the display panel (110) may not include a barrier layer (BRL), and the panel circuit layer (PCL) may be disposed (for example, directly disposed) on the substrate (SUB).

[0098] The barrier layer (BRL) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material). The barrier layer (BRL) may protect the pixels (PX) from moisture permeating through the substrate (SUB) that is vulnerable to moisture permeation. The material of the barrier layer (BRL) may vary depending on the embodiments.

[0099] A panel circuit layer (PCL) may be arranged on one surface of a substrate (SUB) provided with a barrier layer (BRL). The panel circuit layer (PCL) may include circuit elements including pixel transistors (Tpx) and pixel capacitors (Cpx), and wires (e.g., signal lines and power lines).

[0100] The panel circuit layer (PCL) may further include insulating layers arranged on the substrate (SUB). For example, the panel circuit layer (PCL) may include a first insulating layer (INS1) (e.g., a buffer layer), a second insulating layer (INS2) (e.g., a gate insulating layer), a third insulating layer (INS3) (e.g., an interlayer insulating layer), and a first passivation layer (PSV1) (e.g., a first protective layer and / or a first planarization layer) sequentially arranged on the substrate (SUB) along a third direction (D3).

[0101] In one embodiment, the panel circuit layer (PCL) may further include a connection electrode (CNE) and a second passivation layer (PSV2) (e.g., a second protective layer and / or a second planarization layer) disposed on the first passivation layer (PSV1), as illustrated in FIG. 5. Alternatively, the panel circuit layer (PCL) may not include the connection electrode (CNE) and the second passivation layer (PSV2), as illustrated in FIG. 6. In the embodiment of FIG. 6, one electrode of the second transistor (T2) may be connected (e.g., directly connected) to one electrode of the light emitting element (ED).

[0102] In one embodiment, at least one of the first passivation layer (PSV1) and the second passivation layer (PSV2) may have a multilayer structure including an inorganic film (e.g., an inorganic insulating layer) and an organic film (e.g., an organic insulating layer). For example, the first passivation layer (PSV1) may include a first inorganic film (IOL1) and a first organic film (ORL1) sequentially disposed on a third insulating layer (INS3), and the second passivation layer (PSV2) may include a second inorganic film (IOL2) and a second organic film (ORL2) sequentially disposed on the first passivation layer (PSV1).

[0103] In one embodiment, each of the first insulating layer (INS1), the second insulating layer (INS2), the third insulating layer (INS3), the first inorganic film (IOL1), and the second inorganic film (IOL2) may include at least one inorganic insulating layer including an inorganic insulating material (e.g., silicon nitride, silicon oxide, silicon oxynitride, titanium oxide, aluminum oxide, or another inorganic insulating material).

[0104] Each of the first organic film (ORL1) and the second organic film (ORL2) may include at least one organic insulating layer including an organic insulating material (for example, an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or another organic insulating material). The surfaces (for example, upper surfaces) of the first organic film (ORL1) and the second organic film (ORL2) may be substantially flat. The types, materials, shapes, and / or structures of the insulating layers provided on the panel circuit layer (PCL) may vary depending on the embodiments.

[0105] Pixel transistors (Tpx) may be included in a pixel circuit (PC) of each pixel (PX) and may be positioned in a display area (DA). For example, a first transistor (T1) and a second transistor (T2) provided to each pixel (PX) may be positioned in each pixel area (PXA) where the corresponding pixel (PX) is positioned. In addition, at least one other pixel transistor (Tpx) and / or at least one pixel capacitor (Cpx) may be further positioned in each pixel area (PXA).

[0106] In one embodiment, at least one pixel transistor (Tpx) may include a bottom gate electrode (BG). For example, a first transistor (T1) may include a first bottom gate electrode (BG1), and a second transistor (T2) may include a second bottom gate electrode (BG2). In one embodiment, the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) may be provided or formed in the same layer (e.g., the first conductive layer (CDL1)) within the panel circuit layer (PCL).

[0107] A first transistor (T1) may include a first bottom gate electrode (BG1) disposed on a substrate (SUB), a first active layer (ACT1) (also referred to as a “first active pattern”) disposed on the first bottom gate electrode (BG1) and including a first channel region (CH1), a first drain region (DR1), and a first source region (SR1), and a first gate electrode (GE1) (hereinafter referred to as a “first top gate electrode (GE1)”) disposed on the first active layer (ACT1). The first active layer (ACT1) may be disposed on at least a portion of the first bottom gate electrode (BG1). For example, at least a portion of the first active layer (ACT1) including the first channel region (CH1) may overlap the first bottom gate electrode (BG1). A first top gate electrode (GE1) may be disposed on a portion of a first active layer (ACT1) including a first channel region (CH1), and a second insulating layer (INS2) may be disposed between the first top gate electrode (GE1) and the first active layer (ACT1).

[0108] In one embodiment, the first transistor (T1) may further include a first drain electrode (DE1) and a first source electrode (SE1) connected to different portions of the first active layer (ACT1). Alternatively, the first transistor (T1) may not include a separate drain electrode and / or source electrode, and the first drain region (DR1) and / or the first source region (SR1) of the first active layer (ACT1) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the drain electrode and / or the source electrode of the first transistor (T1).

[0109] A first bottom gate electrode (BG1) may be provided or formed on a first conductive layer (CDL1) on a substrate (SUB). In one embodiment, the first conductive layer (CDL1) may be disposed between the substrate (SUB) and the first insulating layer (INS1). For example, the first conductive layer (CDL1) may be disposed on a barrier layer (BRL) and covered by the first insulating layer (INS1).

[0110] The first bottom gate electrode (BG1) may overlap the first active layer (ACT1). For example, the first bottom gate electrode (BG1) may be disposed under the first active layer (ACT1) so as to overlap at least the first channel region (CH1). A first insulating layer (INS1) may be disposed between the first bottom gate electrode (BG1) and the first active layer (ACT1). The first bottom gate electrode (BG1) and the first active layer (ACT1) may be spaced apart from each other by a distance corresponding to the thickness of the first insulating layer (INS1). The first bottom gate electrode (BG1) may face the first top gate electrode (GE1) with the first active layer (ACT1) therebetween.

[0111] The first bottom gate electrode (BG1) may or may not be connected to another electrode of the first transistor (T1). In one embodiment, the first bottom gate electrode (BG1) may be electrically connected to the first top gate electrode (GE1) and may be utilized as a back-gate electrode for adjusting the characteristics of the first transistor (T1).

[0112] The first active layer (ACT1) may be provided or formed on a semiconductor layer (SCL) on a substrate (SUB). In one embodiment, the semiconductor layer (SCL) may be disposed on a first insulating layer (INS1) and covered by a second insulating layer (INS2).

[0113] The first active layer (ACT1) may include a first channel region (CH1) overlapping the first top gate electrode (GE1), and a first drain region (DR1) and a first source region (SR1) spaced apart from each other with the first channel region (CH1) therebetween. For example, the first drain region (DR1) and the first source region (SR1) may be located on both sides of the first channel region (CH1). The first channel region (CH1) may be a region that is not conductive and maintains semiconductor characteristics, and the first drain region (DR1) and the first source region (SR1) may be conductive regions.

[0114] The first active layer (ACT1) may overlap the first bottom gate electrode (BG1) and the first top gate electrode (GE1). For example, the first channel region (CH1) of the first active layer (ACT1) may be positioned between the first bottom gate electrode (BG1) and the first top gate electrode (GE1), and may overlap the first bottom gate electrode (BG1) and the first top gate electrode (GE1).

[0115] The first active layer (ACT1) may be covered (for example, entirely covered) by the second insulating layer (INS2). For example, the first active layer (ACT1) may be covered by the second insulating layer (INS2) except for a portion where at least one contact hole (for example, the first contact hole (CNT1) and the second contact hole (CNT2)) for connection with the first drain electrode (DE1) and / or the first source electrode (SE1) is formed. Accordingly, the amount of hydrogen flowing into (or penetrating) the first active layer (ACT1) in a process for forming a panel circuit layer (PCL) or the like can be reduced, thereby appropriately controlling the conductivity (for example, carrier concentration) of the first active layer (ACT1) and / or the formation length of the first channel region (CH1). In one embodiment, by controlling the thickness of the second insulating layer (INS2) covering a portion of the first active layer (ACT1) that does not overlap with the first top gate electrode (GE1) (for example, the first drain region (DR1) and the first source region (SR1)), the conductivity of the first active layer (ACT1) and / or the formation length of the first channel region (CH1) can be controlled. For example, by reducing the thickness of the second insulating layer (INS2) on the first drain region (DR1) and the first source region (SR1), the first drain region (DR1) and the first source region (SR1) can be controlled to be appropriately conductive without performing a separate doping process during the formation of the panel circuit layer (PCL).

[0116] In one embodiment, the first channel region (CH1) may include a lower portion adjacent to the first bottom gate electrode (BG1) (for example, a lower surface in contact with the first insulating layer (INS1)) and an upper portion adjacent to the first top gate electrode (GE1) (for example, an upper surface in contact with the second insulating layer (INS2)). The lower portion of the first channel region (CH1) may have a first length (L1), and the upper portion of the first channel region (CH1) may have a second length (L2) longer than the first length (L1). For example, on a cross-section of the first active layer (ACT1), the first channel region (CH1) may have a shape such as an inverted trapezoid in which the length (for example, the channel length) increases from the lower portion to the upper portion.

[0117] For example, the first active layer (ACT1) may have a relatively smaller length and / or area of ​​a conductive region (e.g., a first drain region (DR1) and a first source region (SR1)) in an upper portion adjacent to the first top gate electrode (GE1) than in a lower portion adjacent to the first bottom gate electrode (BG1). Accordingly, the first channel region (CH1) may have a longer length and / or area in the upper portion than in the lower portion.

[0118] Additionally, the first channel region (CH1) may have different carrier concentrations in the upper portion adjacent to the first top gate electrode (GE1) and the lower portion adjacent to the first bottom gate electrode (BG1). For example, the first channel region (CH1) may have a higher carrier concentration in the lower portion than in the upper portion.

[0119] A first top gate electrode (GE1) may be provided on a second conductive layer (CDL2) on a substrate (SUB). In one embodiment, the second conductive layer (CDL2) may be disposed on a second insulating layer (INS2) and covered by a third insulating layer (INS3).

[0120] The first top gate electrode (GE1) may be disposed on the first active layer (ACT1) so as to overlap the first channel region (CH1). The first top gate electrode (GE1) and the first active layer (ACT1) may be spaced apart from each other with a second insulating layer (INS2) interposed therebetween.

[0121] In embodiments, the second insulating layer (INS2) may have different thicknesses depending on the portion. For example, the second insulating layer (INS2) may have a first thickness (TH1) on a portion of the first active layer (ACT1) including the first channel region (CH1), and may have a second thickness (TH2) smaller than the first thickness (TH1) on the remaining portion of the first active layer (ACT1). For example, the second insulating layer (INS2) may have a first thickness (TH1) locally on a portion (the first portion of the second insulating layer (INS2)) interposed between the first channel region (CH1) and the first top gate electrode (GE1), and may have a second thickness (TH2) on the remaining portion including a portion disposed on the first source region (SR1) and the first drain region (DR1). In describing the embodiments, a portion of the second insulating layer (INS2) having a first thickness (TH1) is referred to as a first portion of the second insulating layer (INS2), and a portion of the second insulating layer (INS2) having a second thickness (TH2) is referred to as a second portion of the second insulating layer (INS2).

[0122] A first drain electrode (DE1) and a first source electrode (SE1) may be provided on a third conductive layer (CDL3) on a substrate (SUB). In one embodiment, the third conductive layer (CDL3) may be disposed on a third insulating layer (INS3).

[0123] The first drain electrode (DE1) may be connected to a portion of the first active layer (ACT1). For example, the first drain electrode (DE1) may be connected to the first drain region (DR1) by a first contact hole (CNT1) penetrating the second insulating layer (INS2) and the third insulating layer (INS3).

[0124] The first source electrode (SE1) may be connected to another portion of the first active layer (ACT1). For example, the first source electrode (SE1) may be connected to the first source region (SR1) by a second contact hole (CNT2) penetrating the second insulating layer (INS2) and the third insulating layer (INS3).

[0125] The second transistor (T2) may include a second bottom gate electrode (BG2) disposed on a substrate (SUB), a second active layer (ACT2) (also referred to as a “second active pattern”) disposed on the second bottom gate electrode (BG2) and including a second channel region (CH2), a second drain region (DR2), and a second source region (SR2), and a second gate electrode (GE2) (hereinafter referred to as a “second top gate electrode (GE2)”) disposed on the second active layer (ACT2). The second active layer (ACT2) may be disposed on at least a portion of the second bottom gate electrode (BG2). For example, at least a portion of the second active layer (ACT2) including the second channel region (CH2) may overlap the second bottom gate electrode (BG2). A second top gate electrode (GE2) may be disposed on a portion of a second active layer (ACT2) including a second channel region (CH2), and a second insulating layer (INS2) may be disposed between the second top gate electrode (GE2) and the second active layer (ACT2).

[0126] In one embodiment, the second transistor (T2) may further include a second drain electrode (DE2) and a second source electrode (SE2) connected to different portions of the second active layer (ACT2). Alternatively, the second transistor (T2) may not include a separate drain electrode and / or source electrode, and the second drain region (DR2) and / or the second source region (SR2) of the second active layer (ACT2) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the drain electrode and / or the source electrode of the second transistor (T2).

[0127] The second bottom gate electrode (BG2) may be provided or formed on the first conductive layer (CDL1) on the substrate (SUB). For example, the second bottom gate electrode (BG2) may be provided on the first conductive layer (CDL1) together with the first bottom gate electrode (BG1).

[0128] The second bottom gate electrode (BG2) may overlap the second active layer (ACT2). For example, the second bottom gate electrode (BG2) may be disposed under the second active layer (ACT2) so as to overlap at least the second channel region (CH2). A first insulating layer (INS1) may be disposed between the second bottom gate electrode (BG2) and the second active layer (ACT2). The second bottom gate electrode (BG2) and the second active layer (ACT2) may be spaced apart from each other by a distance corresponding to the thickness of the first insulating layer (INS1). The second bottom gate electrode (BG2) may face the second top gate electrode (GE2) with the second active layer (ACT2) therebetween.

[0129] The second bottom gate electrode (BG2) may or may not be connected to one electrode of the second transistor (T2). In one embodiment, the second bottom gate electrode (BG2) may be connected to the second source electrode (SE2) of the second transistor (T2) and may be utilized as a back-gate electrode for adjusting the characteristics of the second transistor (T2).

[0130] The second active layer (ACT2) may be provided or formed on a semiconductor layer (SCL) on a substrate (SUB). In one embodiment, the first active layer (ACT1) and the second active layer (ACT2) may be provided and / or disposed on the same layer (e.g., the same semiconductor layer (SCL)) on the substrate (SUB) and may include the same oxide semiconductor.

[0131] The second active layer (ACT2) may include a second channel region (CH2) overlapping the second top gate electrode (GE2), and a second drain region (DR2) and a second source region (SR2) spaced apart from each other with the second channel region (CH2) therebetween. For example, the second drain region (DR2) and the second source region (SR2) may be located on both sides of the second channel region (CH2). The second channel region (CH2) may be a region that is not conductive and maintains semiconductor characteristics, and the second drain region (DR2) and the second source region (SR2) may be conductive regions.

[0132] The second active layer (ACT2) may overlap the second bottom gate electrode (BG2) and the second top gate electrode (GE2). For example, the second channel region (CH2) of the second active layer (ACT2) may be positioned between the second bottom gate electrode (BG2) and the second top gate electrode (GE2), and may overlap the second bottom gate electrode (BG2) and the second top gate electrode (GE2).

[0133] The second active layer (ACT2) may be covered (for example, entirely covered) by the second insulating layer (INS2). For example, the second active layer (ACT2) may be covered by the second insulating layer (INS2) except for a portion where at least one contact hole (for example, the third contact hole (CNT3) and the fourth contact hole (CNT4)) for connection with the second drain electrode (DE2) and / or the second source electrode (SE2) is formed. Accordingly, the amount of hydrogen flowing into (or penetrating) the second active layer (ACT2) in a process for forming a panel circuit layer (PCL) or the like can be reduced, thereby appropriately controlling the conductivity (for example, carrier concentration) of the second active layer (ACT2) and / or the formation length of the second channel region (CH2). In one embodiment, the conductivity of the second active layer (ACT2) and / or the formation length of the second channel region (CH2) can be controlled by controlling the thickness of the second insulating layer (INS2) covering a portion of the second active layer (ACT2) that does not overlap the second top gate electrode (GE2) (for example, the second drain region (DR2) and the second source region (SR2)).

[0134] In one embodiment, the second channel region (CH2) may include a lower portion (e.g., a lower surface in contact with the first insulating layer (INS1)) adjacent to the second bottom gate electrode (BG2) and an upper portion adjacent to the second top gate electrode (GE2). The upper portion of the second channel region (CH2) may have a longer length than the lower portion of the second channel region (CH2). For example, on a cross-section of the second active layer (ACT2), the second channel region (CH2) may have a shape such as an inverted trapezoid in which the length (e.g., the channel length) increases from the lower portion to the upper portion.

[0135] For example, the second active layer (ACT2) may have a relatively smaller length and / or area of ​​a conductive region (e.g., a second drain region (DR2) and a second source region (SR2)) in an upper portion adjacent to the second top gate electrode (GE2) than in a lower portion adjacent to the second bottom gate electrode (BG2). Accordingly, the second channel region (CH2) may have a longer length and / or area in the upper portion than in the lower portion.

[0136] Additionally, the second channel region (CH2) may have different carrier concentrations in the upper portion adjacent to the second top gate electrode (GE2) and the lower portion adjacent to the second bottom gate electrode (BG2). For example, the second channel region (CH2) may have a higher carrier concentration in the lower portion than in the upper portion.

[0137] The second top gate electrode (GE2) may be provided or formed on the second conductive layer (CDL2) on the second insulating layer (INS2). For example, the second top gate electrode (GE2) may be provided and / or disposed on the same layer as the first top gate electrode (GE1) on the substrate (SUB).

[0138] The second top gate electrode (GE2) may be disposed on the second active layer (ACT2) so as to overlap the second channel region (CH2). The second top gate electrode (GE2) and the second active layer (ACT2) may be spaced apart from each other with a second insulating layer (INS2) interposed therebetween.

[0139] In one embodiment, the second insulating layer (INS2) may have different thicknesses in different portions on the second active layer (ACT2). For example, the second insulating layer (INS2) may have a relatively large thickness on a portion of the second active layer (ACT2) including the second channel region (CH2), and a relatively small thickness on the remaining portion of the second active layer (ACT2). For example, the second insulating layer (INS2) may have a first thickness (TH1) locally in a portion interposed between the second channel region (CH2) and the second top gate electrode (GE2), and a second thickness (TH2) in the remaining portion including a portion disposed on the second source region (SR2) and the second drain region (DR2).

[0140] In one embodiment, the second insulating layer (INS2) may be formed over the entire pixel area (PXA) and / or the display area (DA) including the pixel area (PXA) to cover the active layers of the pixel transistors (Tpx) provided on the semiconductor layer (SCL).

[0141] In one embodiment, the second insulating layer (INS2) may be patterned using the same mask as the mask used in the step of patterning the top gate electrodes (e.g., top gate electrodes of transistors provided in the panel circuit layer (PCL), including pixel transistors (Tpx)) provided or formed in the second conductive layer (CDL2), including the first top gate electrode (GE1) and the second top gate electrode (GE1), or may be etched (e.g., half-etched) to a certain thickness in a portion that does not overlap with the top gates of the transistors by using the top gate electrodes as a mask. Accordingly, the second insulating layer (INS2) may have different thicknesses in a first portion that overlaps with the top gates of the transistors and a second portion corresponding to the remaining portion.

[0142] In addition, the second insulating layer (INS2) may have a pattern shape and / or size corresponding to each top gate electrode at an upper portion (for example, an upper surface of the first portion having the first thickness (TH1)) in contact with each top gate electrode. For example, the second insulating layer (INS2) may have a pattern shape substantially the same as that of the first top gate electrode (GE1) at an upper portion in contact with the first top gate electrode (GE1) (for example, the same pattern shape as that of the lower surface of the first top gate electrode (GE1)), and may have an area substantially the same as that of the first top gate electrode (GE1) (for example, the same area as that of the lower surface of the first top gate electrode (GE1). Accordingly, an abrupt change in length or width may not occur at the boundary between the first top gate electrode (GE1) and the second insulating layer (INS2), and a side surface of the first top gate electrode (GE1) and a side surface of the second insulating layer (INS2) may have a continuously connected inclined surface. For example, the side surface of the first top gate electrode (GE1) and the side surface of the second insulating layer (INS2) may be on the same plane. The second insulating layer (INS2) may have a pattern shape substantially the same as that of the second top gate electrode (GE2) at an upper portion in contact with the second top gate electrode (GE2) (for example, the same pattern shape as that of the lower surface of the second top gate electrode (GE2)) and may have an area substantially the same as that of the second top gate electrode (GE2) (for example, the same area as that of the lower surface of the second top gate electrode (GE2). Accordingly, an abrupt change in length or width may not occur at the boundary between the second top gate electrode (GE2) and the second insulating layer (INS2), and the side surface of the second top gate electrode (GE2) and the side surface of the second insulating layer (INS2) may have a continuously connected inclined surface. For example, the side surface of the second top gate electrode (GE2) and the side surface of the second insulating layer (INS2) may be on the same plane.

[0143] In one embodiment, the second insulating layer (INS1) may be formed in a form that is etched to a certain thickness (e.g., a half-etched form) in a second portion excluding the first portion under each top gate electrode, and may have a step-shaped step portion at the boundary between the first portion and the second portion. The second conductive layer (CDL2) including the first top gate electrode (GE1) and the second top gate electrode (GE2) and the second insulating layer (INS2) may be covered with a third insulating layer (INS3).

[0144] The second drain electrode (DE2) and the second source electrode (SE2) may be provided or formed on the third conductive layer (CDL3) on the substrate (SUB). For example, the second drain electrode (DE2) and the second source electrode (SE2) may be disposed on the third insulating layer (INS3) and covered by the first passivation layer (PSV1).

[0145] The second drain electrode (DE2) may be connected to a portion of the second active layer (ACT2). For example, the second drain electrode (DE2) may be connected to the second drain region (DR2) by a third contact hole (CNT3) penetrating the second insulating layer (INS2) and the third insulating layer (INS3).

[0146] The second source electrode (SE2) may be connected to another portion of the second active layer (ACT2). For example, the second source electrode (SE2) may be connected to the second source region (SR2) by a fourth contact hole (CNT4) penetrating the second insulating layer (INS2) and the third insulating layer (INS3). In one embodiment, the second source electrode (SE2) may be further connected to the second bottom gate electrode (BG2). For example, the second source electrode (SE2) may be connected to the second bottom gate electrode (BG2) by a fifth contact hole (CNT5) penetrating the first insulating layer (INS1), the second insulating layer (INS2), and the third insulating layer (INS3).

[0147] The pixel transistors (Tpx) including the first transistor (T1) and the second transistor (T2) may be covered by at least one passivation layer. For example, the pixel transistors (Tpx) may be covered by the first passivation layer (PSV1) and the second passivation layer (PSV2) as illustrated in FIG. 5, or may be covered by the first passivation layer (PSV1) as illustrated in FIG. 6.

[0148] In the embodiment of FIG. 5, the second transistor (T2) of each pixel (PX) may be connected to the light emitting element (ED) of the corresponding pixel (PX) via a connection electrode (CNE). The connection electrode (CNE) may be provided or formed on a fourth conductive layer (CDL4) on a substrate (SUB). In one embodiment, the fourth conductive layer (CDL4) may be disposed on the first passivation layer (PSV1) and covered by the second passivation layer (PSV2). For example, the fourth conductive layer (CDL4) may be disposed between the first passivation layer (PSV1) and the second passivation layer (PSV2). When the display panel (110) further includes the fourth conductive layer (CDL4), the number of conductive layers provided on the display panel (110) may increase. Accordingly, sufficient design space can be secured for forming various conductive patterns (e.g., electrodes and / or bridge patterns) or wirings within the display panel (110). Accordingly, even when forming the display panel (110) with a high resolution, pixel circuits (PC) and wirings can be easily and / or appropriately formed.

[0149] The connecting electrode (CNE) may be connected to one electrode of the second transistor (T2). For example, the connecting electrode (CNE) may be disposed on the second source electrode (SE2) and connected to the second source electrode (SE2) through at least one contact hole or via hole penetrating the first passivation layer (PSV1).

[0150] In the embodiment of FIG. 6, the second transistor (T2) of each pixel (PX) can be connected to the light-emitting element (ED) of the corresponding pixel (PX) without going through the connection electrode (CNE). For example, the second source electrode (SE2) of each pixel (PX) can be directly connected to the light-emitting element (ED) of the corresponding pixel (PX).

[0151] Each of the electrodes, conductive patterns and / or wires provided or formed on the conductive layers of the panel circuit layer (PCL) may include at least one conductive material, and may each have a single-layer or multi-layer structure. For example, the electrodes, conductive patterns and / or wires provided or formed on each of the first conductive layer (CDL1), the second conductive layer (CDL2), the third conductive layer (CDL3) and the fourth conductive layer (CDL4) may include at least one of copper (Cu), titanium (Ti), molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), silver (Ag), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir), tantalum (Ta), tungsten (W), magnesium (Mg), and other metals, alloys thereof, or other conductive materials, and may each have a single-layer or multi-layer structure. In one embodiment, electrodes, conductive patterns and / or wires disposed on the same conductive layer can be formed simultaneously using the same conductive material.

[0152] In one embodiment, the active layers provided or formed on the semiconductor layer (SCL) may include oxide semiconductors. For example, each of the first active layer (ACT1) and the second active layer (ACT2) may include at least one of zinc oxide (ZnO), zinc-tin oxide (ZTO), indium-zinc oxide (IZO), indium oxide (InO), titanium oxide (TiO), indium-gallium oxide (IGO), indium-gallium-zinc oxide (IGZO), indium-gallium-tin oxide (IGTO), indium-zinc-tin oxide (IZTO), and indium-tin-gallium-zinc oxide (ITGZO), or other oxide semiconductors. The oxide semiconductors used in forming the oxide transistors, including the first transistor (T1) and the second transistor (T2), are not limited to the materials exemplified above, and may vary depending on embodiments.

[0153] In one embodiment, the active layers provided or formed on the same semiconductor layer (SCL) may include the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2) may be formed simultaneously using the same oxide semiconductor.

[0154] In one embodiment, the active layers of the pixel transistors (Tpx) are formed of a high-mobility oxide semiconductor (e.g., a high electron concentration high mobility (e.g., approximately 50 cm)), such as indium-tin-gallium-zinc oxide (ITGZO) or indium-gallium oxide (IGO). 2 / Vs or higher mobility) of the oxide semiconductor). When the pixel transistors (Tpx) are formed with a high-mobility oxide semiconductor, each transistor can be formed in a fine size (for example, a size including an active layer having a width and / or length in the range of approximately several micrometers to several tens of micrometers) while appropriately securing the mobility of each transistor. Accordingly, even in a high-resolution display device with a relatively narrow pixel area (PXA), the pixel transistors (Tpx) can be easily arranged and / or formed, and the device characteristics and / or operating characteristics of the pixel transistors (Tpx) can be appropriately secured. For example, even if the channel length of at least one switching transistor provided in the pixel (PX) is reduced, the operating characteristics (for example, appropriate switching characteristics) of the switching transistor can be secured. Accordingly, the area occupied by the pixel transistors (Tpx) can be appropriately and / or easily reduced, and design space for other circuit elements or wiring can be secured. In addition, by forming pixel transistors (Tpx) with high-mobility oxide semiconductors, the power consumption of the display device (100) can be reduced.

[0155] The light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) and can be located in the display area (DA). For example, the light emitting element layer (LEL) can be disposed on the panel circuit layer (PCL) in the display area (DA).

[0156] The light emitting element layer (LEL) may include light emitting elements (ED) of the pixels (PX). For example, the light emitting element layer (LEL) may include a pixel defining layer (PDL) (also referred to as a “bank”) that partitions or defines a light emitting area of ​​each of the pixels (PX) and a light emitting element (ED) positioned in each light emitting area. In one embodiment, the light emitting element layer (LEL) may further include a spacer (SPC) disposed on a portion of the pixel defining layer (PDL).

[0157] Each light emitting element (ED) may include a first electrode (ET1) (e.g., an anode electrode) connected to at least one pixel transistor (Tpx) (e.g., a second transistor (T2)) included in a corresponding pixel (PX), and an emission layer (EML) and a second electrode (ET2) (e.g., a cathode electrode) sequentially disposed on the first electrode (ET1). In one embodiment, the light emitting element (ED) may further include a first intermediate layer (e.g., a hole layer including a hole transport layer) interposed between the first electrode (ET1) and the emission layer (EML), and a second intermediate layer (e.g., an electron layer including an electron transport layer) interposed between the emission layer (EML) and the second electrode (ET2).

[0158] A first electrode (ET1) of a light emitting element (ED) may be disposed on a panel circuit layer (PCL). In the embodiment of FIG. 5, the first electrode (ET1) may be disposed on a second passivation layer (PSV2) corresponding to each light emitting region, and may be connected to a connection electrode (CNE) through at least one contact hole or via hole penetrating the second passivation layer (PSV2). In the embodiment of FIG. 6, the first electrode (ET1) may be disposed on a first passivation layer (PSV1) corresponding to each light emitting region, and may be directly connected to at least one pixel transistor (Tpx).

[0159] The first electrode (ET1) may include a conductive material. In one embodiment, the first electrode (ET1) may include a metal material having high reflectivity. For example, the first electrode (ET1) may have a single-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or a multi-layer structure (e.g., ITO / Mg, ITO / MgF, ITO / Ag, ITO / Ag / ITO, etc.) including indium-tin-oxide (ITO), indium-zinc-oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), and silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), gold (Au), or nickel (Ni).

[0160] An emission layer (EML) of a light-emitting element (ED) may include a polymer material or a low-molecular material. Light emitted from the emission layer (EML) may contribute to image display. In one embodiment, the emission layer (EML) may be provided for each pixel (PX), and the emission layer (EML) of each pixel (PX) may emit visible light of a color corresponding to the pixel (PX). In another embodiment, the emission layer (EML) may be a common layer shared by pixels (PX) of different colors, and wavelength conversion layers and / or color filters corresponding to the color (or wavelength band) of light to be emitted from each pixel (PX) may be arranged in emission areas of at least some of the pixels (PX).

[0161] The second electrode (ET2) of the light emitting element (ED) may include a conductive material. In one embodiment, the second electrode (ET2) may be a common film formed over the entire display area (DA) in a form that covers the light emitting layer (EML) and the pixel defining layer (PDL). In one embodiment, the second electrode (ET2) may be made of a transparent conductive material (TCO: Transparent Conductive Material) such as ITO, IZO, ZnO, ITZO, etc. that can transmit light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of magnesium (Mg) and silver (Ag).

[0162] The pixel defining layer (PDL) has an opening corresponding to each light-emitting area and can surround the light-emitting area. For example, the pixel defining layer (PDL) can be formed to cover an edge of a first electrode (ET1) of a light-emitting element (ED) and can include an opening that exposes the remaining portion of the first electrode (ET1). An area where the exposed first electrode (ET1) and the light-emitting layer (EML) overlap (or an area including the first electrode) can be defined as the light-emitting area of ​​each pixel (PX).

[0163] In one embodiment, the pixel defining layer (PDL) may include at least one organic insulating layer including an organic insulating material. For example, the pixel defining layer (PDL) may include an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, an unsaturated polyester resin, a polyphenylene ether resin, a polyphenylene sulfide resin, or a benzocyclobutene (BCB), or other organic insulating materials.

[0164] A spacer (SPC) may be disposed on a portion of a pixel defining layer (PDL). The spacer (SPC) may include at least one organic insulating layer including an organic insulating material. The spacer (SPC) may include the same material as the pixel defining layer (PDL) or a different material from the pixel defining layer (PDL). In one embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be sequentially formed through separate mask processes. In another embodiment, the pixel defining layer (PDL) and the spacer (SPC) may be simultaneously formed using a halftone mask. In this case, the pixel defining layer (PDL) and the spacer (SPC) may also be viewed as a single insulating film that is integral with each other.

[0165] An encapsulation layer (ENL) may be disposed on the light emitting element layer (LEL). The encapsulation layer (ENL) may cover the light emitting element layer (LEL) in the display area (DA) and extend to the non-display area (NDA) to be in contact with the panel circuit layer (PCL). For example, the encapsulation layer (ENL) may be disposed in the display area (DA) to cover the light emitting element layer (LEL), and an end of the encapsulation layer (ENL) may be located in a part of the non-display area (NDA) adjacent to the display area (DA). The encapsulation layer (ENL) may block the penetration of oxygen or moisture into the light emitting element layer (LEL), and may alleviate or reduce electrical and / or physical impacts on the panel circuit layer (PCL) and the light emitting element layer (LEL).

[0166] In one embodiment, the encapsulation layer (ENL) may have a multilayer structure including a first encapsulation layer (ENL1), a second encapsulation layer (ENL2), and a third encapsulation layer (ENL3) sequentially arranged on the light emitting element layer (LEL). Each of the first encapsulation layer (ENL1) and the third encapsulation layer (ENL3) may be an inorganic encapsulation layer including an inorganic material. The second encapsulation layer (ENL2) may be an organic encapsulation layer including an organic material. The structure and / or material of the encapsulation layer (ENL) may vary depending on the embodiments.

[0167] Fig. 7 is a cross-sectional view showing a display panel (110) according to one embodiment. For example, Fig. 7 shows a portion of a display area (DA) and a non-display area (NDA) of the display panel (110). Fig. 7 shows a first transistor (T1) and a second transistor (T2) according to the embodiment of Fig. 5 as examples of circuit elements that may be provided or arranged in the display area (DA) of the panel circuit layer (PCL), and shows one of the driving transistors (Tdr) provided or arranged in the driving circuit area (DRA) as an example of additional circuit elements that may be provided in the panel circuit layer (PCL).

[0168] In addition to FIGS. 1 to 6, referring to FIG. 7, the display panel (110) may further include driving transistors (Tdr) arranged in the driving circuit area (DRA). For example, the display panel (110) may further include a plurality of driving transistors (Tdr) arranged in the driving circuit area (DRA) provided to the first driving unit (120) and corresponding to a portion of the non-display area (NDA). In FIG. 7, only one driving transistor (Tdr) is shown as a representative of the driving transistors (Tdr).

[0169] The substrate (SUB) and the display panel (110) including the substrate (SUB) may include a display area (DA) and a non-display area (NDA). In one embodiment, the non-display area (NDA) may include a driving circuit area (DRA). For example, a driving circuit area (DRA) in which a first driving unit (120) is arranged may be defined in the non-display area (NDA).

[0170] The panel circuit layer (PCL) may further include driver transistors (Tdr) in addition to pixel transistors (Tpx). The driver transistors (Tdr) may be arranged in stage areas (e.g., each stage area in which stage circuits of a shift register constituting the first driver (120) are provided) located in the driver circuit area (DRA).

[0171] In one embodiment, at least one driver transistor (Tdr) may be a double-gate structure transistor including a bottom gate electrode (BG). In describing the embodiments, the bottom gate electrode (BG) provided to the driver transistor (Tdr) will be referred to as a “third bottom gate electrode (BG3).” In one embodiment, the third bottom gate electrode (BG3) provided to at least one driver transistor (Tdr) may be connected to another electrode (for example, a gate electrode) of the corresponding driver transistor (Tdr).

[0172] However, the embodiments are not limited thereto. For example, the driver transistors (Tdr) may not include respective bottom gate electrodes (BG).

[0173] The driving transistor (Tdr) may include a third bottom gate electrode (BG3) disposed on a substrate (SUB), a third active layer (ACT3) (also referred to as a “third active pattern”) disposed on a first insulating layer (INS1) on the third bottom gate electrode (BG3) and including a third channel region (CH3), a third drain region (DR3), and a third source region (SR3), and a third gate electrode (GE3) (hereinafter referred to as a “third top gate electrode (GE3)”) disposed on a second insulating layer (INS2) on the third active layer (ACT3). The third active layer (ACT3) may be disposed on at least a portion of the third bottom gate electrode (BG3). For example, at least a portion of the third active layer (ACT3) including the third channel region (CH3) may overlap the third bottom gate electrode (BG3). The third top gate electrode (GE3) may be disposed on a portion of the third active layer (ACT3) including the third channel region (CH3).

[0174] In one embodiment, the driver transistor (Tdr) may further include a third drain electrode (DE3) and a third source electrode (SE3) connected to different portions of the third active layer (ACT3). Alternatively, the driver transistor (Tdr) may not include a separate drain electrode and / or source electrode, and the third drain region (DR3) and / or the third source region (SR3) of the third active layer (ACT3) may be connected to other circuit elements, wiring, and / or conductive patterns, etc., to function as the drain electrode and / or the source electrode of the driver transistor (Tdr).

[0175] The third bottom gate electrode (BG3) may be provided or formed on the first conductive layer (CDL1) on the substrate (SUB). For example, the third bottom gate electrode (BG3) may be provided on the first conductive layer (CDL1) together with the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2).

[0176] The third bottom gate electrode (BG3) may overlap the third active layer (ACT3). For example, the third bottom gate electrode (BG3) may be disposed under the third active layer (ACT3) so as to overlap at least the third channel region (CH3). A first insulating layer (INS1) may be disposed between the third bottom gate electrode (BG3) and the third active layer (ACT3). The third bottom gate electrode (BG3) and the third active layer (ACT3) may be spaced apart from each other by a distance corresponding to the thickness of the first insulating layer (INS1). The third bottom gate electrode (BG3) may face the third top gate electrode (GE3) with the third active layer (ACT3) therebetween.

[0177] The third bottom gate electrode (BG3) may or may not be connected to one electrode of the driver transistor (Tdr). In one embodiment, the third bottom gate electrode (BG3) may be connected to the third top gate electrode (GE3) of the driver transistor (Tdr) and may be utilized as a back gate electrode for adjusting the characteristics of the driver transistor (Tdr).

[0178] The third active layer (ACT3) may be provided or formed on the semiconductor layer (SCL) on the substrate (SUB). In one embodiment, the first active layer (ACT1), the second active layer (ACT2), and the third active layer (ACT3) may be provided and / or disposed on the same layer (e.g., the same semiconductor layer (SCL)) on the substrate (SUB).

[0179] In one embodiment, the third active layer (ACT3) includes the same oxide semiconductor as the first active layer (ACT1) and / or the second active layer (ACT2) and may be formed simultaneously with the first active layer (ACT1) and / or the second active layer (ACT2). For example, the first active layer (ACT1), the second active layer (ACT2), and the third active layer (ACT3) may include the same oxide semiconductor.

[0180] The third active layer (ACT3) may include a third channel region (CH3) overlapping the third top gate electrode (GE3), and a third drain region (DR3) and a third source region (SR3) spaced apart from each other with the third channel region (CH3) interposed therebetween. For example, the third drain region (DR3) and the third source region (SR3) may be located on both sides of the third channel region (CH3). The third channel region (CH3) may be a region that is not conductive and maintains semiconductor characteristics, and the third drain region (DR3) and the third source region (SR3) may be conductive regions.

[0181] The third active layer (ACT3) may overlap with the third bottom gate electrode (BG3) and the third top gate electrode (GE3). For example, the third channel region (CH3) of the third active layer (ACT3) may be positioned between the third bottom gate electrode (BG3) and the third top gate electrode (GE3), and may overlap with the third bottom gate electrode (BG3) and the third top gate electrode (GE3).

[0182] The third active layer (ACT3) may be covered (for example, entirely covered) by the second insulating layer (INS2). For example, the third active layer (ACT3) may be covered by the second insulating layer (INS2) except for a portion where at least one contact hole (for example, the sixth contact hole (CNT6) and the seventh contact hole (CNT7)) for connection with the third drain electrode (DE2) and / or the third source electrode (SE3) is formed. Accordingly, the amount of hydrogen flowing into (or penetrating) the third active layer (ACT3) during the forming process of the panel circuit layer (PCL) may be reduced, thereby appropriately controlling the conductivity of the third active layer (ACT3) and / or the forming length of the third channel region (CH3). In one embodiment, the conductivity of the third active layer (ACT3) and / or the formation length of the third channel region (CH3) can be controlled by controlling the thickness of the second insulating layer (INS2) covering a portion of the third active layer (ACT3) that does not overlap with the third top gate electrode (GE3) (e.g., the third drain region (DR2) and the third source region (SR3)).

[0183] In one embodiment, the third channel region (CH3) may include a lower portion (e.g., a lower surface in contact with the first insulating layer (INS1)) adjacent to the third bottom gate electrode (BG3) and an upper portion adjacent to the third top gate electrode (GE3). The upper portion of the third channel region (CH3) may have a longer length than the lower portion of the third channel region (CH3). For example, on a cross-section of the third active layer (ACT3), the third channel region (CH3) may have a shape such as an inverted trapezoid in which the length (e.g., the channel length) increases from the lower portion to the upper portion.

[0184] For example, the third active layer (ACT3) may have a relatively smaller length and / or area of ​​a conductive region (e.g., a third drain region (DR3) and a third source region (SR3)) in an upper portion adjacent to the third top gate electrode (GE3) than in a lower portion adjacent to the third bottom gate electrode (BG3). Accordingly, the third channel region (CH3) may have a longer length and / or area in the upper portion than in the lower portion.

[0185] Additionally, the third channel region (CH3) may have different carrier concentrations in the upper portion adjacent to the third top gate electrode (GE3) and the lower portion adjacent to the third bottom gate electrode (BG3). For example, the third channel region (CH3) may have a higher carrier concentration in the lower portion than in the upper portion.

[0186] The third top gate electrode (GE3) may be provided on the second conductive layer (CDL2) on the substrate (SUB). In one embodiment, the first top gate electrode (GE1), the second top gate electrode (GE2), and the third top gate electrode (GE3) may be provided and / or arranged on the same layer on the substrate (SUB) and may be formed simultaneously.

[0187] The third top gate electrode (GE3) may be positioned on the third active layer (ACT3) so as to overlap the third channel region (CH3). The third top gate electrode (GE3) and the third active layer (ACT3) may be spaced apart from each other with the second insulating layer (INS2) interposed therebetween.

[0188] In one embodiment, the second insulating layer (INS2) may have different thicknesses in different portions on the third active layer (ACT3). For example, the second insulating layer (INS2) may have a relatively large thickness on a portion of the third active layer (ACT3) including the third channel region (CH3), and a relatively small thickness on the remaining portion of the third active layer (ACT3). For example, the second insulating layer (INS2) may have a first thickness (TH1) locally in a portion interposed between the third channel region (CH3) and the third top gate electrode (GE3), and a second thickness (TH2) in the remaining portion including a portion disposed on the third source region (SR3) and the third drain region (DR3).

[0189] In one embodiment, the second insulating layer (INS2) can be formed over the entire display area (DA) and the driving circuit area (DRA) to cover the active layers of the pixel transistors (Tpx) and the driving transistors (Tdr) provided on the semiconductor layer (SCL).

[0190] In one embodiment, the second insulating layer (INS2) may be etched to a certain thickness in a portion that does not overlap with the top gates of the transistors by using the same mask as the mask used in the step of patterning the top gate electrodes provided in the second conductive layer (CDL2) (for example, the top gate electrodes of the transistors provided in the panel circuit layer (PCL), including the pixel transistors (Tpx) and the driver transistors (Tdr)) or by using the top gate electrodes as a mask. Accordingly, the second insulating layer (INS2) may have different thicknesses in a first portion that overlaps with the top gates of the transistors and a second portion corresponding to the remaining portion.

[0191] In addition, the second insulating layer (INS2) may have a pattern shape and / or size corresponding to each top gate electrode at an upper portion in contact with each top gate electrode. For example, the second insulating layer (INS2) may have a pattern shape substantially the same as that of the third top gate electrode (GE3) at an upper portion in contact with the third top gate electrode (GE3) (for example, the same pattern shape as that of the lower surface of the third top gate electrode (GE3)), and may have an area substantially the same as that of the third top gate electrode (GE3) (for example, the same area as that of the lower surface of the third top gate electrode (GE3). Accordingly, an abrupt change in length or width may not occur at the boundary between the third top gate electrode (GE3) and the second insulating layer (INS2), and the side surface of the third top gate electrode (GE3) and the side surface of the second insulating layer (INS2) may have a continuously connected inclined surface. For example, the side surface of the third top gate electrode (GE3) and the side surface of the second insulating layer (INS2) may be in the same plane.

[0192] The third drain electrode (DE3) and the third source electrode (SE3) may be provided on the third conductive layer (CDL3) on the substrate (SUB). In one embodiment, the third drain electrode (DE3) and the third source electrode (SE3) may be disposed on the same layer as the first and second drain electrodes (DE1, DE2) and the first and second source electrodes (SE1, SE2) on the substrate (SUB). For example, the third drain electrode (DE3) and the third source electrode (SE3) may be disposed on the third insulating layer (INS3) and may be covered by the first passivation layer (PSV1).

[0193] The third drain electrode (DE3) may be connected to a portion of the third active layer (ACT3). For example, the third drain electrode (DE3) may be connected to the third drain region (DR3) via a sixth contact hole (CNT6) penetrating the third insulating layer (INS3).

[0194] The third source electrode (SE3) may be connected to another portion of the third active layer (ACT3). For example, the third source electrode (SE3) may be connected to the third source region (SR3) via a seventh contact hole (CNT7) penetrating the third insulating layer (INS3).

[0195] The transistors provided in the panel circuit layer (PCL) may be covered by at least a first passivation layer (PSV1). For example, the pixel transistors (Tpx) and the driver transistors (Tdr) may be covered by the first passivation layer (PSV1) and the second passivation layer (PSV2).

[0196] FIGS. 8A and 8B are graphs showing the effective channel length of a channel region formed in a transistor according to the etching degree of the gate insulating layer. For example, FIGS. 8A and 8B show the carrier concentration measured in the channel region and the effective channel length according to the carrier concentration measured in the channel region according to the etching degree of the gate insulating layer in a transistor having a gate-sink structure (for example, a double-gate structure transistor in which a bottom gate electrode is connected to a top gate electrode) having a channel region length of 2.5 μm. The gate insulating layer of FIGS. 8A and 8B may be an element corresponding to the second insulating layer (INS2) disclosed in the embodiments of FIGS. 5 to 7.

[0197] In addition to FIGS. 1 to 7, referring to FIGS. 8A and 8B, the effective channel length of the channel region formed in the transistor may vary depending on the degree of etching of the gate insulating layer. For example, FIG. 8A shows the measured carrier concentration in the channel region and the resulting effective channel length in a transistor having a gate-sink structure in which the gate insulating layer is etched by its entire thickness on the drain region and source region to expose the drain region and the source region except for the channel region of the active layer. In contrast, FIG. 8B shows the measured carrier concentration in the channel region and the resulting effective channel length in a transistor having a gate-sink structure in which the gate insulating layer is etched by only a portion of the thickness on the drain region and source region as in the embodiments of FIGS. 5 to 7 so that the active layer is covered (for example, completely covered) by the gate insulating layer. In FIGS. 8A and 8B, the numerical values ​​on the horizontal axis are intended to indicate positions in the channel region, where a point corresponding to 0 may be the starting point of the channel region, and a point corresponding to 2.5 may be the ending point of the channel region. For example, a 2.5 μm section between the point marked 0 and the point marked 2.5 on the horizontal axis may correspond to the channel region. In Figures 8a and 8b, the vertical axis represents the concentration of electrons (n) corresponding to carriers.

[0198] Comparing FIGS. 8A and 8B, by etching only a portion of the gate insulating layer instead of etching the entire thickness, the length of the effective channel formed in the channel region of the transistor can be expanded. For example, in a transistor in which the gate insulating layer is etched to the entire thickness, the amount of hydrogen that excessively flows in (or penetrates) into the source region and the drain region during the manufacturing process of the display panel (110) and diffuses (for example, lateral diffusion) into the channel region can increase. Accordingly, the effective channel length (L) of the bottom channel formed in the lower portion of the channel region BT), the effective channel length (L) of the top channel formed in the upper part of the channel area TP ), and the total effective channel length (L T ) can be relatively shortened. On the other hand, in the transistor of the same size in which the gate insulating layer is etched only to a certain thickness, the amount of hydrogen flowing into (or penetrating) the source region and drain region may be reduced, thereby reducing the amount of hydrogen diffusing into the channel region. Accordingly, the effective channel length (L) of the bottom channel formed in the lower part of the channel region BT '), the effective channel length (L) of the top channel formed in the upper part of the channel area TP '), and the total effective channel length (L T ') can be relatively long. In particular, in transistors where the gate insulating layer is etched only to a certain thickness, the effective channel length (L) of the top channel can be increased by reducing the amount of hydrogen flowing in (or penetrating) from the top of the active layer. TP ') can be increased by a larger amount. Accordingly, the total effective channel length (L) of the transistor T ') may increase.

[0199] FIGS. 9A and 9B are graphs showing changes in the characteristics of a transistor according to the etching degree of a gate insulating layer. For example, FIGS. 9A and 9B show the electrical characteristics of each transistor according to the etching degree of the gate insulating layer in transistors of a gate-sink structure, in which the channel region lengths are 1.5 μm, 2 μm, 2.5 μm, 3 μm, and 3.5 μm, respectively, through the drain-source current (Ids) according to the gate-source voltage (Vgs). The gate insulating layer of FIGS. 9A and 9B may be an element corresponding to the second insulating layer (INS2) disclosed in the embodiments of FIGS. 5 to 7.

[0200] In addition to FIGS. 1 to 7 and FIGS. 8A and 8B, referring to FIGS. 9A and 9B, in a transistor having a structure in which the gate insulating layer is etched to its entire thickness, when the length of the channel region is reduced, the threshold voltage roll-off (Vth roll-off) of the transistor may occur, which may deteriorate the operating characteristics of the transistor. For example, when the length of the channel region is less than 2.5 μm, the transistor may not exhibit operating characteristics suitable as a pixel transistor (Tpx) and / or a driver transistor (Tdr). For example, in a transistor having a channel region of 1.5 μm, the threshold voltage roll-off (Vth roll-off) may occur, and the transistor may substantially operate like a conductor.

[0201] On the other hand, in a transistor having a structure in which the gate insulating layer is etched only to a certain thickness, as in the embodiments of FIGS. 5 to 7, even if the length of the channel region is reduced, the threshold voltage roll-off (Vth roll-off) of the transistor can be prevented and the operating characteristics of the transistor can be improved. For example, a transistor having a channel region length of less than 2.5 μm can also exhibit operating characteristics suitable for use as a pixel transistor (Tpx) and / or a driver transistor (Tdr).

[0202] FIGS. 10 to 16 are cross-sectional views showing a method of manufacturing a display device (100) according to one embodiment. For example, FIGS. 10 to 16 sequentially show steps of forming pixel transistors (Tpx) on a substrate (SUB) among steps of manufacturing the display panel (110) of FIG. 5 or 6. In one embodiment, the driver transistors (Tdr) may be formed simultaneously with the pixel transistors (Tpx) in a manner substantially identical or similar to the pixel transistors (Tpx).

[0203] In addition to FIGS. 1 to 7, 8a, 8b, 9a, and 9b, referring to FIG. 10, a substrate (SUB) including at least a display area (DA) can be provided. The display area (DA) can include a pixel area (PXA).

[0204] In one embodiment, a barrier layer (BRL) may be formed on a substrate (SUB). The barrier layer (BRL) may be formed through a film formation process (e.g., a deposition process) of an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above. The material and / or method for forming the barrier layer (BRL) may vary depending on the embodiments.

[0205] In addition to FIGS. 1 to 10, referring to FIG. 11, a first conductive layer (CDL1) including at least one bottom gate electrode may be formed on a substrate (SUB). For example, a first bottom gate electrode (BG1) and a second bottom gate electrode (BG2) may be formed on a barrier layer (BRL) on the substrate (SUB). The first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) may be formed in each pixel area (PXA).

[0206] The first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) can be formed through a film formation process (e.g., a deposition process) of a conductive film using at least one conductive material exemplified above and a patterning process (e.g., an etching process using a mask) of the conductive film. The forming material and / or method of the first bottom gate electrode (BG1) and the second bottom gate electrode (BG2) can be variously changed according to embodiments.

[0207] In one embodiment, when the display panel (110) further includes a driving transistor (Tdr) (for example, a driving transistor (Tdr) including a third bottom gate electrode (BG3)) as illustrated in FIG. 7, the third bottom gate electrode (BG3) may be formed in the driving circuit area (DRA) simultaneously with forming the first and second bottom gate electrodes (BG1, BG2) in the pixel area (PXA). For example, the third bottom gate electrode (BG3) may be formed in the driving circuit area (DRA) using the same conductive material as the first and second bottom gate electrodes (BG1, BG2).

[0208] Thereafter, a first insulating layer (INS1) covering the first conductive layer (CDL1) can be formed on the substrate (SUB). The first insulating layer (INS1) can be formed through a film formation process of an insulating film using at least one insulating material (for example, an inorganic insulating material) as exemplified above. The material and / or method for forming the first insulating layer (INS1) can be varied in various ways depending on the embodiments.

[0209] In addition to FIGS. 1 to 11, referring to FIG. 12, a semiconductor layer (SCL) including a first active layer (ACT1) and a second active layer (ACT2) can be formed on a first insulating layer (INS1). For example, the first active layer (ACT1) and the second active layer (ACT2) can be formed in each pixel area (PXA). The first active layer (ACT1) can be formed to overlap at least a portion of the first bottom gate electrode (BG1), and the second active layer (ACT2) can be formed to overlap at least a portion of the second bottom gate electrode (BG2).

[0210] In one embodiment, the active layers (ACT) provided on the semiconductor layer (SCL) can be formed simultaneously using the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2) can be formed simultaneously using the same oxide semiconductor. For example, the first active layer (ACT1) and the second active layer (ACT2) can be formed in the pixel area (PXA) through a film formation process and a patterning process of an oxide semiconductor layer using at least one oxide semiconductor as exemplified above.

[0211] In one embodiment, when the display panel (110) further includes the driving transistor (Tdr) illustrated in FIG. 7, the first and second active layers (ACT1, ACT2) may be formed in the pixel area (PXA), and at the same time, the third active layer (ACT3) may be formed in the driving circuit area (DRA). For example, the third active layer (ACT3) may be formed on the first insulating layer (INS1) in the driving circuit area (DRA) using the same oxide semiconductor as the first and second active layers (ACT1, ACT2).

[0212] In addition to FIGS. 1 to 12, referring to FIG. 13, a second insulating layer (INS2) covering a semiconductor layer (SCL) may be formed on a substrate (SUB). For example, a second insulating layer (INS2) covering active layers (e.g., a first active layer (ACT1), a second active layer (ACT2), and / or a third active layer (ACT3)) provided on a semiconductor layer (SCL) may be formed on a substrate (SUB).

[0213] The second insulating layer (INS2) may be first formed over the entire surface of the substrate (SUB) on which the first and second active layers (ACT1, ACT2) are provided. For example, after the second insulating layer (INS2) is formed on the substrate (SUB) on which the semiconductor layer (SCL) is formed through a process for forming an insulating film using at least one insulating material (e.g., an inorganic insulating material) as exemplified above, a subsequent process such as heat treatment (e.g., annealing) may be performed. The material and / or method for forming the second insulating layer (INS2) may vary depending on the embodiments.

[0214] Thereafter, a conductive film (GCDL) can be formed on the second insulating layer (INS2). The conductive film (GCDL) is for forming a second conductive layer (CDL2) including top gate electrodes of transistors, etc., and can be formed through a film formation process (e.g., a deposition process) of the conductive film using at least one conductive material exemplified above.

[0215] In addition to FIGS. 1 to 13, referring to FIG. 14, a second conductive layer (CDL2) including a first top gate electrode (GE1) and a second top gate electrode (GE2) can be formed on a second insulating layer (INS2) by patterning a conductive film (GCDL). For example, by patterning the conductive film (GCDL) by an etching process using a mask, top gate electrodes overlapping with a portion of each of the active layers can be formed. For example, in each pixel area (PXA), a first top gate electrode (GE1) can be formed on the first active layer (ACT1) so as to overlap with a portion of the first active layer (ACT1), and a second top gate electrode (GE2) can be formed on the second active layer (ACT2) so as to overlap with a portion of the second active layer (ACT2).

[0216] In one embodiment, when the display panel (110) further includes the driving transistor (Tdr) illustrated in FIG. 7, the first and second top gate electrodes (GE1, GE2) can be formed in the pixel area (PXA), and at the same time, the third top gate electrode (GE3) can be formed in the driving circuit area (DRA). For example, the first top gate electrode (GE1), the second top gate electrode (GE2), and the third top gate electrode (GE3) can be formed by patterning the conductive film (GCDL).

[0217] In embodiments, a portion of the second insulating layer (INS2) that does not overlap with the top gate electrodes may be etched to a certain thickness using the same mask as the mask used for etching the conductive layer (GCDL) or using the top gate electrodes as a mask. For example, over-etching may be performed in the etching process of the conductive layer (GCDL) using a mask. Alternatively, after the conductive layer (GCDL) is etched and patterned with the top gate electrodes, an additional etching process may be performed using the mask used for etching the conductive layer (GCDL) or the top gate electrodes formed by etching the conductive layer (GCDL) as a mask, thereby etching the second insulating layer (INS2) to a certain thickness in a portion that does not overlap with the top gate electrodes. Accordingly, the second insulating layer (INS2) may be formed to have a relatively large thickness (e.g., first thickness (TH1)) in a first portion located on the channel regions of the transistors, and a relatively small thickness (e.g., second thickness (TH2)) in a second portion located on the drain regions and source regions of the transistors. In addition, the first portion of the second insulating layer (INS2) may have a pattern shape and / or size (e.g., area) corresponding to the top gate electrodes of each of the transistors.

[0218] In the embodiments, by etching the second insulating layer (INS2) to only a portion of its thickness while covering the drain regions and source regions of the transistors with the second insulating layer (INS2), the amount of hydrogen flowing into (or penetrating) the drain regions and source regions of the transistors during the process of manufacturing the display panel (110) can be reduced. Accordingly, even when the active layers of the transistors are formed with a high-mobility oxide semiconductor, the conductivity of the active layers and / or the length of the channel region can be appropriately and / or easily controlled.

[0219] In addition to FIGS. 1 to 14, referring to FIG. 15, a third insulating layer (INS3) may be formed on the top gate electrodes (for example, the first top gate electrode (GE1) and the second top gate electrode (GE2)) provided on the second conductive layer (CDL2) and the second insulating layer (INS2). The third insulating layer (INS3) may be formed through a film forming process of an insulating film using at least one insulating material (for example, an inorganic insulating material) exemplified above. In one embodiment, a subsequent process such as heat treatment may be performed after the third insulating layer (INS3) is formed. The material and / or method for forming the third insulating layer (INS3) may vary depending on the embodiments.

[0220] During the process of forming the third insulating layer (INS3), hydrogen may flow into or permeate the active layers of the semiconductor layer (SCL), including the first active layer (ACT1) and the second active layer (ACT2). For example, hydrogen may flow into or permeate the drain regions and source regions of the active layers that are not covered by the top gate electrodes.

[0221] As hydrogen flows into or permeates the first active layer (ACT1) and the second active layer (ACT2), the first active layer (ACT1) and the second active layer (ACT2) may become partially conductive (e.g., conductive to an N-type). For example, the first drain region (DR1), the first source region (SR1), the second drain region (DR2), and the second source region (SR2) may become conductive. In one embodiment, when the display panel (110) further includes the driving transistor (Tdr) illustrated in FIG. 7, the third drain region (DR3) and the third source region (SR3) may also become conductive.

[0222] In embodiments, the third insulating layer (INS3) may be formed while the active layers are entirely covered by the second insulating layer (INS2). Accordingly, the amount of hydrogen flowing into (or permeating) the active layers from the upper portions of the active layers may be reduced. For example, compared to a case where the third insulating layer (INS3) is formed while the drain region and the source region of each of the active layers are exposed, the amount of hydrogen flowing into (or permeating) the drain region and the source region from the upper portions of each of the active layers may be reduced. Accordingly, the amount of hydrogen diffusing into the channel region may be reduced, so that a channel length (or effective channel length) necessary for securing appropriate characteristics of the transistor can be sufficiently secured in the upper portion of the channel region. Hydrogen may also flow into or permeate the lower portions of each of the active layers from the first insulating layer (INS1), etc. However, if the amount of hydrogen flowing into (or permeating) from the upper portions of each of the active layers is reduced, the total amount of hydrogen flowing into (or permeating) each of the active layers may be reduced. Accordingly, the amount of hydrogen diffusing into the channel region may decrease, thereby increasing the total channel length (or total effective channel length) of each of the active layers. For example, as the top channel length (or effective channel length of the top channel) of each of the active layers increases, the total channel length (or total effective channel length) of each of the active layers may also increase.

[0223] Additionally, in embodiments, the thickness of the second insulating layer (INS2) can be reduced in the second portion compared to the first portion through partial etching. Accordingly, the drain region and source region of each of the active layers can be appropriately conductive without performing additional doping processes, etc.

[0224] In addition to FIGS. 1 to 15, referring to FIG. 16, a first drain electrode (DE1), a first source electrode (SE1), a second drain electrode (DE2), and a second source electrode (SE2) may be formed on the third insulating layer (INS3). In one embodiment, when at least one of the first drain region (DR1), the first source region (SR1), the second drain region (DR2), and the second source region (SR2) replaces at least one of the first drain electrode (DE1), the first source electrode (SE1), the second drain electrode (DE2), and the second source electrode (SE2), at least one of the first drain electrode (DE1), the first source electrode (SE1), the second drain electrode (DE2), and the second source electrode (SE2) may not be formed.

[0225] The first drain electrode (DE1) and the first source electrode (SE1) may be formed to be connected to different portions of the first active layer (ACT1). For example, the first drain electrode (DE1) may be formed to be connected to the first drain region (DR1), and the first source electrode (SE1) may be formed to be connected to the first source region (SR1). The second drain electrode (DE2) and the second source electrode (SE2) may be formed to be connected to different portions of the second active layer (ACT2). For example, the second drain electrode (DE2) may be formed to be connected to the second drain region (DR2), and the second source electrode (SE2) may be formed to be connected to the second source region (SR2). To this end, prior to the formation of the first drain electrode (DE1), the first source electrode (SE1), the second drain electrode (DE2), and the second source electrode (SE2), a plurality of contact holes (for example, the first, second, third, fourth, and fifth contact holes (CNT1, CNT2, CNT3, CNT4, CNT5)) may be formed in the third insulating layer (INS3).

[0226] In one embodiment, when the display panel (110) further includes the driving transistor (Tdr) illustrated in FIG. 7, the first and second drain electrodes (DE1, DE2) and the first and second source electrodes (SE1, SE2) may be formed in the pixel area (PXA), while the third drain electrode (DE3) and the third source electrode (SE3) may be formed in the driving circuit area (DRA). For example, the conductive film formed on the third insulating layer (INS3) may be etched to pattern the first, second, and third drain electrodes (DE1, DE2, DE3) and the first, second, and third source electrodes (SE1, SE2, SE3).

[0227] Through the above-described process, a plurality of pixel transistors (Tpx) including a first transistor (T1) and a second transistor (T2) can be formed in the display area (DA). In an embodiment in which the display panel (110) includes a driving circuit area (DRA), a plurality of driving unit transistors (Tdr) can be formed in the driving circuit area (DRA). In one embodiment, elements provided on the same conductive layer or the same semiconductor layer (SCL) of the display panel (110) can be formed simultaneously.

[0228] After forming the pixel transistors (Tpx) and / or the driver transistors (Tdr), a process of forming a first passivation layer (PSV1) of FIGS. 5 to 7 may be performed. The first passivation layer (PSV1) may cover the pixel transistors (Tpx) and / or the driver transistors (Tdr). In one embodiment, a process of forming a fourth conductive layer (CDL4) including a connection electrode (CNE) of each pixel (PX) on the first passivation layer (PSV1) and a process of forming a second passivation layer (PSV2) covering the fourth conductive layer (CDL4) may be additionally performed. Accordingly, a panel circuit layer (PCL) of the display panel (110) may be formed.

[0229] In one embodiment, when the display panel (110) includes a light emitting element layer (LEL) and an encapsulation layer (ENL) disposed on a panel circuit layer (PCL), the light emitting element layer (LEL) and the encapsulation layer (ENL) may be sequentially formed on the panel circuit layer (PCL). By the above-described process, the display panel (110) according to the embodiments and the display device (100) including the same may be manufactured.

[0230] According to the display device (100) and the manufacturing method thereof according to the embodiments, the second insulating layer (INS2) (e.g., a gate insulating layer) interposed between the active layer and the top gate electrode of each of the transistors including oxide semiconductors (e.g., pixel transistors (Tpx) and / or driver transistors (Tdr)) can be etched in a half-etching manner. Accordingly, the drain regions and source regions of the transistors can be appropriately and / or easily made conductive in a step of forming the third insulating layer (INS3), etc., without performing a separate doping process, and the threshold voltage roll-off (Vth roll-off) of the transistors can be prevented or improved. According to the embodiments, the operating characteristics of the transistors including oxide semiconductors can be appropriately secured.

[0231] In addition, according to embodiments, even in a high-resolution display device (100) in which the size of transistors is reduced, the effective channel length can be appropriately and / or easily expanded or secured. For example, by half-etching the second insulating layer (INS2) so that the second insulating layer (INS2) covers the drain regions and source regions of the transistors, the amount of hydrogen flowing into (or penetrating) the drain regions and source regions can be reduced and / or controlled. Accordingly, by increasing the length of the top channel of each transistor, the total channel length and the total effective channel length of each transistor can be increased to an extent that threshold voltage roll-off (Vth roll-off) can be prevented. Therefore, according to embodiments, the operating characteristics of the transistors can be appropriately and / or easily improved even in a high-resolution display device (100) including transistors of smaller sizes.

[0232] Additionally, according to embodiments, the second insulating layer (INS2) may be etched using the same mask as the mask used to form the top gate electrodes of the transistors or by utilizing the top gate electrodes as a mask. Accordingly, the manufacturing process of the display device (100) may be simplified and the yield may be improved.

[0233] Although embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without altering the technical spirit or essential characteristics of the present invention. Therefore, the embodiments described above should be understood to be illustrative in all respects and not restrictive.

Claims

1. Substrate; A first transistor including a first bottom gate electrode disposed on the substrate, a first active layer disposed on the first bottom gate electrode and including a first channel region, a first drain region, and a first source region, and a first top gate electrode disposed on a portion of the first active layer including the first channel region; A first insulating layer disposed between the first bottom gate electrode and the first active layer; and A second insulating layer is disposed between the first active layer and the first top gate electrode, A display device, wherein the second insulating layer comprises a first portion having a first thickness and disposed on a portion of the first active layer including the first channel region, and a second portion having a second thickness smaller than the first thickness and disposed on the remaining portion of the first active layer.

2. In paragraph 1, A display device, wherein the first channel region includes a lower layer adjacent to the first bottom gate electrode and having a first length, and an upper layer adjacent to the first top gate electrode and having a second length longer than the first length.

3. In paragraph 2, A display device, wherein, on the cross-section of the first active layer, the first channel region has a shape of an inverted trapezoid whose length increases from the lower layer to the upper layer.

4. In paragraph 1, The first channel region includes a lower layer adjacent to the first bottom gate electrode and an upper layer adjacent to the first top gate electrode, A display device, wherein the lower layer of the first channel region has a higher carrier concentration than the upper layer of the first channel region.

5. In paragraph 1, The second insulating layer includes an upper portion in contact with the first top gate electrode, A display device, wherein the upper portion of the second insulating layer and the first top gate electrode have the same pattern shape.

6. In paragraph 1, The second insulating layer includes an upper portion in contact with the first top gate electrode, A display device, wherein the upper portion of the second insulating layer and the first top gate electrode have the same area.

7. In paragraph 1, A display device, wherein the side surface of the first top gate electrode and the side surface of the second insulating layer have a continuously connected inclined surface.

8. In paragraph 1, A display device wherein the second insulating layer has a step-shaped difference at the boundary between the first portion and the second portion.

9. In paragraph 1, A display device further comprising a third insulating layer covering the second insulating layer and the first top gate electrode.

10. In paragraph 9, A first drain electrode disposed on the third insulating layer and connected to the first drain region by a first contact hole penetrating the second insulating layer and the third insulating layer; and further comprising at least one of the first source electrodes disposed on the third insulating layer and connected to the first source region by a second contact hole penetrating the second insulating layer and the third insulating layer; A display device, wherein the second insulating layer entirely covers the first active layer except for a portion where at least one of the first contact hole and the second contact hole is formed.

11. In paragraph 1, A display device, wherein the first bottom gate electrode is electrically connected to the first top gate electrode.

12. In paragraph 1, A display device further comprising a pixel including the first transistor.

13. In paragraph 12, The above pixel further comprises a second transistor, The second transistor is, A second bottom gate electrode disposed on the substrate; A second active layer disposed on the first insulating layer and including a second channel region, a second drain region, and a second source region; and A display device comprising a second top gate electrode disposed on the second insulating layer and disposed on a portion of the second active layer including the second channel region.

14. In paragraph 13, A display device, wherein the second insulating layer covers the second active layer and has the first thickness and the second thickness, respectively, on a portion of the second active layer including the second channel region and the remaining portion of the second active layer.

15. In paragraph 13, A display device, wherein the first active layer and the second active layer include the same oxide semiconductor.

16. In paragraph 12, Further comprising a driving unit connected to the pixel, and a driving unit transistor included in the driving unit, The above driving transistor is, A third bottom gate electrode disposed on the above substrate; a third active layer disposed on the first insulating layer and including a third channel region, a third drain region, and a third source region; and A display device comprising a third top gate electrode disposed on the second insulating layer and disposed on a portion of the third active layer including the third channel region.

17. In paragraph 16, A display device, wherein the second insulating layer covers the third active layer and has the first thickness and the second thickness, respectively, on a portion of the third active layer including the third channel region and the remaining portion of the third active layer.

18. In paragraph 16, A display device, wherein the first active layer and the third active layer include the same oxide semiconductor.

19. A step of forming a first insulating layer on a substrate; A step of forming an active layer on the first insulating layer; A step of forming a second insulating layer covering the active layer on the substrate; A step of forming a conductive film on the second insulating layer; A step of etching the above-mentioned conductive film to form a top gate electrode overlapping a portion of the above-mentioned active layer; and A step of forming a third insulating layer on the second insulating layer and the top gate electrode is included. A method for manufacturing a display device, further comprising, prior to forming the third insulating layer, a step of etching a portion of the second insulating layer that does not overlap with the top gate electrode to a certain thickness by using the same mask as the mask used for etching the conductive film or by using the top gate electrode as a mask.

20. In paragraph 19, Prior to the formation of the first insulating layer, a step of forming a bottom gate electrode on the substrate is further included. A method for manufacturing a display device, wherein the active layer is formed on the first insulating layer so as to overlap at least a portion of the bottom gate electrode.

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