Memory system, electronic device comprising same, and refresh control method

Abstract

An electronic device, according to various embodiments, may comprise: a display; a memory for storing a refresh period; and a processor, wherein the processor may be configured to: determine a first transmission delay time on the basis of a refresh interval (tREFI) corresponding to a first refresh period outputted from the memory; apply the first transmission delay time to the refresh interval; transmit a first refresh command to the memory after delaying by an offset of the first transmission delay time on the basis of a refresh interval (tREFI) corresponding to a second refresh period when the second refresh period is outputted from the memory; and output, via the display, a user interface to update the first transmission delay time to a second transmission delay time when a specified time arrives after the first transmission delay time is determined.

Description

Memory system, electronic device including same, and refresh control method

[0001] Various embodiments disclosed in this document relate to a memory system, an electronic device including the same, and a refresh control method.

[0002] With the development of digital technology, a variety of electronic devices capable of communicating and processing personal information while on the move, such as mobile terminals, electronic notebooks, smartphones, tablet PCs, and wearable devices, are being released.

[0003] These electronic devices may be equipped with various types of memory devices. For example, the electronic device may be equipped with dynamic random access memory (DRAM), which can be used as working memory.

[0004] The aforementioned DRAM includes memory cells composed of capacitors and transistors, and can store data by utilizing the charge stored in the capacitor.

[0005] Typically, charge stored in a capacitor can leak through various paths over time, potentially causing data stored in memory cells to be lost. To prevent data loss, DRAMs perform a refresh operation called a precharge operation, which involves selecting a row of memory cells, activating them, and then closing the word line.

[0006] However, refresh operations consume power, and as the number of refresh operations increases, so does the power consumption. This power consumption due to refresh operations can reduce the power efficiency of DRAM.

[0007] Accordingly, at least one example among various embodiments is to provide a memory system for reducing power consumption according to a refresh operation, an electronic device including the same, and a refresh control method.

[0008] In addition, at least one example among various embodiments provides a memory system for reducing the number of transmissions of a refresh command by applying an offset to a transmission cycle of the refresh command, an electronic device including the same, and a refresh control method.

[0009] According to various embodiments, an electronic device includes a display, a memory storing a refresh cycle, and a processor, wherein the processor determines a first transmission delay time based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory, applies the first transmission delay time to the refresh interval, and when a second refresh cycle is output from the memory, transmits a first refresh command to the memory after delaying by an offset of the first transmission delay time based on the refresh interval (tREFI) corresponding to the second refresh cycle, and when a designated time arrives after the first transmission delay time is determined, outputs a user interface through the display that updates the first transmission delay time to a second transmission delay time.

[0010] According to various embodiments, a memory system includes a volatile memory including a memory controller configured to output a refresh cycle, and a processor operatively connected to the volatile memory, wherein the processor is configured to determine a transmission delay time (a) based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory controller, apply the transmission delay time (a) to the refresh interval, and transmit the refresh command to the volatile memory after delaying by an offset of the transmission delay time (a) based on the refresh interval (tREFI) corresponding to the second refresh cycle when a second refresh cycle is output from the memory controller, and in determining the transmission delay time, the processor may be configured to write a test pattern into the volatile memory, perform a read operation on the volatile memory at each test cycle that increases at a predetermined time interval based on the refresh interval (tREFI) corresponding to the first refresh cycle, and determine a time during which a pattern identical to the test pattern is read as the transmission delay time. there is.

[0011] According to various embodiments, a computer-readable recording medium may be configured to write a test pattern into a memory, perform a read operation on the memory at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory, determine a time during which a pattern identical to the test pattern is read as a transmission delay time, apply the transmission delay time to the refresh interval (tREFI) corresponding to the refresh cycle output from the memory, apply the transmission delay time to the refresh interval, and, when a second refresh cycle is output from the memory, transmit the refresh command to the memory after delaying by an offset of the transmission delay time based on the refresh interval (tREFI) corresponding to the second refresh cycle.

[0012] An operating method of an electronic device according to various embodiments may include an operation of determining a first transmission delay time based on a first refresh cycle output from a memory, an operation of applying the first transmission delay time to the refresh interval, an operation of transmitting a first refresh command to the memory after delaying by an offset of the first transmission delay time based on a refresh interval (tREFI) corresponding to the second refresh cycle when a second refresh cycle is output from the memory, and an operation of outputting a user interface for updating the first delay time to a second transmission delay time when a designated time arrives after the first transmission delay time is determined.

[0013] A memory system according to various embodiments disclosed in this document can reduce the number of transmissions of a refresh command by applying an offset to a command cycle, thereby preventing a decrease in power efficiency of a memory device.

[0014] The effects that can be obtained from this document are not limited to those mentioned above.

[0015] FIG. 1 is a block diagram of an electronic device within a network environment according to various embodiments.

[0016] FIG. 2 is a diagram illustrating the configuration of a memory system according to various embodiments.

[0017] FIG. 3 is a drawing illustrating the configuration of a memory device according to various embodiments.

[0018] FIG. 4 is a drawing for explaining a memory cell array according to various embodiments.

[0019] FIG. 5 is a diagram for explaining a refresh cycle of a memory device according to an embodiment.

[0020] FIG. 6 is a drawing for explaining a register according to various embodiments.

[0021] FIG. 7 is a diagram for explaining the performance of a memory device with respect to leakage charge according to various embodiments.

[0022] FIG. 8 is a diagram illustrating an operation of a host applying an offset to a command cycle according to various embodiments.

[0023] FIG. 9 is a diagram for explaining an operation of determining an offset applied to a command cycle according to various embodiments.

[0024] FIG. 10 is a diagram for explaining the determination point of an offset applied to a command cycle according to various embodiments.

[0025] Figure 11 is a flowchart illustrating the operation of a memory system in various embodiments.

[0026] FIG. 12 is a flowchart illustrating an operation for determining a transmission delay time of a memory system in various embodiments.

[0027] FIG. 13 is a diagram illustrating a user interface for resetting a command cycle according to various embodiments.

[0028] FIG. 14 is a diagram illustrating a user interface that automatically resets a command cycle according to various embodiments.

[0029] In connection with the description of the drawings, the same or similar reference numerals may be used for identical or similar components.

[0030] Hereinafter, various embodiments of this document are described with reference to the attached drawings. However, this is not intended to limit the technology described in this document to specific embodiments, and it should be understood that various modifications, equivalents, and / or alternatives of the embodiments of this document are included. In connection with the description of the drawings, similar reference numerals may be used for similar components.

[0031]

[0032] FIG. 1 is a block diagram of an electronic device (101) within a network environment (100) according to various embodiments.

[0033] Referring to FIG. 1, in a network environment (100), an electronic device (101) may communicate with an electronic device (102) via a first network (198) (e.g., a short-range wireless communication network), or may communicate with at least one of an electronic device (104) or a server (108) via a second network (199) (e.g., a long-range wireless communication network). According to one embodiment, the electronic device (101) may communicate with the electronic device (104) via the server (108). According to one embodiment, the electronic device (101) may include a processor (120), a memory (130), an input module (150), an audio output module (155), a display module (160), an audio module (170), a sensor module (176), an interface (177), a connection terminal (178), a haptic module (179), a camera module (180), a power management module (188), a battery (189), a communication module (190), a subscriber identification module (196), or an antenna module (197). In some embodiments, the electronic device (101) may omit at least one of these components (e.g., the connection terminal (178)), or may have one or more other components added. In some embodiments, some of these components (e.g., the sensor module (176), the camera module (180), or the antenna module (197)) may be integrated into one component (e.g., the display module (160)).

[0034] The processor (120) may control at least one other component (e.g., a hardware or software component) of the electronic device (101) connected to the processor (120) by executing, for example, software (e.g., a program (140)), and may perform various data processing or calculations. According to one embodiment, as at least a part of the data processing or calculation, the processor (120) may store a command or data received from another component (e.g., a sensor module (176) or a communication module (190)) in a volatile memory (132), process the command or data stored in the volatile memory (132), and store the resulting data in a non-volatile memory (134). According to one embodiment, the processor (120) may include a main processor (121) (e.g., a central processing unit or an application processor) or a secondary processor (123) (e.g., a graphics processing unit, a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor) that can operate independently or together therewith. For example, if the electronic device (101) includes a main processor (121) and a secondary processor (123), the secondary processor (123) may be configured to use less power than the main processor (121) or to be specialized for a specified function. The secondary processor (123) may be implemented separately from the main processor (121) or as a part thereof.

[0035] The auxiliary processor (123) may control at least a part of functions or states associated with at least one component (e.g., a display module (160), a sensor module (176), or a communication module (190)) of the electronic device (101), for example, on behalf of the main processor (121) while the main processor (121) is in an inactive (e.g., sleep) state, or together with the main processor (121) while the main processor (121) is in an active (e.g., application execution) state. In one embodiment, the auxiliary processor (123) (e.g., an image signal processor or a communication processor) may be implemented as a part of another functionally related component (e.g., a camera module (180) or a communication module (190)). In one embodiment, the auxiliary processor (123) (e.g., a neural network processing unit) may include a hardware structure specialized for processing artificial intelligence models. The artificial intelligence models may be generated through machine learning. This learning can be performed, for example, on the electronic device (101) itself where the artificial intelligence model is executed, or can be performed through a separate server (e.g., server (108)). The learning algorithm can include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but is not limited to the examples described above. The artificial intelligence model can include multiple artificial neural network layers.The artificial neural network may be one of a deep neural network (DNN), a convolutional neural network (CNN), a recurrent neural network (RNN), a restricted Boltzmann machine (RBM), a deep belief network (DBN), a bidirectional recurrent deep neural network (BRDNN), a deep Q-network, or a combination of two or more of the above, but is not limited to the examples described above. In addition to, or alternatively to, a hardware structure, an artificial intelligence model may include a software structure.

[0036] The memory (130) can store various data used by at least one component (e.g., processor (120) or sensor module (176)) of the electronic device (101). The data can include, for example, software (e.g., program (140)) and input data or output data for commands related thereto. The memory (130) can include volatile memory (132) or non-volatile memory (134).

[0037] The program (140) may be stored as software in the memory (130) and may include, for example, an operating system (142), middleware (144), or an application (146).

[0038] The input module (150) can receive commands or data to be used in a component of the electronic device (101) (e.g., a processor (120)) from an external source (e.g., a user) of the electronic device (101). The input module (150) can include, for example, a microphone, a mouse, a keyboard, a key (e.g., a button), or a digital pen (e.g., a stylus pen).

[0039] The audio output module (155) can output audio signals to the outside of the electronic device (101). The audio output module (155) can include, for example, a speaker or a receiver. The speaker can be used for general purposes, such as multimedia playback or recording playback. The receiver can be used to receive incoming calls. According to one embodiment, the receiver can be implemented separately from the speaker or as part of the speaker.

[0040] The display module (160) can visually provide information to an external party (e.g., a user) of the electronic device (101). The display module (160) may include, for example, a display, a holographic device, or a projector and a control circuit for controlling the device. According to one embodiment, the display module (160) may include a touch sensor configured to detect a touch, or a pressure sensor configured to measure the intensity of a force generated by the touch.

[0041] The audio module (170) can convert sound into an electrical signal, or vice versa, convert an electrical signal into sound. According to one embodiment, the audio module (170) can acquire sound through the input module (150), output sound through the sound output module (155), or an external electronic device (e.g., an electronic device (102), a speaker, or headphones) directly or wirelessly connected to the electronic device (101).

[0042] The sensor module (176) can detect the operating status (e.g., power or temperature) of the electronic device (101) or the external environmental status (e.g., user status) and generate an electrical signal or data value corresponding to the detected status. According to one embodiment, the sensor module (176) can include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, a temperature sensor, a humidity sensor, or an illuminance sensor.

[0043] The interface (177) may support one or more designated protocols that may be used to directly or wirelessly connect the electronic device (101) with an external electronic device (e.g., the electronic device (102)). In one embodiment, the interface (177) may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

[0044] The connection terminal (178) may include a connector through which the electronic device (101) may be physically connected to an external electronic device (e.g., electronic device (102)). According to one embodiment, the connection terminal (178) may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (e.g., a headphone connector).

[0045] A haptic module (179) can convert electrical signals into mechanical stimuli (e.g., vibration or movement) or electrical stimuli that a user can perceive through tactile or kinesthetic sensations. According to one embodiment, the haptic module (179) can include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

[0046] The camera module (180) can capture still images and videos. According to one embodiment, the camera module (180) may include one or more lenses, image sensors, image signal processors, or flashes.

[0047] The power management module (188) can manage power supplied to the electronic device (101). According to one embodiment, the power management module (188) can be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

[0048] A battery (189) may power at least one component of the electronic device (101). In one embodiment, the battery (189) may include, for example, a non-rechargeable primary battery, a rechargeable secondary battery, or a fuel cell.

[0049] The communication module (190) may support the establishment of a direct (e.g., wired) communication channel or a wireless communication channel between the electronic device (101) and an external electronic device (e.g., electronic device (102), electronic device (104), or server (108)), and the performance of communication through the established communication channel. The communication module (190) may operate independently from the processor (120) (e.g., application processor) and may include one or more communication processors that support direct (e.g., wired) communication or wireless communication. According to one embodiment, the communication module (190) may include a wireless communication module (192) (e.g., a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module (194) (e.g., a local area network (LAN) communication module, or a power line communication module). Among these communication modules, the corresponding communication module can communicate with an external electronic device (104) via a first network (198) (e.g., a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network (199) (e.g., a long-range communication network such as a legacy cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (e.g., a LAN or WAN)). These various types of communication modules can be integrated into a single component (e.g., a single chip) or implemented as multiple separate components (e.g., multiple chips). The wireless communication module (192) can verify or authenticate the electronic device (101) within a communication network such as the first network (198) or the second network (199) by using subscriber information (e.g., an international mobile subscriber identity (IMSI)) stored in the subscriber identification module (196).

[0050] The wireless communication module (192) can support 5G networks and next-generation communication technologies following the 4G network, such as NR access technology (new radio access technology). The NR access technology can support high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and connection of multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency communications)). The wireless communication module (192) can support, for example, a high-frequency band (e.g., mmWave band) to achieve a high data transmission rate. The wireless communication module (192) can support various technologies for securing performance in a high-frequency band, such as beamforming, massive multiple-input and multiple-output (MIMO), full dimensional MIMO (FD-MIMO), array antenna, analog beam-forming, or large scale antenna. The wireless communication module (192) can support various requirements specified in the electronic device (101), an external electronic device (e.g., the electronic device (104)), or a network system (e.g., the second network (199)). According to one embodiment, the wireless communication module (192) may support a peak data rate (e.g., 20 Gbps or more) for eMBB realization, a loss coverage (e.g., 164 dB or less) for mMTC realization, or a U-plane latency (e.g., 0.5 ms or less for downlink (DL) and uplink (UL), or 1 ms or less for round trip) for URLLC realization.

[0051] The antenna module (197) can transmit or receive signals or power to or from an external device (e.g., an external electronic device). According to one embodiment, the antenna module (197) may include an antenna including a radiator formed of a conductor or a conductive pattern formed on a substrate (e.g., a PCB). According to one embodiment, the antenna module (197) may include a plurality of antennas (e.g., an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network, such as the first network (198) or the second network (199), may be selected from the plurality of antennas, for example, by the communication module (190). A signal or power may be transmitted or received between the communication module (190) and an external electronic device via the at least one selected antenna. According to some embodiments, in addition to the radiator, another component (e.g., a radio frequency integrated circuit (RFIC)) may be additionally formed as a part of the antenna module (197).

[0052] According to various embodiments, the antenna module (197) may form a mmWave antenna module. According to one embodiment, the mmWave antenna module may include a printed circuit board, an RFIC disposed on or adjacent a first side (e.g., a bottom side) of the printed circuit board and capable of supporting a designated high-frequency band (e.g., a mmWave band), and a plurality of antennas (e.g., an array antenna) disposed on or adjacent a second side (e.g., a top side or a side side) of the printed circuit board and capable of transmitting or receiving signals in the designated high-frequency band.

[0053] At least some of the above components can be interconnected and exchange signals (e.g., commands or data) with each other via a communication method between peripheral devices (e.g., a bus, GPIO (general purpose input and output), SPI (serial peripheral interface), or MIPI (mobile industry processor interface)).

[0054] According to one embodiment, commands or data may be transmitted or received between the electronic device (101) and an external electronic device (104) via a server (108) connected to a second network (199). Each of the external electronic devices (102 or 104) may be the same or a different type of device as the electronic device (101). According to one embodiment, all or part of the operations executed in the electronic device (101) may be executed in one or more of the external electronic devices (102, 104, or 108). For example, when the electronic device (101) is to perform a certain function or service automatically or in response to a request from a user or another device, the electronic device (101) may, instead of or in addition to executing the function or service on its own, request one or more external electronic devices to perform the function or at least a part of the service. One or more external electronic devices that receive the request may execute at least a portion of the requested function or service, or an additional function or service related to the request, and transmit the result of the execution to the electronic device (101). The electronic device (101) may process the result as is or additionally and provide it as at least a portion of a response to the request. For this purpose, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used, for example. The electronic device (101) may provide an ultra-low latency service by using distributed computing or mobile edge computing, for example. In another embodiment, the external electronic device (104) may include an Internet of Things (IoT) device. The server (108) may be an intelligent server utilizing machine learning and / or a neural network. According to one embodiment, the external electronic device (104) or the server (108) may be included in the second network (199).The electronic device (101) can be applied to intelligent services (e.g., smart home, smart city, smart car, or healthcare) based on 5G communication technology and IoT-related technology.

[0055] The electronic device (101) according to various embodiments disclosed in this document may be a device of various forms. The electronic device (101) may include, for example, a portable communication device (e.g., a smartphone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device (101) according to the embodiments of this document is not limited to the aforementioned devices.

[0056] The various embodiments of this document and the terminology used therein are not intended to limit the technical features described in this document to specific embodiments, but should be understood to include various modifications, equivalents, or substitutes of the embodiments. In connection with the description of the drawings, similar reference numerals may be used for similar or related components. The singular form of a noun corresponding to an item may include one or more of the items, unless the context clearly indicates otherwise. In this document, each of the phrases "A or B", "at least one of A and B", "at least one of A or B", "A, B, or C", "at least one of A, B, and C", and "at least one of A, B, or C" can include any one of the items listed together in the corresponding phrase among those phrases, or all possible combinations thereof. Terms such as "first," "second," or "first" or "second" may be used merely to distinguish one component from another, and do not limit the components in any other respect (e.g., importance or order). When a component (e.g., a first component) is referred to as "coupled" or "connected" to another component (e.g., a second component), with or without the terms "functionally" or "communicatively," it means that the component can be connected to the other component directly (e.g., wired), wirelessly, or through a third component.

[0057] The term "module" used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and may be used interchangeably with terms such as logic, logic block, component, or circuit. A module may be an integral component, or a minimum unit or part of such a component that performs one or more functions. For example, according to one embodiment, a module may be implemented in the form of an application-specific integrated circuit (ASIC).

[0058] Various embodiments of the present document may be implemented as software (e.g., a program (140)) including one or more commands stored in a storage medium (e.g., an internal memory (136) or an external memory (138)) readable by a machine (e.g., an electronic device (101)). For example, a processor (e.g., a processor (120)) of the machine (e.g., an electronic device (101)) may call at least one command among the one or more commands stored from the storage medium and execute it. This enables the machine to operate to perform at least one function according to the at least one command called. The one or more commands may include code generated by a compiler or code executable by an interpreter. The machine-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' simply means that the storage medium is a tangible device and does not contain signals (e.g., electromagnetic waves), and the term does not distinguish between cases where data is stored semi-permanently or temporarily on the storage medium.

[0059] According to one embodiment, the method according to the various embodiments disclosed in the present document may be provided as included in a computer program product. The computer program product may be traded as a product between a seller and a buyer. The computer program product may be distributed in the form of a machine-readable storage medium (e.g., compact disc read only memory (CD-ROM)), or may be distributed online (e.g., downloaded or uploaded) via an application store (e.g., Play Store™) or directly between two user devices (e.g., smart phones). In the case of online distribution, at least a portion of the computer program product may be temporarily stored or temporarily generated in a machine-readable storage medium, such as the memory of a manufacturer's server, an application store's server, or an intermediary server.

[0060] According to various embodiments, each component (e.g., a module or a program) of the above-described components may include one or more entities, and some of the entities may be separated and placed in other components. According to various embodiments, one or more components or operations of the aforementioned components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (e.g., a module or a program) may be integrated into a single component. In such a case, the integrated component may perform one or more functions of each of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. According to various embodiments, the operations performed by a module, program, or other component may be executed sequentially, in parallel, iteratively, or heuristically, or one or more of the operations may be executed in a different order, omitted, or one or more other operations may be added.

[0061]

[0062] A memory system (200) for reducing power consumption according to a refresh operation described through the drawings below may be a part of the electronic device (101) described above. In addition, at least one of the various embodiments described through FIGS. 2 to 13 below may be combined with other embodiments.

[0063]

[0064] FIG. 2 is a diagram illustrating the configuration of a memory system (200) according to various embodiments.

[0065] Referring to FIG. 2, a memory system (200) according to various embodiments may include a host (210) (e.g., a processor (120)), a memory (220) (e.g., a memory (130)), and a power control device (230) (e.g., a power management module (188)).

[0066] According to various embodiments, the host (210) may communicate with the memory (220) based on various interface protocols. According to one embodiment, the various interface protocols may be one of Peripheral Component Interconnect - Express (PCI-E), Advanced Technology Attachment (ATA), Serial ATA (SATA), Parallel ATA (PATA), or Serial Attached SCSI (SAS). However, this is merely an example, and various embodiments are not limited thereto. For example, the interface protocols between the host (210) and the memory (220) may include other interfaces such as Universal Serial Bus (USB), Multi-Media Card (MMC), Enhanced Small Disk Interface (ESDI), or Integrated Drive Electronics (IDE).

[0067] According to various embodiments, the power control device (230) can supply power required for various components of the memory system (200). According to one embodiment, the power control device (230) can control the power supply to the memory (220).

[0068] According to various embodiments, the memory (220) may be a storage device composed of semiconductor elements.

[0069] According to one embodiment, the memory (220) may be a memory (e.g., a volatile memory (132)) that enables data storage only while power is supplied. For example, the memory (220) may include at least one of DRAM, SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), LPDDR SDRAM (Low Power Double Data Rate SDRAM), or GDDR SDRAM (Graphics Double Data Rate SDRAM). However, the memory device (223) according to various embodiments is not limited to the above-described examples.

[0070] According to one embodiment, the memory (220) may perform an operation corresponding to a control command received from the host (210). For example, the control command may be associated with at least one of an active operation, a write operation, a read operation, or a precharge operation. However, this is merely an example, and various embodiments are not limited thereto. For example, the refresh command described below with reference to FIG. 6 may also correspond to a control command.

[0071] According to an embodiment, the memory (220) may include a memory controller (221), a memory device (223), a register (225), and a temperature sensor (227).

[0072] According to various embodiments, the memory controller (221) can control the overall operation of the memory (220). According to one embodiment, the memory controller (221) can control data exchange between the host (210) and the memory (220). For example, the memory controller (221) can control the memory device (223) according to a control command received from the host (210).

[0073] According to various embodiments, the memory device (223) can store data under the control of the memory controller (221).

[0074] The memory device (223) will be described in detail with reference to FIGS. 3 and 4 below.

[0075]

[0076] FIG. 3 is a drawing illustrating a configuration of a memory device (223) according to various embodiments. FIG. 4 is a drawing illustrating a memory cell array (310) according to various embodiments.

[0077] Referring to FIG. 3, a memory device (223) according to various embodiments may include a memory cell array (310), an address buffer (addr buffer) (320), a row decoder (row dec) (330), a column decoder (col dec) (340), a command decoder (cmd dec) (312), a control logic (control logic) (314), a sense amplifier (s / a) (350), and a data input / output circuit (data i / o circuit) (360).

[0078] According to various embodiments, the memory cell array (310) may include a plurality of memory cells (MC) in which data is stored. As illustrated in FIG. 4, the plurality of memory cells (MC) may be provided in a matrix form arranged in rows and columns. In this regard, the memory cell array (310) may include a plurality of word lines (WL) and a plurality of bit lines (BL) connected to the memory cells (MC). For example, the plurality of word lines (WL) may be connected to rows of the memory cells (MC), and the plurality of bit lines (BL) may be connected to columns of the memory cells (MC).

[0079] According to various embodiments, the command decoder (312) can decode a control command (CMD) received from the memory controller (221) to cause control signals corresponding to the control command to be generated in the control logic (314).

[0080] According to various embodiments, the control logic (314) may control the operation of the memory cell array (310) based on the decoding result of the command decoder (312). According to one embodiment, the control logic (314) may generate a control signal related to at least one of an active operation, a write operation, a read operation, or a precharge operation and provide the control signal to the memory cell array (310).

[0081] According to various embodiments, the address buffer (320) may receive an address (ADDR) from the memory controller (221). The address (ADDR) may include a row address (RA) addressing a row of the memory cell array (310) and a column address (CA) addressing a column of the memory cell array (310). According to one embodiment, the address buffer (320) may transmit the received row address (RA) to the row decoder (330) and transmit the received column address (CA) to the column decoder (340).

[0082] According to various embodiments, the row decoder (330) may select any one of a plurality of word lines (WL) connected to the memory cell array (310). According to one embodiment, the row decoder (330) may decode a row address (RA) received from the address buffer (320), select any one word line corresponding to the row address (RA), and activate the selected word line.

[0083] According to various embodiments, the column decoder (340) may select any one of a plurality of bit lines (BL) of the memory cell array (310). According to one embodiment, the column decoder (340) may decode a column address (CA) received from the address buffer (320) and select any one corresponding to the column address (CA).

[0084] According to various embodiments, the sense amplifier unit (350) may include a plurality of bit line sense amplifiers connected to each bit line (BL) of the memory cell array (310). The bit line sense amplifier may sense a voltage change of the connected bit line (BL), amplify the voltage change, and output the amplified voltage.

[0085] According to various embodiments, the data input / output circuit (360) can output data generated based on the sensed amplified voltage from the sense amplifier unit (350) to the outside through the data lines (DQ).

[0086] As described above, the memory controller (221) can store data in a memory cell (MC). This memory cell (MC) may be composed of one transistor (401) and one capacitor (403).

[0087] According to an embodiment, when the memory controller (221) stores data of “1” (or “high”) in the memory cell (MC), it may apply a high potential to the memory cell (MC) to charge the capacitor (403). In addition, when the memory controller (221) stores data of “0” (or “low”) in the memory cell (MC), it may apply a low potential to the memory cell (MC) to discharge the capacitor (403).

[0088] At this time, if the capacitor (403) of the memory cell (MC) is ideal, the charge charged in the capacitor (403) should always be maintained, but as time passes, the charge stored in the capacitor (403) may leak, causing data stored in the memory cell (MC) to be lost.

[0089] In this regard, the memory system (200) can enable continuous data retention by performing a refresh operation before data stored in a memory cell (MC) is lost. According to one embodiment, the refresh operation can be performed through a precharge operation, which is an operation of selecting a row of memory cells, making them active, and then closing the word line again.

[0090] According to various embodiments, the refresh operation of the memory system (200) may be performed based on a refresh command provided by the host (210).

[0091] According to one embodiment, the host (210) may determine a transmission interval (or transmission time) (hereinafter referred to as “command period”) of a refresh command based on a refresh period (refresh multiplier or refresh rate) stored in a register (225), and transmit the refresh command to the memory (220) based on the command period. Accordingly, the memory (220) may perform a refresh operation after receiving the refresh command from the host (210). For example, the refresh period updated in the register (225) may be associated with the internal temperature of the memory (220) (e.g., the memory device (223)).

[0092] The refresh cycle related to this will be specifically explained with reference to FIGS. 5 and 6 below.

[0093]

[0094] FIG. 5 is a diagram for explaining a refresh cycle of a memory device (223) according to an embodiment. FIG. 6 is a diagram for explaining a register (225) according to various embodiments.

[0095] Referring to FIG. 5, the register (225) may be updated with a refresh cycle having a longer cycle as the internal temperature of the memory (220) (e.g., memory device (223)) is lower, and the register (225) may be updated with a refresh cycle having a relatively shorter cycle as the internal temperature is higher.

[0096] For example, as illustrated in FIG. 5, when the internal temperature is approximately -25°C, the refresh operation may be performed at a cycle of approximately '31.2 μs', and when the internal temperature gradually increases and approaches approximately 85°C, the refresh operation may be specified to be performed at a cycle of approximately '0.4875 μs'. This takes into account the situation in which the amount of leaked charge also increases as the internal temperature of the memory (220) increases. However, this is merely an example, and various embodiments are not limited thereto. For example, in the register (225), a refresh cycle having a shorter cycle may be updated as the internal temperature decreases, or a specified refresh cycle may be updated regardless of the internal temperature. In addition, the numerical values ​​of the internal temperature and the refresh cycle described in FIG. 5 are according to one embodiment, and various embodiments are not limited thereto.

[0097] According to one embodiment, the register (225) may include mode register 4 (hereinafter referred to as 'MR4') defined in the Joint Electron Device Engineering Council (JEDEC) standard. For example, as illustrated in FIG. 6, among the operands of MR4, OP[4:0] may indicate a refresh cycle according to the internal temperature.

[0098] For example, the value set in OP[4:0] of MR4 may indicate a refresh cycle required at the current internal temperature of the memory (220). For example, referring to FIGS. 5 and 6, when the current internal temperature of the memory (220) is approximately 85° C., '0.125x' may be set in OP[4:0] of MR4 as a value indicating a refresh cycle. This means that the refresh cycle required at the current internal temperature is approximately '0.4875 μs'.

[0099] According to various embodiments, the memory controller (221) can periodically or continuously update the refresh cycle stored in the register (225).

[0100] In this regard, the memory controller (221) can determine the refresh cycle required at the current internal temperature of the memory (220) based on the reference cycle and store it in the register (225). The reference cycle may be information that divides the temperature range (e.g., approximately -25°C to 85°C) in which the memory device (223) can operate normally into multiple temperature sections and defines a refresh cycle for each temperature section.

[0101] For example, the memory controller (221) can check the internal temperature of the memory (220) based on information output through the temperature sensor (227) and obtain a refresh cycle corresponding to the internal temperature of the memory (220) from the reference cycle.

[0102] The above description describes a configuration in which only the refresh cycle corresponding to the current internal temperature of the memory (220) is updated in the register (225).

[0103] However, this is merely an example, and various embodiments are not limited thereto. For example, a reference cycle in which a refresh cycle is defined for each temperature range distinguished from the temperature range in which the memory device (223) can operate normally may be stored in the register (225).

[0104] In this case, the host (210) can check the internal temperature of the memory (220) based on information output through the memory (220) (e.g., temperature sensor (227)). In addition, the host (210) can obtain a temperature range corresponding to the internal temperature of the memory (220) and a corresponding refresh cycle from the reference cycle stored in the memory (220), and transmit a refresh command based on the temperature range and the refresh cycle.

[0105] However, even when the refresh cycle arrives, the charge stored in the memory device (223) may not leak to a level that would cause data loss. In this way, a refresh operation performed without the charge leaking to a level that would cause data loss may reduce the power efficiency of the memory device (223).

[0106] In this regard, the memory system (200) according to various embodiments can reduce the number of transmissions of a refresh command by applying an offset (e.g., transmission delay time) to the command cycle, thereby preventing a decrease in power efficiency of the memory device (223). For a detailed description thereof, please refer to the drawings below.

[0107]

[0108] FIG. 7 is a diagram for explaining the performance of a memory device (223) with respect to leakage charge according to various embodiments. FIG. 8 is a diagram for explaining the operation of a host (210) applying an offset to a command cycle according to various embodiments.

[0109] As mentioned above, the refresh cycle (or command cycle) can be determined based on the temperature range defined in the reference cycle.

[0110] However, the amount of charge leaked due to temperature changes may vary depending on the performance of the memory device (223). This performance for leakage charge may vary slightly depending on the structure or manufacturing process conditions of the memory device (223).

[0111] In other words, when the memory device (223) has a first level of performance against leakage charge, the charge stored in the capacitor (403) may leak to a level that causes data loss at a time (e.g., a first time point (t1) (701)) when a designated refresh cycle (e.g., approximately 3.9 μs) arrives. Accordingly, the host (210) needs to transmit a refresh command to the memory (220) at the first time point (t1) (701), the second time point (t2) (702), the third time point (t3) (703), and the fourth time point (t4) (704) based on the designated refresh cycle, as shown in 710 of FIG. 7.

[0112] However, if the memory device (223) has a second level of performance higher than the first level for leakage charge, the charge stored in the capacitor (403) may not leak to a level that causes data loss even when a designated refresh cycle arrives. In other words, as in 730 of FIG. 7, the charge stored in the capacitor (403) may leak to a level that causes data loss at a point in time (e.g., a fifth point in time (t2+ a) (705)) when a certain amount of time (a) has elapsed (733) from the point in time (e.g., a second point in time (t2) (702)) when the designated refresh cycle arrives.

[0113] As previously mentioned, a refresh operation performed without charge leakage to a level that would cause data loss may degrade the power efficiency of the memory device (223). Therefore, in order to prevent the power efficiency of the memory device (223) from degrading, it is necessary to perform the refresh operation in a situation where charge leakage has occurred to a level that would cause data loss.

[0114] In this regard, the host (210) according to various embodiments may determine a command cycle based on a refresh cycle stored in a register (225), and apply an offset (a) to the command cycle to delay the transmission time of the refresh command by a certain amount of time.

[0115] According to one embodiment, the host (210) can determine a second time point (t2) (802) at which to transmit a second refresh command based on a first time point (t1) (801) at which the first refresh command is transmitted and a refresh interval (tREFI) (e.g., approximately 3.9 μs) corresponding to a refresh cycle (refresh multiplier or refresh rate) stored in a register (225). At this time, the host (210) can transmit the second refresh command at a delay time point (t2+a) (803) applied to an offset (a) at the second time point (t2) (802) instead of transmitting the second refresh command at the second time point (t2) (802).

[0116] In addition, the host (210) may not transmit the third refresh command and the fourth refresh command at the third time point (t3) (804) and the fourth time point (t4) (806) that are confirmed based on the first time point (t1) (801) at which the first refresh command is transmitted and the refresh interval (tREFI) corresponding to the refresh cycle (refresh multiplier or refresh rate) stored in the register (225), but may transmit the third refresh command and the fourth refresh command at the delay time point (t3+a) (805) at which the offset (a) is applied to the third time point (t3) (804) and the delay time point (t4+a) (807) at which the offset (a) is applied to the fourth time point (t4) (806).

[0117] In other words, the host (210) can reduce the number of transmissions of the refresh command by delaying transmission of the refresh command until just before the charge stored in the memory device (223) leaks to a level that would cause data loss.

[0118] Below, we will specifically explain how to determine the offset (a) to be applied to the command cycle.

[0119]

[0120] FIG. 9 is a diagram for explaining an operation of determining an offset (a) applied to a command cycle according to various embodiments.

[0121] According to various embodiments, in determining the offset (a), the host (210) may write a test pattern to the memory device (223). For example, the operation of writing the test pattern may include an operation of writing data of “1” (or “high”) to the memory cell (MC). However, this is merely exemplary, and various embodiments are not limited thereto. For example, data of “0” (or “low”) may be written to the memory cell (MC), or a test pattern combining data of “1” and data of “0” may be written. In addition, according to an embodiment, the test pattern may be written to the remaining memory cells (MC) except for the memory cell (MC) in which the bootstrap code is stored.

[0122] According to various embodiments, the host (210) may perform an operation of reading a test pattern and determine an offset (a) based on at least a portion of the reading result.

[0123] According to one embodiment, the host (210) may determine the time during which a pattern identical to the test pattern is read out (e.g., the time before a pattern different from the test pattern is read out) as the offset (a).

[0124] In this regard, the host (210) can determine the readout time based on the second time point (t2) (902) at which a designated refresh interval (e.g., approximately 3.9 μs) arrives from the first time point (t1) (901), as illustrated in FIG. 9.

[0125] For example, the reading time point (hereinafter referred to as a step) for reading a test pattern may include a first reading time point (t2+1x)(903) (e.g., the first step) in which a certain time (x) (a step interval of the reading time point below) (e.g., approximately 0.3 μs) is increased based on the second time point (t2)(902), a second reading time point (t2+2x)(904) (e.g., the second step) in which a certain time (x) is increased based on the first reading time point, a third reading time point (t2+3x)(905) (e.g., the third step) in which a certain time is increased based on the second reading time point (t2+2x)(904), and a fourth reading time point (t2+4x)(906) (e.g., the fourth step) in which a certain time is increased based on the third reading time point (t2+3x)(905). there is.

[0126] For example, if a pattern identical to the test pattern is confirmed up to the third reading point, and a pattern different from the test pattern is confirmed at the fourth reading point (t2+4x) (906) (e.g., the fourth step), the host (210) may determine the time (910) (e.g., 0.15 μs * 3 steps) = 0.45 μs) from the second reading point (t2) (902) to the third reading point (t2+3x) (905) as an offset.

[0127] According to various embodiments, the host (210) may apply the determined offset to a refresh interval corresponding to a refresh cycle. For example, the refresh interval with the applied offset may be the time from the first time point (t1) (901) to the third read time point (t2+3x) (905) (e.g., 3.9 μs + 0.45 μs) = 4.35 μs).

[0128] According to one embodiment, the host (210) may apply an offset to a refresh interval (tREFI) corresponding to a refresh cycle (refresh multiplier or refresh rate) stored in the register (225). For example, the host (210) may generate a refresh interval to which an offset is applied through testing and calculation for the refresh interval corresponding to each refresh cycle based on each refresh cycle (e.g., the first refresh cycle to the nth refresh cycle) stored in the register (225). In addition, the host (210) may store the offset applied to the refresh interval corresponding to each refresh cycle stored in the register (225) (or the refresh interval to which the offset is applied) in a separate storage space (e.g., the non-volatile memory (134)). In this case, even after the reboot operation of the electronic device (101), the host (210) can transmit a refresh command based on data stored in a separate storage space (e.g., non-volatile memory (134)).

[0129] According to one embodiment, the host (210) may determine the refresh interval by applying an offset at the time when the refresh cycle stored in the non-volatile memory (134) arrives. For example, when the first refresh cycle is output from the register (225), the host (210) may transmit a refresh command based on a refresh interval corresponding to a second refresh cycle delayed by the offset from the first refresh cycle.

[0130] As described above, the host (210) may perform an operation of reading all memory cells (MC) while increasing the reading time by one step based on the second time point (t2) (902) in order to read the test pattern. For example, the step interval of the reading time point may be specified for each refresh interval. For example, in the case of the first refresh interval (e.g., approximately 3.9 μs), the step interval of the reading time point may be specified as approximately 0.3 μs, and in the case of the second refresh interval (e.g., approximately 1.95 μs), the step interval of the reading time point may be specified as approximately 0.15 μs. However, this is merely an example, and various embodiments are not limited thereto. For example, the step interval at the time of reading may have a longer or shorter period than the aforementioned period, depending on the state of the electronic device (101).

[0131]

[0132] FIG. 10 is a diagram for explaining the determination point of an offset (a) applied to a command cycle according to various embodiments.

[0133] Before the explanation, the MR4 Trip Level illustrated in FIG. 10 means the point at which the MR4 refresh multiplier changes (e.g., changes from MR4=0x03 to MR4=0x86), the Device Temp Margin means the maximum temperature margin (e.g., approximately ≥ 2 ℃) between the time after the MR4 trip and the time until the actual MR4 value reaches the host (201), and the System Response delay may mean the delay until the actual MR4 value is updated to the host (210) after the MR4 read command. In addition, Tsens interval means MR4 register value update interval (tTSI), Read Interval means the cycle in which the host (210) sends an MR4 read command (MR4 read command) to the memory (220) (e.g., DRAM), and <(Tsens Interval+Read Interval+System Response Delay) is the total sum of tTSI, Read Interval, and System Response Delay, which can satisfy the conditions below.

[0134]

[0135] In the above <Mathematical Formula 1>, TempGradient can represent the maximum temperature gradient experienced by the memory (220) at a temperature of interest in the range of 2°C.

[0136] Referring to FIG. 10, the memory (220) can update the refresh cycle in the register (225) based on a pre-specified MR4 register value update interval (Tsens Interval). For example, a first value (0x03) indicating a refresh cycle can be updated based on a first update interval (1005). In addition, when a second update interval (1006), a third update interval (1007), and a fourth update interval (1008) arrive, a second value (0x86), a third value (0x86), a fourth value (0x86), and a fifth value (0x06) can be updated.

[0137] Additionally, the host (210) can also obtain a refresh cycle from the register (225) at each designated read command transmission cycle (Read Interval) and use this to determine the command cycle. For example, in the first read command transmission cycle (1001), the first value (0x03) updated in the first update interval (1005) can be obtained, and in the second read command transmission cycle (1003), the fourth value (0x86) updated in the fourth update interval (1008) can be obtained.

[0138] However, as soon as the first value is acquired in the first read command transmission cycle (1001), the internal temperature of the memory (200) may change, causing a situation in which the actual refresh cycle also changes from the first value to the second value. In other words, if the temperature of the memory (200) changes frequently, the refresh cycle acquired by the host (210) may be different from the refresh cycle currently updated in the register (225).

[0139] Accordingly, the host (210) according to various embodiments may determine the offset (a) in a situation where the temperature of the memory (220) does not change frequently. For example, a situation where the temperature of the memory (220) does not change frequently may be a situation where refresh cycles of the same value are continuously obtained through the register (225).

[0140]

[0141] The aforementioned memory system (200) is not limited to one embodiment, and various embodiments are not limited thereto. For example, at least one of the components of the memory system (200) according to various embodiments may be omitted, or one or more other components may be added to the configuration of the memory system (200). Furthermore, at least one of the aforementioned components may be integrated with another component. For example, depending on the embodiment, the register (221) may be integrated with the memory controller (223) and / or the memory device (223).

[0142] In addition, the electronic device (101) having the memory system (200) according to various embodiments may output a user interface (or a user interface that induces resetting of the command cycle) that resets a command cycle (e.g., a refresh cycle or an offset) at a specified time interval (e.g., once a year). For example, the offset (e.g., a transmission delay time) operation described above with reference to FIGS. 7 to 10 may be performed in the first boot operation of the electronic device (101) (e.g., the first boot operation after manufacturing), and the electronic device (101) may also determine a new offset together with a reboot operation based on an input to the user interface after the first boot operation.

[0143] According to one embodiment, as illustrated in FIG. 13, a user interface (1310) for resetting a command cycle may include information (1301) indicating that resetting the command cycle is necessary and an item (1303) for receiving user input related to resetting or canceling the command cycle.

[0144] In this regard, when a user input related to resetting the command cycle is received, the electronic device (101) may perform an operation of applying a new offset to the refresh interval. For example, the electronic device (101) may store the new offset in a memory (130) (e.g., a non-volatile memory (134)) and use it to transmit a refresh command.

[0145] Additionally or optionally, the command cycle (e.g. refresh cycle or offset) can be automatically (or regardless of user input) reset at specified intervals (e.g. once a year).

[0146] In this regard, the electronic device (101) may provide a user interface (1410) for activating or deactivating a function for automatically resetting a command cycle, as illustrated in FIG. 14. According to an embodiment, the user interface (1410) may include an item (1401) for receiving a user input related to activating or deactivating the function for automatically resetting a command cycle and information (e.g., a description) (1403) about the function for automatically resetting a command cycle.

[0147] For example, when the function to automatically reset the command cycle is activated, the electronic device (101) may automatically reset the command cycle at a specified time interval.

[0148] For example, when the function to automatically reset the command cycle is disabled, the electronic device (101) may output a user interface (e.g., the user interface (1310) of FIG. 13) that resets the command cycle at specified intervals. According to an embodiment, the electronic device (101) may omit the operation of outputting the user interface that resets the command cycle even when the specified time arrives.

[0149] However, this is merely an example, and various embodiments are not limited thereto. For example, the electronic device (101) may perform an operation of determining a new offset together with a reboot operation at predetermined time intervals, regardless of the activation of the function for automatically resetting the command cycle. Furthermore, the electronic device (101) may determine a new offset each time a reboot operation is performed, regardless of the activation of the function for automatically resetting the command cycle.

[0150]

[0151] According to various embodiments, an electronic device (101) includes a display (160), a memory that stores a refresh cycle, and a processor (120), wherein the processor (120) determines a first transmission delay time based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory (130), applies the first transmission delay time to the refresh interval, and when a second refresh cycle is output from the memory (130), delays by an offset of the first transmission delay time based on the refresh interval (tREFI) corresponding to the second refresh cycle and then transmits a first refresh command to the memory (130), and when a designated time arrives after the first transmission delay time is determined, outputs a user interface (or a user interface that induces updating of the first transmission delay time to the second transmission delay time) through the display (160).

[0152] According to various embodiments, in determining the first transmission delay time, the processor (120) may be configured to write a test pattern into the memory (130), perform a read operation on the memory (130) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to the first refresh cycle, and determine the time during which a pattern identical to the test pattern is read as the first transmission delay time.

[0153] According to various embodiments, the processor (120) may be configured to determine a second transmission delay time based on a refresh interval (tREFI) corresponding to a third refresh cycle output from the memory (130) based on an input instructing an update with the second transmission delay time, apply the second transmission delay time to the refresh interval, and, when a fourth refresh cycle is output from the memory (130), delay the second transmission delay time by an offset of the second transmission delay time based on the refresh interval (tREFI) corresponding to the fourth refresh cycle and then transmit a second refresh command to the memory (130).

[0154] According to various embodiments, in determining the second transmission delay time, the processor (120) may be configured to write a test pattern into the memory (130), perform a read operation on the memory (130) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to the third refresh cycle, and determine the time during which a pattern identical to the test pattern is read as the second transmission delay time.

[0155] According to various embodiments, a memory system (200) includes a volatile memory (220) including a memory controller (221) configured to output a refresh cycle, and a processor (210) operatively connected to the volatile memory (132), wherein the processor (210) is configured to determine a transmission delay time (a) based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory controller (221), apply the transmission delay time (a) to the refresh interval, and, when a second refresh cycle is output from the memory controller (221), delay the refresh command by an offset of the transmission delay time (a) based on the refresh interval (tREFI) corresponding to the second refresh cycle and then transmit the refresh command to the volatile memory (220).

[0156] According to various embodiments, in determining the transmission delay time, the processor (210) may be configured to write a test pattern into the volatile memory (220), perform a read operation on the volatile memory (220) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to the first refresh cycle, and determine the time during which a pattern identical to the test pattern is read as the transmission delay time.

[0157] According to various embodiments, the memory system (200) includes a register (225) whose refresh cycle is updated at a specified cycle, and the processor (210) may be configured to store a second refresh cycle to which the transmission delay time (a) is applied in the register (225).

[0158] According to various embodiments, the refresh cycle of the register (225) can be updated according to the internal temperature of the volatile memory (220).

[0159] According to various embodiments, the processor (210) may be configured to obtain a refresh cycle that is repeated at a certain level among the refresh cycles output from the memory controller (221) for a specified period of time as the first refresh cycle.

[0160] According to various embodiments, the memory system (200) further includes a nonvolatile memory (134), and the processor (210) may be configured to store the transmission delay time in the nonvolatile memory (134) and apply the transmission delay time to a refresh interval (tREFI) corresponding to a refresh cycle output from the memory controller (221).

[0161]

[0162] FIG. 11 is a flowchart illustrating operations (1100) of a memory system (200) according to various embodiments. In connection with the operations described below through FIG. 11, reference may be made to the descriptions related to FIGS. 7 and 8. Furthermore, the operations in the embodiments below may be performed sequentially, but are not necessarily performed sequentially. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Furthermore, at least one of the aforementioned operations may be omitted depending on the embodiment.

[0163] Referring to FIG. 11, a memory system (200) (e.g., a host (210)) according to various embodiments may determine a transmission delay time based on a first transmission cycle (or refresh cycle) output from a memory (220) in operation 1110. The transmission delay time may be the time required for the charge stored in the memory device (223) to leak from the first transmission cycle to a level that causes data loss. According to one embodiment, the first transmission cycle may be a time point at which the host (210) transmits a first refresh command to the memory (220). For example, the first transmission cycle may be determined by a refresh cycle stored in a register (225).

[0164] According to various embodiments, the memory system (200) (e.g., the host (210)) may apply a transmission delay time to a transmission cycle output from the memory (220) in operation 1120. According to one embodiment, the memory system (200) (e.g., the host (210)) may apply a transmission delay time (e.g., an offset) to a refresh interval (tREFI) corresponding to a refresh cycle (refresh multiplier or refresh rate) stored in a register (225) (or a refresh cycle output from the memory (220). In this case, the memory system (200) (e.g., the host (210)) may not transmit the refresh command in the original transmission cycle and may postpone transmission of the refresh command by the transmission delay time.

[0165] According to various embodiments, the memory system (200) (e.g., host (210)) may transmit a refresh command (refresh command) to the memory (220) based on a second transmission cycle to which a transmission time output from the memory (220) is applied in operation 1130.

[0166]

[0167] FIG. 12 is a flowchart illustrating an operation (1100) for determining a transmission delay time of a memory system (200) according to various embodiments. With respect to the operations described in FIG. 12 , reference may be made to the description related to FIG. 9 . Furthermore, the operations in the following embodiments may be performed sequentially, but are not necessarily performed sequentially. For example, the order of the operations may be changed, and at least two operations may be performed in parallel. Furthermore, at least one of the aforementioned operations may be omitted depending on the embodiment.

[0168] Referring to FIG. 12, a memory system (200) (e.g., a host (210)) according to various embodiments may write a test pattern into a memory (220) in operation 1210. For example, the memory system (200) (e.g., a memory controller (221)) may include an operation of writing data of “1” (or “high”) into a memory cell (MC).

[0169] According to various embodiments, the memory system (200) (e.g., host (210)) may perform an operation of reading a test pattern based on a test cycle that increases at regular time intervals in operation 1220.

[0170] According to various embodiments, the memory system (200) (e.g., the host (210)) may determine the transmission delay time based on the time at which a pattern identical to the test pattern is read in operation 1230. For example, the memory system (200) (e.g., the host (210)) may determine the time required before a pattern different from the test pattern is read as the transmission delay time.

[0171]

[0172] An operating method of an electronic device (101) according to various embodiments may include an operation of determining a first transmission delay time based on a first refresh cycle output from a memory (130), an operation of applying the first transmission delay time to the refresh interval, an operation of transmitting a first refresh command to the memory (130) after delaying by an offset of the first transmission delay time based on a refresh interval (tREFI) corresponding to the second refresh cycle when a second refresh cycle is output from the memory (130), and an operation of outputting a user interface for updating the first delay time to a second transmission delay time (or a user interface for inducing updating the first delay time to a second transmission delay time) when a designated time arrives after the first transmission delay time is determined.

[0173] According to various embodiments, the operation of determining the first transmission delay time may include an operation of writing a test pattern into the memory (130), an operation of performing a read operation on the memory (130) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to the first refresh cycle, and an operation of determining a time during which a pattern identical to the test pattern is read as the first transmission delay time.

[0174] According to various embodiments, the operating method of the electronic device may include an operation of determining a second transmission delay time based on a refresh interval (tREFI) corresponding to a third refresh cycle output from the memory (130) based on an input instructing an update with the second transmission delay time, an operation of applying the second transmission delay time to the refresh interval, and an operation of transmitting a second refresh command to the memory (130) after delaying by an offset of the second transmission delay time based on the refresh interval (tREFI) corresponding to the fourth refresh cycle when a fourth refresh cycle is output from the memory.

[0175] According to various embodiments, the operation of determining the second transmission delay time may include an operation of writing a test pattern into the memory (130), an operation of performing a read operation on the memory (130) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to the third refresh cycle, and an operation of determining a time during which a pattern identical to the test pattern is read as the second transmission delay time.

[0176] A computer-readable recording medium according to various embodiments may execute an operation of writing a test pattern into a memory (220), performing a read operation on the memory (220) at each test cycle that increases at a predetermined time interval based on a refresh interval (tREFI) corresponding to a first refresh cycle output from the memory (220), determining a time during which a pattern identical to the test pattern is read as a transmission delay time, applying the transmission delay time to the refresh interval (tREFI) corresponding to the refresh cycle output from the memory (220), applying the transmission delay time to the refresh interval, and, when a second refresh cycle is output from the memory (220), delaying by an offset of the transmission delay time based on the refresh interval (tREFI) corresponding to the second refresh cycle and then transmitting the refresh command to the memory (220).

[0177] According to various embodiments, the computer-readable recording medium can obtain the first refresh cycle and the second refresh cycle from a register (225) in which the refresh cycle is updated at a specified cycle.

[0178] According to various embodiments, the computer-readable recording medium can obtain a first refresh cycle and a second refresh cycle corresponding to the internal temperature of the memory (220).

[0179] According to various embodiments, a computer-readable recording medium can obtain a refresh cycle that is repeated at a certain level among the refresh cycles output from the memory (220) for a specified time as the first refresh cycle.

[0180] According to various embodiments, the computer-readable recording medium stores the transmission delay time in a non-volatile memory (134), and when the second refresh cycle is output from the memory, the transmission delay time can be obtained from the non-volatile memory (134).

Claims

1. In an electronic device (101), display (160); Memory (130) storing the refresh cycle; and Includes a processor (120), The above processor (120) The first transmission delay time is determined based on the refresh interval (tREFI) corresponding to the first refresh cycle output from the above memory (130), Applying the above first transmission delay time to the above refresh interval, When the second refresh cycle is output from the memory (130), the first refresh command is transmitted to the memory (130) after delaying by the offset of the first transmission delay time based on the refresh interval (tREFI) corresponding to the second refresh cycle. An electronic device configured to output, through the display (160), a user interface for updating the first transmission delay time to a second transmission delay time when a designated time has arrived after the first transmission delay time has been determined.

2. In paragraph 1, In determining the first transmission delay time, the processor (120) Write a test pattern into the above memory (130), A read operation for the memory (130) is performed at each test cycle that increases at a certain time interval based on the refresh interval (tREFI) corresponding to the first refresh cycle. An electronic device configured to determine a time during which a pattern identical to the above test pattern is read as the first transmission delay time.

3. In paragraph 1, The above processor (120) Based on the input instructing update with the second transmission delay time, the second transmission delay time is determined based on the refresh interval (tREFI) corresponding to the third refresh cycle output from the memory (130), Applying the above second transmission delay time to the above refresh interval, An electronic device configured to transmit a second refresh command to the memory (130) after delaying by an offset of the second transmission delay time based on a refresh interval (tREFI) corresponding to the fourth refresh cycle when a fourth refresh cycle is output from the memory (130).

4. In paragraph 3, In determining the second transmission delay time, the processor (120) Write a test pattern into the above memory (130), A read operation is performed on the memory (130) at each test cycle that increases at a certain time interval based on the refresh interval (tREFI) corresponding to the third refresh cycle. An electronic device configured to determine a time during which a pattern identical to the above test pattern is read as the second transmission delay time.

5. In the memory system (200), A volatile memory (220) including a memory controller (221) configured to output a refresh cycle; and It includes a processor (210) operatively connected to the above volatile memory (132), The above processor (210) The transmission delay time (a) is determined based on the refresh interval (tREFI) corresponding to the first refresh cycle output from the above memory controller (221), Apply the above transmission delay time (a) to the above refresh interval, When the second refresh cycle is output from the memory controller (221), the refresh command is transmitted to the volatile memory (220) after delaying by an offset of the transmission delay time (a) based on the refresh interval (tREFI) corresponding to the second refresh cycle. In determining the above transmission delay time, the processor (210), Write a test pattern into the above volatile memory (220), A read operation is performed on the volatile memory (220) at each test cycle that increases at a certain time interval based on the refresh interval (tREFI) corresponding to the first refresh cycle. A memory system configured to determine the time during which a pattern identical to the above test pattern is read as the transmission delay time.

6. In paragraph 5, Includes a register (225) whose refresh cycle is updated at a specified cycle, The above processor (210) A memory system configured to store a second refresh cycle to which the transmission delay time (a) is applied in the register (225).

7. In paragraph 6, A memory system in which the refresh cycle of the register (225) is updated according to the internal temperature of the volatile memory (220).

8. In at least one of paragraphs 5 and 6, The above processor (210) A memory system configured to obtain a refresh cycle that is repeated at a certain level among the refresh cycles output from the memory controller (221) for a specified time as the first refresh cycle.

9. In paragraph 5, It further includes non-volatile memory (134), The above processor (210) The above transmission delay time is stored in the non-volatile memory (134), A memory system configured to apply the transmission delay time to a refresh interval (tREFI) corresponding to a refresh cycle output from the memory controller (221).

10. In a computer-readable recording medium, Write a test pattern into memory (220), A read operation is performed on the memory (220) at each test cycle that increases at a certain time interval based on the refresh interval (tREFI) corresponding to the first refresh cycle output from the memory (220). The time during which a pattern identical to the above test pattern is read is determined as the transmission delay time, The transmission delay time is applied to the refresh interval (tREFI) corresponding to the refresh cycle output from the above memory (220), Apply the above transmission delay time to the above refresh interval, A recording medium that executes an operation of transmitting the refresh command to the memory (220) after delaying by an offset of the transmission delay time based on a refresh interval (tREFI) corresponding to the second refresh cycle when the second refresh cycle is output from the memory (220). In Article 11.10, A recording medium that obtains the first refresh cycle and the second refresh cycle from a register (225) whose refresh cycle is updated at a specified cycle.

12. In paragraph 11, A recording medium that obtains a first refresh cycle and a second refresh cycle corresponding to the internal temperature of the above memory (220).

13. In at least one of paragraphs 10 and 11, A recording medium that acquires a refresh cycle that is repeated at a certain level among the refresh cycles output from the memory (220) for a specified period of time as the first refresh cycle.

14. In Article 10 The above transmission delay time is stored in nonvolatile memory (134), A recording medium that applies the transmission delay time to the refresh cycle output from the above memory.

15. In the operating method of an electronic device (101), An operation of determining a first transmission delay time based on a first refresh cycle output from a memory (130); An operation of applying the first transmission delay time to the refresh interval; When a second refresh cycle is output from the memory (130), an operation of transmitting a first refresh command to the memory (130) after delaying by an offset of the first transmission delay time based on a refresh interval (tREFI) corresponding to the second refresh cycle; and A method comprising the action of outputting a user interface for updating the first delay time to a second transmission delay time when a designated time has arrived after the first transmission delay time has been determined.

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