ADVANCED SUB-μm SEMICONDUCTOR MEMORY CHIP MANUFACTURING IN ZERO-GRAVITY ENVIRONMENT

Abstract

A method of manufacturing a semiconductor device comprising the steps of: providing an inkjet printer having a conductive nozzle in a zero gravity or microgravity environment; positioning a substrate at an outlet of the conductive nozzle; printing a metal material with the inkjet printer to form at least one metal layer on the substrate; and printing an insulating material with the inkjet printer to form an insulating layer on at least a portion of the first metal layer; wherein the conductive nozzle is configured to form a Taylor Cone with the metal material or the insulating material. Related devices are also disclosed.

Description

[0001] TITLE

[0002] Advanced Sub-pm Semiconductor Memory Chip Manufacturing In Zero-Gravity

[0003] Environment

[0004] CROSS-REFERENCE TO RELATED APPLICATIONS

[0005] This application claims priority to U.S. provisional application No. 63 / 580,885 filed on September 6, 2023, incorporated herein by reference in its entirety

[0006] STATEMENT OF GOVERNMENT SUPPORT

[0007] This invention was made with government support under 80NSSC23PB528 and 80NSSC24PA330 awarded by the National Aeronautics & Space Administration. The government has certain rights in the invention.

[0008] BACKGROUND OF THE INVENTION

[0009] With the exponential growth of data, advances in machine learning (ML) and artificial intelligence, and the digital transition of the workplace, the need to develop next-generation processors for the multitude of existing and growing number of digital devices is clear. Advanced functional chips are an important focus, because the more functional the integrated chip is in a system, the more powerful the performance it will provide.

[0010] There are several approaches that can be used. For example, one method is the chiplet, where the functional chips (e.g., Graphics processing unit, GPU; DRAM or SRAM L3 cache) are integrated close to the computing die (TSMC SoIC (System on Integrated Chips)). The advantage of this includes fast speed or decreased latency of data. However, process fabrication of such chips is currently cost prohibitive due to the advanced process node (e.g., 3nm) required EUV, or double patterning lithography methods that are required. Another method to integrate the functional chip can be processed by mature process nodes (e.g., Tower Semiconductor > 0.25pm; TSMC: 0.35pm). There is a focus on various spectrum nodes for CPU applications, but for the 3D stacking method, an alternative process or solution needs to be developed to reduce the cost / time compared to standard fabrication process while retaining high quality / reliability / performance. Another example is the strategic radiation hardened (SRH) non-volatile memory (NVM), which is currently employed within the various proposal agents across numerous space and strategic systems. The technology must be suitable to use in agents’ systems requiring trusted onshore fabrication. The SRH NVM needs to be scalable and support the design of a family of multi-chip modules (MCM) of different storage capacity. The resulting device should be capable of QML (qualified manufacturers list) qualification. For space QMLV (qualified manufacturers list verification) and QMLV-RHA (radiation hardness assurance), the radiation specification (total ionizing dose, TID) is needed from 50 krad to 300 krad for space electronics applications, and Advanced Next Generation Strategic Radiation hardened Memory (ANGSTRM) requires an even higher objective (i.e. > 1000 krad with restrained total operating power per memory device and less than lOmW, retention (w / o refresh) of 15 years and endurance required up to 1012cycles).

[0011] To achieve this using current manufacturing methods, it requires an incredibly costly system, utilizing hundreds of masks, and complex lithography, etching, and deposition / growth steps or stages. Thus, there is a need in the art for improved semiconductor manufacturing systems and methods. The present invention meets this need.

[0012] SUMMARY OF THE INVENTION

[0013] Some embodiments of the invention disclosed herein are set forth below, and any combination of these embodiments (or portions thereof) may be made to define another embodiment.

[0014] In another aspect, a method of manufacturing a semiconductor device comprises the steps of: providing an inkjet printer having a conductive nozzle in a zero gravity or microgravity environment; positioning a substrate at an outlet of the conductive nozzle; printing a metal material with the inkjet printer to form at least one metal layer on the substrate; and printing an insulating material with the inkjet printer to form an insulating layer on at least a portion of the first metal layer; wherein the conductive nozzle is configured to form a Taylor Cone with the metal material or the insulating material.

[0015] In one embodiment, the at least one metal layer is at least two parallel layers separated by a gap, and wherein the insulating layer is further printed onto the substrate within the gap.

[0016] In one embodiment, the insulating layer is free of voids.

[0017] In one embodiment, the insulating layer has a thickness of than 200 nm.

[0018] In one embodiment, the inkjet printer is an electrohydrodynamic inkjet printer.

[0019] In one embodiment, a feature size of the at least one metal layer is in the range of 50 nm to 200 pm.

[0020] In one embodiment, a feature size of the at least one insulating layer is in the range of 50 nm to 200 pm.

[0021] In one embodiment, the method further comprises the step of printing a ZnO nanoparticle ink with the inkjet printer.

[0022] In one embodiment, the method further comprises the step of printing a ZnO reactive ink with the inkjet printer.

[0023] In one embodiment, an ink used for the printing has at least one of a conductivity of 0.01 S to 0.33 S, a viscosity of 8 cP to 14 cP.

[0024] In another aspect, a semiconductor device comprises a semiconductor device produced via the above method.

[0025] In another aspect, a method of manufacturing a ReRAM, comprising the steps of: providing an inkjet printer having a conductive nozzle in a zero gravity or microgravity environment; positioning a substrate at an outlet of the conductive nozzle; printing a first insulating material with the inkjet printer to form a first insulating layer on the substrate; printing a first metal material with the inkjet printer to form a first plurality of parallel metal layers on at least a portion of the first insulating layer; printing a second insulating layer with the inkjet printer to form a second insulating layer on at least a portion of the first plurality of parallel metal layers; printing a second metal material with the inkjet printer to form a second plurality of parallel metal layers on at least a portion of the second insulating layer; printing a third insulating material with the inkjet printer to form a third insulating layer on at least a portion of the second plurality of parallel metal layers; printing a dielectric material with the inkjet printer to form a dielectric layer on at least a portion of the third insulating layer; and printing a third metal material with the inkjet printer to form a third plurality of parallel metal layers on at least a portion of the dielectric layer.

[0026] In one embodiment, adjacent stacks of first metal layer, second insulating layer, second metal layer and third insulating layer are separated by gaps.

[0027] In one embodiment, a portion of the dielectric layer is in contact with the first insulating layer within one of the gaps.

[0028] In one embodiment, at least a portion of the third plurality of parallel metal layers is printed onto the first insulating layer or the dielectric layer within one of the gaps. In one embodiment, the inkjet printer is an electrohydrodynamic inkjet printer. In one embodiment, a feature size of the first, second, or third plurality of parallel metal layers is in the range of 50 nm to 200 pm.

[0029] In one embodiment, a feature size of the first, second, or insulating layers is in the range of 50 nm to 200 pm.

[0030] In one embodiment, a feature size of the dielectric material is in the range of 50 nm to 200 pm.

[0031] In another aspect, a ReRAM comprises a ReRAM is produced via the above method.

[0032] BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The following detailed description of embodiments of the invention will be better understood when read in conjunction with the appended drawings. It should be understood, however, that the invention is not limited to the precise arrangements and instrumentalities of the embodiments shown in the drawings.

[0034] Fig. 1A is a set of images depicting existing PVD and CVD process manufacturing defects (voiding effect). Fig. IB depicts the technical improvement of the disclosed inkjet-based inventive system and method, and patterned silicon prepared for voiding and coverage verification in zero gravity (0-g) or micro gravity (p-g) environments.

[0035] Fig. 2A and Fig. 2B are a set of images depicting space enabled advanced devices and semiconductors. Inkjet printing for 3-dimensional ReRAM memory (no etching process required) and manufacturing flow in a 0-g / p-g environment is also shown.

[0036] Fig. 3 A - Fig. 3E are a set of images and data depicting metal oxide-based ReRAM devices with CMOS compatible materials for SEADS. Shown are simple stacked structures (Fig. 3A), mask-lite process (Fig. 3B), DC I-V memory characterization (Fig. 3C), and endurance (Fig. 3D) and retention (Fig. 3E) reliability performance. The performance met part of the ANGSTRM requirement (total operation power per memory device about 2mW; post-TID retention sustained to 15yrs; TID: 5M rad (Si)) and even beyond the specification (ISSRDC 2022 and ISSRDC 2023).

[0037] Fig. 4A - Fig. 4E are a set of images depicting the scaling capability of inkjet printing technology examined by patterned silicon. Graphene oxide ink and Ag inked on u -trench is shown in Fig. 4C. Defect-less and non-uniformity of coverage were confirmed in a gravity environment.

[0038] Fig. 5A - Fig. 5D show basic DC I-V electrical characterization: linear- as-dep (Fig. 5A), post-lM radiation (Fig. 5B), post-2M radiation (Fig. 5C), and post-5M radiation (Fig. 5D) behaviors of a HfOx / RuOx ReRAM device.

[0039] Fig. 6 shows the correlation of “Drift” (current shifting ratio, %) behaviors with pre-rad current states in control (no radiation, time only), post-rad (50k-400k), and postrad (1M-5M) in HfOx / RuOx ReRAM devices.

[0040] Fig. 7 shows memory window vs. various radiation conditions (pre-rad / post- rad / TID dose), in HfOx / RuOx ReRAM devices (data including at least 15 devices per TID dose, and 10 switching cycles per devices).

[0041] Fig. 8 shows PHITS (Particle and Heavy Ion Transport Code System) Monte Carlo simulation results in TiN / Ti / HfOx / RuOx / TiN ReRAM devices. The radiation induced energy is deposited clearly on the HfOx layer in the stack of the HfOx / RuOx ReRAM devices.

[0042] Fig. 9A - Fig. 9D show technical improvement of materials-related p-g impacts in inkjet printing technology (ink preparation, manufacturing, applications, and chip product). Fig. 9A shows the ink preparation stage before printing, Fig. 9B shows the manufacturing stage, Fig. 9C shows the application stage after printing, and Fig. 9D shows the product stage.

[0043] Fig. 10 shows in-space Electrohydrodynamic Inkjet Printer (In-space EHD Printer.

[0044] Fig. 11 shows successful TRL validations of the In-space EHD printer under microgravity via parabolic flight tests. Designed patterns were printed using silver nanoink in 10 consecutive parabolas. Barium Titanate Oxide nanoinks were also EHD- printed.

[0045] Fig. 12 and Fig. 13 show how the in-space EHD Printer utilizes electrical forces to drive the material flow creating micro-structures of p-g printed patterns in a denser structure with fewer pores (Fig. 12), where a higher resolution was achieved, and how EHD printing could print various materials for 2D and 3D structure in the range of 200 nm to 300 pm (Fig. 13).

[0046] Fig. 14A and Fig. 14B show a semiconductor thin fdm and functional layer, Zinc oxide (ZnO) nanoparticle-based and reactive inks considered for EHD printing (Fig. 14A) and XRD results between reactive ink-A and reactive ink-B with various sintering conditions (Fig. 14B). Reactive ink-A (implemented as active layer on devices) has better crystallinity (-43% improvement) as compared to reactive ink-B.

[0047] Fig. 15 shows a high aspect ratio (HAR) trench design and process (top), post OPL mask open (bottom left), and final structure (bottom right) used to examine the inks gap-filling capability and impact of the 0-g / p-g environment.

[0048] Fig. 16 shows CVD sputter deposition (top), PVD growth (middle), and Ag Inkjet printing (bottom) on HAR trenches. The red circles identify gap filling defects.

[0049] Fig. 17 shows Ag Inkjet printing with print-up-sintering-up, “positive” gravity (top), and Ag Inkjet printing with print-up-sintering-down, “negative” gravity (bottom).

[0050] Fig. 18A - Fig. 18D shows details of a RRAM device, including a RRAM device design (Fig. 18 A), all-printed metal-insulator-metal test structures by EHD printer (Fig. 18B), current-voltage (I-V) characteristics (Fig. 18C) and SCLC current transport behaviors on ZnO printed RRAM devices (Fig. 18D). Fig. 19 shows Inkjet Printing for 3-Dimensional ReRAM memory (no etching process required) and manufacturing in 0-g / p-g environment. Technical improvement of inkjet printing in trenching filling, no defective voids observed, and expected 0-g / p-g environment can provide better conformity (thinner in the bottom trench) to enable the maskless, etching-free process for 3D memory and advanced sub-pm semiconductor devices.

[0051] DETAILED DESCRIPTION

[0052] It is to be understood that the figures and descriptions of the present invention have been simplified to illustrate elements that are relevant for a clear understanding of the present invention, while eliminating, for the purpose of clarity many other elements found in related systems and methods. Those of ordinary skill in the art may recognize that other elements and / or steps are desirable and / or required in implementing the present invention. However, because such elements and steps are well known in the art, and because they do not facilitate a better understanding of the present invention, a discussion of such elements and steps is not provided herein. The disclosure herein is directed to all such variations and modifications to such elements and methods known to those skilled in the art.

[0053] The invention is further described in detail by reference to the following experimental examples. These examples are provided for purposes of illustration only and are not intended to be limiting unless otherwise specified. Thus, the invention should in no way be construed as being limited to the following examples, but rather, should be construed to encompass any and all variations which become evident as a result of the teaching provided herein.

[0054] Without further description, it is believed that one of ordinary skill in the art can, using the preceding description and the following illustrative examples, make and utilize the present invention and practice the claimed methods. The following working examples therefore are not to be construed as limiting in any way the remainder of the disclosure.

[0055] Definitions Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains. Although any methods and materials similar or equivalent to those described herein can be used in the practice for testing of the present invention, exemplary materials and methods are described herein. In describing and claiming the present invention, the following terminology will be used.

[0056] It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting.

[0057] The articles “a” and “an” are used herein to refer to one or to more than one (i.e., to at least one) of the grammatical object of the article. By way of example, “an element” means one element or more than one element.

[0058] “About” as used herein when referring to a measurable value such as an amount, a temporal duration, and the like, is meant to encompass variations of ±20%, ±10%, ±5%, ±1%, or ±0.1% from the specified value, as such variations are appropriate.

[0059] The terms “patient,” “subject,” “individual,” and the like are used interchangeably herein, and refer to any animal amenable to the systems, devices, and methods described herein. The patient, subject or individual may be a mammal, and in some instances, a human.

[0060] Ranges: throughout this disclosure, various aspects of the invention can be presented in a range format. It should be understood that the description in range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 2.7, 3, 4, 5, 5.3, and 6. This applies regardless of the breadth of the range.

[0061] As contemplated herein, the present invention relates in part to an ink-jet based system and method to produce sub-micron semiconductor chips in a zero-gravity and / or micro-gravity environment. In some embodiments, the method is mask-less and / or etch- less, and scalable as a high throughput technique to produce 3D resistive random-access memory (ReRAM) devices or similar. In some embodiments, the method is an all-in-one inkjet printing technology requiring very little or otherwise limited space compared to space requirements of conventional systems and methods. In some embodiments, the method can be performed in a gravitational force range of 0 g to 1 g (9.8 m / s2). This small space requirement for the inventive methods are particularly suitable and configured for use in low earth orbit (LEO) and / or a space environment. In some embodiments, the system and method may further enable the development of a robust commercial space economy in low-Earth orbit that will create terrestrial and on-orbit high-quality jobs and stimulate sustainable non-NASA utilization of future commercial LEO destinations and orbital platforms. Accordingly, the inventive system and methods are a significant and unexpected improvement over conventional chip production techniques that require multi-step, cleanroom processes, which require multiple high cost components of equipment.

[0062] In some embodiments, the disclosed system and method utilize inkjet printing suitable and configured for advanced sub-pm semiconductor chip manufacturing in zerogravity and / or low gravitational force environments. In some embodiments, the feature size of a device produce by the method can be as small as 50 um by 50 um square. Thus, the inventive inkjet printing system presented herein is a promising alternative process for manufacturing companies in that it provides a non-contact (defect reduction), direct printing (mask-less) method, and etching-free process. Also, for wafer-level manufacturing, the system and method includes a highly integrated printing method and can be scalable, where several nozzles can be utilized simultaneously to print at production. Furthermore, the inkjet printing system and method described herein can also be used to replace established subtractive process sequences, reducing waste, energy consumption, and making electronics production more ecological, and more economical at the same time. The 0-g / p-g (zero-gravity or microgravity) environment of the system and method described herein provides beneficial effects on inkjet printing technology that can provide better trench filling and conformity, and less voiding defects for advanced sub-pm semiconductor manufacturing in a 0-gravity environment. Moreover, in-space or LEO manufacturing could potentially solve the current chip shortage issues / crisis in USA and meet onshore fabrication requirements. Tn some embodiments, the system and method of the present invention utilize 0-g / p-g environments to reduce or eliminate defects (voiding) and provide coverage improvements in high aspect ratio trenches.

[0063] Fig. 1 A shows a conventional Atmospheric Pressure Chemical Vapor Deposition (APCVD), Low-Pressure Chemical Vapor Deposition (LPCVD) or Physical Vapor Deposition (PVD) process manufacturing defects. Voids are created due to the growth / deposition mechanism independent with the vacuum with or without gravity, specifically at the top corner regions in high aspect ratio trenches (HAR). Voids will be formed using conventional methos such as CVD, PVD, or similar. With printing, the void formation issue can be eliminated which is preferred for semiconductor process.

[0064] As shown in Fig. IB, inkjet printing of a semiconductor device in a 0-g or p-g environment provides superior HAR filling, conformity, and avoids voiding (vs. APCVD / LPCVD / PVD), thereby enabling the manufacturing process to be maskless and / or etching-free. Coverage is also improved using 0-g and p-g printing. In some embodiments and also as shown in Fig. IB, inkjet printing in a 0-g or p-g environment intrinsically reduces the thickness (d) at the bottom trench which allows the manufacturer to eliminate the etching process needed in the traditional CMOS processes for simple stacked architecture design used in 3-dimensional memory and advanced sub-pm semiconductor devices.

[0065] Fig. 2A and Fig. 2B shows an exemplary inkjet printing manufacturing process flow and a resulting device structure in a 0-g or p-g environment for a semiconductor device, such as a 3D ReRAM (resistive random-access memory) device without any etching process requirement. This enables the Space Enabled Advanced Devices and Semiconductors (SEADS) by inkjet printing for advanced sub-pm semiconductor chip manufacturing in a 0-g or p-g environment (IP-pCHIP), which reduces the manufacturing time and cost, as well as the area savings per memory bit cell in Power- Performance- Area-Cost (PPAC) analysis. In some embodiments the device is directly printed (i.e. maskless), and / or the process is etching free. In one embodiment, the device includes area saving per memory bit cell of 4F2 / N where F is the pitch size and N is the stack layer, due to the manufacturing method.

[0066] As shown in Fig. 2A, with the resulting structure shown in Fig. 2B, the method includes printing a first insulator layer 201 (II) on a substrate in a 0-g or p-g environment, followed by printing a first metal layer 202 (Ml) on the first insulator layer in a 0-g or p-g environment, followed by printing a second insulator layer 203 (12) on the Ml layer in a 0-g or p-g environment, followed by printing a second metal layer 204 (M2) on the second insulator layer in a 0-g or p-g environment, and followed by printing a third insulator layer 205 (13) on the M2 layer in a 0-g or p-g environment. It should be appreciated that any number N of insulator (IN) and / or metal (MN) layers may be printed in the 0-g or p-g environment, and each layer may cover a portion of, or all of, the underlying layer or layers. The direction of printing can be the same or different for each subsequent layer. Next, a dielectric layer 206 is printed on at least a portion of, or all of, the top layer of the insulator / metal layer set. Lastly, a top metal layer 207 (M3) is printed on top of the dielectric layer in a 0-g or p-g environment. In some embodiments, additional layers and / or interlayers comprising, for example, PDMS and / or ZnO, are also included.

[0067] In some embodiments, the present system and method provides for semiconductor chip performance boosting and cost reduction in the LEO / space environment. As contemplated herein, 0-g / p-g environment in LEO / ISS / CLDs surprisingly and unexpectedly permits for the maskless, etching-free process for 3 -dimensional memory and advanced semiconductor devices as well as scaling capability (better trench filling and conformity, and fewer voiding defects) as compared to existing technology. Fig. 3 A shows a schematic of an exemplary HfOx-based ReRAM device (TiN / Ti / HfOx / RuOx / TiN) and Fig. 3B shows an image of patterned devices examined by optical microscope (OM). The fabrication process flow comprises a CMOS process (e.g., PVD / ALD) and shadow mask. As shown in Fig. 3 A - Fig. 3E, HfOx-based ReRAM devices have been fabricated by CMOS-compatible materials and mask-lite processes (e.g., shadow mask), which enables a manufacturing flow with a maskless, etching-free process via a direct printing process for 3 -dimensional memory fabricated in LEO / ISS / CLDs. In some embodiments, the disclosed methods and systems may be used to improve the PPAC in current commercial products, for example by using PVD and CVD processes in HAR trenches in place of existing CMOS processes and technologies, which may cause defects and voids in HAR stacked structures. Compared to the inkjet printing process, the graphene oxide and Ag ink process shown in Fig. 4A - 4E demonstrates that the inks can flow / fill into the trench well without any defects. Further, the inkjet process in a 0-g or p-g environment provides surprisingly and unexpectedly better HAR trench coverage and conformity with a thinner layer or smaller value. This is shown in the images of Fig. 4C, as well as the comparative diagrams in Fig. 4D and Fig. 4E. Fig. 4D shows a diagram that illustrates a thinner deposit (d) when the ink is printed in a zero gravity or microgravity environment. Fig. 4D shows improved coverage versus Fig. 4E, which shows a diagram of coverage in a gravity environment. The thicker deposition profile (D in Fig. 4E is greater than d in Fig. 4D) necessitates etching, which adds to cost and complexity as discussed herein. Ultimately, the SEADS may be designed as functional chips through Foveros and SoIC on Intel / TSMC next generation processors.

[0068] Strategic Radiation Hardened (SRH) non-volatile memory (NVM) is currently employed within numerous space and strategic systems. In some embodiments, the disclosed technology is suitable to use in systems requiring trusted onshore fabrication. The SRH NVM may be scalable and may support the design of a family of Multi-Chip Modules (MCM) of different storage capacities. The device may be capable of QML (qualified manufacturers list) qualification. For space QMLV (qualified manufacturers list verification) and QMLV-RHA (radiation hardness assurance), a radiation specification (total ionizing dose, TID) is needed from 50 krad to 300 krad for space electronics applications, and Advanced Next Generation Strategic Radiation hardened Memory (ANGSTRM) requires an even higher greater than 1000 krad with restrained total operating power per memory device less than lOmW, retention (w / o refresh) of 15 years and endurance required up to 1012cycles. Resistive random-access memory (ReRAM) using various metal oxides (i.e., SiCh, HfCh, TiCh, AI2O3) have attracted a great deal of attention since the current nonvolatile memory (NVM) and embedded-NVM approach scaling limits. The disclosed systems and methods are applicable in almost all engineering fields including but not limited to computational logic circuits, memory circuits, neuromorphic applications, and artificial intelligence. ReRAM also has great potential (density > 32Gb, endurance ~1012cycles) for aerospace, military, and nuclear industry applications, probable radiation sources include X-ray and gamma-ray radiation, protons, energetic electrons, and heavy-ion bombardment. The disclosed systems include HfOx-based ReRAM devices (TiN / Ti / HfOx / RuOx / TiN) fabricated with CMOS- compatible materials via mask-lite process (e.g., shadow mask), enabling a manufacturing flow with maskless, etching-free processes by directly printing 3- dimensional memory fabricated in low earth orbit (LEO), International Space Station (ISS), and commercial LEO destinations (CLDs). The effect of gamma-ray irradiation (IM ~ 5M rad) included shifting states (sometimes called “drift”) and the effect matched the memory window without any further degradation due to a filament-type switching mechanism rather than charge-trapping memory, supported by PHITS (Particle and Heavy Ion Transport Code System) Monte Carlo simulation results. Disclosed herein is a 3D fabrication process leveraging the ISS microgravity (p-g) environment with an inkjet printing technology, which demonstrates potential in-space manufacturing with an efficient footprint and cost reduction for advanced devices fabricated in LEO (e.g., Space Enabled Advanced Devices and Semiconductors, SEADS).

[0069] Fig. 5A - Fig. 5D show I-V characterizations (Pre- / Post- radiation) - 60Co y ray treatment was used as the radiation source to investigate the total ionizing dose (TID) effects on the devices (IM ~ 5M rad). Fig. 6 shows the shifting of states (or “drift”) between pre- and post-radiation with the correlation of pre-radiation states. The data points for control devices show only the time relaxation process without any radiation (open circles), which is used as the baseline to characterize and decouple the impact of gamma irradiation on HfOx-based ReRAM devices (marked Rad-RuOx (50k-400k) and Rad-RuOx (1M-5M) from time-induced relaxation. Fig. 7 shows the memory window characterizations of post-gamma irradiation (from 50k-5M rad) devices. As shown, the memory window increases by twice as much compared to the pre-radiation condition (50k-400k) then slightly degrades or matches (1M-5M). Note that the switching parameters did not show major degradation as compared to prior work except the variability increasing. To further understanding the radiation impact on stacked structures in HfOx-based ReRAM devices, a PHITS (Particle and Heavy Ion Transport Code System) Monte Carlo simulation was performed, with the results shown in Fig. 8. The HfOx layer in the stack of the HfOx / RuOx ReRAM devices was exposed to radiation induced energy, where it may change the device characterizations in a variety of ways (good or bad direction, as shown in Fig. 7). Table 1 below shows a comparison of gamma irradiation between published literature and the disclosed device. In summary, the work demonstrated herein met part of the ANGSTRM requirement (total operation power per memory device ~2mW; post-TID retention sustained to 15yrs; TID: 5M rad (Si)) and even went beyond the specification requirement by surpassing the required IM rad to a higher dose of 5M rad, thus showing superior results upon higher radiation stress. Additionally, further experiments were performed which focused on the 3D fabrication process by leveraging parabolic flight and ISS microgravity (p-G) environments for potential in-space semiconductor manufacturing with an efficient footprint and cost reduction for SEADS.

[0070] Table 1

[0071] Developing an inkjet printer technology for semiconductor device manufacturing in ISS / CLDs provides a significant improvement in the quality of life for people on Earth by providing a superior quality of thin films, which are commonly grown on earth (shown in Fig. 9A- Fig. 9D, sample preparation and manufacturing stages). This technology enables the manufacturing of advanced functional chips and devices using for example a mask-free, etching-free process, by enabling better trench filling, and avoiding the CVD-voiding effect (i.e. defect-reduction) as disclosed herein. Fig. 9A-Fig. 9D show ink properties, crystallinity, microelectronics, computational applications, and improved Power-Performance- Area-Cost (PPAC) by leveraging the 0-gravity environment for in- space electronics manufacturing and product design.

[0072] In the ink preparation stage (Fig. 9A) microgravity removes convection, sedimentation, and buoyancy that can disrupt physical and chemical processes. This leads to less aggregation and sedimentation of colloidal active materials thus providing higher stability and longer ink shelf life. The higher stability allows for more loading of active materials (i.e. less additives).

[0073] In the manufacturing stage (Fig. 9B) diffusion and surface tension dominant processes provide for more uniform structures at the individual molecular level. In printing, microgravity leads to less spread of the printed layers leading to higher resolution. In crystal growth, microgravity leads to bigger crystal size with fewer defects thus increasing quality.

[0074] In the application stage (Fig 9C), for printing, a higher concentration of the active material in the inks provides for superior performance and operation stability. In crystal growth, the higher quality crystals provide for superior efficiency and lifetime of the devices. Further, multilayer and multi -material fabrication is able to be performed to form integrated systems with multiple functional devices.

[0075] In the product stage (Fig. 9D) physical and electrical modeling of the printing design rules, transistor / RC extraction, and reliability modeling for product end-of-life usage projections are performed. EDA tools or collaboration for building blocks and supplemental libraries can also be implemented. Space foundry, Fablab for in-space, and LEO manufacturing with CLDs can also be implemented.

[0076] Fig. 10 shows an in-space EHD printer where printing applies an electrical force through the ink via a conductive nozzle to create a Taylor Cone. The Taylor Cone allows the ink to overcome the surface tension at the nozzle and be drawn into droplets with a smaller diameter than the nozzle itself. It allows small droplets to pinch off from the meniscus creating conductive patterns as small as 50 nm to 200 pm. To successfully achieve this phenomenon, EHD printing requires a precise set of process parameters: flow rate, applied voltage, nozzle to substrate stand-off distance, platform speed, and specific ink characteristics (conductivity, viscosity, surface tension, etc.). Currently, there are no such relative tools available at ISS R&D, thus the EHD system is the best fit for several reasons. (1) To date, most 3D printing techniques cannot be operated in a gravity- free environment because gravity is one of the dominating factors for successful printing, which relies on mechanisms such as liquid or powder forced flow. EHD printing utilizes electrical force to drive liquid ink deposition and achieve 3D printing in gravity-free environments. In three previous parabolic flight campaigns, the disclosed lab-built EHD system was demonstrated successfully at TRL 4-6 (Fig. 11). (2) EHD printing is an emerging Additive Manufacturing (AM) process that allows the fabrication of electrical components at the micro and even nano scale. For most traditional inkjet printing technologies, the printing dimension is limited by the nozzle size (best resolution ~10 pm). In EHD printing, a Taylor cone is formed, and droplets are generated at the tip of the liquid cone shape. The generated droplets are much smaller than the nozzle size (usually 1 :7 droplet size over nozzle size). EHD printing is capable of fabricating functional devices at a resolution ranging from sub-100 nm to 200 pm (Fig. 12 and Fig. 13).

[0077] An ultrasmall nanoparticle dispersion and reactive ink solution was also developed. The ultrasmall nanoparticle ink is a stable dispersion of ZnO particles less than 10 nm in diameter. Fig. 14A shows the scale of the ZnO particles in the ultrasmall nanoparticle ink in a TEM micrograph. ZnO nanoparticle ink has ultra-small particle size, provides for smooth printing, and provides for a uniform and continuous film, however it can also have carbon contamination, can be challenging in regards to stability, and may cause possible nozzle clogging. As an alternative, ZnO reactive ink has no nozzle clogging issues, provides for smooth printing, and provides for various solvent options, however it may include impurities due to low temperature sintering, thick films are hard to achieve, and may have issues with film continuity. In some cases, the reactive ink is completely particle free and undergoes decomposition upon heating, leaving behind a ZnO product as demonstrated by XRD results in Fig. 14B of a ZnO layer deposited on a substrate coated with reactive ink following heat treatment. Furthermore, the results suggest the ability to control crystallite size through solvent selection with reactive ink A showing a higher level of crystallinity than reactive ink B. The reactive inks produce an ultra-stable solution due to its total exclusion of solid content which also serves to avoid nozzle clogging that could be brought about due to aggregation of nanoparticle-based inks. Both inks were able to print smoothly and successfully. Due to the minimal risk of aggregation and nozzle clogging, its far greater level of stability and, its greater potential in applications requiring high levels of resolution when printing, such as printing into or between existing features, ZnO reactive ink was ultimately chosen for final testing.

[0078] Fig. 15 shows the design and process flow for high aspect ratio (HAR) Si trench structures. Herein, the aspect ratio of a trench is about 10 which is the testing vehicle for examining the inks’ gap-filling capability, and the impact of the 0-g / p-g environment. Fig. 16 (top and middle) show the conventional chemical vapor deposition (CVD, Si3N4) or physical vapor deposition (PVD, Si Oc) process manufacturing defects, called “voiding effect”, i.e., the top thin film has merged due to the nonuniform deposition, in that higher deposition volume caused film closure on the top, which subverts the very large-scale integration (VLSI) process and leads to open circuit failure on interconnect applications. This phenomenon is independent of vacuum level and gravity level. The defective voids can be viewed clearly in the middle of the devices made by the PVD process as well as the CVD process. That indicates that conventional semiconductor process development on HAR trench structures is hindered, even in vacuum and 0-g / p-g process environments. In inkjet printing technology, thanks to surface tension (i.e., with no impact from or independent of gravity), the trench filling is quite uniform even at 200 nm pitch size (50 nm in width, Ag inks coated by EHD printer). Fig. 16 (bottom) shows that there is no voiding effect as compared to existing technology in the inkjet printing process in sub- pm semiconductor manufacturing process. Meanwhile, the technical improvement of inkjet in 0-g / p-g environment provides better HAR filling conformity. To further confirm the gravity impact and modeling on inks, “print-up-sintering-up” (f positive” gravity), and “print-up-sintering-down” (f negative” gravity) were performed. Fig. 17 shows SEM images of “ positive” gravity and “negative” gravity devices. In negative gravity, the printed thin film was modulated by gravity (i.e., inks accumulated on the trench top) rather than fully dominated by the surface tension. This depicts one technical improvement of inkjet in 0-g / p-g environment, in that it provides better HAR filling conformity, enabling a maskless, etching-free process for 3-dimensional memory and advanced sub-pm semiconductor devices.

[0079] To validate the basic layers’ functionality for parabolic flight and ISS implementation, a simple test structure was designed (Ag / ZnO / Ag crossbar), shown in Fig. 18A - Fig. 18B. The ZnO reactive ink-A shows better switching characteristics as compared to ZnO ink-B (no switching), which results from the crystallinity -level improvement in ZnO reactive ink-A. Fig. 18C - Fig. 18D further show the resistive switching characteristics of the devices (>10 samples). The forming voltage is around 0.72V with 2.2 mA indicating a forming-free process; the switching voltage is below IV for both SET and RESET process at low voltage operation. Current transport behaviors are dominated by space charge-limited current (SCLC) for both LRS and HRS (R2of 99%). The disclosed resistive random-access memory (RRAM) device shows quite low voltage requirements for larger array design as compared to other inkjet printing memories and better than those which use conventional PVD processes (required forming process). Table 2 below shows a benchmark ZnO and inkjet printed memory performance comparison.

[0080] Table 2

[0081] Fig. 19 shows an inkjet printing process for manufacturing 3D RRAM device structures in 0-g / p-g environments without etching process requirements due to better conformity coverage. In existing processes, due to the thicker deposit in the bottom trench (noted as “weight effect”), the bottom memory cell will not work unless an additional etching process is implemented (e.g., etch-back process), which results in a significant increase in fabrication cost, process complexity, and equipment expenditure in the IS S) Also, it subverts semiconductor memory scaling due to inefficient area per memory cell (fewer stacked layers). In a PPAC (Power-Performance- Area-Cost) analysis, the disclosed inkjet printing technology can eliminate the photolithography process as well as reduce or eliminate the mask cost (4 masks with the same manufacturing process). Furthermore, the disclosed technology mitigates the requirement for etching post-deposition and reduces the process complexity. As a result, SEADS and in-space manufacture become more ecological and more economical by leveraging 0-g / p-g environments in the ISS. The disclosed method takes a phased approach to the development of proof-of-concept production systems that can be well-facilitated in space manufacturing of advanced functional chips like computational nonvolatile memory (NVM) devices.

[0082] In conclusion, a flight-ready EHD inkjet printing technology for device microfabrication in lower orbit was developed, and the gravity impact in the advanced sub -pm semiconductor process flow and device integrated design was evaluated. A study on the ISS using an EHD printer to print NVM device structures in orbit would enable inspace electronics manufacturing.

[0083] The disclosures of each and every patent, patent application, and publication cited herein are hereby incorporated herein by reference in their entirety. While this invention has been disclosed with reference to specific embodiments, it is apparent that other embodiments and variations of this invention may be devised by others skilled in the art without departing from the true spirit and scope of the invention. The appended claims are intended to be construed to include all such embodiments and equivalent variations.

Claims

CLAIMSWhat is claimed is:

1. A method of manufacturing a semiconductor device, comprising the steps of: providing an inkjet printer having a conductive nozzle in a zero gravity or microgravity environment; positioning a substrate at an outlet of the conductive nozzle; printing a metal material with the inkjet printer to form at least one metal layer on the substrate; and printing an insulating material with the inkjet printer to form an insulating layer on at least a portion of the first metal layer; wherein the conductive nozzle is configured to form a Taylor Cone with the metal material or the insulating material.

2. The method of claim 1, wherein the at least one metal layer is at least two parallel layers separated by a gap, and wherein the insulating layer is further printed onto the substrate within the gap.

3. The method of claim 2, wherein the insulating layer is free of voids.

4. The method of claim 2, wherein the insulating layer has a thickness less than 200 nm.

5. The method of claim 1, wherein the inkjet printer is an electrohydrodynamic inkjet printer.

6. The method of claim 1, wherein a feature size of the at least one metal layer is in the range of 50 nm to 200 pm.

7. The method of claim 1, wherein a feature size of the at least one insulating layer is in the range of 50 nm to 200 pm.

8. The method of claim 1 , further comprising the step of printing a ZnO nanoparticle ink with the inkjet printer.

9. The method of claim 1, further comprising the step of printing a ZnO reactive ink with the inkjet printer.

10. The method of claim 1, wherein an ink used for the printing has a conductivity of 0.01 S to 0.33 S.

11. The method of claim 1, wherein an ink used for the printing has a viscosity of 8 to 14 cP.

12. A semiconductor device produced by the method of claim 1.

13. A method of manufacturing a ReRAM, comprising the steps of: providing an inkjet printer having a conductive nozzle in a zero gravity or microgravity environment; positioning a substrate at an outlet of the conductive nozzle; printing a first insulating material with the inkjet printer to form a first insulating layer on the substrate; printing a first metal material with the inkjet printer to form a first plurality of parallel metal layers on at least a portion of the first insulating layer; printing a second insulating layer with the inkjet printer to form a second insulating layer on at least a portion of the first plurality of parallel metal layers; printing a second metal material with the inkjet printer to form a second plurality of parallel metal layers on at least a portion of the second insulating layer; printing a third insulating material with the inkjet printer to form a third insulating layer on at least a portion of the second plurality of parallel metal layers; printing a dielectric material with the inkjet printer to form a dielectric layer on at least a portion of the third insulating layer; and printing a third metal material with the inkjet printer to form a third plurality of parallel metal layers on at least a portion of the dielectric layer.

14. The method of claim 13, wherein adjacent stacks of first metal layer, second insulating layer, second metal layer and third insulating layer are separated by gaps.

15. The method of claim 14, wherein a portion of the dielectric layer is in contact with the first insulating layer within one of the gaps.

16. The method of claim 15, wherein at least a portion of the third plurality of parallel metal layers is printed onto the first insulating layer or the dielectric layer within one of the gaps.

17. The method of claim 13, wherein the inkjet printer is an electrohydrodynamic inkjet printer.

18. The method of claim 13, wherein a feature size of the first, second, or third plurality of parallel metal layers is in the range of 50 nm to 200 pm.

19. The method of claim 13, wherein a feature size of the first, second, or insulating layers is in the range of 50 nm to 200 pm.

20. A ReRAM produced by the method of claim 13.

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