Memory extension method and system, chip and storage medium

Abstract

A memory extension system, comprising: a last level cache controller, and a DDR controller and a CXL controller that are connected to the last level cache controller. A first DDR memory is mounted on the DDR controller, and a second DDR memory is mounted on the CXL controller; an extended cache space is allocated in the first DDR memory, and is configured to cache the most recently used data in the second DDR memory; and the last level cache controller is configured to determine, upon receiving an access request for the second DDR memory from a bus, whether a cache hit is implemented in the extended cache space, when the cache hit is implemented, perform an access operation on the extended cache space by means of the DDR controller, and when the cache hit is not implemented, directly access the second DDR memory by means of the CXL controller.

Description

Memory expansion method, system, chip and storage medium

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 13, 2023, with application number 202311175208.2, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of data storage technology, for example, to a memory expansion method, system, chip and storage medium. Background Art

[0003] In current System on Chip (SOC) chip applications, communication between the SOC chip and DDR memory particles is achieved using a Double Data Rate SDRAM (DDR) controller and a physical interface. Generally speaking, DDR memory particles are not directly integrated into the SOC chip. These DDR memory particles are connected to the DDR controller on the SOC chip through welding or slots. Among them, the DDR controller is a hardware module on the SOC chip, which is responsible for managing and controlling the data transmission and operation of the DDR memory particles. The DDR controller and DDR memory particles use a specific physical interface (such as DDR5) for communication.

[0004] In SOC chip design, one or more DDR controller channels are usually designed, and each channel can connect to one or more DDR memory particles. The data width of each channel directly affects the size of the memory bandwidth. Usually, the number of DDR controller channels of a SOC chip is limited by the size of the chip and the complexity of the design. Generally speaking, the number of DDR controller channels of a SOC chip will not exceed 8. According to the JEDEC DDR5 specification, the maximum supported capacity of each channel is 128GB. Therefore, the memory capacity of a SOC chip depends on the number of its DDR controller channels and the maximum capacity supported by each channel. Generally speaking, there is an upper limit on the memory capacity of a SOC chip (it is difficult to exceed 1TB).

[0005] In practical applications, the exponential growth of applications such as artificial intelligence and cloud computing has placed higher demands on the memory of server chips. This not only requires an exponential increase in memory capacity, but also the memory access latency is closely related to the computing performance of the application scenario. Therefore, efficient memory expansion has become necessary. The method of expanding memory in related art is to increase memory by connecting NVMe (Non Volatile Memory Express)-based solid-state drives (SSDs) cards via the PCIe / CXL (Peripheral Component Interconnect Express / Compute Express Link) interface. However, the memory expansion method in related art has the following shortcomings: the latency overhead of the expanded traditional memory is large. Generally speaking, the latency of DDR memory is very low, usually in the nanosecond level, while the latency of NVMe-based SSD cards is relatively high, usually in the microsecond level. At the same time, this expanded memory requires software to participate in the processing, which is inefficient, resulting in poor read and write performance after expansion, and cannot meet the needs of high-real-time applications.

[0006] Summary of the Invention

[0007] The present application provides a memory expansion method, system, chip, and storage medium that can achieve high-speed memory capacity expansion and reduce latency when accessing the expanded memory.

[0008] As one aspect of the present application, a memory expansion system is provided, comprising:

[0009] A final-level cache controller, which is provided in the SOC chip and connected to the bus;

[0010] A double data rate synchronous dynamic random access memory (DDR) controller, wherein the DDR controller is provided in the SOC chip and connected to the last-level cache controller;

[0011] a Compute Express Link (CXL) controller, the CXL controller being disposed in the SOC chip and connected to the last-level cache controller;

[0012] a first DDR memory, wherein the first DDR memory is mounted on the DDR controller;

[0013] a second DDR memory, wherein the second DDR memory is mounted on the CXL controller;

[0014] Wherein, an extended cache space is allocated in the first DDR memory, and is configured to cache the most recently used data in the second DDR memory;

[0015] The last-level cache controller is configured to, after receiving an access request to the second DDR memory from the bus, determine whether the access request is a cache hit for the extended cache space based on the target address of the access request; in response to determining that the access request is a cache hit for the extended cache space, perform an access operation on the extended cache space through the DDR controller; and in response to determining that the access request is not a cache hit for the extended cache space, directly access the second DDR memory through the CXL controller and update the corresponding cache line in the extended cache space.

[0016] Another aspect of the present application further provides a method for memory expansion, which is implemented in the aforementioned system, and the method includes:

[0017] The last-level cache controller receives an access request to a target memory from a bus;

[0018] When the target memory is the second DDR memory, mapping is performed according to the target address of the access request, and determining whether the access request has a cache hit on the extended cache space;

[0019] In response to determining that the access request has a cache hit on the extended cache space, performing an access operation on the extended cache space through a DDR controller;

[0020] In response to determining that the access request does not cache hit the extended cache space, directly access the second DDR memory through the CXL controller and update the corresponding cache line in the extended cache space.

[0021] In another aspect of the present application, a chip is provided, which is equipped with the aforementioned system.

[0022] In another aspect of the present application, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps of the aforementioned method are implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] FIG1 is a schematic diagram of a typical connection structure between a SOC chip and a DDR memory in the related art;

[0024] FIG2 is a schematic structural diagram of an embodiment of a memory expansion system provided by the present application;

[0025] FIG3 is a schematic diagram of the structure of the last-level cache controller in FIG2 ;

[0026] FIG4 is a schematic diagram of the structure of the last level cache (LLC) control module in FIG3 ;

[0027] FIG5 is a schematic diagram of the main flow of an embodiment of a memory expansion method provided by the present application;

[0028] FIG6 is a schematic diagram showing the principle of a read operation in an embodiment of the present application;

[0029] FIG7 is a schematic diagram showing the principle of a read operation in another embodiment of the present application;

[0030] FIG8 is a schematic diagram of cache line status information recorded in the LLC tag array module involved in FIG7 ;

[0031] FIG9 is a schematic diagram showing the principle of a read operation in another embodiment of the present application;

[0032] FIG10 is a schematic diagram of cache line status information recorded in the LLC tag array module involved in FIG9 . DETAILED DESCRIPTION

[0033] In one embodiment, as shown in FIG2 , which shows a schematic structural diagram of a system for implementing high-speed memory expansion in a SOC provided by the present application; combined with FIG3 and FIG4 , in this embodiment, the system at least includes:

[0034] A last-level cache controller 1 connected to the bus is provided in the SOC chip, and a DDR controller 2 and a CXL controller 3 are connected to the last-level cache controller 1; for example, the last-level cache controller 1 and the bus, the DDR controller 2 and the CXL controller 3 can communicate through a protocol such as an Advanced eXtensible Interface (AXI) or a Coherent Hub Interface (CHI).

[0035] The DDR controller 2 is mounted with a first DDR memory 4, and the CXL controller 3 is mounted with a second DDR memory 5; an extended cache space 40 is allocated in the first DDR memory 4, configured to cache the most recently used data in the second DDR memory 5;

[0036] The last-level cache controller 1 is configured to, upon receiving an access request to the second DDR memory 5 from the bus, determine whether a cache hit occurs in the extended cache space 40 based on the target address of the access request. If a cache hit occurs, the last-level cache controller 1 accesses the extended cache space 40 through the DDR controller 2. If a cache hit occurs, the last-level cache controller 1 directly accesses the second DDR memory 5 through the CXL controller 3 and updates the corresponding cache line in the extended cache space 40.

[0037] For example, the CXL controller 3 is connected to at least one DDR expander 7 via a CXL switch 6 , and each DDR expander 7 is connected to at least one second DDR memory 5 .

[0038] The CXL controller is responsible for managing communications on the bus and controlling access to the connected second DDR memory. It can provide support for the CXL protocol, including processing requests and responses, as well as processing CXL commands and data; manage communication with the CXL switch to transfer data to the correct second DDR memory or read data from the second DDR memory; and can also provide data forwarding and control between the SOC and external memory.

[0039] The CXL switch 6 is responsible for routing and forwarding memory access requests. Its functions include routing requests from the CXL controller to the corresponding secondary DDR memory, providing hardware-level memory address mapping to ensure access to the correct secondary DDR memory, and supporting read and write operations on the connected secondary DDR memory.

[0040] The DDR expander 7 is configured to expand the memory capacity of the SOC chip. Its functions include: providing an additional second DDR memory to increase the overall memory capacity, receiving memory access requests from the SOC chip, and providing read and write operations to the connected second DDR memory.

[0041] It is understandable that the SOC chip also includes functional components such as a central processing unit (CPU), a computing subsystem, and a high-speed IO interface, which are not the focus of this application and will not be described in detail here.

[0042] For example, as shown in FIG3 , the last-level cache controller 1 includes:

[0043] LLC control module 10, configured to receive access requests to target memory from the bus and control corresponding access operations;

[0044] an LLC cache line control module 11 configured to record status information (such as a valid bit, a dirty bit, etc.) of each cache line in the extended cache space of the first DDR memory, and interaction information between the LLC cache line control module 11 and the second DDR memory;

[0045] an LLC tag array module 12 configured to store, when the target address of the access request is located in the second DDR memory, mapping information of the target address in the extended cache space, the mapping information including a tag corresponding to each cache line in the extended cache space, and the LLC tag array module 12 configured to record the physical address of each cache line in the extended cache space and the target address in the second DDR memory;

[0046] For example, in one example, the size of each cache line in the extended cache space is set to 64 bytes, meaning that each cache line can store 64 bytes of data. The extended cache space is divided into 256 sets, each cache line has a tag, and each set has four cache lines, i.e., four-way associativity. For each target address of the second DDR memory, a mapping relationship between it and the extended cache space can be pre-set. For example, in one example, a hash function can be used to determine which set the target address belongs to. Utilizing the LLC tag array module 12, the requested target address can be compared with the information in its corresponding set to determine whether it is a cache hit. For example, when data at address 0x100 is to be read, the cache will use a hash function to map the address to a specific set (e.g., Set 1). It is understood that other mapping relationships may also be used in other examples. Then, the four cache lines in Set 1 are checked to see if the tag matches the address 0x100. If a match is successful, it indicates a cache hit; if the tags do not match, it indicates a cache miss.

[0047] The least recently used (LRU) algorithm module 13 is configured to determine cache lines in the extended cache space that need to be replaced with new data based on an LRU algorithm. For example, the LRU algorithm module 13 may maintain an LRU linked list and replace data by adjusting the positions of nodes in the linked list. The LRU algorithm module may track the most recently used cache lines and, when the cache is full, prioritize replacing the least recently used cache lines, thereby maximizing the retention of recently used data in the second DDR memory within the corresponding extended cache space and improving the cache hit rate.

[0048] It can be understood that, in the example of the present application, the specific data of the cache line is stored in the extended cache space 40 of the first DDR memory 4, and the last-level cache controller 1 can manage the status and update of the extended cache space 40.

[0049] For example, as shown in FIG4 , the LLC control module 10 includes:

[0050] An access command receiving unit 100 is configured to receive an access request to the first DDR memory or the second DDR memory from a bus;

[0051] The target memory determining unit 101 is configured to determine the target memory of the access request according to the target address in the received access request;

[0052] The first processing unit 102 is configured to, when the target memory determined by the target memory determining unit 101 is the first DDR memory, access the first DDR memory through the DDR controller;

[0053] The second processing unit 103 is configured to, when the target memory determined by the target memory determining unit 101 is the second DDR memory, perform mapping according to the target address of the access request to obtain tag information, and use the tag information to query the LLC tag array module to determine whether the access request hits the extended cache intermediate cache;

[0054] The third processing unit 104 is configured to obtain a corresponding physical address of the extended cache space from the LLC tag array module when determining that the access request has a cache hit on the extended cache space, and perform an access operation on the corresponding physical address of the extended cache space through the DDR controller;

[0055] The fourth processing unit 105 is configured to, when determining that the access request misses the extended cache space, directly access the target address in the second DDR memory through the CXL controller; write the access content at the target address in the second DDR memory to the corresponding cache line in the extended cache space according to the LRU algorithm module; and update the state of the cache line in the extended cache space to which the access content is written in the LLC tag array module;

[0056] The setting unit 106 is configured to set the working mode of the last-level cache controller, and the working modes include: cache mode and non-cache mode; and when set in cache mode, the specific values ​​of the cache line size (Cache line size), set index (Set index) and way (Way) corresponding to the extended cache space.

[0057] For example, in this application, the last-level cache controller can set the total cache capacity (Cache size) to zero, thereby operating in non-caching mode; while in caching mode, its cache capacity (Cache size) is: Set index * Way * Cache line size. For example, setting the operating mode of the last-level cache controller can be achieved by configuring registers or control registers of the last-level cache controller.

[0058] When the last-level cache controller operates in non-cached mode, the extended cache space in the first DDR memory does not participate in the operation. All read and write commands bypass the last-level cache controller and are transmitted to the downstream DDR controller and CXL controller. They are then processed by the read and write response arbitration and then sent up.

[0059] When the last-level cache controller works in cache mode, the space of the first DDR memory is divided into two parts, one part (such as the low address space) is the system memory space, which can be directly accessed; and the other part (such as the high address space) is used as an extended cache space to cache the most recently used data in the second DDR memory.

[0060] For example, the data cached in the extended cache space is the data of the second DDR memory (i.e., the extended DDR memory), which has no direct relationship with the CPU cache size. At the same time, for better performance, in some examples of this application, the cache line size can be flexibly set to: 0.5MB, 1MB, 2MB, ..., 2 i MB, where i = -1, 0, 1, 2, ..., etc. is configurable.

[0061] The number of set indexes is set to 1024.

[0062] The number of ways is set to 2, 4, ..., 2 j , where j=0, 1, 2, 3, 4, etc. are configurable.

[0063] It is understood that in this application, the last-level cache controller adopts a cache-like structure. Unlike a typical cache, its cache line data is set in the extended cache space of the first DDR memory. This allows the last-level cache controller in this application to have greater design flexibility.

[0064] The detailed principles of this application will be explained below with reference to specific examples.

[0065] As shown in FIG5 , the present application further provides a method for implementing high-speed memory expansion in a SOC, which is implemented in the system described in FIG2 to FIG4 . In conjunction with FIG6 to FIG10 , in this embodiment, the method includes the following steps:

[0066] Step S10, the last-level cache controller receives an access request to the target memory from the bus;

[0067] For example, step S10 includes:

[0068] The target memory for access is determined according to the target address in the received access request, where the target memory is the first DDR memory or the second DDR memory.

[0069] The method further includes:

[0070] When the target memory determined by the target memory determining unit is the first DDR memory, an access operation is performed on the first DDR memory according to the target address through the DDR controller.

[0071] Step S11 : when the target memory is the second DDR memory, mapping is performed according to the target address of the access request, and it is determined whether the access request has a cache hit in the extended cache space.

[0072] For example, step S11 includes:

[0073] Obtaining label information corresponding to the target address according to a predetermined mapping relationship;

[0074] A query is performed in the LLC tag array module based on the tag information. If the target address is recorded in the corresponding tag array of the LLC tag array module, it is determined that the access request has a cache hit on the extended cache space. If the target address is not recorded in the corresponding tag array of the LLC tag array module, it is determined that the access request has not a cache hit on the extended cache space.

[0075] Step S12: when the access request hits the extended cache space, accessing the extended cache space through the DDR controller;

[0076] For example, step S12 includes:

[0077] When it is determined that the access request hits the extended cache space cache, the physical address of the extended cache space corresponding to the target address is obtained in the LLC tag array module;

[0078] An access operation is performed on a corresponding physical address of the extended cache space through the DDR controller.

[0079] Step S13: When the access request does not hit the extended cache space, directly access the second DDR memory through the CXL controller and update the corresponding cache line in the extended cache space.

[0080] For example, step S13 includes:

[0081] directly accessing the target address in the second DDR memory through the CXL controller;

[0082] and writing the access content in the target address in the second DDR memory into the corresponding cache line in the extended cache space according to the LRU algorithm module;

[0083] The state of the cache line in which the access content is written in the extended cache space is updated in the LLC tag array module.

[0084] The method further includes:

[0085] The operating mode of the last-level cache controller needs to be pre-set, and the operating mode includes: cache mode and non-cache mode;

[0086] Set the specific values ​​of the cache line size, set index, and way corresponding to the extended cache space in cache mode.

[0087] The following is an explanation of the method involved in this application with reference to specific examples:

[0088] Assume that the size of the first DDR memory (basic memory) attached to the DDR controller in a SOC chip is 64GB, and the size of the second DDR memory (extended memory) attached to the CXL controller is 512GB. If the extended cache space is set to 4GB, then the total memory size of the system is 512 + 64 - 4 = 572GB. Table 1 below lists the partition information table of the target address in an example:

[0089] Table 1, target address partition information table

[0090] When the system accesses the target address range of 0x0_0000_0000 to 0xe_ffff_ffff, which belongs to the first address region 1, the last-level cache controller 1 bypasses the transmission and directly accesses the space of the first DDR memory connected to the chip DDR controller.

[0091] When the system accesses addresses in the range 0xf_0000_0000 to 0x7e_ffff_ffff, which belongs to the second address region 2, the last-level cache controller first checks the corresponding address in the LLC tag array module 12 to see if the address space has a cache hit. If the address cache hits, the transfer accesses the extended cache space of the first DDR memory attached to the DDR controller, as this extended cache space is used as a cache stack. If the address does not hit the cache, the transfer switches to accessing the corresponding memory in the CXL Controller. The data returned by the access is written to the extended cache space in the first DDR memory, and the cache status of the corresponding LLC_TAG at the address is updated in the LLC tag array module.

[0092] The following uses different addresses to illustrate the whole process:

[0093] As shown in Figure 6, when the access command received by the last-level cache controller is a read command, its read target address is 0x4_0000_0000. According to the description in Table 1 above, it belongs to the first address area and can directly access the memory space of the first DDR memory connected to the corresponding DDR controller, read the corresponding content from the first DDR memory, and send it to the bus.

[0094] As shown in Figure 7, when the access command received by the last-level cache controller is a read command, the read target address is 0xf_1000_0000, which belongs to the second address area according to Table 1. In this case, the last-level cache controller first checks whether there is a cache hit in the LLC tag array module. For the sake of convenience, the configuration of the extended cache space is set as follows:

[0095] Cache line size: 1MB

[0096] Number of Ways: 4

[0097] Number of Sets: 256

[0098] In this example, the read target address 0xf_1000_0000 is first mapped. The method used in this embodiment is to divide the address into 1MB cache line sizes and then perform modulo calculation, that is:

[0099] (0xf_1000_1000 / 0x10_0000)%1024

[0100] The tag index is 256. The last-level cache controller checks the LLC tag array module index 256 corresponding to way 0 to 3. As shown in FIG8 , the address corresponding to index 256 and way 3 matches the read target address, so the address is considered a cache hit.

[0101] Therefore, the last-level cache controller will read the actual access address (physical address) of way3 corresponding to index256 in the extended memory space, which is address 0xf_d000_0000.

[0102] At this time, the DDR controller can read the content of the corresponding cache line from the extended cache space of the first DDR memory according to the address 0xf_d000_0000, and upload it to the bus.

[0103] As shown in FIG9 , in step 1, when the access command received by the last-level cache controller is a read command, the read target address is 0x70_2000_0000, which belongs to the second address area according to Table 1. In step 2, the last-level cache controller first checks whether there is a cache hit in the LLC tag array module. For the sake of convenience, the configuration of the extended cache space is set as follows:

[0104] Cache line size: 1MB

[0105] Number of Ways: 4

[0106] Number of Sets: 256

[0107] In this example, first, the read target address 0x70_2000_0000 is mapped to obtain its corresponding label index 512.

[0108] The last-level cache controller will check the corresponding value in way0~3 corresponding to index512 of the LLC tag array module, assuming that this target address does not hit;

[0109] The last-level cache controller will continue to update the state of the LLC tag array module, as shown in Figure 10. Assuming that index 512 of way0 is in an invalid state, the actual access address corresponding to the target address (the actual access address here is the physical address of way0 corresponding to index 512 in the cache space to which the target address is mapped, which is in an invalid state) is updated, and its state is marked as 0->1. In the event of a cache miss, the last-level cache controller will still update the state data of the LLC tag array module (i.e., update the mapping information stored in the LLC tag array module and the physical address of the cache line to which the target address is mapped in the extended cache space) to record the cache state of the physical address of the cache line mapped to the target address in the extended cache space and provide subsequent cache operations. This ensures cache consistency and optimizes subsequent read operations.

[0110] Then, step 3 is executed, the last-level cache controller sends the read target address to the CXL controller, and directly reads a complete cache line of data from the second DDR memory through the CXL controller;

[0111] In steps 4 and 5, the received read data is returned to the upstream bus;

[0112] And through steps 6 and 7, the read data is filled into the corresponding position of the extended cache space of the first DDR memory. At this time, the entire transmission operation is completed to keep the data in the extended cache space up to date.

[0113] It is understandable that the above method of the present application is introduced using three read operation commands as examples. The method provided by the present application can also be used for write operation commands. Those skilled in the art can refer to the above introduction for implementation.

[0114] Accordingly, another aspect of the present application further provides a chip, which is deployed with the system described in Figures 2 to 4 above. For more details, please refer to the above description of Figures 2 to 4, which will not be repeated here.

[0115] Accordingly, another aspect of the present application further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described in Figures 5 to 10 . For more details, please refer to the description of Figures 5 to 10 , which will not be repeated here. The computer-readable storage medium may be a non-transitory computer-readable storage medium.

[0116] The present application provides a method, system, device and storage medium for implementing high-speed memory expansion in a SOC. By adding a second DDR memory as extended memory via a CXL interface, the problem of insufficient memory space in the related art can be avoided. At the same time, the basic memory (i.e., the first DDR memory) is divided, and a part of it is used as an extended cache space to store the most recently used data in the second DDR memory, which can significantly reduce the latency of accessing the second DDR memory.

[0117] The present application sets a last-level cache controller in the SOC chip to manage the first DDR memory and the second DDR memory, eliminating the need for upper-layer software to participate in the transfer of data in the extended memory, thereby improving efficiency.

[0118] The implementation of this application can conveniently achieve high-speed memory space expansion, effectively reduce the access delay of the entire memory space, and improve the convenience of upper-level software.

[0119] Those skilled in the art will appreciate that the embodiments of the present application can be provided as methods, devices, or computer program products. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code.

[0120] The present application is described with reference to the flow chart and / or block diagram of the method, device (system), and computer program product according to the embodiment of the present application. It should be understood that each flow process and / or box in the flow chart and / or block diagram and the combination of the flow process and / or box in the flow chart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processing machine or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one flow chart flow or multiple flows and / or one box or multiple boxes of the block diagram.

Claims

1. A memory expansion system, comprising: A final cache controller, which is arranged in a system-on-chip (SOC) chip and connected to the bus; A double rate synchronous dynamic random access memory DDR controller, wherein the DDR controller is arranged in the SOC chip and connected to the last level cache controller; A computing quick connection CXL controller, wherein the CXL controller is disposed in the SOC chip and connected to the last level cache controller; A first DDR memory, wherein the first DDR memory is mounted on the DDR controller; a second DDR memory, wherein the second DDR memory is mounted on the CXL controller; Wherein, an extended cache space is allocated in the first DDR memory, and the extended cache space is configured to cache the most recently used data in the second DDR memory; The last-level cache controller is configured to, after receiving an access request to the second DDR memory from the bus, determine whether the access request is a cache hit for the extended cache space according to the target address of the access request; in response to determining that the access request is a cache hit for the extended cache space, perform an access operation on the extended cache space through the DDR controller; in response to determining that the access request is not a cache hit for the extended cache space, directly access the second DDR memory through the CXL controller and update the corresponding cache line in the extended cache space.

2. The system of claim 1, wherein: The last level cache controller comprises: A last level cache LLC control module, configured to receive an access request to a target memory from the bus and control a corresponding access operation; An LLC cache line control module, configured to record status information of each cache line in the plurality of cache lines in the extended cache space, and interaction information between the LLC cache line control module and the second DDR memory; an LLC tag array module, configured to store mapping information of the target address in the extended cache space when the target address of the access request is located in the second DDR memory, the mapping information including a tag of each cache line in the extended cache space, and the LLC tag array module is configured to record a physical address of each cache line in the extended cache space and the target address; The least recently used LRU algorithm module is configured to determine the cache lines in the extended cache space that need to be replaced with new data according to the LRU algorithm.

3. The system of claim 2, wherein: The LLC control module comprises: an access command receiving unit, configured to receive an access request to the first DDR memory or the second DDR memory from the bus; a target memory determining unit, configured to determine a target memory of the access request according to a target address in the access request; a first processing unit, configured to, when the target memory determined by the target memory determining unit is the first DDR memory, perform an access operation on the first DDR memory through the DDR controller; a second processing unit, configured to, when the target memory determined by the target memory determining unit is the second DDR memory, map according to the target address of the access request to obtain tag information, and use the tag The information is queried in the LLC tag array module to determine whether the access request is a cache hit in the extended cache space; a third processing unit, configured to obtain a corresponding physical address of the extended cache space in the LLC tag array module in response to determining that the access request hits the extended cache space, and perform an access operation on the corresponding physical address of the extended cache space through the DDR controller; a fourth processing unit, configured to, in response to determining that the access request does not cache hit the extended cache space, directly access the target address in the second DDR memory through the CXL controller; and write the access content in the target address in the second DDR memory into the corresponding cache line in the extended cache space according to the LRU algorithm module; and update the state of the cache line in the extended cache space where the access content is written in the LLC tag array module.

4. The system of claim 3, wherein: The LLC control module comprises: A setting unit is configured to set the working mode of the last-level cache controller, wherein the working modes include: a cache mode and a non-cache mode; and to set, in the cache mode, a cache line size, a group index, and a way value corresponding to the extended cache space.

5. The system according to any one of claims 1 to 4, wherein: The CXL controller is connected to at least one DDR expander via a CXL switch, and each DDR expander is connected to at least one of the second DDR memories.

6. A method for implementing high-speed memory expansion in a system on chip (SOC), implemented in the system according to any one of claims 1 to 5, the method comprising: The last level cache controller receives an access request to a target memory from a bus; When the target memory is a second rate synchronous dynamic random access memory (DDR) memory, mapping is performed according to the target address of the access request, and determining whether the access request has a cache hit on the extended cache space; In response to determining that the access request has a cache hit on the extended cache space, performing an access operation on the extended cache space through a DDR controller; In response to determining that the access request does not cache hit the extended cache space, the CXL controller directly accesses the second DDR memory through a computational shortcut connection, and updates a corresponding cache line in the extended cache space.

7. The method of claim 6, wherein: The last-level cache controller receives an access request to a target memory from a bus, comprising: According to the target address in the access request, a target memory of the access request is determined, and the target memory is the first DDR memory or the second DDR memory.

8. The method of claim 7, further comprising: When the target memory determining unit determines that the target memory is a first DDR memory, the DDR controller performs an access operation on the first DDR memory according to the target address.

9. The method according to claim 7, wherein when the target memory is a second DDR memory, mapping is performed according to the target address of the access request, and determining whether the access request is a cache hit for the extended cache space comprises: According to a predetermined mapping relationship, obtaining label information corresponding to the target address; A query is performed in the last-level cache LLC tag array module according to the tag information, and in response to determining that the target address is recorded in the corresponding tag array of the LLC tag array module, it is determined that the access request has a cache hit on the extended cache space, and in response to determining that the target address is not recorded in the corresponding tag array of the LLC tag array module, it is determined that the access request has not a cache hit on the extended cache space.

10. The method of claim 9, wherein: In response to determining that the access request hits the extended cache space, performing an access operation on the extended cache space through a DDR controller includes: In response to determining that the access request hits the extended cache space cache, obtaining, in the LLC tag array module, a physical address of the extended cache space corresponding to the target address; The DDR controller is used to access the corresponding physical address of the extended cache space.

11. The method of claim 9, wherein: In response to determining that the access request does not cache hit the extended cache space, directly accessing the second DDR memory through the CXL controller and updating the corresponding cache line in the extended cache space includes: Directly accessing the target address in the second DDR memory through the CXL controller; Writing the access content in the target address in the second DDR memory into a corresponding cache line in the extended cache space according to a least recently used (LRU) algorithm module; The state of the cache line in which the access content is written in the extended cache space is updated in the LLC tag array module.

12. The method according to any one of claims 6 to 11, further comprising: Setting the working mode of the last-level cache controller, the working mode including: cache mode and non-cache mode; Set the cache line size, group index and way value corresponding to the extended cache space in the cache mode.

13. A chip having the system according to any one of claims 1 to 5 implemented therein.

14. A computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the method according to any one of claims 6 to 12.

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