Identification apparatus for topology structure, and server

Abstract

The present application relates to the technical field of PCIe topology structures, and discloses an identification apparatus for a topology structure, and a server. The identification apparatus comprises: a first switch circuit, configured to be connected to a cascade interface of a first switch, and a second switch circuit, configured to be connected to a switching interface of a second switch; and a first extension circuit, configured to be connected to an interface of a first processor, and a second extension circuit, configured to be connected to an interface of a second processor; wherein when the first switch circuit is connected to the switching interface and when the first switch circuit is not connected to the switching interface, the first switch circuit outputs different level states, respectively, and when the second switch circuit is connected to the first extension circuit and when the second switch circuit is connected to the second extension circuit, the second switch circuit outputs different level states, respectively. According to the present application, the level states of two switch circuits are used, so that the mode of the current topology structure can be conveniently and quickly determined, and human resources and time costs can be saved.

Description

Topology structure identification device and server

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 12, 2023, with application number 202311169400.0 and application name “Topology Structure Identification Device and Server”, all contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of PCIe topology technology, and in particular to a topology identification device and server. Background Art

[0004] Driven by computing demands in fields like artificial intelligence (AI), big data, and cloud computing, AI (Artificial Intelligence) servers of various architectures have gained widespread adoption. A common AI server computing unit combination is the CPU + GPU (Central Processing Unit + Graphics Processing Unit).

[0005] There are three typical PCIe (Peripheral Component Interconnect Express) topologies in AI server application scenarios: Balance Mode, Common Mode, and Cascade Mode. Each topology mode corresponds to a topology structure. Different topologies are achieved in hardware through different cable configurations and corresponding PCIe SW (switch) FW (firmware).

[0006] The three PCIe topologies vary in terms of peer-to-peer (P2P) bandwidth, latency, computing performance, and deep learning inference and analysis capabilities. Each has its own advantages and disadvantages, and each has its own suitable application scenarios. Therefore, during AI server assembly and production, the correct PCIe cable connections must be confirmed to ensure that the PCIe topology meets customer requirements before shipment.

[0007] Currently, cable connections are generally checked visually to see if they are correct. However, due to the complex routing of cables in the system and the need to confirm each cable one by one, the entire process is labor-intensive, time-consuming, and inefficient.

[0008] Summary of the Invention

[0009] In view of this, the present application provides a topology structure identification device and server.

[0010] In a first aspect, the present application provides a topology identification device, comprising: a first switching circuit, a second switching circuit, a first expansion circuit, and a second expansion circuit;

[0011] The first switch circuit is configured to be connected to the cascade interface of the first switch, and the second switch circuit is configured to be connected to the switching interface of the second switch; in the cascade mode, the cascade interface is connected to the switching interface of the second switch;

[0012] The first expansion circuit is configured to be connected to an interface of the first processor, and the second expansion circuit is configured to be connected to an interface of the second processor; in a balanced mode, the switching interface of the second switch is connected to the interface of the second processor; in a universal mode, the switching interface of the second switch is connected to the interface of the first processor;

[0013] When the first switch circuit is connected to the switching interface of the second switch and when the first switch circuit is not connected to the switching interface of the second switch, the first switch circuit outputs different level states respectively; and

[0014] When the second switch circuit is connected to the first expansion circuit and when the second switch circuit is connected to the second expansion circuit, the second switch circuit outputs different level states respectively.

[0015] In some embodiments, the first switch circuit is an active switch circuit or a passive switch circuit, and the second switch circuit is an active switch circuit or a passive switch circuit; the first expansion circuit is a pull-up circuit or a pull-down circuit, and the second expansion circuit is a pull-up circuit or a pull-down circuit, wherein, when the second expansion circuit is a pull-up circuit, the first expansion circuit is a pull-down circuit, and when the second expansion circuit is a pull-down circuit, the first expansion circuit (210) is a pull-up circuit;

[0016] When the active switch circuit or the passive switch circuit is connected to the pull-up circuit, the active switch circuit or the passive switch circuit outputs a first level state;

[0017] When the active switch circuit or the passive switch circuit is connected to the pull-down circuit, the active switch circuit or the passive switch circuit outputs a second level state;

[0018] When the active switch circuit is connected to the passive switch circuit, both the active switch circuit and the passive switch circuit output a first level state;

[0019] When the two active switch circuits are connected, both active switch circuits output a first level state; and

[0020] When the two passive switch circuits are connected, both passive switch circuits output the second level state;

[0021] When the first level state is a high level, the second level state is a low level; and when the first level state is a low level, the second level state is a high level.

[0022] In some embodiments, the identification device further includes: a third expansion circuit;

[0023] The third expansion circuit is configured to be connected to the first slot; the first slot is mounted under the first switch, and in the balanced mode or the universal mode, the cascade interface is connected to the first slot; and

[0024] When the first switch circuit is connected to the switching interface of the second switch and when the first switch circuit is connected to the third expansion circuit, the first switch circuit outputs different level states.

[0025] In some embodiments, the second switch includes a first switching interface; the second switch circuit is configured to be connected to the first switching interface;

[0026] In balanced mode, the first switching interface is connected to the interface of the second processor; in universal mode, the first switching interface is connected to the interface of the first processor; in cascade mode, the cascade interface is connected to the first switching interface; and

[0027] When the first switch circuit is connected to the second switch circuit and when the first switch circuit is connected to the third expansion circuit, the first switch circuit outputs different level states.

[0028] In some embodiments, when the first switch circuit is a passive switch circuit and the second switch circuit is an active switch circuit, the third expansion circuit is a pull-down circuit;

[0029] In the case where the first switch circuit is an active switch circuit and the second switch circuit is a passive switch circuit, the third expansion circuit is a pull-down circuit;

[0030] In the case where both the first switch circuit and the second switch circuit are active switch circuits, the third expansion circuit is a pull-down circuit; and

[0031] In the case that both the first switch circuit and the second switch circuit are passive switch circuits, the third expansion circuit is a pull-up circuit.

[0032] In some embodiments, the identification device further includes: a third switch circuit; the second switch includes a first switching interface and a second switching interface;

[0033] The second switch circuit is configured to be connected to the first switch interface; the third switch circuit is configured to be connected to the second switch interface;

[0034] In balanced mode, the first switching interface is connected to the interface of the second processor; in universal mode, the first switching interface is connected to the interface of the first processor; in cascade mode, the cascade interface is connected to the second switching interface; and

[0035] When the first switch circuit is connected to the third switch circuit and when the first switch circuit is connected to the third expansion circuit, the first switch circuit outputs different level states.

[0036] In some embodiments, when both the first switch circuit and the third switch circuit are active switch circuits, the third expansion circuit is a pull-down circuit;

[0037] In the case where the first switch circuit is an active switch circuit and the third switch circuit is a passive switch circuit, the third expansion circuit is a pull-down circuit;

[0038] In a case where the first switch circuit is a passive switch circuit and the third switch circuit is an active switch circuit, the third expansion circuit is a pull-down circuit; and

[0039] In the case that both the first switch circuit and the third switch circuit are passive switch circuits, the third expansion circuit is a pull-up circuit.

[0040] The present application utilizes the level state of the first switch circuit output and the level state of the second switch circuit output to conveniently determine the mode of the current topology structure, that is, to determine whether it is a balanced mode, a universal mode, or a cascade mode.

[0041] In some embodiments, the identification device further includes a third switch circuit; the second switch includes a first switching interface and a second switching interface;

[0042] The second switch circuit is configured to be connected to the first switch interface; the third switch circuit is configured to be connected to the second switch interface; in the balanced mode, the first switch interface is connected to the interface of the second processor; in the universal mode, the first switch interface is connected to the interface of the first processor; in the cascade mode, the cascade interface is connected to the first switch interface or the second switch interface; and

[0043] When the cascade interface is connected to the first switching interface or the second switching interface, the three level states output by the first switch circuit, the second switch circuit and the third switch circuit are not exactly the same as the three level states output by the first switch circuit, the second switch circuit and the third switch circuit in the balanced mode or the universal mode.

[0044] In some embodiments, when the first switch circuit is connected to the second switch circuit and when the first switch circuit is connected to the third switch circuit, the first switch circuit outputs the same level state.

[0045] In some embodiments, the first switching circuit is an active switching circuit; or

[0046] The first switch circuit is a passive switch circuit, and the second switch circuit and the third switch circuit are both active switch circuits.

[0047] In some embodiments, the identification device further includes: a third expansion circuit; the third expansion circuit is a pull-down circuit;

[0048] The third expansion circuit is configured to be connected to the first slot; and

[0049] The first slot is connected to the first switch, and in a balanced mode or a universal mode, the cascade interface is connected to the first slot.

[0050] In some embodiments, the identification device further includes: a third expansion circuit; the third expansion circuit is a pull-up circuit;

[0051] The third expansion circuit is configured to be connected to the first slot;

[0052] The first slot is mounted under the first switch, and in a balanced mode or a universal mode, the cascade interface is connected to the first slot; and

[0053] The first switch circuit, the second switch circuit and the third switch circuit are all passive switch circuits.

[0054] The topology structure identification device provided in the present application has a cascade mode with different connection modes that does not affect the level state of the output of the first switch circuit, and can identify the mode of the current topology structure.

[0055] In some embodiments, when the first switch circuit is connected to the second switch circuit and when the first switch circuit is connected to the third switch circuit, the first switch circuit outputs different level states;

[0056] Furthermore, when the third switch circuit is connected to the first switch circuit and when the third switch circuit is not connected to the first switch circuit, the third switch circuit outputs different level states respectively.

[0057] In some embodiments, the identification device further includes: a fourth expansion circuit; the fourth expansion circuit is configured to be connected to the second slot; the second slot is mounted under the second switch, and in the balanced mode or the universal mode, the second switching interface is connected to the second slot; and

[0058] When the third switch circuit is connected to the first switch circuit and when the third switch circuit is connected to the fourth expansion circuit, the third switch circuit outputs different level states respectively.

[0059] In some embodiments, the first switch circuit is a passive switch circuit, the second switch circuit is an active switch circuit, the third switch circuit is a passive switch circuit, the third expansion circuit is a pull-down circuit, and the fourth expansion circuit is a pull-up circuit. The identification device also includes: a third expansion circuit; the third expansion circuit is configured to be connected to the first slot; the first slot is mounted under the first switch, and in balanced mode or universal mode, the cascade interface is connected to the first slot.

[0060] In some embodiments, the third expansion circuit is a pull-up circuit, the fourth expansion circuit is a pull-down circuit, the first switch circuit is a passive switch circuit, the second switch circuit is a passive switch circuit, and the third switch circuit is an active switch circuit, and the identification device further includes: a third expansion circuit; the third expansion circuit is configured to be connected to the first slot; and

[0061] The first slot is connected to the first switch, and in a balanced mode or a universal mode, the cascade interface is connected to the first slot.

[0062] The topology structure identification device provided in the present application can still identify the mode of the current topology structure and determine whether it is the balanced mode, general mode, cascade mode 1, or cascade mode 2 by combining the three level states output by the three switching circuits when the cascade mode of different connection methods affects the output of the first switching circuit.

[0063] In some embodiments, the active switching circuit includes a first transistor, a first voltage-dividing resistor, and a first current-limiting resistor;

[0064] A first end of the first voltage-dividing resistor is connected to a power supply, and a second end of the first voltage-dividing resistor is connected to a control end of the first transistor;

[0065] A first end of the first current limiting resistor is connected to a power supply, and a second end of the first current limiting resistor is connected to a first end of the first transistor; and

[0066] The second end of the first transistor is grounded; the control end of the first transistor controls whether the first end and the second end of the first transistor are conductive, and the control end of the first transistor is configured to be connected to the interface of the switch; the first end of the first transistor is configured to be in an output level state.

[0067] In some embodiments, the pull-down circuit includes a pull-down resistor connected to ground; the resistance values ​​of the first voltage divider resistor and the pull-down resistor satisfy: VCC1×R down / (R down +R 11) <Vth1;

[0068] Among them, VCC1 represents the voltage value of the power supply connected to the first voltage divider resistor, R 11 Indicates the resistance of the first voltage divider resistor, R down represents the resistance of the pull-down resistor, and Vth1 represents the turn-on voltage of the first transistor.

[0069] In some embodiments, the passive switch circuit includes a second transistor, a second voltage-dividing resistor, and a second current-limiting resistor;

[0070] A first end of the second voltage-dividing resistor is connected to the control end of the second transistor, and a second end of the second voltage-dividing resistor is grounded;

[0071] A first end of the second current limiting resistor is connected to the power supply, and a second end of the second current limiting resistor is connected to the first end of the second transistor; and

[0072] The second end of the second transistor is grounded; the control end of the second transistor controls whether the first end and the second end of the second transistor are conductive, and the control end of the second transistor is configured to be connected to the interface of the switch; the first end of the second transistor is configured to be in an output level state.

[0073] In some embodiments, the pull-up circuit includes a pull-up resistor connected to a power supply; the resistance values ​​of the second voltage divider resistor and the pull-up resistor satisfy: VCC2×R 21 / (R up +R 21 )>Vth2;

[0074] Among them, VCC2 represents the voltage value of the power supply connected to the pull-up resistor, R 21 Indicates the resistance of the second voltage divider resistor, R up represents the resistance of the pull-up resistor, and Vth2 represents the turn-on voltage of the second transistor.

[0075] In some embodiments, the identification device further includes: a controller;

[0076] The controller is connected to the output terminals of the plurality of switch circuits, and is configured to determine a mode of the current topology structure according to the level states of the outputs of the plurality of switch circuits; and

[0077] The plurality of switch circuits include a first switch circuit and a second switch circuit.

[0078] In a second aspect, the present application provides a server, comprising: a first processor, a second processor, a first switch, a second switch, and any one of the identification devices of the first aspect.

[0079] In some embodiments, the server further includes: a baseboard management controller; the baseboard management controller is connected to the controller of the identification device, and the baseboard management controller is used to obtain the mode of the current topology structure determined by the controller. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0081] FIG1 shows a schematic diagram of a topological structure of a balanced mode;

[0082] FIG2 shows a schematic diagram of a topological structure of a general mode;

[0083] FIG3 shows a schematic diagram of a topological structure of a cascade mode;

[0084] FIG4 shows a schematic diagram of another topological structure of the cascade mode;

[0085] FIG5 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0086] FIG6 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0087] FIG7 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0088] FIG8 is a schematic structural diagram of an identification device of another topological structure according to an embodiment of the present application;

[0089] FIG9 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0090] FIG10 is a schematic structural diagram of an identification device of another topological structure according to an embodiment of the present application;

[0091] FIG11 is a schematic structural diagram of another topological structure identification device according to an embodiment of the present application;

[0092] FIG12 is a schematic diagram of a connection method of a topological structure identification device according to an embodiment of the present application;

[0093] FIG13 is a schematic diagram of another connection method of the topological structure identification device in an embodiment of the present application;

[0094] FIG14 is a schematic structural diagram of an identification device of another topological structure according to an embodiment of the present application;

[0095] FIG15 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0096] FIG16 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0097] FIG17 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0098] FIG18 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0099] FIG19 is a schematic structural diagram of a topological structure identification device according to an embodiment of the present application;

[0100] FIG20 is a schematic diagram of a topological structure identification device according to an embodiment of the present application;

[0101] FIG21 is a schematic structural diagram of a topological structure identification device in an embodiment of the present application.

[0102] Explanation of the accompanying drawings: 110, first switching circuit; 120, second switching circuit; 130, third switching circuit; 210, first expansion circuit; 220, second expansion circuit; 230, third expansion circuit; 240, fourth expansion circuit; 300, controller; S5, cascade interface; S1, first switching interface; S0, second switching interface; CPU0, first processor; CPU1, second processor; SW_A, first switch; SW_B, second switch; SLOT4, first slot; SLOT6, second slot; Q1, first transistor; R11, first voltage divider resistor; R12, first current limiting resistor; Q2, second transistor; R21, second voltage divider resistor; R22, second current limiting resistor. DETAILED DESCRIPTION

[0103] To make the purpose, technical solutions, and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, other embodiments obtained by those skilled in the art without making creative efforts are all within the scope of protection of this application.

[0104] In the description of this application, it should be noted that the terms "first," "second," and "third" are used for descriptive purposes only and should not be understood to indicate or imply relative importance. Unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to internal connections between two components. Those skilled in the art will understand the meaning of the above terms in this application based on the circumstances.

[0105] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0106] Three typical PCIe topologies are shown in Figures 1 to 3.

[0107] Figure 1 shows a topology for balanced mode. In balanced mode, GPUs are evenly distributed to each CPU, and CPUs communicate with each other via Ultra Path Interconnect (UPI). As shown in Figure 1, the PCIe interface (PE0) of one central processing unit (CPU0) is connected to a PCIe interface (S6) of switch SW_A, and the other four PCIe interfaces of switch SW_A are connected to the slots (SLOTs) of four graphics processors (GPU0, GPU1, GPU2, and GPU3), namely SLOT0, SLOT1, SLOT2, and SLOT3, respectively. Similarly, the PCIe interface (PE0) of another central processing unit (CPU1) is connected to a PCIe interface (S1) of switch SW_B, and the other four PCIe interfaces of switch SW_B are connected to the slots (SLOTs) of four graphics processors (GPU6, GPU7, GPU8, and GPU9), namely SLOT8, SLOT9, SLOT10, and SLOT11, respectively.

[0108] When changing the PCIe topology, the PCIe interface connected to the GPU is generally fixed. You can change to another PCIe topology by configuring the connection method of other PCIe interfaces.

[0109] Figure 2 shows a topology for universal mode. In universal mode, different switches connect to the same CPU. As shown in Figure 2, if switch SW_B is connected to the PCIe interface (S1) of CPU1's PCIe interface (PE0) instead of the PCIe interface (S1) of CPU0's PCIe interface (PE2), both switches SW_A and SW_B will be connected to the same CPU0, switching from balanced mode to universal mode.

[0110] FIG3 shows a topology structure of the cascade mode. In the cascade mode, the switches are in a cascade topology, for example, switches SW_A and SW_B are cascaded. As shown in FIG3 , the PCIe interface (S1) of switch SW_B is connected to the PCIe interface (S5) for cascading in switch SW_A to switch SW_A, and the cascade mode can be switched. In the balanced mode or the universal mode, the PCIe interface (S5) for cascading in switch SW_A can be connected to other devices. As shown in FIG1 or FIG2 , the PCIe interface (S5) for cascading can be connected to the slot SLOT4 of the graphics processor (GPU4) or the AIC (Add-In Card) device (AIC0).

[0111] Figure 4 illustrates another topology in cascade mode. In cascade mode, switches form a cascade topology, for example, switches SW_A and SW_B are cascaded. As shown in Figure 4, the second switch interface S0 of the second switch SW_B is connected to the cascade interface S5 of the first switch SW_A, which is used for cascade connection. Furthermore, the first switch interface S1 of the second switch SW_B cannot be connected to processors CPU0 or CPU1. Generally, to efficiently utilize interface resources, the first switch interface S1 is connected to the second slot SLOT6 originally connected to the second switch interface S0, thus achieving cascade mode.

[0112] When switching to cascade mode is required, as shown in Figure 3, cascade interface S5 can be connected to the first switching interface S1, or, as shown in Figure 4, cascade interface S5 can also be connected to the second switching interface S0. Generally, the switching interface connected to cascade interface S5 is selected based on the principle of proximity. For example, if cascade interface S5 is closer to the second switching interface S0 and switching to cascade mode is required, the topology shown in Figure 4 can be adopted, that is, cascade interface S5 is connected to the second switching interface S0. For the convenience of subsequent description, the cascade mode shown in Figure 3 is referred to as "cascade mode 1", and the cascade mode shown in Figure 4 is referred to as "cascade mode 2".

[0113] It is understood that in actual situations, only balanced mode, universal mode, and cascade mode 1 can be used. Alternatively, only balanced mode, universal mode, and cascade mode 2 can be used. Alternatively, all four modes, balanced mode, universal mode, cascade mode 1, and cascade mode 2, can be used. When cascading is required, only one of cascade mode 1 and cascade mode 2 can be used.

[0114] Based on the differences between the above-mentioned PCIe topology structures, an embodiment of the present application provides a topology structure identification device, which sets corresponding circuit structures for some PCIe interfaces. Under different cable configuration modes, the identification device can output different high and low level states, thereby being able to identify which mode of PCIe topology structure is currently adopted.

[0115] For the convenience of description, some concepts involved in the embodiments of the present application are first explained.

[0116] First processor, second processor: The three PCIe topologies involve at least two central processing units (CPUs), one of which is referred to as the first processor and the other as the second processor. As shown in Figures 1 to 3, CPU0 represents the first processor and CPU1 represents the second processor.

[0117] First switch, second switch: The three PCIe topologies involve at least two switches, one of which is referred to as the first switch and the other as the second switch. As shown in Figures 1 to 3, SW_A represents the first switch and SW_B represents the second switch.

[0118] Cascade interface: The first switch has multiple PCIe interfaces. In cascade mode, a PCIe interface on the first switch is connected to a PCIe interface on the second switch, thereby achieving cascade connection between the first and second switches. For ease of description, this PCIe interface on the first switch is referred to as a cascade interface. It is understood that this cascade interface is a type of PCIe interface.

[0119] For example, as shown in Figure 3, in cascade mode, PCIe interface S5 of the first switch SW_A is connected to PCIe interface S1 of the second switch. As shown in Figures 1 and 2, in balanced or universal mode, PCIe interface S5 of the first switch SW_A is not cascaded and is connected to slot SLOT4. Therefore, PCIe interface S5 is a cascade interface, and will be referred to as S5 below.

[0120] First switching interface: The second switch also has multiple PCIe interfaces. In balanced mode or universal mode, a PCIe interface on the second switch connects to the PCIe interface of the second processor and the first processor, respectively. This PCIe interface of the second switch is used to implement topology switching and is a type of switching interface. For ease of description, this PCIe interface of the second switch is referred to as the first switching interface. It is understood that this first switching interface is also a type of PCIe interface.

[0121] For example, referring to Figures 1 and 2 , in balanced mode, the PCIe interface S1 of the second switch SW_B is connected to the PCIe interface of the second processor CPU1. In general mode, the PCIe interface S1 of the second switch SW_B is connected to the PCIe interface of the first processor CPU0. Therefore, the PCIe interface S1 is the first switching interface, and S1 is subsequently used to represent the first switching interface.

[0122] First slot: The first switch, through multiple PCIe interfaces, can communicate with multiple PCIe devices connected to the first switch. In balanced or universal mode, the first switch's cascade interface can also communicate with a PCIe device. A PCIe device has a slot for communicating with the switch. In this embodiment, the slot connected to the cascade interface is referred to as the first slot. It is understood that this first slot is also a PCIe interface.

[0123] For example, referring to FIG1 and FIG2 , in the balanced mode or the general mode, the cascade interface S5 of the first switch SW_A is connected to the slot SLOT4 to communicate with GPU4 or AIC0. The slot SLOT4 is the first slot mentioned above, and SLOT4 will be used to represent the first slot later.

[0124] Second Switching Interface: In addition to the first switching interface, when switching between different modes, the connection method of another PCIe interface in the second switch may also change to achieve mode switching. This PCIe interface is referred to as the second switching interface. For example, in Figures 1 to 4, PCIe interface S0 of the second switch SW_B can be the second switching interface. As shown in Figure 4, when switching to cascade mode, the first switch SW_A can be connected to the second switching interface S0 to switch to cascade mode.

[0125] Second slot: For a PCIe device connected to the second switch, if a slot of the PCIe device can communicate with the second switch interface, the slot of the PCIe device is referred to as a second slot. For example, as shown in Figures 1 to 3, slot SLOT6 can communicate with the second switch interface S0, so slot SLOT6 is referred to as a second slot. It is understood that both the second switch interface and the second slot are also a type of PCIe interface.

[0126] According to some embodiments of the present application, a topology identification device embodiment is provided. Figure 5 is a schematic diagram of the structure of a topology identification device according to an embodiment of the present application. As shown in Figure 5, the topology identification device includes: a first switching circuit 110, a second switching circuit 120, a first expansion circuit 210, and a second expansion circuit 220.

[0127] The first switch circuit 110 is configured to connect to the cascade interface S5 of the first switch SW_A, and the second switch circuit 120 is configured to connect to the first switching interface S1 of the second switch SW_B. In cascade mode, the cascade interface S5 is connected to the switching interface of the second switch SW_B. For example, as shown in Figure 5, in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1 of the second switch SW_B. Correspondingly, the second switch circuit 120 is also connected to the first switching interface S1.

[0128] The first expansion circuit 210 is configured to connect to an interface of the first processor CPU0, and the second expansion circuit 220 is configured to connect to an interface of the second processor CPU1. In balanced mode, the switching interface of the second switch SW_B is connected to an interface of the second processor CPU1. In universal mode, the switching interface of the second switch SW_B is connected to an interface of the first processor CPU0.

[0129] For example, the switching interface of the second switch SW_B can be the first switching interface S1. As shown in Figure 5, SW_A S5 represents the cascade interface S5 of the first switch SW_A, and SW_B S1 represents the first switching interface S1 of the second switch SW_B. CPU0_PE2 represents the interface of the first processor CPU0, and CPU1_PE0 represents the interface of the second processor CPU1. The first switching circuit 110 can be connected to the cascade interface S5, and the second switching circuit 120 can be connected to the first switching interface S1. The first expansion circuit 210 can be connected to the interface CPU0_PE2, and the second expansion circuit 220 can be connected to the interface CPU1_PE0.

[0130] FIG5 shows the connection modes of various interfaces (including the cascade interface S5 , the first switching interface S1 , etc.) in the balanced mode, the general mode, and the cascade mode 1 , which correspond one-to-one to the connection modes shown in FIG1 to FIG3 .

[0131] In the balance mode, as shown in FIG1 and FIG5 , the first switching interface S1 is connected to the interface CPU1_PE0 of the second processor CPU1 , the cascade interface S5 is connected to the first slot SLOT4 , and the second switching interface S0 is connected to the second slot SLOT6 .

[0132] In the general mode, as shown in FIG2 and FIG5 , the first switching interface S1 is connected to the interface CPU0_PE2 of the first processor CPU0 , the cascade interface S5 is connected to the first slot SLOT4 , and the second switching interface S0 is connected to the second slot SLOT6 .

[0133] In cascade mode 1, as shown in FIG3 and FIG5 , the first switching interface S1 is connected to the cascade interface S5 , and the second switching interface S0 is connected to the second slot SLOT6 .

[0134] In this embodiment, a switching circuit (for example, a first switching circuit 110, a second switching circuit 120) or an expansion circuit (for example, a first expansion circuit 210, a second expansion circuit 220) is set for some PCIe interfaces. When two PCIe interfaces are connected, the two circuits set in this embodiment can be connected separately.

[0135] In some embodiments, as shown in FIG5 , when the first switching interface S1 is connected to the interface CPU0_PE2 of the first processor, the second switch circuit 120 can be connected to the first expansion circuit 210. When the first switching interface S1 is connected to the interface CPU1_PE0 of the second processor, the second switch circuit 120 can be connected to the second expansion circuit 220. When the first switching interface S1 is connected to the cascade interface S5, the second switch circuit 120 can be connected to the first switch circuit 110.

[0136] For example, a PCIe interface has multiple pins, and unused pins can be used to connect the circuit provided in this embodiment to the unused pins of the corresponding PCIe interface. When two PCIe interfaces are connected, the unused pins of the two PCIe interfaces are connected, thereby connecting the two circuits provided in this embodiment. It can be understood that the first switch circuit 110 is connected to the unused pin of the cascade interface S5, the second switch circuit 120 is connected to the unused pin of the first switching interface S1, the first expansion circuit 210 is connected to the unused pin of the first processor interface CPU0_PE2, and the second expansion circuit 220 is connected to the unused pin of the interface CPU1_PE0 of the second processor CPU1. These unused pins correspond to the same number.

[0137] In this embodiment, the first switch circuit 110 and the second switch circuit 120 are both switching circuits, each having a switch that can be turned on or off. By controlling whether the switch is on or off, different voltage levels can be output. For example, when the switch is on, the switch circuit outputs a high voltage level. When the switch is off, the switch circuit outputs a low voltage level. Alternatively, when the switch is on, the switch circuit outputs a low voltage level. When the switch is off, the switch circuit outputs a high voltage level.

[0138] When the first switch circuit 110 is connected to the switching interface of the second switch SW_B and when the first switch circuit 110 is not connected to the switching interface of the second switch SW_B, the first switch circuit 110 outputs different level states, that is, the level states 1 are different. When the switching interface of the second switch SW_B is the first switching interface S1, the second switch circuit 120 is connected to the first switching interface S1, and the first switch circuit 110 is connected to the second switch circuit 120, the first switch circuit 110 outputs one level state. When the first switch circuit 110 is not connected to the second switch circuit 120, the first switch circuit 110 outputs another level state.

[0139] In some embodiments, as shown in FIG5 , in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1, that is, the first switch circuit 110 is connected to the second switch circuit 120. In balanced mode or universal mode, the cascade interface S5 is not connected to the first switching interface S1. For example, the cascade interface S5 is not connected to other PCIe interfaces, or the cascade interface S5 is connected to the first slot SLOT4. In this case, the first switch circuit 110 is not connected to the second switch circuit 120. In these two cases, the first switch circuit 110 outputs different electrical levels. Therefore, based on the electrical level output by the first switch circuit 110, it can be determined whether the current topology mode is the cascade mode.

[0140] Furthermore, when the second switch circuit 120 is connected to the first expansion circuit 210 and when the second switch circuit 120 is connected to the second expansion circuit 220, the second switch circuit 120 outputs different level states, that is, the level states 2 are different. In some embodiments, when the second switch circuit 120 is connected to the first expansion circuit 210, the second switch circuit 120 outputs one level state. When the second switch circuit 120 is connected to the second expansion circuit 220, the second switch circuit 120 outputs another level state.

[0141] In some embodiments, taking the connection of the second switch circuit 120 to the first switch interface S1 as an example, as shown in FIG5 , in balanced mode, the first switch interface S1 is connected to the interface CPU1_PE0, that is, the second switch circuit 120 is connected to the second expansion circuit 220. In universal mode, the first switch interface S1 is connected to the interface CPU0_PE2, that is, the second switch circuit 120 is connected to the first expansion circuit 210. In these two modes, the second switch circuit 120 outputs different level states, so the balanced mode and universal mode can be distinguished based on the level state output by the second switch circuit 120. For example, if the current mode is determined not to be cascade mode based on the level state output by the first switch circuit 110, that is, the current mode is balanced mode or universal mode, the distinction can be made based on the level state output by the second switch circuit 120.

[0142] The level state is divided into high level and low level. Based on the level output by the switch circuit (eg, the first switch circuit 110 and the second switch circuit 120 ), the level state outputted by the switch circuit can be determined.

[0143] The topology identification device provided in this embodiment provides a switch circuit capable of outputting a level state for each of the cascade interface S5 and the switching interface (e.g., the first switching interface S1), and provides an expansion circuit for each of the interfaces of the two processors, so that in different topology modes, the first switch circuit and the second switch circuit can output different level states. The level states of the two switch circuits can be used to quickly and easily determine the current topology mode. Based on this identification device, the current topology mode can be automatically identified without human intervention, which can save human resources and time costs, facilitate production line personnel to directly confirm whether the cable position is correct, and improve production efficiency.

[0144] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG6 is a schematic structural diagram of the device for identifying a topology structure according to an embodiment of the present application. As shown in FIG6 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, and a second expansion circuit 220. The operating principles of the first switch circuit 110, the second switch circuit 120, the first expansion circuit 210, and the second expansion circuit 220 can be found in the description of the embodiment shown in FIG5 and are not further described here.

[0145] In this embodiment, one of the first expansion circuit 210 and the second expansion circuit 220 is a pull-up circuit, and the other is a pull-down circuit. For example, the first expansion circuit 210 is a pull-up circuit, and the second expansion circuit 220 is a pull-down circuit. Alternatively, the first expansion circuit 210 is a pull-down circuit, and the second expansion circuit 220 is a pull-up circuit. By configuring the first expansion circuit 210 and the second expansion circuit 220 with different circuit structures, the second switch circuit 120 can output different voltage levels when connected to the first expansion circuit 210 or the second expansion circuit 220.

[0146] The main function of the pull-up circuit is to provide a high level. The pull-up circuit mainly includes a pull-up resistor connected to a power supply. As shown in Figure 6, the first expansion circuit 210 is a pull-up circuit, wherein the resistor R1 is the pull-up resistor, and the power supply VCC can provide the required voltage.

[0147] The main function of the pull-down circuit is to provide a low level. The pull-down circuit mainly includes a pull-down resistor connected to ground. As shown in Figure 6, the second expansion circuit 220 is a pull-down circuit, wherein the resistor R2 is the pull-down resistor, and the resistor R2 is grounded.

[0148] Furthermore, in this embodiment, the first switch circuit 110 is an active switch circuit or a passive switch circuit, and the second switch circuit 120 is an active switch circuit or a passive switch circuit. For example, one of the first switch circuit 110 and the second switch circuit 120 is an active switch circuit, and the other is a passive switch circuit. Alternatively, both the first switch circuit 110 and the second switch circuit 120 are active switch circuits or passive switch circuits.

[0149] An active switching circuit refers to a switching circuit that includes an internal power supply. In this embodiment, an active switching circuit includes an internal power supply that can control the on / off switching of the switch. Correspondingly, a passive switching circuit refers to a switching circuit that does not include an internal power supply. In this embodiment, a passive switching circuit does not include an internal power supply that can control the on / off switching of the switch. To change the output voltage level of the passive switching circuit, an external power supply is required.

[0150] Whether it is an active switching circuit or a passive switching circuit, it can output different level states when connected to a pull-up circuit or a pull-down circuit. In this embodiment, the first level state and the second level state are used to represent different level states. It can be understood that one of the first level state and the second level state is a high level and the other is a low level.

[0151] In some embodiments, when the active switch circuit or the passive switch circuit is connected to the pull-up circuit, the active switch circuit or the passive switch circuit outputs a first level state. When the active switch circuit or the passive switch circuit is connected to the pull-down circuit, the active switch circuit or the passive switch circuit outputs a second level state. That is, when the switch circuit is connected to the expansion circuit, the level state output by the switch circuit is independent of whether the switch circuit is an active switch circuit or a passive switch circuit.

[0152] For example, regardless of whether the second switch circuit 120 is an active switch circuit or a passive switch circuit, when the second switch circuit 120 is connected to a pull-up circuit (e.g., the first expansion circuit 210), it outputs a first level state. When the second switch circuit 120 is connected to a pull-down circuit (e.g., the second expansion circuit 220), it outputs a second level state.

[0153] In addition, when two switch circuits are interconnected, for example, when the first switch circuit 110 is connected to the second switch circuit 120 , the two switch circuits output the same level state.

[0154] In some embodiments, when an active switch circuit is connected to a passive switch circuit, both the active switch circuit and the passive switch circuit output a first level state. When two active switch circuits are connected, both active switch circuits output a first level state. When two passive switch circuits are connected, both passive switch circuits output a second level state.

[0155] In this embodiment, the power supply within the active switch circuit can achieve a similar control effect as the power supply within the pull-up circuit. When the active switch circuit is connected to a passive switch circuit or another active switch circuit, it is similar to being connected to a pull-up circuit, and the first level state is output. When two passive switch circuits are connected, it is similar to being connected to a pull-down circuit, and the second level state is output.

[0156] For example, in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1, and the first switch circuit 110 is connected to the second switch circuit 120. In this case, the first switch circuit 110 and the second switch circuit 120 output the same level state. If one of the two is an active switching power supply, both output the first level state. If both are passive switching circuits, both output the second level state.

[0157] The topology identification device provided in this embodiment utilizes pull-up circuits, pull-down circuits, active switching circuits, and passive switching circuits to conveniently change the level of the switching circuits in different topology modes. Furthermore, the logical relationships between the various circuits in this embodiment are easily implemented, allowing the current topology mode to be identified based on simple circuits.

[0158] In some embodiments, as shown in Figure 6 , the active switch circuit includes a first transistor Q1 , a first voltage-dividing resistor R11 , and a first current-limiting resistor R12 . Figure 6 takes the second switch circuit 120 as an example of an active switch circuit.

[0159] One end of the first voltage-dividing resistor R11 is connected to the power supply, and the other end is connected to the control end of the first transistor Q1. One end of the first current-limiting resistor R12 is connected to the power supply, and the other end is connected to the first end of the first transistor Q1. The second end of the first transistor Q1 is grounded. The control end of the first transistor Q1 controls whether the first and second ends of the first transistor Q1 are conductive and is configured to be connected to an interface of the switch. The first end of the first transistor Q1 is configured to output a level.

[0160] In this embodiment, the first transistor Q1 is a transistor having three terminals, one of which is a control terminal for controlling whether the transistor is turned on, and the other two terminals are connected to a circuit loop to change the working state of the circuit loop. For example, the first transistor Q1 can be a triode or a field-effect transistor (MOS). Wherein, when the first transistor Q1 is a triode, the base of the triode is the control terminal of the transistor, and the collector and emitter of the triode are the first terminal and the second terminal of the transistor. When the first transistor Q1 is a field-effect transistor, the gate of the field-effect transistor is the control terminal of the transistor, and the source and drain of the field-effect transistor are the first terminal and the second terminal of the transistor. As shown in Figure 6, the first transistor Q1 is an NMOS, whose drain is connected to the first current-limiting resistor R12, and the source is grounded.

[0161] Furthermore, the control terminal of the first transistor Q1 can be connected to an interface of a switch. In other words, when an active switch circuit is connected to an interface of a switch, the control terminal of its first transistor Q1 is connected to the interface of the switch. As shown in FIG6 , the second switch circuit 120 is an active switch circuit. By connecting the control terminal of its first transistor Q1 to the first switching interface S1, the second switch circuit 120 can be connected to the first switching interface S1.

[0162] In this embodiment, the control terminal of the first transistor Q1 is connected to an interface of the switch, such as the cascade interface S5, the first switching interface S1, etc. When the interface of the switch is connected to another interface, the voltage at the control terminal of the first transistor Q1 can be changed, thereby turning the first transistor Q1 on or off. A first voltage-dividing resistor R11 connected to the control terminal of the first transistor Q1 can perform a voltage dividing function, such that when the control terminal of the first transistor Q1 is connected to different circuits (e.g., a pull-up circuit, a pull-down circuit, etc.), the voltage at the control terminal varies, thereby turning the first transistor Q1 on or off.

[0163] The first current-limiting resistor R12 can play a certain protective role, allowing the active switching circuit to output a normal level state. As shown in Figure 6, when the first transistor Q1 is turned on, under the action of the first current-limiting resistor R12, the first terminal of the first transistor Q1 is grounded, and its output level state is a low level. When the first transistor Q1 is turned off, the first current-limiting resistor R12 acts as a pull-up resistor, which can pull up the voltage at the first terminal of the first transistor Q1, so that the level state output by the first terminal of the first transistor Q1 is a high level.

[0164] In this embodiment, an active switch circuit with a simple structure can be constructed based on the first transistor Q1, the first voltage-dividing resistor R11 and the first current-limiting resistor R12, ensuring that the overall structure of the identification device is simple and easy to implement.

[0165] In some embodiments, when the active switch circuit is connected to the pull-up circuit, the first transistor Q1 can be turned on. Correspondingly, when the active switch circuit is connected to the pull-down circuit, the first transistor Q1 needs to be turned off, that is, the voltage at the control terminal of the first transistor Q1 needs to be less than the turn-on voltage Vth1 of the first transistor Q1. In some embodiments, the pull-down circuit includes a grounded pull-down resistor. The resistance values ​​of the first voltage divider resistor R11 and the pull-down resistor satisfy: VCC1×R down / (R down +R 11 ) <Vth1;

[0166] Among them, VCC1 represents the voltage value of the power supply connected to the first voltage divider resistor R11, R 11 Represents the resistance of the first voltage divider resistor R11, R down represents the resistance of the pull-down resistor, and Vth1 represents the turn-on voltage of the first transistor Q1.

[0167] In this embodiment, when the active switch circuit is connected to the pull-down circuit, the first voltage-dividing resistor R11 of the active switch circuit and the pull-down resistor of the pull-down circuit form a voltage-dividing circuit. The voltage between the two is the voltage of the control terminal of the first transistor Q1, which is VCC1×R down / (R down +R 11 ), selecting resistors of appropriate resistance values ​​as the first voltage-divider resistor R11 and the pull-down resistor can make the voltage at the control terminal lower than the on-state voltage Vth1 of the first transistor Q1. For example, if the power supply voltage connected to the first voltage-divider resistor R11 is 3.3V, i.e., VCC1 = 3.3V, and the resistance value of the first voltage-divider resistor R11 is set to 1000 ohms, and the resistance value of the pull-down resistor is set to 100 ohms, then when the active switching circuit is connected to the pull-down circuit, the voltage at the control terminal of the first transistor Q1 is approximately 0.3V, which is lower than the on-state voltage Vth1 of the first transistor Q1 (for example, the on-state voltage Vth1 is generally not less than 0.7V), which meets the requirements.

[0168] In some embodiments, as shown in Figure 6 , the passive switch circuit includes a second transistor Q2 , a second voltage-dividing resistor R21 , and a second current-limiting resistor R22 . Figure 6 takes the example of the first switch circuit 110 being a passive switch circuit.

[0169] One end of the second voltage-dividing resistor R21 is connected to the control terminal of the second transistor Q2, and the other end is grounded. One end of the second current-limiting resistor R22 is connected to the power supply, and the other end is connected to the first end of the second transistor Q2. The second end of the second transistor Q2 is grounded. The control terminal of the second transistor Q2 controls whether the first and second ends of the second transistor Q2 are conductive and is configured to be connected to an interface of the switch. The first end of the second transistor Q2 is configured to be in an output level state.

[0170] In this embodiment, the second transistor Q2 is similar to the first transistor Q1, and the second transistor Q2 can be a triode or a field-effect transistor (MOS). Wherein, when the second transistor Q2 is a triode, the base of the triode is the control terminal of the transistor, and the collector and emitter of the triode are the first and second terminals of the transistor. Wherein, when the second transistor Q2 is a field-effect transistor, the gate of the field-effect transistor is the control terminal of the transistor, and the source and drain of the field-effect transistor are the first and second terminals of the transistor. To ensure that when the active switching circuit and the passive switching circuit are connected, the two output the same level state, the first transistor Q1 and the second transistor Q2 can be transistors of the same type, that is, both are triodes or both are field-effect transistors.

[0171] Furthermore, the control terminal of the second transistor Q2 can be connected to an interface of a switch. In other words, when a passive switch circuit is connected to an interface of a switch, the control terminal of its second transistor Q2 is connected to the interface of the switch. As shown in FIG6 , the first switch circuit 110 is a passive switch circuit. By connecting the control terminal of its second transistor Q2 to the cascade interface S5, the first switch circuit 110 can be connected to the cascade interface S5.

[0172] In this embodiment, the control terminal of the second transistor Q2 is connected to an interface of the switch, such as the cascade interface S5, the first switching interface S1, etc. When the interface of the switch is connected to another interface, the voltage at the control terminal of the second transistor Q2 can be changed, thereby turning the second transistor Q2 on or off. A second voltage-dividing resistor R21 connected to the control terminal of the second transistor Q2 can perform a voltage dividing function, such that when the control terminal of the second transistor Q2 is connected to different circuits (e.g., a pull-up circuit, a pull-down circuit, etc.), the voltage at the control terminal varies, thereby turning the second transistor Q2 on or off.

[0173] In addition, the working principle of the second current limiting resistor R22 is similar to that of the first current limiting resistor R12, which will not be described in detail here.

[0174] In this embodiment, a passive switch circuit with a simple structure can be constructed based on the second transistor Q2, the second voltage-dividing resistor R21 and the second current-limiting resistor R22, ensuring that the overall structure of the identification device is simple and easy to implement.

[0175] In some embodiments, when the passive switch circuit is connected to the pull-down circuit, the second transistor Q2 is turned off because the control terminal of the second transistor Q2 is not connected to the power supply. Accordingly, when the passive switch circuit is connected to the pull-up circuit, the second transistor Q2 needs to be turned on, that is, the voltage at the control terminal of the second transistor Q2 needs to be greater than the turn-on voltage Vth2 of the second transistor Q2. In some embodiments, the pull-up circuit includes a pull-up resistor connected to the power supply. The resistance values ​​of the second voltage divider resistor R21 and the pull-up resistor satisfy: VCC2×R 21 / (R up +R 21 )>Vth2;

[0176] Among them, VCC2 represents the voltage value of the power supply connected to the pull-up resistor, R 21 Indicates the resistance of the second voltage divider resistor R21, R up represents the resistance of the pull-up resistor, and Vth2 represents the turn-on voltage of the second transistor Q2.

[0177] In this embodiment, when the passive switch circuit is connected to the pull-up circuit, the pull-up resistor of the pull-up circuit and the second voltage-dividing resistor R21 of the passive switch circuit form a voltage-dividing circuit. The voltage between the two is the voltage of the control terminal of the second transistor Q2, which is VCC2×R 21 / (R up +R 21), selecting resistors of appropriate resistance values ​​as the second voltage-divider resistor R21 and the pull-up resistor can make the voltage at the control terminal greater than the turn-on voltage Vth2 of the second transistor Q2. For example, the power supply voltage connected to the pull-up resistor is 3.3V, i.e., VCC2 = 3.3V. If the resistance values ​​of the second voltage-divider resistor R21 and the pull-up resistor are both set to 1000 ohms, then when the passive switch circuit is connected to the pull-up circuit, the voltage at the control terminal of the second transistor Q2 is approximately 1.65V, which is greater than the turn-on voltage Vth2 of the second transistor Q2 and meets the requirements.

[0178] Furthermore, to ensure that both the first transistor Q1 and the second transistor Q2 are conductive when the active switching circuit and the passive switching circuit are connected, a first voltage-dividing resistor R11 and a second voltage-dividing resistor R21 having appropriate resistance values ​​may be provided. For example, the first voltage-dividing resistor R11 and the second voltage-dividing resistor R21 may have the same resistance value, or the first voltage-dividing resistor R11 may have a smaller resistance value than the second voltage-dividing resistor R21.

[0179] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG7 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG7 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, and a second expansion circuit 220. Furthermore, the device for identifying a topology structure further includes: a third expansion circuit 230.

[0180] As shown in Figure 7, the third expansion circuit 230 is configured to connect to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A. In balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. Furthermore, when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third expansion circuit 230, the first switch circuit 110 outputs different voltage levels.

[0181] To maximize the utilization of a switch's PCIe interface, it's generally not left idle. For example, as shown in Figure 7 , in balanced mode or universal mode, cascade interface S5 can be connected to the first slot SLOT4 attached to the first switch SW_A. In cascade mode, cascade interface S5 is not connected to the first slot SLOT4, but rather to a switching interface of the second switch SW_B, such as the first switching interface S1. In this embodiment, by providing a third expansion circuit 230 for the first slot SLOT4, the first switch circuit 110 can be connected to the third expansion circuit 230 in balanced mode or universal mode, enabling the first switch circuit 110 to output an appropriate power level.

[0182] In some embodiments, in cascade mode, the cascade interface S5 can be connected to the first switching interface S1, that is, the cascade mode is the above-mentioned cascade mode 1. In this case, when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third expansion circuit 230, the first switch circuit 110 outputs different level states. That is, when the first switch circuit 110 is connected to the second switch circuit 120, the first switch circuit 110 outputs one level state. When the first switch circuit 110 is connected to the third expansion circuit 230, the first switch circuit 110 outputs another level state.

[0183] As shown in Figure 7, in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1, that is, the first switch circuit 110 is connected to the second switch circuit 120. In balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. In these two modes, the first switch circuit 110 outputs different electrical levels. Therefore, based on the electrical level output by the first switch circuit 110, it can be determined whether the current topology mode is cascade mode.

[0184] In this embodiment, by providing the third expansion circuit 230 for the first slot SLOT4, it is convenient to implement the first switch circuit 110 outputting different level states in different modes, so as to determine whether the current topology structure is the cascade mode.

[0185] In some embodiments, the first switch circuit 110 and the second switch circuit 120 can be active switch circuits or passive switch circuits, which are four cases in total. In each case, a topology mode can be identified by selecting an appropriate third expansion circuit 230 .

[0186] The first case: when the first switch circuit 110 is a passive switch circuit and the second switch circuit 120 is an active switch circuit, the third expansion circuit 230 is a pull-down circuit.

[0187] In some embodiments, as shown in FIG6 , in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, i.e., the first switch circuit 110 is connected to the third expansion circuit 230, i.e., the passive switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. Taking the structure shown in FIG6 as an example, when the second transistor Q2 is turned off, the first switch circuit 110 outputs a high level, i.e., level state 1 is a high level.

[0188] In cascade mode 1, the first switch circuit 110 is connected to the second switch circuit 120, that is, the passive switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the second switch circuit 120 output a first level state. Taking the structure shown in Figure 6 as an example, when the second transistor Q2 is turned on, the first switch circuit 110 outputs a low level, that is, level state 1 is a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 1.

[0189] Second situation: when the first switch circuit 110 is an active switch circuit and the second switch circuit 120 is a passive switch circuit, the third expansion circuit 230 is a pull-down circuit.

[0190] In some embodiments, in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, that is, the first switch circuit 110 is connected to the third expansion circuit 230, that is, the active switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. For example, if the structure of the active switch circuit and the passive switch circuit is as shown in Figure 6, the first switch circuit 110 outputs a high level.

[0191] In cascade mode 1, the first switch circuit 110 is connected to the second switch circuit 120, that is, the passive switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the second switch circuit 120 output a first level state. For example, if the structure of the active switch circuit and the passive switch circuit is as shown in Figure 6, the first switch circuit 110 outputs a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 1.

[0192] The third case: when the first switch circuit 110 and the second switch circuit 120 are both active switch circuits, the third expansion circuit 230 is a pull-down circuit.

[0193] In some embodiments, in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, that is, the first switch circuit 110 is connected to the third expansion circuit 230, that is, the active switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. For example, if the structure of the active switch circuit is as shown in Figure 6, the first switch circuit 110 outputs a high level.

[0194] In cascade mode 1, the first switch circuit 110 is connected to the second switch circuit 120, that is, the active switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the second switch circuit 120 output a first level state. For example, if the structure of the active switch circuit is as shown in Figure 6, the first switch circuit 110 outputs a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 1.

[0195] Fourth situation: when the first switch circuit 110 and the second switch circuit 120 are both passive switch circuits, the third expansion circuit 230 is a pull-up circuit.

[0196] In some embodiments, as shown in FIG8 , in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, i.e., the first switch circuit 110 is connected to the third expansion circuit 230, i.e., the passive switch circuit is connected to the pull-up circuit, and the first switch circuit 110 outputs a first level state. Taking the structure shown in FIG8 as an example, when the second transistor Q2 is turned on, the first switch circuit 110 outputs a low level, i.e., level state 1 is a low level.

[0197] In cascade mode 1, the first switch circuit 110 is connected to the second switch circuit 120, that is, a passive switch circuit is connected to a passive switch circuit, and both the first switch circuit 110 and the second switch circuit 120 output a second level state. Taking the structure shown in Figure 8 as an example, when the second transistor Q2 is turned off, the first switch circuit 110 outputs a high level, that is, level state 1 is a high level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 1.

[0198] Figures 6 and 8 illustrate an example in which the first expansion circuit 210 is a pull-up circuit and the second expansion circuit 220 is a pull-down circuit. While this affects the output level of the second switch circuit 120 in balanced mode or universal mode, the second switch circuit 120 can still output different levels in balanced mode or universal mode, effectively maintaining the ability to distinguish between balanced mode and universal mode. This is not discussed in detail in this embodiment.

[0199] In this embodiment, when switching to cascade mode, the cascade interface S5 of the first switch SW_A is switched to the first switching interface S1 connected to the second switch SW_B. That is, in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1. In this case, the current topology mode can be conveniently determined by using the level states output by the two switch circuits (i.e., level state 1 output by the first switch circuit 110 and level state 2 output by the second switch circuit 120), that is, whether the current topology mode is balanced mode, universal mode, or cascade mode 1.

[0200] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG9 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG9 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, and a second expansion circuit 220. Furthermore, the device for identifying a topology structure further includes: a third expansion circuit 230 and a third switch circuit 130.

[0201] As shown in Figure 9, the third expansion circuit 230 is configured to connect to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. The third switch circuit 130 is configured to connect to the second switch interface S0 of the second switch SW_B. In cascade mode, the cascade interface S5 is connected to the second switch interface S0, that is, the first switch circuit 110 is connected to the third switch circuit 130. This cascade mode is the aforementioned cascade mode 2. Furthermore, the first switch circuit 110 outputs different power levels when the first switch circuit 110 is connected to the third switch circuit 130 and when the first switch circuit 110 is connected to the third expansion circuit 230.

[0202] To maximize the utilization of a switch's PCIe interface, it's typically not left idle. For example, as shown in Figure 9 , in balanced mode or universal mode, cascade interface S5 can be connected to first slot SLOT4 attached to the first switch SW_A. In cascade mode 2, cascade interface S5 is not connected to first slot SLOT4, but instead to a switching interface of the second switch SW_B, such as second switching interface S2. In this embodiment, by providing a third expansion circuit 230 for first slot SLOT4, the first switch circuit 110 can be connected to the third expansion circuit 230 in balanced mode or universal mode, enabling the first switch circuit 110 to output an appropriate power level.

[0203] In some embodiments, in cascade mode 2, the cascade interface S5 can be connected to the second switching interface S0. When the first switch circuit 110 is connected to the third switch circuit 130 and when the first switch circuit 110 is connected to the third expansion circuit 230, the first switch circuit 110 outputs different level states. That is, when the first switch circuit 110 is connected to the third switch circuit 130, the first switch circuit 110 outputs one level state. When the first switch circuit 110 is connected to the third expansion circuit 230, the first switch circuit 110 outputs another level state.

[0204] As shown in Figure 9, in cascade mode 2, the cascade interface S5 is connected to the second switching interface S0, that is, the first switch circuit 110 is connected to the third switch circuit 130. In balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. In these two modes, the first switch circuit 110 outputs different electrical levels. Therefore, based on the electrical level output by the first switch circuit 110, it can be determined whether the current topology mode is cascade mode 2.

[0205] In this embodiment, by providing the third expansion circuit 230 for the first slot SLOT4 , it is convenient to implement the first switch circuit 110 outputting different level states in different modes, so as to determine whether the current topology structure is cascade mode 2 .

[0206] In some embodiments, one of the first expansion circuit 210 and the second expansion circuit 220, which can be connected to the second switch circuit 120, is a pull-up circuit, and the other is a pull-down circuit. Therefore, regardless of whether the second switch circuit 120 is an active or passive switch circuit, the level state of the second switch circuit 120 output can be used to distinguish between balanced mode and common mode. Furthermore, the first switch circuit 110 and the third switch circuit 130 can also be active or passive switch circuits, for a total of four possible scenarios. In each case, selecting the appropriate third expansion circuit 230 can identify the topology mode.

[0207] The first case: when the first switch circuit 110 is a passive switch circuit and the third switch circuit 130 is an active switch circuit, the third expansion circuit 230 is a pull-down circuit.

[0208] In some embodiments, as shown in FIG10 , in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, i.e., the first switch circuit 110 is connected to the third expansion circuit 230, i.e., the passive switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. Taking the structure shown in FIG10 as an example, when the second transistor Q2 is turned off, the first switch circuit 110 outputs a high level, i.e., level state 1 is a high level.

[0209] In cascade mode 2, the first switch circuit 110 is connected to the third switch circuit 130, that is, the passive switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the third switch circuit 130 output a first level state. Taking the structure shown in Figure 10 as an example, when the second transistor Q2 is turned on, the first switch circuit 110 outputs a low level, that is, level state 1 is a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 2.

[0210] Second situation: when the first switch circuit 110 is an active switch circuit and the third switch circuit 130 is a passive switch circuit, the third expansion circuit 230 is a pull-down circuit.

[0211] In some embodiments, in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, that is, the first switch circuit 110 is connected to the third expansion circuit 230, that is, the active switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. For example, if the structure of the active switch circuit and the passive switch circuit is as shown in Figure 10, the first switch circuit 110 outputs a high level.

[0212] In cascade mode 2, the first switch circuit 110 is connected to the third switch circuit 130, that is, the passive switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the third switch circuit 130 output a first level state. For example, if the structure of the active switch circuit and the passive switch circuit is as shown in Figure 10, the first switch circuit 110 outputs a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 2.

[0213] The third case: when both the first switch circuit 110 and the third switch circuit 130 are active switch circuits, the third expansion circuit 230 is a pull-down circuit.

[0214] In some embodiments, in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, that is, the first switch circuit 110 is connected to the third expansion circuit 230, that is, the active switch circuit is connected to the pull-down circuit, and the first switch circuit 110 outputs a second level state. For example, if the structure of the active switch circuit is as shown in Figure 10, the first switch circuit 110 outputs a high level.

[0215] In cascade mode 2, the first switch circuit 110 is connected to the third switch circuit 130, that is, the active switch circuit is connected to the active switch circuit, and both the first switch circuit 110 and the third switch circuit 130 output a first level state. For example, if the structure of the active switch circuit is as shown in Figure 10, the first switch circuit 110 outputs a low level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 2.

[0216] Fourth situation: when the first switch circuit 110 and the third switch circuit 130 are both passive switch circuits, the third expansion circuit 230 is a pull-up circuit.

[0217] In some embodiments, as shown in FIG11 , in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4, i.e., the first switch circuit 110 is connected to the third expansion circuit 230, i.e., the passive switch circuit is connected to the pull-up circuit, and the first switch circuit 110 outputs a first level state. Taking the structure shown in FIG11 as an example, when the second transistor Q2 is turned on, the first switch circuit 110 outputs a low level, i.e., level state 1 is a low level.

[0218] In cascade mode 2, the first switch circuit 110 is connected to the third switch circuit 130, that is, a passive switch circuit is connected to a passive switch circuit, and both the first switch circuit 110 and the third switch circuit 130 output a second level state. Taking the structure shown in Figure 11 as an example, when the second transistor Q2 is turned off, the first switch circuit 110 outputs a high level, that is, level state 1 is a high level. Therefore, the level state output by the first switch circuit 110 can indicate whether the current topology is cascade mode 2.

[0219] In Figures 10 and 11 , the second switch circuit 120 is a passive switch circuit, the first expansion circuit 210 is a pull-up circuit, and the second expansion circuit 220 is a pull-down circuit. While the pull-down and pull-up conditions affect the output level of the second switch circuit 120 in balanced or universal mode, the second switch circuit 120 can still output different levels in balanced or universal mode, effectively enabling the distinction between balanced and universal modes. This is not discussed in detail in this embodiment.

[0220] In this embodiment, when switching to cascade mode, the cascade interface S5 of the first switch SW_A is switched to the second switching interface S0 connected to the second switch SW_B. That is, in cascade mode 2, the cascade interface S5 is connected to the second switching interface S0. In this case, the current topology mode can be conveniently determined by using the level states output by the two switch circuits (i.e., level state 1 output by the first switch circuit 110 and level state 2 output by the second switch circuit 120), that is, whether the current topology mode is balanced mode, universal mode, or cascade mode 2.

[0221] It should be noted that, when it is necessary to identify the mode of the current topology structure, although all three switch circuits can output corresponding level states, it is possible to identify the current balanced mode, common mode, or cascade mode 2 by only using the level states of two of the switch circuits, so it is possible to ignore the level state 3 output by the third switch circuit 130. In addition, it can be understood that in this embodiment, transistors and resistors in active switch circuits (or passive switch circuits) are represented by unified reference numerals, but different switch circuits can use transistors and resistors of the same specifications, or transistors and resistors of different specifications, and this embodiment does not limit this. As shown in Figure 12A, the first switch circuit 110 and the second switch circuit 120 are both passive switch circuits, and both have a second voltage divider resistor R21. The second voltage divider resistor R21 in the first switch circuit 110 and the second voltage divider resistor R21 in the second switch circuit 120 can have the same or different resistance values, which can be determined based on actual conditions.

[0222] In order to determine which mode the current topology structure corresponds to, namely the balanced mode in Figure 1, the general mode in Figure 2, the cascade mode 1 in Figure 3, and the cascade mode 2 in Figure 4, the topology structure identification device provided in the embodiment of the present application is also provided with a third switching circuit, which cooperates with each other or introduces more level states through circuits to distinguish between the balanced mode, the general mode and the cascade mode when the user may use the cascade mode 1 and the cascade mode 2.

[0223] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. Figures 12 and 13 are schematic structural diagrams of a device for identifying a topology structure according to an embodiment of the present application. As shown in Figures 12 and 13, the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, and a second expansion circuit 220. Furthermore, it also includes a third switch circuit 130. Figure 12 illustrates the connection methods in balanced mode, universal mode, and cascade mode 1, and Figure 13 illustrates the connection methods in balanced mode, universal mode, and cascade mode 2. It will be understood that in Figures 12 and 13, the connection methods in balanced mode and universal mode are the same.

[0224] The third switch circuit 130 is configured to connect to the second switching interface S0 of the second switch SW_B. In cascade mode, the cascade interface S5 is connected to the first switching interface S1 or the second switching interface S0. As shown in FIG12 , the cascade interface S5 is connected to the first switching interface S1. Alternatively, as shown in FIG13 , the cascade interface S5 is connected to the second switching interface S0.

[0225] When the cascade interface S5 is connected to the first switching interface S1 or the second switching interface S0, the three level states output by the first switch circuit 110, the second switch circuit 120 and the third switch circuit 130 are not exactly the same as the three level states output by the first switch circuit 110, the second switch circuit 120 and the third switch circuit 130 in the balanced mode or the common mode.

[0226] In this embodiment, the first switch circuit 110, the second switch circuit 120, and the third switch circuit 130 can output three level states, namely, level state 1, level state 2, and level state 3. The current topology mode can be determined based on these three level states. The three output level states are not completely the same in different modes, namely, the balanced mode, the universal mode, the cascade mode 1, and the cascade mode 2. Therefore, these four topology modes can be distinguished. Regardless of whether the cascade interface S5 is connected to the first switching interface S1 to achieve cascade connection or to the second switching interface S0 to achieve cascade connection, the current topology mode can be correctly identified.

[0227] In some embodiments, the first switch circuit 110 outputs the same level state when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third switch circuit 130. That is, the level state output when the first switch circuit 110 is connected to the second switch circuit 120 and the level state output when the first switch circuit 110 is connected to the third switch circuit 130 are the same, that is, the level state 3 is the same.

[0228] In this embodiment, in cascade mode 1, as shown in FIG12 , the cascade interface S5 is connected to the first switching interface S1, the first switch circuit 110 is connected to the second switch circuit 120, and the first switch circuit 110 can output a level state. In cascade mode 2, as shown in FIG13 , the cascade interface S5 is connected to the second switching interface S0, the first switch circuit 110 is connected to the third switch circuit 130, and the first switch circuit 110 can also output a level state. In cascade mode 1 and cascade mode 2, the first switch circuit 110 outputs the same level state, and in balanced mode or universal mode, the level state output by the first switch circuit 110 is different from the level state output in the cascade mode (such as cascade mode 1). Therefore, in this case, based on the level state output by the first switch circuit 110, it is possible to determine whether the current topology mode is the cascade mode, without distinguishing between cascade mode 1 and cascade mode 2.

[0229] It can be understood that, since the first switch circuit 110 outputs the same level state in both cascade mode 1 and cascade mode 2, that is, whether the cascade interface S5 is connected to the first switching interface S1 or the second switching interface S0 does not affect the level state output by the first switch circuit 110, the topology mode of the current topology structure can be determined based solely on the level state 1 output by the first switch circuit 110 and the level state 2 output by the second switch circuit 120, that is, the level state 3 output by the third switch circuit 130 can be omitted. Of course, if necessary, the level state 3 output by the third switch circuit 130 can also be used to distinguish between cascade mode 1 and cascade mode 2 in the cascade mode.

[0230] Alternatively, in some embodiments, the first switch circuit 110 outputs different level states when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third switch circuit 130. That is, the first switch circuit 110 outputs one level state when connected to the second switch circuit 120, and outputs another level state when connected to the third switch circuit 130, that is, the level states 3 are different.

[0231] It is understood that in this case, when the first switch circuit 110 is connected to the third switch circuit 130, that is, in cascade mode 2, the level state output by the first switch circuit 110 is the same as the level state output by the first switch circuit 110 in either balanced mode or universal mode, making it difficult to identify the topology mode. In this embodiment, a suitable third switch circuit 130 is selected so that the third switch circuit 130 outputs different level states when the third switch circuit 130 is connected to the first switch circuit 110 and when the third switch circuit 130 is not connected to the first switch circuit 110, respectively, to enable identification of cascade mode 2.

[0232] In cascade mode 2, the second switching interface S0 is connected to the cascade interface S5, that is, the third switch circuit 130 is connected to the first switch circuit 110. At this time, the third switch circuit 130 outputs a level state. In balanced mode, universal mode, or cascade mode 1, the second switching interface S0 is not connected to the cascade interface S5. For example, as shown in Figure 12, the second switching interface S0 is connected to the second slot SLOT6. At this time, the third switch circuit 130 is not connected to the first switch circuit 110 and outputs a different level state. Therefore, the level state 3 output by the third switch circuit 130 can be used to determine whether the current topology mode is cascade mode 2. If it is not cascade mode 2, as described above, based on the first switch circuit 110 and the second switch circuit 120, it can be identified whether the current topology mode is balanced mode, universal mode, or cascade mode 1.

[0233] In this embodiment, even if different cascade modes (i.e., cascade mode 1 and cascade mode 2) affect the level state of the first switch circuit 110, combined with the three level states output by the three switch circuits (i.e., the first switch circuit 110, the second switch circuit 120, and the third switch circuit 130), it is also possible to accurately identify whether the current topology mode is the balanced mode, the general mode, the cascade mode 1, or the cascade mode 2.

[0234] In some embodiments, as shown in FIG14 , the identification device may further include a third expansion circuit 230 and / or a fourth expansion circuit 240 . The third expansion circuit 230 is configured to connect to the first slot SLOT4 . The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4 . The fourth expansion circuit 240 is configured to connect to the second slot SLOT6 . The second slot SLOT6 is attached to the second switch SW_B, and in balanced mode or universal mode, the second switching interface S0 is connected to the second slot SLOT6 . FIG14 does not illustrate the cable connection method in cascade mode 2.

[0235] By providing expansion circuits for the first slot SLOT4 and the second slot SLOT6 , the switch circuit can output a required level state when connected to the third expansion circuit 230 or the fourth expansion circuit 240 based on appropriate expansion circuits.

[0236] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG15 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG15 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, a second expansion circuit 220, and a third switch circuit 130. Furthermore, when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third switch circuit 130, the first switch circuit 110 outputs the same level state.

[0237] As shown in FIG15 , the first switch circuit 110 is a passive switch circuit, and the second switch circuit 120 and the third switch circuit 130 are both active switch circuits.

[0238] In this embodiment, in cascade mode 1, the cascade interface S5 is connected to the first switching interface S1, that is, the first switch circuit 110 is connected to the second switch circuit 120, that is, the passive switch circuit is connected to the active switch circuit. Therefore, the first switch circuit 110 and the second switch circuit 120 both output the first level state. Taking the structure shown in Figure 15 as an example, the first switch circuit 110 and the second switch circuit 120 both output a low level. In cascade mode 2, the cascade interface S5 is connected to the second switching interface S0, that is, the first switch circuit 110 is connected to the third switch circuit 130. In this case, the passive switch circuit is connected to the active switch circuit. Therefore, the first switch circuit 110 and the third switch circuit 130 still both output the first level state. Taking the structure shown in Figure 15 as an example, the first switch circuit 110 and the second switch circuit 120 both output a low level. Therefore, in either cascade mode 1 or cascade mode 2, the level state output by the first switch circuit 110 is the first level state.

[0239] To enable the first switch circuit 110 to output the second level state in balanced mode or universal mode, a third expansion circuit 230 can be provided for the first slot SLOT4. This third expansion circuit 230 is a pull-down circuit. The third expansion circuit 230 is configured to be connected to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4.

[0240] Take the structure shown in Figure 15 as an example. In balanced mode, the second transistor Q2 of the first switch circuit 110 is turned off, and the level state 1 output by it is a high level. The first transistor Q1 of the second switch circuit 120 is turned off, and the level state 2 output by it is a high level. In common mode, the level state 1 output by the first switch circuit 110 remains unchanged and remains a high level. The first transistor Q1 of the second switch circuit 120 is turned on, and the level state 2 output by it is a low level. In cascade mode 1, the second transistor Q2 of the first switch circuit 110 and the first transistor Q1 of the second switch circuit 120 are both turned on, so the level states 1 and 2 are both low levels. In cascade mode 2 (the connection method of cascade mode 2 is not shown in Figure 15), the second transistor Q2 of the first switch circuit 110 and the first transistor Q1 of the third switch circuit 130 are both turned on, so the level states 1 and 3 are both low levels.

[0241] 1 represents a high level and 0 represents a low level. The three level states in the four modes can be seen in Table 1 below. Among them, “——” represents a level state that does not need to be paid attention to, which can be a high level or a low level.

[0242] Table 1

[0243] It is understood that when the first expansion circuit 210 is a pull-down circuit and the second expansion circuit 220 is a pull-up circuit, only level state 2 is affected. That is, in the balanced mode, level state 2 is a low level, and in the universal mode, level state 2 is a high level. The current topology mode can still be determined by using these three level states. This will not be described in detail later.

[0244] Among them, the switch circuit and the expansion circuit are connected to the idle pins of the PCIe interface to achieve connection with the corresponding interface. In addition, when the pins of the PCIe interface are divided into two sides, A and B, and when two PCIe interfaces are connected, the A-side pin of one PCIe interface will be connected to the B-side pin of the other PCIe interface. In this embodiment, pin 27 of the PCIe interface is an idle pin, so the switch circuit and the expansion circuit are connected to pin 27 of the corresponding interface. In addition, pin 27 of the A side is marked as A27, and pin 27 of the B side is marked as B27. By connecting to pin A27 or pin B27, the switch circuit and the expansion circuit can be connected to the corresponding PCIe interface, and when two PCIe interfaces are connected, the connection between the switch circuit and the expansion circuit can be achieved.

[0245] As shown in Figure 15, both the first expansion circuit 210 and the second expansion circuit 220 are connected to pin A27. The second switch circuit 120 is connected to pin B27 of the first switching interface S1, allowing the second switch circuit 120 to connect to either the first expansion circuit 210 or the second expansion circuit 220. The first switch circuit 110 is connected to pin A27 of the cascade interface S7, and the third switch circuit 130 is connected to pin B27 of the second switching interface S0. In cascade mode 1 or cascade mode 2, the first switch circuit 110 can connect to the second switch circuit 120 and the third switch circuit 130, respectively. Accordingly, the third expansion circuit 230 is connected to pin B27 of the first slot SLOT4. If a fourth expansion circuit is present, it is connected to pin A27 of the second slot SLOT6.

[0246] In the topology identification device provided in this embodiment, cascade modes of different connection modes do not affect the level state of the output of the first switch circuit 110, and the current topology mode can be identified.

[0247] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG16 is a schematic structural diagram of the device for identifying a topology structure according to an embodiment of the present application. As shown in FIG16 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, a second expansion circuit 220, and a third switch circuit 130. Furthermore, when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third switch circuit 130, the first switch circuit 110 outputs the same level state.

[0248] As shown in FIG16 , the first switch circuit 110 is an active switch circuit. The second switch circuit 120 and the third switch circuit 130 can be active switch circuits or passive switch circuits, which is not limited in this embodiment. FIG16 illustrates an example in which the second switch circuit 120 and the third switch circuit 130 are both passive switch circuits.

[0249] In this embodiment, when the first switch circuit 110 is an active switch circuit, regardless of the type of switch circuit used by the second switch circuit 120 or the third switch circuit 130, the active switch circuit outputs the first level state. Therefore, the level state output by the first switch circuit 110 is the same, that is, the first level state, in either cascade mode 1 or cascade mode 2. For example, taking the structure shown in FIG16 as an example, when the active switch circuit is connected to the active switch circuit or the passive switch circuit, the transistors therein (including the first transistor Q1 and the second transistor Q2) are all turned on, so the level state 1 output by the first switch circuit 110 is a low level.

[0250] To enable the first switch circuit 110 to output the second level state in balanced mode or universal mode, a third expansion circuit 230 can be provided for the first slot SLOT4. This third expansion circuit 230 is a pull-down circuit. The third expansion circuit 230 is configured to be connected to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4.

[0251] Take the structure shown in Figure 16 as an example. In balanced mode, the first transistor Q1 of the first switch circuit 110 is turned off, and the level state 1 of its output is a high level. The second transistor Q2 of the second switch circuit 120 is turned off, and the level state 2 of its output is a high level. In common mode, the level state 1 of the first switch circuit 110 remains unchanged and remains a high level. The second transistor Q2 of the second switch circuit 120 is turned on, and the level state 2 of its output is a low level. In cascade mode 1, the first transistor Q1 of the first switch circuit 110 and the second transistor Q2 of the second switch circuit 120 are both turned on, so the level states 1 and 2 are both low levels. In cascade mode 2 (the connection method of cascade mode 2 is not shown in Figure 16), the first transistor Q1 of the first switch circuit 110 and the second transistor Q2 of the third switch circuit 130 are both turned on, so the level states 1 and 3 are both low levels.

[0252] In the four modes, the three level states are the same as those shown in the above embodiment, and can be seen in Table 1 above.

[0253] In the topology identification device provided in this embodiment, cascade modes of different connection modes do not affect the level state of the output of the first switch circuit 110, and the current topology mode can be identified.

[0254] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG17 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG17 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a first expansion circuit 210, a second expansion circuit 220, and a third switch circuit 130. Furthermore, when the first switch circuit 110 is connected to the second switch circuit 120 and when the first switch circuit 110 is connected to the third switch circuit 130, the first switch circuit 110 outputs the same level state.

[0255] The first switch circuit 110, the second switch circuit 120, and the third switch circuit 130 are all passive switch circuits. When the first switch circuit 110 is connected to the second switch circuit 120 or the third switch circuit 130, the first switch circuit 110 outputs a second level state. For example, taking the structure shown in FIG17 as an example, when the passive switch circuits or the passive switch circuits are connected, the second transistors Q2 therein are all turned off, so the level state 1 output by the first switch circuit 110 is a high level.

[0256] Furthermore, to enable the first switch circuit 110 to output the first level state in balanced mode or universal mode, a third expansion circuit 230 can be provided for the first slot SLOT4. This third expansion circuit 230 is a pull-up circuit. The third expansion circuit 230 is configured to be connected to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4.

[0257] See Figure 17 . In balanced mode, the second transistor Q2 of the first switch circuit 110 is turned on, and the level state 1 outputted by it is a low level. The second transistor Q2 of the second switch circuit 120 is turned off, and the level state 2 outputted by it is a high level. In common mode, the level state 1 outputted by the first switch circuit 110 remains unchanged and remains a low level. The second transistor Q2 of the second switch circuit 120 is turned on, and the level state 2 outputted by it is a low level. In cascade mode 1, the second transistor Q2 of the first switch circuit 110 and the second transistor Q2 of the second switch circuit 120 are both turned off, so both level state 1 and level state 2 are high levels. In cascade mode 2 (the connection method of cascade mode 2 is not shown in Figure 17 ), the second transistor Q2 of the first switch circuit 110 and the second transistor Q2 of the third switch circuit 130 are both turned off, so both level state 1 and level state 3 are high levels.

[0258] 1 represents a high level and 0 represents a low level. The three level states in the four modes can be seen in Table 2 below. Among them, “——” represents a level state that does not need to be paid attention to, which can be a high level or a low level.

[0259] Table 2

[0260] In the topology identification device provided in this embodiment, cascade modes of different connection modes do not affect the level state of the output of the first switch circuit 110, and the current topology mode can be identified.

[0261] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG18 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG18 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a third switch circuit 130, a first expansion circuit 210, and a second expansion circuit 220. In cascade mode 1 or cascade mode 2, the first switch circuit 110 outputs different level states, and the third switch circuit 130 also outputs different level states.

[0262] Furthermore, as shown in FIG18 , the identification device further includes a fourth expansion circuit 240. The fourth expansion circuit 240 is configured to be connected to the second slot SLOT6. The second slot SLOT6 is attached to the second switch SW_B, and in balanced mode or universal mode, the second switching interface S0 is connected to the second slot SLOT6. The third switch circuit 130 outputs different level states when the third switch circuit 130 is connected to the first switch circuit 110 and when the third switch circuit 130 is connected to the fourth expansion circuit 240.

[0263] In this embodiment, in cascade mode 2, the cascade interface S5 is connected to the second switching interface S0, that is, the third switch circuit 130 is connected to the first switch circuit 110. In balanced mode, universal mode, or cascade mode 2, the second switching interface S0 is connected to the second slot SLOT6, that is, the third switch circuit 130 is connected to the fourth expansion circuit 240. In these two modes, the third switch circuit 130 outputs different levels. Therefore, based on the level of the third switch circuit 130 output, it is possible to determine whether the current topology is cascade mode 2. Furthermore, if it is not cascade mode 2, the current topology can be determined based on the level of the first switch circuit 110 and the second switch circuit 120 outputs.

[0264] In some embodiments, as shown in FIG18 , the identification device further includes a third expansion circuit 230. The third expansion circuit 230 is configured to connect to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. The third expansion circuit 230 is a pull-down circuit, and the fourth expansion circuit 240 is a pull-up circuit. The first switch circuit 110 is a passive switch circuit, the second switch circuit 120 is an active switch circuit, and the third switch circuit 130 is a passive switch circuit. Using a pull-down circuit as the third expansion circuit enables the first switch circuit 110 to output different level states in cascade mode 1 and balanced mode or universal mode, as described in the first case shown in the above embodiment.

[0265] As shown in Figure 18, in balanced mode, the second transistor Q2 of the first switch circuit 110 is turned off, and the level state 1 output by it is a high level. The first transistor Q1 of the second switch circuit 120 is turned off, and the level state 2 output by it is a high level. In common mode, the level state 1 output by the first switch circuit 110 remains unchanged and remains a high level. The first transistor Q1 of the second switch circuit 120 is turned on, and the level state 2 output by it is a low level. In cascade mode 1, the second transistor Q2 of the first switch circuit 110 and the first transistor Q1 of the second switch circuit 120 are both turned on, so the level states 1 and 2 are both low levels. In cascade mode 2 (the connection method of cascade mode 2 is not shown in Figure 18), the second transistor Q2 of the first switch circuit 110 and the second transistor Q2 of the third switch circuit 130 are both turned off, so the level states 1 and 3 are both high levels.

[0266] Furthermore, in cascade mode 2, the second switch circuit 120 is connected to the fourth expansion circuit 240, so the first transistor Q1 of the second switch circuit 120 is turned on, and the level state 2 output by the second switch circuit 120 is a low level. To distinguish between the common mode and cascade mode 2, the third switch circuit 130 is required to output different level states in the common mode and cascade mode 2. In this embodiment, since the fourth expansion circuit 240 is a pull-up circuit, in the common mode, the third switch circuit 130 is connected to the fourth expansion circuit 240, the second transistor Q2 of the third switch circuit 130 is turned on, and the level state 3 output by the third switch circuit 130 is a low level, which is different from the high level output in cascade mode 2, thereby distinguishing between the common mode and cascade mode 2.

[0267] 1 represents a high level and 0 represents a low level. The three level states in the four modes can be seen in Table 3 below. Among them, "——" represents a level state that does not need to be paid attention to, which can be a high level or a low level. Based on the structure shown in Figure 18, it can be seen that in balanced mode, general mode, or cascade mode 1, level state 3 remains unchanged. Therefore, in Table 1 below, in balanced mode or cascade mode 1, level state 3 is also a low level.

[0268] Table 3

[0269] The topology structure identification device provided in this embodiment can still identify the current topology structure mode and determine whether it is the balanced mode, common mode, cascade mode 1, or cascade mode 2 by combining the three level states output by the three switch circuits when the cascade mode of different connection methods affects the output of the first switch circuit 110.

[0270] According to some embodiments of the present application, an embodiment of a device for identifying a topology structure is provided. FIG19 is a schematic structural diagram of a device for identifying a topology structure according to an embodiment of the present application. As shown in FIG19 , the device for identifying a topology structure includes: a first switch circuit 110, a second switch circuit 120, a third switch circuit 130, a first expansion circuit 210, and a second expansion circuit 220. In cascade mode 1 or cascade mode 2, the first switch circuit 110 outputs different level states, and the third switch circuit 130 also outputs different level states.

[0271] Furthermore, as shown in FIG19 , the identification device further includes a fourth expansion circuit 240. The fourth expansion circuit 240 is configured to be connected to the second slot SLOT6. The second slot SLOT6 is attached to the second switch SW_B, and in balanced mode or universal mode, the second switching interface S0 is connected to the second slot SLOT6. The third switch circuit 130 outputs different power levels when the third switch circuit 130 is connected to the first switch circuit 110 and when the third switch circuit 130 is connected to the fourth expansion circuit 240.

[0272] In this embodiment, in cascade mode 2, the cascade interface S5 is connected to the second switching interface S0, that is, the third switch circuit 130 is connected to the first switch circuit 110. In balanced mode, universal mode, or cascade mode 2, the second switching interface S0 is connected to the second slot SLOT6, that is, the third switch circuit 130 is connected to the fourth expansion circuit 240. In these two modes, the third switch circuit 130 outputs different levels. Therefore, based on the level of the third switch circuit 130 output, it is possible to determine whether the current topology is cascade mode 2. Furthermore, if it is not cascade mode 2, the current topology can be determined based on the level of the first switch circuit 110 and the second switch circuit 120 outputs.

[0273] In some embodiments, as shown in FIG19 , the identification device further includes a third expansion circuit 230. The third expansion circuit 230 is configured to be connected to the first slot SLOT4. The first slot SLOT4 is attached to the first switch SW_A, and in balanced mode or universal mode, the cascade interface S5 is connected to the first slot SLOT4. The third expansion circuit 230 is a pull-up circuit, and the fourth expansion circuit 240 is a pull-down circuit. The first switch circuit 110 is a passive switch circuit, the second switch circuit 120 is a passive switch circuit, and the third switch circuit 130 is an active switch circuit. Using a pull-up circuit as the third expansion circuit enables the first switch circuit 110 to output different level states in cascade mode 1 and balanced mode or universal mode, as described in the fourth case shown in the above embodiment.

[0274] As shown in Figure 19, in balanced mode, the second transistor Q2 of the first switch circuit 110 is turned on, and the level state 1 output by it is a low level. The second transistor Q2 of the second switch circuit 120 is turned off, and the level state 2 output by it is a high level. In common mode, the level state 1 output by the first switch circuit 110 remains unchanged and remains a low level. The second transistor Q2 of the second switch circuit 120 is turned on, and the level state 2 output by it is a low level. In cascade mode 1, the second transistor Q2 of the first switch circuit 110 and the second transistor Q2 of the second switch circuit 120 are both turned off, so the level states 1 and 2 are both high levels. In cascade mode 2 (the connection method of cascade mode 2 is not shown in Figure 19), the second transistor Q2 of the first switch circuit 110 and the first transistor Q1 of the third switch circuit 130 are both turned on, so the level states 1 and 3 are both low levels.

[0275] Furthermore, in cascade mode 2, the second switch circuit 120 is connected to the fourth expansion circuit 240, so the second transistor Q2 of the second switch circuit 120 is turned off, and the level state 2 output by the second switch circuit 120 is a high level. To distinguish between balanced mode and cascade mode 2, the third switch circuit 130 is required to output different level states in balanced mode and cascade mode 2. In this embodiment, since the fourth expansion circuit 240 is a pull-down circuit, in balanced mode, the third switch circuit 130 is connected to the fourth expansion circuit 240, the first transistor Q1 of the third switch circuit 130 is turned off, and the level state 3 output by the third switch circuit 130 is a high level, which is different from the low level output in cascade mode 2. This allows for distinction between balanced mode and cascade mode 2.

[0276] 1 represents a high level and 0 represents a low level. The three level states in the four modes can be seen in Table 4 below. Among them, "——" represents a level state that does not need to be paid attention to, which can be a high level or a low level. Based on the structure shown in Figure 19, it can be seen that in balanced mode, general mode or cascade mode 1, level state 3 remains unchanged. Therefore, in Table 1 below, in general mode or cascade mode 1, level state 3 is also a high level.

[0277] Table 4

[0278] The topology structure identification device provided in this embodiment can still identify the current topology structure mode and determine whether it is the balanced mode, common mode, cascade mode 1, or cascade mode 2 by combining the three level states output by the three switch circuits when the cascade mode of different connection methods affects the output of the first switch circuit 110.

[0279] According to some embodiments of the present application, a topology identification device embodiment is provided. The identification device can identify whether the current topology is balanced mode, universal mode, or cascade mode 2. That is, the identification device may not identify cascade mode 1. Figure 20 is a schematic structural diagram of a topology identification device according to an embodiment of the present application. As shown in Figure 20, the topology identification device includes: a first switch circuit 110, a second switch circuit 120, a third switch circuit 130, a first expansion circuit 210, a second expansion circuit 220, a third expansion circuit 230, and a fourth expansion circuit 240.

[0280] As shown in FIG20 , the first switch circuit 110 is a passive switch circuit, the second switch circuit 120 is a passive switch circuit, and the third switch circuit 130 is an active switch circuit. The first expansion circuit 210 is a pull-up circuit, the second expansion circuit 220 is a pull-down circuit, and the third expansion circuit 230 and the fourth expansion circuit 240 are both pull-down circuits.

[0281] In balanced mode, the second transistor Q2 of the first switch circuit 110 is off, and its output level state 1 is high. The second transistor Q2 of the second switch circuit 120 is off, and its output level state 2 is high. Furthermore, the third switch circuit 130 is connected to pin A27 of the second switching interface S0, while pin B27 of the second slot SLOT is left floating. Therefore, the first transistor Q1 of the second switch circuit 120 is on, and its output level state 3 is low.

[0282] In the general mode, the level state 1 outputted by the first switch circuit 110 remains unchanged and remains at a high level. The second transistor Q2 of the second switch circuit 120 is turned on, and the level state 2 outputted by the second switch circuit 120 is at a low level. The level state 3 outputted by the third switch circuit 130 remains unchanged and remains at a low level.

[0283] In cascade mode 2, the second transistor Q2 of the first switch circuit 110 and the first transistor Q1 of the third switch circuit 130 are both on, so both level states 1 and 3 are low. The second switch circuit 120 is connected to pin A27 of the second slot SLOT, and the second transistor Q2 of the second switch circuit 120 is off, so its output level state is high.

[0284] Furthermore, in cascade mode 2, the second switch circuit 120 is connected to the fourth expansion circuit 240, so the second transistor Q2 of the second switch circuit 120 is turned off, and the level state 2 output by the second switch circuit 120 is a high level. To distinguish between balanced mode and cascade mode 2, the third switch circuit 130 is required to output different level states in balanced mode and cascade mode 2. In this embodiment, since the fourth expansion circuit 240 is a pull-down circuit, in balanced mode, the third switch circuit 130 is connected to the fourth expansion circuit 240, the first transistor Q1 of the third switch circuit 130 is turned off, and the level state 3 output by the third switch circuit 130 is a high level, which is different from the low level output in cascade mode 2. This allows for distinction between balanced mode and cascade mode 2.

[0285] 1 represents a high level and 0 represents a low level. The three level states in the three modes are shown in Table 5 below.

[0286] Table 5

[0287] The topology identification device provided in this embodiment, combined with the three level states output by the three switch circuits, can identify the mode of the current topology structure and determine whether it is the balanced mode, the common mode, or the cascade mode 2.

[0288] According to an embodiment of the present application, an embodiment of a device for identifying a topology structure is provided. The device may include the circuits of the device for identifying a topology structure provided in any of the above embodiments, such as the first switch circuit 110, the second switch circuit 120, the first expansion circuit 210, the second expansion circuit 220, etc. Furthermore, the device may further include a controller 300. Figure 21 is a schematic diagram of the structure of a device for identifying a topology structure according to an embodiment of the present application.

[0289] The controller 300 is connected to the output terminals of a plurality of switching circuits and is configured to determine the mode of the current topology structure based on the level states output by the plurality of switching circuits. The plurality of switching circuits include a first switching circuit 110 and a second switching circuit 120. Alternatively, the plurality of switching circuits may further include a third switching circuit 130. The controller 300 collects level states 1 and 2, or level states 1, 2, and 3, and determines the mode of the current topology structure based on the high and low levels represented by these level states. The controller 300 may be a device having logic functions, such as a CPLD (Complex Programmable Logic Device), an FPGA (Field Programmable Gate Array), or the like.

[0290] Based on the same application concept, an embodiment of the present application further provides a server, which may be an AI server. As shown in FIG21 , the server includes: a first processor CPU0, a second processor CPU1, a first switch SW_A, a second switch SW_B, and the identification device provided in any of the above embodiments.

[0291] As shown in Figure 21, the first processor CPU0 and the second processor CPU1 are located on the mainboard (MB), and the first switch SW_A and the second switch SW_B are located on the switch board (SW Board). Furthermore, the first expansion circuit 210 and the second expansion circuit 220 can be located on the mainboard, and the first switch circuit 110 and the second switch circuit 120 can be located on the switch board. Similarly, the third switch circuit 130, the third expansion circuit 230, the fourth expansion circuit 240, and so on can also be located on the switch board. Based on the multiple switch states output by the identification device, the connection mode between the processors and switches in the server can be determined, that is, the topology mode can be determined.

[0292] In some embodiments, the server further includes a baseboard management controller (BMC), which is connected to the controller 300 of the identification device to obtain the current topology mode determined by the controller 300. As shown in FIG21 , the controller 300 and the BMC communicate via an interface J122. For example, the interface J122 may be an I2C (Inter-Integrated Circuit) interface.

[0293] As shown in Figure 21, after the cable between the processor and the switch is inserted, the identification device can output the corresponding level status, so that the controller 300 can determine the PCIe topology of the server based on these level states, and notify the BMC through I2C, so that production line personnel can know the current PCIe topology of the server through the BMC web page.

[0294] Although the embodiments of the present application have been described with reference to the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present application, and such modifications and variations shall fall within the scope defined by the appended claims.

Claims

1. A topological structure recognition device, characterized in that: include: A first switch circuit (110), a second switch circuit (120), a first expansion circuit (210), and a second expansion circuit (220); The first switch circuit (110) is configured to be connected to a cascade interface (S5) of a first switch (SW_A), and the second switch circuit (120) is configured to be connected to a switching interface of a second switch (SW_B); in a cascade mode, the cascade interface (S5) is connected to a switching interface of the second switch (SW_B); The first expansion circuit (210) is configured to be connected to an interface of a first processor (CPU0), and the second expansion circuit (220) is configured to be connected to an interface of a second processor (CPU1); in a balanced mode, a switching interface of the second switch (SW_B) is connected to an interface of the second processor (CPU1); in a common mode, a switching interface of the second switch (SW_B) is connected to an interface of the first processor (CPU0); When the first switch circuit (110) is connected to the switching interface of the second switch (SW_B), and when the first switch circuit (110) is not connected to the switching interface of the second switch (SW_B), the first switch circuit (110) outputs different level states respectively; When the second switch circuit (120) is connected to the first expansion circuit (210), and when the second switch circuit (120) is connected to the second expansion circuit (220), the second switch circuit (120) outputs different level states respectively.

2. The identification device according to claim 1, characterized in that The first switch circuit (110) is an active switch circuit or a passive switch circuit, and the second switch circuit (120) is an active switch circuit or a passive switch circuit; the first expansion circuit (210) is a pull-up circuit or a pull-down circuit; and the second expansion circuit (220) is a pull-up circuit or a pull-down circuit, wherein, when the second expansion circuit (220) is a pull-up circuit, the first expansion circuit (210) is a pull-down circuit, and when the second expansion circuit (220) is a pull-down circuit, the first expansion circuit (210) is a pull-up circuit; When the active switch circuit or the passive switch circuit is connected to the pull-up circuit, the active switch circuit or the passive switch circuit outputs a first level state; In the case where the active switch circuit or the passive switch circuit is connected to the pull-down circuit, the active switch circuit or the passive switch circuit outputs a second level state; When the active switch circuit is connected to the passive switch circuit, both the active switch circuit and the passive switch circuit output a first level state; When the two active switch circuits are connected, both of the two active switch circuits output a first level state; and When the two passive switch circuits are connected, both of the two passive switch circuits output a second level state; Wherein, when the first level state is a high level, the second level state is a low level, and when the first level state is a low level, the second level state is a high level.

3. The identification device according to claim 2, characterized in that: Also includes: A third expansion circuit (230); The third expansion circuit (230) is configured to be connected to the first slot (SLOT4); the first slot (SLOT4) is connected to the first switch (SW_A), and in a balanced mode or a universal mode, the cascade interface (S5) is connected to the first slot (SLOT4); as well as When the first switch circuit (110) is connected to the switching interface of the second switch (SW_B), and when the first switch circuit (110) is connected to the third expansion circuit (230), the first switch circuit (110) outputs different level states.

4. The identification device according to claim 3, characterized in that: The second switch (SW_B) comprises a first switching interface (S1); the second switch circuit (120) is configured to be connected to the first switching interface (S1); In the balanced mode, the first switching interface (S1) is connected to the interface of the second processor (CPU1); in the general mode, the first switching interface (S1) is connected to the interface of the first processor (CPU0); in the cascade mode, the cascade interface (S5) is connected to the first switching interface (S1); and When the first switch circuit (110) is connected to the second switch circuit (120), and when the first switch circuit (110) is connected to the third expansion circuit (230), the first switch circuit (110) outputs different level states.

5. The identification device according to claim 4, characterized in that: When the first switch circuit (110) is a passive switch circuit and the second switch circuit (120) is an active switch circuit, the third expansion circuit (230) is a pull-down circuit; When the first switch circuit (110) is an active switch circuit and the second switch circuit (120) is a passive switch circuit, the third expansion circuit (230) is a pull-down circuit; When both the first switch circuit (110) and the second switch circuit (120) are active switch circuits, the third expansion circuit (230) is a pull-down circuit; as well as When both the first switch circuit (110) and the second switch circuit (120) are passive switch circuits, the third expansion circuit (230) is a pull-up circuit.

6. The identification device according to claim 3, characterized in that: Also includes: A third switch circuit (130); the second switch (SW_B) comprises a first switch interface (S1) and a second switch interface (S0); The second switch circuit (120) is configured to be connected to the first switch interface (S1); the third switch circuit (130) is configured to be connected to the second switch interface (S0); In the balanced mode, the first switching interface (S1) is connected to the interface of the second processor (CPU1); in the general mode, the first switching interface (S1) is connected to the interface of the first processor (CPU0); in the cascade mode, the cascade interface (S5) is connected to the second switching interface (S0); and When the first switch circuit (110) is connected to the third switch circuit (130), and when the first switch circuit (110) is connected to the third expansion circuit (230), the first switch circuit (110) outputs different level states.

7. The identification device according to claim 6, characterized in that When both the first switch circuit (110) and the third switch circuit (130) are active switch circuits, the third expansion circuit (230) is a pull-down circuit; When the first switch circuit (110) is an active switch circuit and the third switch circuit (130) is a passive switch circuit, the third expansion circuit (230) is a pull-down circuit; When the first switch circuit (110) is a passive switch circuit and the third switch circuit (130) is an active switch circuit, the third expansion circuit (230) is a pull-down circuit; as well as When both the first switch circuit (110) and the third switch circuit (130) are passive switch circuits, the third expansion circuit (230) is a pull-up circuit.

8. The identification device according to claim 2, characterized in that: It also includes a third switch circuit (130); the second switch (SW_B) includes a first switching interface (S1) and a second switching interface (S0); The second switch circuit (120) is configured to be connected to the first switch interface (S1); the third switch circuit (130) is configured to be connected to the second switch interface (S0); in a balanced mode, the first switch interface (S1) is connected to an interface of the second processor (CPU1); in a common mode, the first switch interface (S1) is connected to an interface of the first processor (CPU0); in a cascade mode, the cascade interface (S5) is connected to the first switch interface (S1) or the second switch interface (S0); and When the cascade interface (S5) is connected to the first switching interface (S1) or the second switching interface (S0), the three level states output by the first switch circuit (110), the second switch circuit (120) and the third switch circuit (130) are not completely the same as the three level states output by the first switch circuit (110), the second switch circuit (120) and the third switch circuit (130) in a balanced mode or a common mode.

9. The identification device according to claim 8, characterized in that When the first switch circuit (110) is connected to the second switch circuit (120), and when the first switch circuit (110) is connected to the third switch circuit (130), the first switch circuit (110) outputs the same level state.

10. The identification device according to claim 9, characterized in that: The first switch circuit (110) is an active switch circuit; or The first switch circuit (110) is a passive switch circuit, and the second switch circuit (120) and the third switch circuit (130) are both active switch circuits.

11. The identification device according to claim 10, characterized in that: Also includes: A third expansion circuit (230); the third expansion circuit (230) is a pull-down circuit; The third expansion circuit (230) is configured to be connected to the first slot (SLOT4); and The first slot (SLOT4) is connected to the first switch (SW_A), and in a balanced mode or a universal mode, the cascade interface (S5) is connected to the first slot (SLOT4).

12. The identification device according to claim 9, characterized in that: It also includes: a third expansion circuit (230); the third expansion circuit (230) is a pull-up circuit; The third expansion circuit (230) is configured to be connected to the first slot (SLOT4); The first slot (SLOT4) is connected to the first switch (SW_A), and in a balanced mode or a universal mode, the cascade interface (S5) is connected to the first slot (SLOT4); and The first switch circuit (110), the second switch circuit (120) and the third switch circuit (130) are all passive switch circuits.

13. The identification device according to claim 8, characterized in that When the first switch circuit (110) is connected to the second switch circuit (120), and when the first switch circuit (110) is connected to the third switch circuit (130), the first switch circuit (110) outputs different level states; as well as When the third switch circuit (130) is connected to the first switch circuit (110), and when the third switch circuit (130) is not connected to the first switch circuit (110), the third switch circuit (130) outputs different level states respectively.

14. The identification device according to claim 13, characterized in that: Also includes: a fourth expansion circuit (240); the fourth expansion circuit (240) is configured to be connected to the second slot (SLOT6); the second slot (SLOT6) is mounted under the second switch (SW_B), and in a balanced mode or a universal mode, the second switching interface (S0) is connected to the second slot (SLOT6); and When the third switch circuit (130) is connected to the first switch circuit (110), and when the third switch circuit (130) is connected to the fourth expansion circuit (240), the third switch circuit (130) outputs different level states respectively.

15. The identification device according to claim 14, characterized in that The third expansion circuit (230) is a pull-down circuit, the fourth expansion circuit (240) is a pull-up circuit, the first switch circuit (110) is a passive switch circuit, the second switch circuit (120) is an active switch circuit, and the third switch circuit (130) is a passive switch circuit. The identification device further comprises: a third expansion circuit (230); the third expansion circuit (230) is configured to be connected to the first slot (SLOT4); and The first slot (SLOT4) is connected to the first switch (SW_A), and in a balanced mode or a universal mode, the cascade interface (S5) is connected to the first slot (SLOT4).

16. The identification device according to claim 14, characterized in that The third expansion circuit (230) is a pull-up circuit, the fourth expansion circuit (240) is a pull-down circuit, the first switch circuit (110) is a passive switch circuit, the second switch circuit (120) is a passive switch circuit, and the third switch circuit (130) is an active switch circuit. The identification device further comprises: a third expansion circuit (230); the third expansion circuit (230) is configured to be connected to the first slot (SLOT4); and The first slot (SLOT4) is connected to the first switch (SW_A), and in a balanced mode or a universal mode, the cascade interface (S5) is connected to the first slot (SLOT4).

17. The identification device according to any one of claims 2 to 16, characterized in that: The active switch circuit comprises a first transistor (Q1), a first voltage-dividing resistor (R11) and a first current-limiting resistor (R12); A first end of the first voltage-dividing resistor (R11) is connected to a power source, and a second end of the first voltage-dividing resistor (R11) is connected to a control end of the first transistor (Q1); A first end of the first current limiting resistor (R12) is connected to a power source, and a second end of the first current limiting resistor (R12) is connected to a first end of the first transistor (Q1); and The second end of the first transistor (Q1) is grounded; the control end of the first transistor (Q1) controls whether the first end of the first transistor (Q1) and the second end of the first transistor (Q1) are conductive, and the control end of the first transistor (Q1) is configured to be connected to an interface of a switch; and the first end of the first transistor (Q1) is configured to be in an output level state.

18. The identification device according to claim 17, characterized in that The pull-down circuit includes a pull-down resistor connected to ground; the resistance values ​​of the first voltage-dividing resistor (R11) and the pull-down resistor satisfy: VCC1×R down / (R down +R 11 ) <Vth1; Wherein, VCC1 represents the voltage value of the power supply connected to the first voltage-dividing resistor (R11), R 11 represents the resistance value of the first voltage-dividing resistor (R11), R down represents the resistance of the pull-down resistor, and Vth1 represents the on-voltage of the first transistor (Q1).

19. The identification device according to any one of claims 2 to 16, characterized in that: The passive switch circuit comprises a second transistor (Q2), a second voltage-dividing resistor (R21) and a second current-limiting resistor (R22); A first end of the second voltage-dividing resistor (R21) is connected to a control end of the second transistor (Q2), and a second end of the second voltage-dividing resistor (R21) is grounded; A first end of the second current limiting resistor (R22) is connected to a power source, and a second end of the second current limiting resistor (R22) is connected to a first end of the second transistor (Q2); and The second end of the second transistor (Q2) is grounded; the control end of the second transistor (Q2) controls whether the first end and the second end of the second transistor (Q2) are conductive, and is configured to be connected to an interface of a switch; and the first end of the second transistor (Q2) is configured to be in an output level state.

20. The identification device according to claim 19, characterized in that The pull-up circuit includes a pull-up resistor connected to a power supply; the resistance values ​​of the second voltage-dividing resistor (R21) and the pull-up resistor satisfy: VCC2×R 21 / (R up +R 21 )>Vth2; Wherein, VCC2 represents the voltage value of the power supply connected to the pull-up resistor, R 21 represents the resistance value of the second voltage-dividing resistor (R21), R up represents the resistance of the pull-up resistor, and Vth2 represents the on-voltage of the second transistor (Q2).

21. The identification device according to claim 1, characterized in that Also includes: Controller (300); The controller (300) is connected to the output ends of the plurality of switch circuits, and the controller (300) is configured to determine the mode of the current topology structure according to the level states of the outputs of the plurality of switch circuits; as well as The plurality of switch circuits include the first switch circuit (110) and the second switch circuit (120).

22. A server, characterized in that: include: A first processor (CPU0), a second processor (CPU1), a first switch (SW_A), a second switch (SW_B), and an identification device as claimed in any one of claims 1 to 21.

23. The server according to claim 22, characterized in that Also includes: Baseboard management controller; The baseboard management controller is connected to the controller (300) of the identification device, and the baseboard management controller is used to obtain the mode of the current topology structure determined by the controller (300).

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