Data transfer device and computer system

Abstract

A data transfer device (30) is provided with a plurality of transfer destination identifying units (41) which accept input of data of interest of a data flow in which a plurality of arithmetic processes are connected, and which identify the next transfer destination of the input data of interest on the basis of transfer destination information of the data of interest. The data transfer device (30) is provided with a switch (50) configured to be capable of simultaneously connecting any of a plurality of input ports (51) and any of a plurality of output ports (52) in any combination. The transfer destination identifying units (41) each control the switch (50) independently of one other, connect the input port (51) connected thereto to the output port (52) connected to the transfer destination identified by the transfer destination identifying unit (41) itself, and input the data of interest to the input port (52).

Description

Data transfer device and computer system

[0001] The present invention relates to a data transfer device and a computer system.

[0002] Technological innovation is progressing in many fields, including machine learning, artificial intelligence (AI), and the Internet of Things (IoT), and by utilizing various data, services are being actively enhanced and added value is being provided. These technologies require large amounts of calculations, and therefore an information processing infrastructure is essential.

[0003] For example, Non-Patent Document 1 points out that modern computers are unable to keep up with the rapidly increasing amount of data, and that in order to achieve further evolution in the future, "post-Moore technology" that goes beyond Moore's Law must be established.

[0004] As a post-Moore technology, for example, a technology called flow-centric computing is disclosed in Non-Patent Document 2. Flow-centric computing is different from the conventional computing concept of processing data where it is located, and introduces a new concept of moving data to a location where a computing function is present and processing the data there.

[0005] “NTT Technology Report for Smart World 2020,” Nippon Telegraph and Telephone Corporation, 2020, https: / / www.rd.ntt / _assets / pdf / techreport / NTT_TRFSW_2020_EN_W.pdf. R. Takano and T. Kudoh, “Flow-centric computing leveraged by photonic circuit switching for the post-Moore era,” Tenth IEEE / ACM International Symposium on Networks-on-Chip (NOCS), Nara, 2016, pp. 1–3. https: / / ieeexplore.ieee.org / abstract / document / 7579339

[0006] In the above-described flow-centric computing, the target data for the data flow operation must be transferred to the next destination, and it is important to reduce the delay during this transfer.

[0007] An object of the present invention is to reduce delays in the transfer of data that is the subject of a data flow operation.

[0008] In order to solve the above problem, the data transfer device of the present invention comprises a plurality of destination determination units that receive target data of a data flow that links a plurality of arithmetic processes and determine the next destination of the input target data based on destination information of the target data, and a switch that has a plurality of input ports and a plurality of output ports and is configured to be able to simultaneously connect any combination of any of the plurality of input ports to any of the plurality of output ports, and each of the plurality of destination determination units controls the switch independently of each other to connect an input port of the plurality of input ports that is connected to it to an output port of the plurality of output ports that is connected to the destination that it has determined, and inputs the target data to the input port.

[0009] The computer system of the present invention comprises a data transfer device and a plurality of calculation units connected one-to-one to a plurality of first destination determination units which are at least a part of the plurality of destination determination units, wherein the plurality of calculation units are respectively connected as the destination to a plurality of first output ports which are at least a part of the plurality of output ports of the switch, and each of the plurality of calculation units executes calculation processing which constitutes a data flow.

[0010] The computer system of the present invention comprises a data transfer device and a plurality of calculation units connected to a plurality of first destination determination units which are at least a part of the plurality of destination determination units, wherein the plurality of first destination determination units and the plurality of calculation units are connected in a one-to-many relationship, and the plurality of calculation units are respectively connected as the destination to a plurality of first output ports which are at least a part of the plurality of output ports of the switch, and each of the plurality of calculation units executes calculation processing which constitutes a data flow.

[0011] According to the present invention, delays in the transfer of data subject to data flow operations are reduced.

[0012] Fig. 1 is a block diagram showing the configuration of a computer system according to one embodiment of the present invention. Fig. 2 is a diagram showing an example of the configuration of data transferred in the computer system of Fig. 1. Fig. 3 is a diagram for explaining the operation of the computer system of Fig. 1. Fig. 4 is a diagram showing an example of the configuration of a correspondence table used in the computer system of Fig. 1. Fig. 5 is a block diagram showing the configuration of a computer system according to a modified example of the present invention.

[0013] (Embodiments) Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings, but the present invention is not limited to the following embodiments.

[0014] A computer system 10 according to the first embodiment shown in FIG. 1 is configured to execute a data flow in which a plurality of arithmetic processes are linked together.

[0015] The computer system 10 includes arithmetic circuits 20-1 to 20-N that perform arithmetic processing on input data, and a data transfer device 30 that transfers data from outside the system 10 and data resulting from processing from each of the arithmetic circuits 20-1 to 20-N to one of the arithmetic circuits 20-1 to 20-N or to outside the system 10. Hereinafter, the arithmetic circuits 20-1 to 20-N will also be collectively referred to as arithmetic circuits 20. Furthermore, the operations executed by the arithmetic circuits 20-1 to 20-N will be referred to as the first to Nth operations, respectively. For example, the arithmetic circuit 20-1 executes the first operation.

[0016] The computer system 10 may, for example, consist of a single server computer. Accordingly, the computer system 10 also includes a processor 11 such as a central processing unit (CPU), a main memory 12, and a non-volatile storage 13 for storing programs executed by the processor 11. Each arithmetic circuit 20 is configured as a single-chip field-programmable gate array (FPGA) serving as an accelerator. Here, each arithmetic circuit 20 executes one type of arithmetic processing. The execution unit for executing the arithmetic processing, which is provided in the arithmetic circuit 20, is configured or deleted at a desired timing. The desired timing includes when the computer system 10 is running. The execution unit for the arithmetic processing is configured or deleted by, for example, the processor 11. The arithmetic circuit 20 may be an application-specific integrated circuit (ASIC), a graphics processing unit (GPU), or the like. The arithmetic circuit 20 may also be a processor for executing a program.

[0017] Each of the first through Nth arithmetic processes may be an arithmetic process performed on target data of the data flow. The target data includes data before being input to the data flow (pre-processing data), data resulting from intermediate arithmetic processes included in the data flow (intermediate data), and data resulting from the final arithmetic process of the data flow (final data). Each of the first through Nth arithmetic processes constitutes at least one data flow among a plurality of data flows at least a portion of which can be executed by the computer system 10. For example, the first through third arithmetic processes are linked to form a first data flow, and the fourth arithmetic process, together with an arithmetic process executed by an arithmetic circuit provided in another computer system, constitutes a second data flow. Furthermore, for example, the first arithmetic process constitutes a third data flow together with the fifth arithmetic process in addition to the first data flow.

[0018] The first to Nth arithmetic processes may be different from one another, or some of them may be the same type of process. The arithmetic processes performed on data include, in addition to arithmetic operations on the data, processing, aggregation, and combination of target data, such as decoding encoded video data, reducing or enlarging the image size of image data, detecting a specific object from image data, and decrypting or encrypting image data.

[0019] The arithmetic circuits 20-1 to 20-N are each assigned an arithmetic circuit ID "#1" to "#N" that identifies the circuit. Note that "#1" to "#N" are simply numbers, and in reality, IP addresses or the like are assigned.

[0020] The data transfer device 30 includes a plurality of destination specification circuits 41-1 to 41-N connected to the arithmetic circuits 20-1 to 20-N, respectively, and one or more destination specification circuits 41-N+1 to 41-L (where L is an integer equal to or greater than N+1; here, L=N+2) to which data supplied from outside the computer system 10 is input. The destination specification circuits 41-1 to 41-L are also collectively referred to as destination specification circuits 41. The data transfer device 30 further includes a switch 50 to which each destination specification circuit 41 is connected.

[0021] As will be described later, the destination specification circuit 41 specifies the next destination of the input data, for example, the arithmetic circuit 20 that will perform the next arithmetic operation, and transfers the data to the destination via the switch 50. Each of the destination specification circuits 41-1 to 41-L is configured with an FPGA, an ASIC, or the like, and is configured to be able to operate independently of one another.

[0022] The switch 50, under the control of the destination specification circuit 41, transmits the data from the destination specification circuit 41 to the next destination.

[0023] The switch 50 includes a plurality of input ports 51-1 to 51-L to which the destination specification circuits 41-1 to 41-L are respectively connected. The switch 50 further includes output ports 52-1 to 52-N to which the arithmetic circuits 20-1 to 20-N are respectively connected, and one or more output ports 52-N+1 to 52-L for transmitting data to the outside of the computer system 10. The input ports 51-1 to 51-L are also collectively referred to as input ports 51. The output ports 52-1 to 52-L are also collectively referred to as output ports 52. The ports 51 and 52 are physical ports and may be general input / output interfaces, I / O ports such as Ethernet ports or PCIe ports.

[0024] The switch 50 is configured to be able to simultaneously connect any combination of input ports 51-1 to 51-L and any combination of output ports 52-1 to 52-L under the control of the destination specification circuit 41. Such a switch 50 is, for example, a crossbar switch.

[0025] Here, target data of a data flow input from outside to the computer system 10 will be described with reference to FIG. 2. The target data is accompanied by destination information for the target data, i.e., information that can identify the destination. Here, the destination information is stored in a header added before the target data, but the position of the destination information relative to the target data is arbitrary. The destination information stores the arithmetic circuit IDs of the arithmetic circuits 20 or external arithmetic circuits of the computer system 10 that perform multiple arithmetic operations on the data body using a data flow, in the order in which the arithmetic operations are performed. For example, as shown in FIG. 2, the destination information for target data that is arithmetically processed by the first data flow, in which a first arithmetic operation is performed, a second arithmetic operation is performed, and finally a third arithmetic operation is performed, includes, from the beginning of the data, "#1," which is the arithmetic circuit ID of the arithmetic circuit 20-1 that performs the first arithmetic operation, "#2," which is the arithmetic circuit ID of the arithmetic circuit 20-2 that performs the second arithmetic operation, and "#3," which is the arithmetic circuit ID of the arithmetic circuit 20-3 that performs the third arithmetic operation. The transfer destination information also includes at its end a processing result destination address (for example, an IP address) that identifies the destination of the data resulting from the processing of the entire data flow.

[0026] Next, the operation of the computer system 10 will be described with reference to FIG. 3. Here, target data, which is pre-processed data to be processed by the data flow, is input from the outside to the destination specification circuit 41-L of the computer system 10 (step S11). The target data is assumed to be data to be processed by the first data flow. As described above, destination information is attached to the target data (see FIG. 3). Data to be transferred below, such as the target data, may be divided into packets before being transferred. In such a case, destination information is stored in the header of each packet, and the arithmetic circuit 20 or the like combines the data bodies of the packets to obtain the data to be processed.

[0027] The destination specification circuit 41-L analyzes the destination information among the input target data and destination information (hereinafter, also referred to as input data) and acquires the first arithmetic circuit ID "#1" among the multiple arithmetic circuit IDs included in the destination information. By acquiring the first arithmetic circuit ID, the arithmetic circuit identified by the arithmetic circuit ID is specified as the next destination of the target data.

[0028] The transfer destination specification circuit 41-L holds a correspondence table showing the relationship between transfer destinations and the output ports to which the transfer destinations are connected, as shown in Fig. 4. In the correspondence table, the transfer destinations are represented by their identification information, i.e., the arithmetic circuit ID. The output ports are represented by port numbers (here, the code of the output port).

[0029] The destination specification circuit 41-L refers to the correspondence table using the acquired arithmetic circuit ID "#1" as a key, and acquires the port number "52-1" corresponding to the arithmetic circuit ID "#1." The destination specification circuit 41-L then controls the switch 50 (S12) to connect the input port 51-L connected to itself to the output port 52-1 of the acquired port number (S13). After controlling the connection between the input port 51-L and the output port 52-1, the destination specification circuit 41-L inputs input data to the switch 50 (S14). As a result, the input data is input to the arithmetic circuit 20-1 connected to the output port 52-1 via the data transfer path connecting the input port 51-L and the output port 52-1 (S15). As a result, the input data is transferred to the destination specified by the destination specification circuit 41-L.

[0030] The transfer destinations included in the correspondence table may be only the arithmetic circuit 20 included in the computer system 10. If the arithmetic circuit ID obtained above is not included in the correspondence table, the transfer destination specification circuit 41-L may, for example, connect the input port 51-L and the output port 52-L and output the input data as is to the outside of the system 10. Furthermore, a correspondence table is prepared individually for each of the transfer destination specification circuits 41-1 to 41-L. If the transfer destinations included in the correspondence table also include arithmetic circuits external to the computer system 10, the arithmetic circuit ID of the transfer destination is associated with one of the port numbers 52-N+1 to 52-L of the output ports connected to the outside of the computer system 10.

[0031] The arithmetic circuit 20-1 performs a first arithmetic process on target data from the input data. The arithmetic circuit 20-1 also deletes the first arithmetic circuit ID "#1" from the destination information. The arithmetic circuit 20-1 uses the data resulting from the first arithmetic process, i.e., the intermediate data, as new target data, and generates intermediate post-operation data by adding the destination information after the deletion of the arithmetic circuit ID "#1" to the target data. The arithmetic circuit 20-1 transmits the generated intermediate post-operation data to the destination specification circuit 41-1 connected to the arithmetic circuit 20-1 (step S16).

[0032] The destination specification circuit 41-1 analyzes the destination information of the received post-intermediate computation data and acquires the first computation circuit ID "#2" from among the computation circuit IDs included in the additional data. In other words, the destination specification circuit 41-1 specifies the destination of the current post-intermediate computation data. The destination specification circuit 41-1 uses the acquired computation circuit ID "#2" as a key to refer to its own correspondence table and acquires the port number "52-2" corresponding to the computation circuit ID "#2". Thereafter, the destination specification circuit 41-1 controls the switch 50 (S17) to connect the input port 51-1 connected to itself to the output port 52-2 of the acquired port number (S18). After controlling the connection between the input port 51-1 and the output port 52-2, the destination specification circuit 41-1 inputs the post-intermediate computation data to the switch 50 (S19). As a result, the intermediate post-operation data is input to the operation circuit 20-2 connected to the output port 52-2 via the switch 50, more specifically, via the input port 51-1, the output port 52-2, and the data transfer path connecting both ports (S20).

[0033] After this, the calculation circuit 20-2, like the calculation circuit 20-1, performs a second calculation process on the target data (intermediate data) contained in the intermediate calculation-post data and deletes the first calculation circuit ID "#2" from the transfer destination information, and outputs the target data and transfer destination information after the second calculation process and after the calculation circuit ID deletion as second intermediate calculation-post data to the transfer destination determination circuit 41-2 (step S21).

[0034] The second intermediate post-operation data output to the destination specification circuit 41-2 is input to the operation circuit 20-3 via the destination specification circuit 41-2 and the switch 50 (steps S22 to S25). At this time, the destination specification circuit 41-2, like the destination specification circuit 41-1, refers to the correspondence table it holds and controls the connection between the input port 51-2 and the output port 52-3.

[0035] The arithmetic circuit 20-3 performs a third arithmetic process on the target data of the second intermediate post-operation data and deletes the leading arithmetic circuit ID "#3" from the destination information, and outputs the target data and destination information after the third arithmetic process and after the deletion of the arithmetic circuit ID as third intermediate post-operation data to the destination specification circuit 41-3 (step S26). At this point, the destination information no longer includes the arithmetic circuit ID, so the third intermediate post-operation data becomes the final post-operation data after each arithmetic process by the data flow has been completed.

[0036] If the destination information for the final post-computation data does not include a computation circuit ID, the destination specification circuit 41-3 connects the input port 51-3 of the switch 50 connected to itself to any one of the output ports 52-L+1 to 52-L, in this case, to output port 52-L, in order to transfer the final post-computation data to an external location in the system 10 (steps S27 and S28). The destination specification circuit 41-3 then transmits the final post-computation data to the input port 51-3, with the destination address (e.g., IP address) of the final post-computation data included at the end of the destination information and, if necessary, the MAC address obtained by referencing a routing table, set in the header or the like as the final destination and the destination of the next device (step S29). This ultimately results in the processing result of the first data flow being sent to the final destination (step S30).

[0037] In this embodiment, the switch 50 is configured to simultaneously connect multiple pairs of any combination of input ports 51-1 to 51-L and output ports 52-1 to 52-L. For example, the combination of input port 51-2 and output port 52-1 and the combination of input port 51-3 and output port 52-2 can be simultaneously connected. Meanwhile, each destination specification circuit 41 can independently control the switch 50, connecting the input port 51 connected to itself with the output port 52 connected to the destination specified by the destination specification circuit 41, and inputting target data to the connected input port 51. Therefore, as long as the output ports 52 do not overlap, multiple pairs of input ports 51 and output ports 52 can be independently connected, and data transfer is also performed in parallel between each pair. Conventionally, such parallel transfer was not performed, resulting in data congestion during transfer when multiple types of data flows were executed simultaneously in parallel. The parallel transfer of this embodiment eliminates such congestion. In this way, according to this embodiment, delays in the transfer of target data for data flow operations are reduced (including elimination of delays).

[0038] In this embodiment, each transfer destination determination circuit 41 holds a correspondence table between the transfer destination and the output port to which this transfer destination is connected, and refers to this correspondence table to identify the output port 52 to connect to the input port 51, thereby realizing the connection between the input port 51 and the output port 52 with a simple circuit configuration.

[0039] In this embodiment, the switch 50 is a crossbar switch, which allows parallel transfer of data performed by a plurality of data flows to be realized with a simple configuration.

[0040] In this embodiment, the destination specification circuits 41-N+1 to 41-L and the output ports 52-N+1 to 52-L are connected to the outside of the computer system 10, so that data supplied from the outside can also pass through the destination specification circuits 41-N+1 to 41-L. Moreover, under the control of the destination specification circuits 41-N+1 to 41-L, data can be output to the outside from the output ports 52-N+1 to 52-L.

[0041] (Variation 1) In the above embodiment, the arithmetic circuits 20-1 to 20-N are connected to the destination specification circuits 41-1 to 41-N in a one-to-one relationship. However, as shown in the computer system 110 of FIG. 5, multiple destination specification circuits 41 and multiple arithmetic circuits 20 may be connected in a one-to-multiple relationship (see the destination specification circuit 41-1 and the multiple arithmetic circuits 20-1 and 20-2). In the one-to-multiple relationship, the overall circuit size of the multiple destination specification circuits 41 can be made smaller than in the one-to-one relationship, reducing the control and implementation costs of the destination specification circuit 41. In the one-to-one relationship, multiple data flows are executed independently without interfering with each other. Furthermore, since multiple data flows do not mix with each other, the system can be isolated and virtualization is also possible. Furthermore, when a specific data flow is congested, the impact on other data flows can be reduced.

[0042] (Variation 2) As a variation, multiple computer systems may be connected. That is, the computer system 10 or 110 may be configured to include an arithmetic circuit provided in each of multiple computers, rather than a single computer. That is, the computer system 10 or 110 may include an arithmetic circuit 20 of another computer connected to the data transfer device 30 via a network, a router, a network switch, or the like. In such a case, the transfer destination specification circuit 41, for example, references a predetermined routing table and includes information such as the IP address of the final transfer destination arithmetic circuit 20 and the MAC address of the next device to send data, in the data to be transferred.

[0043] In such a modified example, the correspondence table held by the destination specification circuit 41 may register information about all destinations (such as arithmetic circuit IDs) of other computer systems, or may register information about only a portion of the destinations. Furthermore, the destinations in the correspondence table may be represented by the addresses of the other computer systems themselves. If the correspondence table contains only a portion of all possible destinations, it is easy to determine in advance what should be registered in the correspondence table when setting the target data and destination information that can pass through the destination specification circuit 41 before the start of operation, and the correspondence table can be implemented with less control cost. For example, if the destinations in the correspondence table are the addresses of the other computer systems themselves, the correspondence table does not need to include information about the arithmetic circuits that the other computer systems have, and the correspondence table can be implemented with less control cost.

[0044] Furthermore, the function of the transfer destination specification circuit 41 may be provided in a network switch or host machine that connects computer systems together, thereby enabling data transfer to other computer systems to be performed in the network switch or host machine.

[0045] (Variation 3) In the above, one execution unit for arithmetic processing is configured for each arithmetic circuit 20, but multiple types of execution units may be configured. In this case, the arithmetic circuit ID includes, for example, the address of the arithmetic circuit 20 as well as data identifying the execution unit for the arithmetic processing (for example, the address of the execution unit). The arithmetic circuit 20 simply performs the arithmetic processing using the execution unit indicated by the data.

[0046] (Modification 4) The transfer destination information does not have to be added to the target data and transferred. For example, a configuration may be adopted in which the transfer destination information is transferred via a separate signal line in synchronization with the target data.

[0047] (Variation 5) The correspondence table is set before the execution of the data flow starts. This setting may be performed inline with the execution line of the data flow by inputting a predetermined control packet into the computer system 10, or may be performed out-of-line using a management port or the like provided in the system 10.

[0048] (Variation 6) Executable data flows may be added or deleted as appropriate. For example, when a data flow is added, it is not necessary to change the settings of all data flows, i.e., to replace the entire correspondence table, and only information about the added data flow (information about the transfer destination and output port) may be added to the correspondence table. The same applies when a data flow is deleted; only information about the deleted data flow may be deleted from the correspondence table.

[0049] (Variation 7) The destination specification circuit 41 may monitor its own operating status and data flow rate, and may change the correspondence table, i.e., the executable data flow, when the operating status or data flow rate exceeds a predetermined threshold. The changes to the correspondence table may be specified externally. This change reduces the load on a specific destination specification circuit 41 and / or a specific arithmetic circuit 20.

[0050] (Variation 8) The destination specification circuit 41 may change the correspondence table, i.e., the executable data flows, when the data size of the correspondence table it holds exceeds a predetermined threshold. In this way, the time required to refer to the correspondence table is reduced and the time required for transfer processing among multiple data flows is equalized.

[0051] (Scope of the present invention) The present invention is not limited to the above-described embodiments and modifications. For example, the present invention includes various modifications to the above-described embodiments and modifications that can be understood by a person skilled in the art within the scope of the technical concept of the present invention. The configurations listed in the above-described embodiments and modifications can be combined as appropriate within a range that does not contradict. Furthermore, any of the above-described configurations can be deleted.

[0052] (Supplementary Notes) Examples of configurations disclosed in the above embodiments and variations are given below. (Supplementary Note 1) A data transfer device comprising: a plurality of transfer destination specification units that receive input target data of a data flow in which a plurality of arithmetic processes are linked, and specify a next transfer destination for the input target data based on transfer destination information for the input target data; and a switch having a plurality of input ports and a plurality of output ports, configured to be able to simultaneously connect a plurality of pairs of any combination of any of the plurality of input ports and any of the plurality of output ports, wherein each of the plurality of transfer destination specification units independently controls the switch to connect an input port of the plurality of input ports connected to itself with an output port of the plurality of output ports connected to the transfer destination specified by itself, and inputs the target data to the input port. (Supplementary Note 2) The data transfer device according to Supplementary Note 1, wherein each of the plurality of transfer destination specification units holds a correspondence table between transfer destinations and output ports to which the transfer destinations are connected, and specifies the output port to be connected to the input port by referring to the correspondence table. (Supplementary Note 3) The data transfer device according to Supplementary Note 1 or 2, wherein the switch is a crossbar switch. (Supplementary Note 4) A computer system comprising: the data transfer device according to any one of Supplements 1 to 3; and a plurality of arithmetic units connected in a one-to-one relationship to a plurality of first destination specification units that are at least a part of the plurality of destination specification units, wherein the plurality of arithmetic units are connected as the transfer destinations to a plurality of first output ports that are at least a part of the plurality of output ports of the switch, and each of the plurality of arithmetic units executes arithmetic processing that constitutes a data flow. (Supplementary Note 5) A computer system comprising: the data transfer device according to any one of Supplements 1 to 3; and a plurality of arithmetic units connected to a plurality of first destination specification units that are at least a part of the plurality of destination specification units, wherein the plurality of first destination specification units and the plurality of arithmetic units are connected in a one-to-multiple relationship, and the plurality of arithmetic units are connected as the transfer destinations to a plurality of first output ports that are at least a part of the plurality of output ports of the switch, and each of the plurality of arithmetic units executes arithmetic processing that constitutes a data flow.(Supplementary Note 6) The computer system described in Supplementary Note 4 or 5, wherein the plurality of forwarding destination specification units are made up of the plurality of first forwarding destination specification units that are a part of the plurality of forwarding destination specification units and the remaining one or more second forwarding destination specification units, the plurality of output ports are made up of the plurality of first output ports that are a part of the plurality of forwarding destination specification units and the remaining one or more second output ports, and the second forwarding destination specification unit and the second output port are connected to the outside of the computer system.

[0053] 10...Computer system, 11...Processor, 12...Main memo, 13...Storage, 20-1 to 20-N...Arithmetic circuit, 30...Data transfer device, 41-1 to 41-N to 41-L...Destination specification circuit L, 50...Switch, 51-1 to 51-N to 51-L...Input port, 52-1 to 52-N to 52-L...Output port, 110...Computer system.

Claims

1. A data transfer device comprising: a plurality of destination determination units which receive target data of a data flow in which a plurality of arithmetic processes are linked, and which determine the next destination of the input target data based on destination information of the target data; and a switch which has a plurality of input ports and a plurality of output ports, and is configured to be able to simultaneously connect any combination of any of the plurality of input ports to any of the plurality of output ports, wherein each of the plurality of destination determination units independently controls the switch to connect an input port of the plurality of input ports connected to itself to an output port of the plurality of output ports connected to the destination determined by itself, and inputs the target data to the input port.

2. The data transfer device according to claim 1, wherein each of the plurality of transfer destination determination units holds a correspondence table between transfer destinations and output ports to which the transfer destinations are connected, and refers to the correspondence table to determine the output port to be connected to the input port.

3. The data transfer device according to claim 1, wherein the switch is a crossbar switch.

4. A computer system comprising: the data transfer device according to claim 1; and a plurality of calculation units connected in a one-to-one relationship to a plurality of first destination specification units which are at least a portion of the plurality of destination specification units, wherein the plurality of calculation units are respectively connected as the destination to a plurality of first output ports which are at least a portion of the plurality of output ports of the switch, and each of the plurality of calculation units executes a calculation process constituting a data flow.

5. A computer system comprising: the data transfer device according to claim 1; and a plurality of calculation units connected to a plurality of first destination determination units which are at least a part of the plurality of destination determination units, wherein the plurality of first destination determination units and the plurality of calculation units are connected in a one-to-multiple relationship, and the plurality of calculation units are respectively connected as the destination to a plurality of first output ports which are at least a part of the plurality of output ports of the switch, and each of the plurality of calculation units executes a calculation process which constitutes a data flow.

6. A computer system as described in claim 4 or 5, wherein the multiple destination determination units are composed of the multiple first destination determination units which are a part of the multiple destination determination units and the remaining one or more second destination determination units, the multiple output ports are composed of the multiple first output ports which are a part of the multiple output ports and the remaining one or more second output ports, and the second destination determination unit and the second output port are connected to the outside of the computer system.

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