Ternary full adder circuit and ternary full adder circuit design method

Abstract

The present invention relates to a ternary full adder circuit and, more specifically, to a ternary full adder circuit using an anti-ambipolar transistor, and a ternary full adder circuit design method, wherein the ternary full adder circuit is implemented using the anti-ambipolar transistor to implement an intermediate state, so that leakage current generated during a switching operation can be significantly reduced.

Description

Ternary full-adder circuit and design method of a ternary full-adder circuit

[0001] The present invention relates to a ternary full-adder circuit, and more particularly, to a ternary full-adder circuit using anti-ambipolar transistors and a method for designing a ternary full-adder circuit.

[0002]

[0003] With the advancement of Fourth Industrial Revolution technologies like artificial intelligence, the amount of data to be processed is increasing exponentially. Consequently, the demand for devices capable of processing more data in a single period of time has grown. To meet this demand, smaller devices have been developed to accommodate more devices within the same footprint, thereby improving speed.

[0004] However, as current binary-based systems approach the nanometer scale, uniform component fabrication and further integration are becoming impossible. Furthermore, because current binary-based systems process data in two representations, an astronomical number of components is required to handle the current high data volumes.

[0005] To solve these problems, the development of a ternary system is required.

[0006] The ternary system offers the advantage of handling more data than the binary system by processing data in three representations (-1, 0, 1, or 0, 1, 2). However, the existing ternary system suffers from the problem of large leakage current when implementing intermediate states.

[0007]

[0008] The technical problem of the present invention is proposed to solve such problems, and its purpose is to provide a ternary full-adder circuit and a ternary full-adder circuit design method using a semi-bipolar transistor.

[0009] However, the purpose of the present invention is not limited to the above purpose, and other purposes not mentioned can be clearly understood from the description below.

[0010]

[0011] In order to achieve the above-described object, according to an embodiment of the present invention, a ternary full adder circuit that performs an operation and outputs a sum output signal and a carry output signal when a first input signal, a second input signal, and a carry input signal having any one of ternary logic values ​​are input, comprises: a first half adder comprising a first SUM gate that performs a first operation on the first input signal and the second input signal to output a sum signal and a first NCONS gate that outputs a first carry signal according to the first operation; a second half adder comprising a second SUM gate that performs a second operation on the sum signal of the first half adder and the carry input signal to output the sum output signal and a second NCONS gate that outputs a second carry signal according to the second operation; And a NANY gate that operates on a first carry signal of the first half adder and a second carry signal of the second half adder to output a carry output signal; wherein each of the first half adder, the second half adder, and the NANY gate may include a ground network composed of at least one anti-ambipolar transistor connected to a ground power supply (GND) for outputting an intermediate logic value among the ternary logic values.

[0012] At this time, the ground network of the first SUM gate and the second SUM gate may include a positive semi-bipolar transistor; and a negative semi-bipolar transistor for each input signal, which is connected in series to the positive semi-bipolar transistor.

[0013] Additionally, the ground network included in the NANY gate may be configured to include a positive anti-bipolar transistor; and a negative anti-bipolar transistor connected in parallel to the positive anti-bipolar transistor, the drain of which is connected to an N-type transistor connected to a ground voltage source, and the source of which is connected to an output node.

[0014] Additionally, the ground network included in the first NCONS gate and the second NCONS gate is connected in parallel to the output node and can be connected by alternately arranging a negative anti-bipolar transistor and a positive anti-bipolar transistor for each input signal.

[0015] In addition, each margin buffer is further connected to each output node that outputs the sum output signal and the carry output signal, and each margin buffer may include a ground network in which at least two anti-bipolar transistors are connected in a stacked manner.

[0016] At this time, one or more STI gates may be further included to compensate for the values ​​of each of the above margin buffers.

[0017] In order to achieve the above-described object, a method for designing a ternary full-adder circuit according to an embodiment of the present invention includes the steps of: setting a switching condition according to a ternary logic value; setting one or more ternary logic gates according to the set switching condition; and designing a ternary full-adder circuit by combining the set ternary logic gates; wherein the one or more logic gates may be configured to include a ground network including at least one anti-ambipolar transistor connected to a ground power supply (GND) for outputting an intermediate logic value among the ternary logic values.

[0018] At this time, the ternary logic values ​​are -1, 0, +1, and the ternary full adder circuit may be a balanced ternary full adder circuit.

[0019]

[0020] According to the ternary full-adder circuit and the ternary full-adder circuit design method of the present invention, by using a semi-bipolar transistor to implement an intermediate state, the leakage current generated during a switching operation is greatly reduced, thereby enabling the implementation of a more efficient ternary full-adder circuit.

[0021] In addition, various effects other than the above-described effects may be disclosed directly or implicitly in the detailed description according to the embodiments of the present invention to be described later.

[0022]

[0023] Figure 1 is an exemplary diagram for explaining the structure of a semi-bipolar transistor of the present invention.

[0024] Figures 2 and 3 are graphs for explaining the characteristics of a semi-bipolar transistor.

[0025] Fig. 4 illustrates a circuit diagram and symbol of an STI gate using a semi-bipolar transistor of the present invention.

[0026] FIG. 5 is an exemplary diagram for explaining the on / off switching operation according to the channel direction of the semi-bipolar transistor of the present invention.

[0027] Fig. 6 illustrates a circuit diagram and symbol of a NANY gate using a semi-bipolar transistor of the present invention.

[0028] Fig. 7 illustrates a circuit diagram and symbol of a TAND gate using a semi-bipolar transistor of the present invention.

[0029] Fig. 8 illustrates a circuit diagram and symbol of a TNOR gate using a semi-bipolar transistor of the present invention.

[0030] Fig. 9 illustrates a circuit diagram and symbol of an NCONS gate using a semi-bipolar transistor of the present invention.

[0031] Fig. 10 illustrates a circuit diagram and symbol of a SUM gate using a semi-bipolar transistor of the present invention.

[0032] FIG. 11 is a diagram illustrating a ternary full adder circuit according to an embodiment of the present invention.

[0033] FIG. 12 is a diagram illustrating a ternary full adder circuit according to another embodiment of the present invention.

[0034] FIG. 13 is a circuit diagram illustrating a stacked STI gate according to another embodiment of the present invention.

[0035] FIG. 14 is an exemplary diagram comparing output waveforms of a ternary full adder circuit according to another embodiment of the present invention.

[0036] Figure 15 is a flowchart for explaining a method for designing a ternary full adder circuit according to an embodiment of the present invention.

[0037]

[0038] <Description of drawing symbols>

[0039] 100: STI Gate

[0040] 110: Top Network

[0041] 120: Bottom network

[0042] 130: Grounding network

[0043] 700: Ternary full adder circuit

[0044] 710: First half adder

[0045] 720: Second half adder

[0046] 730: NANY Gate

[0047]

[0048] In order to more clearly explain the features and advantages of the problem-solving means of the present invention, the present invention will be described in more detail with reference to specific embodiments of the present invention illustrated in the attached drawings.

[0049] However, detailed descriptions of known functions or components that may obscure the gist of the present invention in the following description and attached drawings are omitted. It should also be noted that, where possible, identical components are indicated with identical reference numerals throughout the drawings.

[0050] The terms and words used in the following description and drawings should not be interpreted as limited to their conventional or dictionary meanings, but should be interpreted with meanings and concepts that conform to the technical idea of ​​the present invention based on the principle that the inventor can appropriately define the concept of the term to best describe his or her invention. Therefore, the embodiments described in this specification and the configurations illustrated in the drawings are merely the most preferred embodiments of the present invention and do not represent all of the technical idea of ​​the present invention. Therefore, it should be understood that there may be various equivalents and modified examples that can replace them at the time of filing this application.

[0051] Additionally, terms containing ordinal numbers, such as "first," "second," etc., are used to describe various components, and are only used to distinguish one component from another, not to limit said components. For example, without departing from the scope of the present invention, a second component could be referred to as a "first component," and similarly, a first component could also be referred to as a "second component."

[0052] Additionally, when a component is referred to as being "connected" or "connected" to another component, this means that the component can be connected or connected logically or physically. In other words, while a component may be directly connected or connected to another component, it should be understood that other components may exist in between, and that the component may be connected or connected indirectly.

[0053] In addition, the terminology used in this specification is only used to describe specific embodiments and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly indicates otherwise. In addition, it should be understood that the terms "comprises" or "has" described in this specification are intended to specify the presence of a feature, number, step, operation, component, part, or combination thereof described in the specification, but do not exclude in advance the possibility of the presence or addition of one or more other features, numbers, steps, operations, components, parts, or combinations thereof.

[0054] Below, before describing a ternary full-adder circuit and a ternary full-adder circuit design method according to an embodiment of the present invention, an anti-ambipolar transistor (AAT) used in the ternary full-adder circuit of the present invention will first be described.

[0055] FIG. 1 is an exemplary diagram for explaining the structure of a semi-bipolar transistor of the present invention, and FIGS. 2 and 3 are graphs for explaining the characteristics of the semi-bipolar transistor.

[0056] First, referring to FIG. 1, a semi-bipolar transistor (30) used in a ternary full-adder circuit according to an embodiment of the present invention will be described. The semi-bipolar transistor (30) according to an embodiment of the present invention may be configured to include a substrate (310), an insulating film (320), a channel (330), and an electrode (340).

[0057] The substrate (310) may include a semiconductor substrate such as doped silicon (Si) and may serve as a gate electrode (G, 311).

[0058] And, an insulating film (320) is formed on the substrate (310). Here, the insulating film (320) may use, for example, hafnium oxide (HfO2), and the insulating film (320) may include a structure that completely covers one surface of the substrate (310).

[0059] The electrode (340) includes a source electrode (S, 341) and a drain electrode (D, 342), and may be made of, for example, an Ag material. In addition, when an input voltage is applied from the gate electrode (S, 311), the source electrode (341) and the drain electrode (342) are connected to each other to form a channel (330).

[0060] More specifically, the channel (330) of the semi-bipolar transistor (30) of the present invention is configured to include two types of channels.

[0061] That is, the semi-bipolar transistor (30) of the present invention can exhibit two current characteristics at once, namely, the N-type channel (331) characteristic and the P-type channel (332) characteristic, by using two types of N-type channels (331) and P-type channels (332).

[0062] The current resistance characteristics of these N-type channels (331) and P-type channels (332) are shown in Fig. 2, where the N-type channel (331) has a low V GS It transmits a very small current with high resistance, and the P type channel (332) has a high V GS In this way, V transmits a very small current with high resistance. GS As the current increases, the current characteristic of the anti-ambipolar transistor (30) increases until it reaches a peak and then decreases, showing an inverted V-shaped curve. In the present invention, a ternary logic gate capable of showing an intermediate state can be implemented by utilizing the current characteristic of the anti-ambipolar transistor (30).

[0063] In addition, the channel (330) can generally be configured to include materials such as MoS2, MoSe2, WS2, WSe2, MoTe2, and ReS2, but in the case of a transistor including such materials, the problem of increased manufacturing cost may arise.

[0064] Therefore, in order to solve this problem in the embodiment of the present invention, the N-type channel (331) may use indium oxide (InO), and the P-type channel (332) may use a single-wall carbon nanotube (SWCNT).

[0065] Here, the thickness of the SWCNT can affect the magnitude of the maximum current, and in a preferred embodiment of the present invention, a three-layer SWCNT can be applied.

[0066] In this way, the semi-bipolar transistor (30) according to the embodiment of the present invention does not flow current because the channel is not connected (N-ch OFF, P-ch OFF) at high level input voltage and low level input voltage, and the maximum current (V) is input when the specified input voltage, i.e., ground voltage (GND, 0 V) ​​is input.PEAK ), it exhibits characteristics that are different from those of a typical CMOS transistor that operates at high-level input voltage and low-level input voltage.

[0067] By utilizing the current characteristics of such a semi-bipolar transistor (30), as shown in Fig. 3, by using three transistors that perform independent operations, each connected to a different voltage source, to output different output voltages depending on the level of the input voltage, it is possible to implement a ternary logic gate capable of expressing three types of data.

[0068] Hereinafter, the semi-bipolar transistor switching operation will be described in more detail, focusing on the STI gate among the ternary logic gates according to an embodiment of the present invention.

[0069] Fig. 4 illustrates a circuit diagram and symbol of an STI gate using a semi-bipolar transistor of the present invention.

[0070] Referring to FIG. 4, the STI (Standard Ternary Inverter) gate (100) according to an embodiment of the present invention means a basic ternary inverter circuit, i.e., a NOT gate.

[0071] The STI gate (100) of the present invention is a gate that inverts the input signal (A) and outputs it as an output signal (Y), and is located at the top based on the node of the output signal (Y), and is connected to a drain power source, i.e., a high level voltage source (V DD ) is located at the bottom of the output node (Y), and is connected to the upper network (110), which is the source power, i.e., the low level voltage source (V SS ) and a ground network (130) connected to a ground power source (GND, 0V).

[0072] The network referred to in the present invention refers to a structure in which elements are physically connected to each other, and can be used in the same meaning as a circuit. The upper network referred to in the present invention is a high-level voltage source (V DD ) is connected to a drain power supply and includes one or more P-type transistors having a drain voltage (V DD ) network, and the lower network is a low-level voltage source (V SS ) is connected to a source power supply and includes a source voltage (V) including one or more N-type transistors. SS ) network. The ground network is also connected to a ground supply (GND), which is an intermediate level voltage source, and may be composed of a combination of transistors including one or more anti-bipolar transistors.

[0073] An STI gate (100) according to an embodiment of the present invention may be composed of an upper network (110) composed of one P-type transistor, a lower network (120) composed of one N-type transistor, and a ground network (130) composed of one semi-bipolar transistor.

[0074] The P-type transistor of the upper network (110) and the N-type transistor of the lower network (120) are CMOS (Complementary Metal-Oxide Semiconductor) transistors that operate complementarily to each other, and the ground network (130) can be arranged in parallel with the upper network (110) and the lower network (120).

[0075] In this STI gate (100), the gates of each transistor constituting the upper network (110), the lower network (120), and the ground network (130) are commonly connected to an input signal (A) at point P1, the drains of each transistor of the upper network (110) and the lower network (120) are connected to an output signal (Y) at point P2, and the semi-bipolar transistor drain of the ground network (130) is connected at point P3 to output an output signal (Y).

[0076] Each transistor constituting each network (110, 120, 130) of the STI gate (100) according to an embodiment of the present invention has its source connected to a different voltage source as described above, and outputs the voltage of the different voltage sources as an output voltage according to the voltage level of the input voltage, thereby enabling output of multiple logic states.

[0077] Here, the input voltage can have a voltage value between a high level voltage and a low level voltage, for example, the voltage of the input voltage can be 1V, 0V, -1V.

[0078] At this time, if the input signal (A) is a low level voltage (-1 V), the upper network (110) is switched on, and the lower network (120) and the ground network (130) are switched off, so that a high level voltage source (V) is connected to the P-type transistor of the upper network (110), which is the drain voltage. DD ) is output as an output signal (Y).

[0079] And when the input signal (A) is a high level voltage (1 V), the upper network (110) is switched off, the lower network (120) is switched on, and the ground network (130) is switched off. Therefore, the source and drain of the N-type transistor of the lower network (120) are connected to the low level voltage source V, which is the source power source. SSA voltage of (-1V) is output through the drain as an output signal (Y).

[0080] And when the input signal (A) is an intermediate voltage, i.e., a ground voltage (0 V), both the upper network (110) and the lower network (120) are switched off, and according to the characteristics of the semi-polar transistor that turns on when the input voltage is a ground voltage, the semi-polar transistor of the ground network (130) is switched on, so that the voltage of the voltage source (GND, 0 V) ​​is output as the output signal (Y).

[0081] In this way, the SIT gate (100) of the present invention uses three different transistors each connected to a different independent voltage source, thereby receiving different input voltages (V A ) are input, different output voltages (V Y ) can be output, and through this, three operating states can be expressed, and the role of outputting the intermediate state by connecting to a voltage source is performed by a semi-bipolar transistor.

[0082] A semi-bipolar transistor according to an embodiment of the present invention includes two channels, an N-type channel and a P-type channel, as described with reference to FIG. 1. The semi-bipolar transistor of the present invention described with reference to FIG. 4 operates as a positive network in which the N-type channel is connected to a ground voltage source (GND, 0 V) ​​as a source electrode and the P-type channel is connected to a drain electrode, and when the two channels are connected to each other, the ground voltage connected to the source electrode is output as an output signal. However, depending on the implementation method, the semi-bipolar transistor may also operate as a negative network in which the directions of the channels are opposite, which will be described with reference to FIG. 5.

[0083] FIG. 5 is for explaining the on / off switching operation according to the channel direction of the semi-bipolar transistor of the present invention, and FIG. 5 (a) illustrates that the on / off switching operation may vary depending on the channel direction of the semi-bipolar transistor, i.e., whether it is a positive network or a negative network.

[0084] In other words, the semi-bipolar transistor according to the embodiment of the present invention described above has a positive network (AAT) P ) as input voltage (V IN ) is 0V, the connected voltage source ground voltage (0V) is output.

[0085] However, the semi-bipolar transistor of the present invention has a negative network (AAT) N ) is operated as a drain electrode, that is, when the P-type channel is connected to the ground voltage and the N-type channel operates as a drain electrode, the input voltage (V IN ) can be switched on and operate even at low level voltages, such as negative voltages.

[0086] That is, the semi-bipolar transistor according to the embodiment of the present invention is input from the gate to the source with an input voltage (V GS ) can operate not only at 0 V but also at -1 V, and by controlling the switching operation in the channel direction, more diverse switching operation control is possible.

[0087] In addition, a semi-bipolar transistor can be used to further refine the switching operation according to the channel direction, while at the same time reducing the threshold voltage (V T ) differently (e.g., ) By constructing a switching truth table and controlling the switching operation, more diverse and efficient ternary logic gates can be implemented. In addition to the STI gate described above, various ternary logic gates such as TNAND (Ternary Negative AND), TAND (Ternary AND), TNOR (Ternary Negative OR), TOR (Ternary OR), NCONS (Negative Consensus), CONS (Consensus), NANY (Negative-Accept Anything), ANAY (Accept Anything), and TSUM (Ternary Summation) can be implemented, and ternary logic circuits such as a ternary full adder (Balanced Ternary Full Adder, BTFA) can be implemented by combining various ternary logic gates.

[0088] Hereinafter, a logic gate using a semi-bipolar transistor according to an embodiment of the present invention will be described in more detail with reference to FIGS. 6 to 10.

[0089] Fig. 6 illustrates a circuit diagram and symbol of a NANY gate using a semi-bipolar transistor of the present invention.

[0090] Referring to Fig. 6, the NANY (Negative-accept anything) gate (200) is for carry calculation, is a logic gate in which the output of the logic of the ANY (Accept anything) gate is inverted, and can operate similarly to a TNOR gate.

[0091] These NANY gates (200) can perform operations according to the following truth table.

[0092]

[0093] NANY gate (200) is drain power (V DD ) connected to the upper network (210), source power (V SS) and a ground network (230) connected to the ground power (0V), and when the logic input pairs of the first input signal (A) and the second input signal (B) are (-1, -1), (0, -1), (-1, 0), '+1' is output, and when the logic input pairs are (+1, +1), (0, +1), (+1, 0), '-1' is output. In addition, H and L represent the threshold voltage (V) of the input voltage for the switching operation. T ) is illustrated, and considering each situation, the upper network (210) and the lower network (220) can be configured to include one or more corresponding P-type or N-type transistors.

[0094] In addition, points N1 and N2 represent connections of output signals (Y) output from the upper network (210) and the lower network (220), and points N3 to N5 represent points of output signals (Y) output through the ground network (230). In order to transmit an intermediate logic value of '0', the ground network (230) connects two positive anti-bipolar transistors (P) in series, as many as the number of input signals (A, B), and connects a negative anti-bipolar transistor (N) in parallel so that the ground network (230) can operate even at '-1'. In addition, in order to perform a switching operation when either one of the first input signal (A) and the second input signal (B) is '-1' and the other is '+1', a negative anti-bipolar transistor (N) that operates when it is '-1' and an N-type transistor (L) can be connected in series, respectively, to configure the switching operation.

[0095] At this time, the threshold voltage of the N-type transistor (L) of the ground network (230) may be higher than the ground voltage and lower than that of the semi-bipolar transistor.

[0096] Through this configuration, the NANY gate (200) according to the embodiment of the present invention can transmit '0' in situations of (+1, -1), (0, 0), and (-1, +1).

[0097] In this way, the present invention can implement a circuit that operates even at a '-' input by utilizing the switching characteristics of a semi-bipolar transistor that can operate negatively or positively depending on the direction of the channel, and can construct a truth table representing switching conditions according to ternary logic values ​​as shown in below by utilizing the characteristics of this semi-bipolar transistor.

[0098]

[0099] Hereinafter, another logic gate of the present invention will be described in detail. Fig. 7 illustrates a circuit diagram and symbol of a TAND gate using a semi-bipolar transistor of the present invention.

[0100] Referring to FIG. 7, a TAND (Ternary AND) gate (300) according to an embodiment of the present invention outputs a drain power (V) based on a node where an output signal (Y) is output. DD ) connected to the upper network, source power (V SS ) and a ground network connected to the ground power supply (OV), and the output signal (Y) output from each network is output through N1, N2, N3, and N4.

[0101] The TAND gate (300) of the present invention outputs '-1' if at least one of the logical input pairs (IN1, IN2) of the first input signal (A) and the second input signal (B) is '-1', and outputs '+1' if both logical input pairs are '+1'.

[0102] At this time, the TAND gate (300) can output an output signal (Y) 0 through the N2 point by connecting in series each of the positive anti-bipolar transistors (P) for outputting when the logical input pair is (0, 0) according to the input signal, and by connecting in series each of the positive anti-bipolar transistors (P) and the N-type transistor for outputting when the logical input pair is (0, +1) or (+1, 0). N3 is a point that outputs a logical state '0' when the input pair is (+1, 0), and N4 is a point that outputs a logical state '0' when it is (0, +1).

[0103] Fig. 8 illustrates a circuit diagram and symbol of a TNOR gate using a semi-bipolar transistor of the present invention.

[0104] Referring to Fig. 8, the TNOR (Ternary Negative OR) gate (400) is a logic gate in which the output of the logic of the TOR (Ternary OR) gate is inverted, and is a logic gate in which the output of the TOR gate is inverted in .

[0105] A TNOR gate (400) according to an embodiment of the present invention is configured to output a drain power (V) based on a node where an output signal (Y) is output. DD ) connected to the upper network, source power (V SS ) and a ground network connected to the ground power supply (OV), and the output signal (Y) output from each network is output through N1, N2, N3, and N4. Among these, N3 is a point where the logic state '0', which is the output signal (Y) in the case of a logic input pair (0, -1), is output, and N4 is a point where the logic state '0', which is the output signal (Y) in the case of a logic input pair (-1, 0), is output.

[0106] For this purpose, the grounding network may be configured to include a positive anti-bipolar transistor (P) connected in series with a negative anti-bipolar transistor (N), and a negative anti-bipolar transistor (N) connected in series with a positive anti-bipolar transistor (P).

[0107] Fig. 9 illustrates a circuit diagram and symbol of an NCONS gate using a semi-bipolar transistor of the present invention.

[0108] Referring to Fig. 9, the NCONS (Negative Consensus) gate (600) is a logic gate that performs a carry operation in a ternary addition operation, and is a gate in which the output of the CONS (Consensus) gate is inverted.

[0109] These NCONS gates (600) are based on the node where the output signal (Y) is output, and the drain power (V DD ) connected to the upper network, source power (V SS ) and a ground network connected to the ground power supply (OV), and the output signal (Y) output from each network is shown to be output through N1, N2, N3, N4, and N5.

[0110] In the NCONS gate (600), if the logical input pair is (-1, -1), the output becomes the logical state '+1', if the logical input pair is (+1, +1), the output becomes the logical state '-1', and for all other logical input pairs, the output becomes the logical state '0'.

[0111] The NCONS gate (600) of the present invention for outputting a logic state '0' uses four anti-bipolar transistors connected in parallel to the node of the output signal (Y), and can be configured by arranging a negative anti-bipolar transistor (N) and a positive anti-bipolar transistor (P) for a first input signal (A), and arranging a negative anti-bipolar transistor (N) and a positive anti-bipolar transistor (P) for a second input signal (B).

[0112] Fig. 10 illustrates a circuit diagram and symbol of a SUM gate using a semi-bipolar transistor of the present invention.

[0113] Referring to Fig. 10, the SUM gate (500) performs an addition operation on the first input signal (A) and the second input signal (B) output through the NANY gate, and the drain power (V) is based on the node where the output signal (Y) is output. DD ) connected to the upper network, source power (V SS ) and a ground network connected to the ground power supply (OV), and the first input signal (A) and the second input signal (B) output through the NANY gate are transmitted to each network via point N1 and output as an output signal (Y) via points N2, N3, and N4.

[0114] The ground network of such a SUM gate (500) is connected to a ground power supply and may be configured to include a positive anti-bipolar transistor (P) connected in series with the drain of each of the negative anti-bipolar transistors (N) for the first input signal and the second input signal (B).

[0115] The ternary logic gate using the semi-bipolar transistor of the present invention has been described above with reference to FIGS. 6 to 10.

[0116] As described above, the ternary logic gate of the present invention can operate at low power by using a semi-bipolar transistor that can operate in various ways by changing the channel direction and threshold voltage, and can stably implement ternary operation without loss of leakage current, and by combining such ternary logic gates, a more efficient ternary full-adder circuit can be implemented.

[0117] This will be explained with reference to Fig. 11.

[0118] FIG. 11 is a diagram illustrating a ternary full adder circuit according to an embodiment of the present invention.

[0119] Referring to FIG. 11, a ternary full adder circuit (700) according to an embodiment of the present invention is one of the arithmetic logic devices, and is a circuit that outputs the sum of the input signal and a carry signal when an input signal is input.

[0120] The ternary full-adder circuit (700) of the present invention includes three input signal nodes and two output signal nodes. That is, the ternary full-adder circuit (700) of the present invention includes a first input signal (A), a second input signal (B), and a carry input signal (C). IN ) is input through each input node, and the sum output signal (S) is output through each of the two output nodes. OUT ) and carry output signal (C OUT ) can be printed.

[0121] In particular, the ternary full adder circuit (700) according to an embodiment of the present invention is a ternary full adder capable of ternary operations, and the first input signal (A) and the second input signal (B) can have ternary logic values. Here, the ternary logic values ​​can be unbalanced logic values ​​of '0', '1', and '2', and balanced logic values ​​of '-1', '0', and '1'.

[0122] A ternary full adder circuit (700) according to one embodiment of the present invention is described as a balanced ternary full adder using balanced logic values ​​of '-1', '0', and '1', but can also be applied to an unbalanced ternary full adder circuit using unbalanced logic values ​​of '0', '1', and '2'.

[0123] A ternary full adder circuit (700) according to an embodiment of the present invention may be composed of two half adders (710, 720) and one NANY gate (730).

[0124] Each of the first half adder (710) and the second half adder (720) is composed of a SUM gate and an NCONS gate. For convenience of explanation, they are described separately as the first SUM gate and the second SUM gate, and the first NCONS gate and the second NCONS gate. However, the logic operation process is substantially the same gate, with only some differences in the types of input signals.

[0125] First, the first half adder (710) is composed of a first SUM gate and a first NCONS gate, and the first SUM gate performs a first operation, i.e., an addition operation, on the first input signal (A) and the second input signal (B) to output a sum signal. In addition, the first NCONS gate outputs a first carry signal according to the addition operation of the first SUM gate.

[0126] The second half adder (720) is composed of a second SUM gate and a second NCONS gate, and the second SUM gate receives the sum signal output through the first half adder (710) and the carry input signal (C IN ) is input, the second operation, i.e. addition operation, is performed to generate the sum output signal (S OUT ) is output, and the second NCONS gate outputs the second carry signal according to the addition operation of the second half adder (720).

[0127] And the NANY gate operates on the first carry signal of the first half adder (710) and the second carry signal of the second half adder (720) to generate a carry output signal (C OUT ) will be printed.

[0128] Each of the gates constituting the ternary full-adder according to the embodiment of the present invention includes a ground network composed of at least one semi-bipolar transistor for outputting an intermediate state among ternary logic values ​​as described through FIGS. 6 to 10, thereby enabling a ternary full-adder circuit using ternary logic values ​​to be implemented more efficiently without leakage current.

[0129] Meanwhile, a ternary full adder circuit according to another embodiment of the present invention may be configured to further include a margin buffer for further improved current characteristics.

[0130] This is explained with reference to FIGS. 12 to 14.

[0131] FIG. 12 is a diagram illustrating a ternary full-adder circuit according to another embodiment of the present invention, FIG. 13 is a circuit diagram illustrating a stacked STI gate according to another embodiment of the present invention, and FIG. 14 is an exemplary diagram comparing output waveforms of a ternary full-adder circuit according to another embodiment of the present invention.

[0132] First, referring to FIGS. 12 and 13, a ternary full adder circuit (800) according to another embodiment of the present invention generates a sum output signal (S OUT ) and carry output signal (C OUT ) may be configured to further include a first margin buffer (811) and a second margin buffer (812) in the output nodes where each is output, and an STI gate (813, 814, 815) for compensating the values ​​of the first margin buffer (811) and the second margin buffer (812) may be placed in the front end.

[0133] The above first margin buffer (811) and second margin buffer (812) refer to the SIT' gate (900) configured with a stacked semi-polar transistor in the STI gate (100) described with reference to FIG. 4.

[0134] Referring to FIG. 13 for the STI' gate (900), the STI' gate (900) includes an upper network (910) composed of P-type transistors, a lower network (920) arranged in series with the upper network (910) and operating complementarily, and a ground network may be composed of a stacked semi-bipolar transistor in which a first semi-bipolar transistor (930) and a second semi-bipolar transistor (940) are connected in series.

[0135] In this way, by configuring the first semi-bipolar transistor (930) and the second semi-bipolar transistor (940) in a stacked form (N1), the current path of the semi-bipolar transistors (930, 940) can be suppressed to exhibit a more improved output state, and the narrow transfer characteristic of the N-type transistor can be improved, thereby ensuring a more efficient switching operation of the N-type transistor.

[0136] In addition, by configuring the first semi-bipolar transistor (930) and the second semi-bipolar transistor (940) in a stacked form (N1), an excellent output margin is provided as indicated by the Optimized BTFA in FIG. 14, enabling a more optimized equal distribution, thereby improving the stability of the overall output waveform compared to the Original BTFA.

[0137] The above has described the ternary logic gate according to an embodiment of the present invention and the ternary full adder circuit formed by combining the same.

[0138] The ternary logic gate and ternary full-adder circuit according to an embodiment of the present invention may be implemented by inkjet printing, but is not limited thereto, and the ternary logic gate and ternary full-adder circuit according to an embodiment of the present invention may be implemented by other methods.

[0139] Hereinafter, a method for designing a ternary full adder circuit using a semi-bipolar transistor of the present invention will be described.

[0140] Figure 15 is a flowchart for explaining a method for designing a ternary full adder circuit according to an embodiment of the present invention.

[0141] Referring to Fig. 15, the ternary full-adder circuit of the present invention can be first constructed from a step of setting a switching condition according to a ternary logic value (S100). In particular, the ternary full-adder circuit design method of the present invention uses one or more anti-ambipolar transistors for outputting an intermediate logic value among ternary logic values, and the channel direction and threshold voltage (V) of the anti-ambipolar transistor T ) by changing the switching conditions, and constructing a switching truth table as shown in the above-described , and using this, one or more ternary logic gates can be set (S200).

[0142] Here, one or more ternary logic gates can implement various ternary logic gates such as STI (Standard Ternary Inverter), TNAND (Ternary Negative AND), TAND (Ternary AND), TNOR (Ternary Negative OR), TOR (Ternary OR), NCONS (Negative Consensus), CONS (Consensus), NANY (Negative-Accept Anything), ANAY (Accept Anything), and TSUM (Ternary Summation), and by combining various ternary logic gates, a ternary logic circuit such as a ternary full adder (Balanced Ternary Full Adder, BTFA) can be implemented (S300).

[0143] In addition, in one embodiment of the present invention, a ternary full-adder circuit is implemented using ternary logic gates as an example, but various logic circuits as well as a ternary full-adder circuit can be implemented.

[0144] The above has described a ternary full adder circuit and a ternary full adder circuit design method according to an embodiment of the present invention.

[0145] While the present invention has been described with reference to the embodiments illustrated in the drawings, these are merely exemplary, and those skilled in the art will understand that various modifications and equivalent embodiments are possible. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the patent claims.

[0146]

[0147] The present invention relates to a ternary full-adder circuit, and more particularly, to a ternary full-adder circuit using anti-ambipolar transistors and a method for designing a ternary full-adder circuit.

[0148] According to the present invention, by implementing a ternary full-adder circuit using a semi-bipolar transistor to implement an intermediate state, the leakage current generated during switching operation can be significantly reduced, thereby contributing to the popularization of ternary systems, and thus has sufficient potential for industrial use.

Claims

In a ternary full adder circuit that performs an operation and outputs a sum output signal and a carry output signal when a first input signal, a second input signal, and a carry input signal having any one of the 1.3 logic values ​​are input, A first half adder comprising a first SUM gate that performs a first operation on the first input signal and the second input signal and outputs a sum signal, and a first NCONS gate that outputs a first carry signal according to the first operation; A second half adder comprising a second SUM gate that performs a second operation on the sum signal of the first half adder and the carry input signal to output the sum output signal, and a second NCONS gate that outputs a second carry signal according to the second operation; and A NANY gate that operates on the first carry signal of the first half adder and the second carry signal of the second half adder to output a carry output signal; Includes, A ternary full adder circuit, characterized in that each of the first half adder, the second half adder, and the NANY gate includes a ground network comprising at least one anti-ambipolar transistor connected to a ground power supply (GND) for outputting an intermediate logic value among the ternary logic values.

2. In paragraph 1, The ground network of the first SUM gate and the second SUM gate is positive anti-bipolar transistor; and A negative anti-bipolar transistor for each input signal, connected in series with the positive anti-bipolar transistor; A ternary full adder circuit characterized by comprising:

3. In paragraph 1, The ground network included in the above NANY gate is positive anti-bipolar transistor; and A negative anti-bipolar transistor connected in parallel to the above positive anti-bipolar transistor, the drain of which is connected to an N-type transistor connected to a ground voltage source, and the source of which is connected to the output node; A ternary full adder circuit characterized by including:

4. In paragraph 1, The ground network included in the first NCONS gate and the second NCONS gate is A ternary full adder circuit characterized by having a negative anti-bipolar transistor and a positive anti-bipolar transistor for each input signal connected in parallel to the output node and connected alternately.

5. In paragraph 1, Each margin buffer is further connected to each output node that outputs the sum output signal and the carry output signal, Each of the above margin buffers is A ternary full adder circuit characterized by comprising a ground network in which at least two semi-bipolar transistors are connected in a stacked configuration.

6. In paragraph 5, A ternary full adder circuit characterized by further comprising one or more STI gates for compensating the values ​​of each of the above margin buffers.

7. Step of setting switching conditions according to 3rd party logic values; A step of setting one or more ternary logic gates according to the above set switching conditions; and A step of designing a ternary full adder circuit by combining the above-described ternary logic gates; Includes, One or more of the above logic gates A method for designing a ternary full adder circuit, characterized in that it includes a ground network comprising at least one anti-ambipolar transistor connected to a ground power supply (GND) for outputting an intermediate logic value among the above ternary logic values.

8. In paragraph 7, The above ternary logic values ​​are -1, 0, +1, A method for designing a ternary full adder circuit, characterized in that the above ternary full adder circuit is a balanced ternary full adder circuit.

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