Storage device, system-on-a-chip comprising same, and computing apparatus

Abstract

The present disclosure relates to a storage device, a system-on-a-chip comprising same, and a computing apparatus. The storage device comprises a storage module and a clock gating module. The storage module comprises a plurality of latch units each allocated an address, an input end of each latch unit being used for receiving written data. The clock gating module comprises first-stage clock gating units, and second-stage clock gating units coupled between the plurality of latch units and the first-stage clock gating units. Each first-stage clock gating unit receives an input clock signal and an enable signal obtained on the basis of first decoding a write address, and outputs an enable clock signal to a corresponding clock gating unit amongst the second-stage clock gating units. Each second-stage clock gating unit receives an enable clock signal output by a corresponding clock gating unit amongst the first-stage clock gating units and an enable signal obtained on the basis of second decoding the write address, and outputs the enable clock signal to a corresponding latch unit.

Description

Storage device, system on chip including the storage device, and computing device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the application with CN application number 202311212878.7 and application date September 20, 2023, and claims its priority. The disclosed content of the CN application is hereby introduced as a whole into this application. Technical Field

[0003] The present disclosure relates to the technical field of integrated circuits, and more particularly, to a storage device, a system on chip including the storage device, and a computing apparatus. Background Art

[0004] FIG1 schematically illustrates a latch storage array with latches as storage cells, the size of which can be represented by a bit width n and a depth m. The n-bit bit width limits a storage cell of the latch storage array to n bits, that is, the width of each data write is n bits and the width of each data read is n bits. The depth m limits the number of n-bit storage cells included in the latch storage array. An address can be assigned to each storage cell in the latch storage array, such as addresses 0, 1, 2, ..., (m-1) as shown in FIG1. ​​When performing a write operation, address decoding can be performed based on the write address to write data to the corresponding storage cell in the latch storage array. When performing a read operation, address decoding can be performed based on the read address to read the data stored in the corresponding storage cell in the latch storage array.

[0005] Summary of the Invention

[0006] According to a first aspect of the present disclosure, a storage device is provided, comprising a storage module and a clock gating module. The storage module comprises a plurality of latch units, each of which is assigned an address. The input end of each latch unit in the plurality of latch units is configured to receive write data. The clock gating module comprises a first-level clock gating unit and a second-level clock gating unit coupled between the plurality of latch units and the first-level clock gating unit. Each clock gating unit in the first-level clock gating unit is configured to receive an input clock signal and an enable signal obtained by decoding a first address based on a write address, and output an enable clock signal to a corresponding clock gating unit in the second-level clock gating unit. Each clock gating unit in the second-level clock gating unit is configured to receive an enable clock signal output by a corresponding clock gating unit in the first-level clock gating unit and an enable signal obtained by decoding a second address based on the write address, and output an enable clock signal to a corresponding latch unit in the plurality of latch units.

[0007] In some embodiments, the clock gating module further includes one or more levels of clock gating units coupled between the first-level clock gating unit and the second-level clock gating unit. Each clock gating unit in each level of the one or more levels of clock gating units is configured to receive an enable clock signal output by a corresponding clock gating unit in an upper level of the one or more levels of clock gating units and an enable signal obtained by decoding a corresponding address of a write address, and output the enable clock signal to a corresponding clock gating unit in a lower level of the one or more levels of clock gating units. In such an embodiment, each clock gating unit in the first-level clock gating unit is configured to receive an input clock signal and an enable signal obtained by decoding the first address based on the write address and output the enable clock signal to the corresponding clock gating unit in the uppermost clock gating unit in the one or more levels of clock gating units, and each clock gating unit in the second-level clock gating unit is configured to receive the enable clock signal output by the corresponding clock gating unit in the lowermost clock gating unit in the one or more levels of clock gating units and the enable signal obtained by decoding the second address based on the write address and output the enable clock signal to the corresponding latch unit in the multiple latch units.

[0008] In some embodiments, the plurality of latch units are grouped hierarchically, and the groups formed by grouping the plurality of latch units at each hierarchical level are obtained by further dividing the groups formed by grouping the plurality of latch units at the previous hierarchical level. The number of levels of clock gating units included in the clock gating control module may correspond to the number of levels of the grouping of the plurality of latch units. The number of clock gating units included in each level of clock gating units in the clock gating control module may correspond to the number of groups formed by grouping the plurality of latch units at the corresponding hierarchical level.

[0009] In some embodiments, the enable signal received by each clock gating unit in each level of clock gating units in the clock gating module is obtained based on address decoding corresponding to a corresponding level of the write address.

[0010] In some embodiments, the address of each latch unit in the plurality of latch units includes different parts corresponding to different levels. In some embodiments, the addresses of latch units in the same group at the same level have the same part.

[0011] In some embodiments, the address is binary. In some embodiments, the address decoding corresponding to each level of the write address is associated with a corresponding number of bits of the write address. In some embodiments, the number of bits of the corresponding number of bits is determined by the number of bits in a binary representation of the ratio of the number of groups formed by grouping the plurality of latch units at that level to the number of groups formed by grouping the plurality of latch units at the previous level.

[0012] In some embodiments, each clock gating unit in the first-level clock gating unit is coupled to a corresponding group of latch units obtained by grouping the multiple latch units at the first level via clock gating units at other levels in the clock gating module, and each clock gating unit in the second-level clock gating unit is coupled to a corresponding group of latch units obtained by grouping the multiple latch units at a second level lower than the first level.

[0013] In some embodiments, the memory module further includes an additional latch unit and an additional clock gating unit. The additional latch unit is assigned an address and its input is configured to receive the write data. The additional clock gating unit is coupled to the additional latch unit and is configured to receive the input clock signal and an enable signal obtained based on address decoding of the write address and output an enable clock signal to the additional latch unit.

[0014] In some embodiments, the storage device further includes a trigger unit and a clock source unit. The trigger unit is configured to output the write data to the storage module based on a received clock signal. The clock source unit is coupled to the trigger unit and the clock gating module, respectively, and is configured to provide the input clock signal. In some embodiments, the storage device further includes a clock delay unit, coupled between the clock source unit and the trigger unit, and configured to receive the input clock signal and delay the input clock signal based on a delay of an enable clock signal received by a latch unit corresponding to the write address in the storage module relative to the input clock signal, and output the delayed input clock signal to the trigger unit. In some embodiments, the clock delay unit includes one or more of the following: a clock buffer; an inverter. In some embodiments, the trigger unit is rising-edge triggered, and the rising edge of the delayed input clock signal is closer to the rising edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module than to the rising edge of the input clock signal. In some embodiments, the trigger unit is falling-edge triggered, and the falling edge of the delayed input clock signal is closer to the falling edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module than the falling edge of the input clock signal.

[0015] According to a second aspect of the present disclosure, a system on chip is provided, comprising the storage device according to the first aspect of the present disclosure.

[0016] According to a third aspect of the present disclosure, a computing device is provided, comprising the system on chip according to the second aspect of the present disclosure.

[0017] Other features and advantages of the present disclosure will become more apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0019] The present disclosure can be more clearly understood from the following detailed description with reference to the accompanying drawings, in which:

[0020] FIG1 shows a latch storage array with latches as storage units;

[0021] FIG2 shows a logic gate circuit;

[0022] FIG3 shows a circuit diagram of a memory device according to some comparative examples of the present disclosure;

[0023] FIG4 shows a circuit diagram of a memory device according to some embodiments of the present disclosure;

[0024] FIG5 shows a circuit diagram of a clock gating unit according to some embodiments of the present disclosure;

[0025] FIG6 shows an example waveform diagram of various signals of the clock gating unit of FIG5 ;

[0026] FIG7 shows a circuit diagram of a clock gating unit according to some embodiments of the present disclosure;

[0027] FIG8 shows an example waveform diagram of various signals of the clock gating unit of FIG7 ;

[0028] FIG9 shows a circuit diagram of a clock gating unit according to some embodiments of the present disclosure;

[0029] FIG10 shows a circuit diagram of a memory device according to some embodiments of the present disclosure;

[0030] FIG11 shows a circuit diagram of a clock gating module according to some embodiments of the present disclosure;

[0031] FIG12 shows a circuit diagram of a memory device according to some embodiments of the present disclosure;

[0032] FIG13 shows a schematic block diagram of a storage device according to some embodiments of the present disclosure;

[0033] FIG. 14 shows example waveform diagrams of some signals of the storage device of FIG. 13 .

[0034] Note that in the embodiments described below, the same reference numerals are sometimes used in common across different drawings to denote the same parts or parts having the same functions, and their repeated descriptions are omitted. In this specification, similar reference numerals and letters are used to denote similar items. Therefore, once an item is defined in one drawing, it need not be further discussed in subsequent drawings.

[0035] To facilitate understanding, the positions, sizes, and ranges of various structures shown in the drawings and the like may not always represent actual positions, sizes, and ranges. Therefore, the disclosed invention is not limited to the positions, sizes, and ranges disclosed in the drawings and the like. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components. DETAILED DESCRIPTION

[0036] Various exemplary embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. It should be noted that unless otherwise specifically stated, the relative arrangements of components and steps, numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0037] The following description of at least one exemplary embodiment is merely illustrative and is not intended to limit the present disclosure, its application, or use. In other words, the structures and methods herein are presented in an exemplary manner to illustrate various embodiments of the structures and methods of the present disclosure. However, those skilled in the art will appreciate that these are merely exemplary of the disclosure that may be implemented, and are not exhaustive. Furthermore, the drawings are not necessarily drawn to scale, and some features may be exaggerated to illustrate details of specific components.

[0038] In addition, technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0039] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0040] In the present disclosure, each unit is generally implemented by a circuit, and thus the terms "unit" and "circuit" are used interchangeably herein. For example, "latch unit" and "latch circuit" are used interchangeably, the terms "clock gating unit" and "clock gating circuit" are used interchangeably, "flip-flop unit" and "flip-flop circuit" are used interchangeably, "clock source unit" and "clock source circuit" are used interchangeably, "clock delay unit" and "clock delay circuit" are used interchangeably, and so on.

[0041] FIG2 shows a logic gate circuit. As shown in FIG2, the logic gate (illustrated as a NOT gate) includes a DD and ground terminal V SS The gates of the PMOS transistor and the NMOS transistor are connected as the input terminals of the logic gate to receive the voltage V in The drain of the PMOS transistor is connected to the drain of the NMOS transistor as the output of the logic gate to output V out The logic gate is connected to the load capacitor C load The static power consumption of this circuit includes leakage power consumption, and the dynamic power consumption includes flip power consumption and short-circuit power consumption. When the logic gate flips, the switch current I switch This will cause the load capacitance C load In addition, when both the PMOS transistor and the NMOS transistor are turned on, the short-circuit current I sc In particular, the flip power dissipation is calculated as P switch =(V DD 2 ×C load ×T r )÷2, where V DD Indicates the power supply voltage, C load represents the load capacitance, T r It represents the flip rate of the signal (for example, if the clock signal flips twice in one cycle, the flip rate of the clock signal is 2), that is, the frequency of logic gate flipping.

[0042] When writing data to the latch, the logic gate circuit of the latch will flip, thereby generating dynamic power consumption. When the flip rate of the signal in the latch is higher, according to the above analysis, the dynamic power consumption may be higher, which is not desirable. For example, FIG3 shows a memory device 10 according to some comparative examples of the present disclosure. The memory device 10 includes a plurality of (for example, sixteen) latch units 120, 121, ..., 122 arranged in an array. 15 (Herein, sometimes collectively referred to as latch units 12). Each latch unit 12 may have an input terminal D, an output terminal Q, and a clock control terminal G. The clock control terminal G is configured to receive an input clock signal clk. When the input clock signal clk causes the clock control terminal G of the latch unit 12 to flip, the data received at the input terminal D of the latch unit 12 may be written into the latch unit 12. 15 In front of each latch unit 12, a plurality of multiplexer units (MUX) 110, 111, ..., 11 15The memory device 10 includes a plurality of multiplexer units 11 (hereinafter, sometimes collectively referred to as multiplexer units 11). The first input terminal of each multiplexer unit 11 is used to receive the write data wd and the second input terminal is used to receive the output at the output terminal Q of the corresponding one of the latch units 12. The output terminal of each multiplexer unit 11 is coupled to the input terminal D of the corresponding one of the latch units 12. The memory device 10 may further include or be coupled to an address decoding unit 13, which is configured to perform address decoding on the write address to generate selection signals sel0, sel1, ..., sel 15 These selection signals are fed into the multiplexer units 110, 111, ..., 11 15 To select whether to output the write data wd to the corresponding latch units 120, 121, ..., 12 15 Or hold latch units 120, 121, ..., 12 15 For example, assuming that the write address corresponds to the latch unit 120, the selection signal sel0 is configured to select the write data wd as the output of the multiplexer unit 110 so that the write data wd is written into the latch unit 120, and the selection signals sel1, ..., sel 15 is configured to select latch units 121, ..., 12 15 The original data of the multiplexer unit 111, ..., 11 15 The output of the latch unit 121, ..., 12 15 Therefore, when performing a write operation, the clock control terminal G of each latch unit 12 undergoes a signal inversion, and the signals within each multiplexer unit 11 also invert, which results in higher dynamic power consumption. Moreover, the bit width of the multiplexer unit 11 must be the same as that of the latch unit 12, thus occupying a larger chip area.

[0043] To this end, the present disclosure provides a storage device that omits the aforementioned complex multiplexer logic and instead uses clock control logic to perform write operations on the latch units specified by the write address, thereby simplifying the data write logic, saving chip area, and reducing power consumption. The storage devices according to various embodiments of the present disclosure are described in detail below with reference to the accompanying drawings. It should be understood that actual storage devices may also include other components, and to avoid obscuring the key points of the present disclosure, these other components are not discussed herein and are not shown in the accompanying drawings.

[0044] FIG4 shows a memory device 100 according to some embodiments of the present disclosure. The memory device 100 includes a plurality of latch units 1200, 1201, ..., 120 15(Herein, these may sometimes be collectively referred to as latch units 120.) Each latch unit 120 may have an input terminal D, an output terminal Q, and a clock control terminal G. Each of these latch units 120 may be assigned an address. These latch units 120 may be arranged in the form of an array (e.g., a one-dimensional array, a two-dimensional array, etc.). Although sixteen latch units are shown in FIG4 , this is merely exemplary and not restrictive, and the present disclosure may be applicable to memory devices including any suitable number of latch units.

[0045] The input terminal D of each latch unit 120 can be configured to receive write data wd. Since the write data wd has been received at the input terminal D of each latch unit 120, whether the received write data wd is written into the latch unit 120 can be controlled by the clock control terminal G of each latch unit 120.

[0046] To this end, the storage device 100 may further include a plurality of clock gating units 1400, 1401, ..., 140 15 Each clock gating unit 140 is coupled to a corresponding latch unit 120 (specifically, its clock control terminal G). Each clock gating unit 140 is configured to receive an input clock signal clk and an enable signal en obtained by address decoding based on the write address, and output an enable clock signal enclk to the clock control terminal G of the corresponding latch unit 120. This causes the clock control terminal G of the corresponding latch unit 120 to invert when the corresponding latch unit 120 corresponds to the write address, thereby writing the write data wd thereto. However, when the corresponding latch unit 120 does not correspond to the write address, the clock control terminal G of the corresponding latch unit 120 does not invert, thereby preventing the write data wd from being written thereto.

[0047] Specifically, each clock gating unit 140 may have a clock terminal CK, an enable terminal EN, and an output terminal CKG. The clock terminal CK of each clock gating unit 140 may be configured to receive an input clock signal clk. The enable terminal EN of each clock gating unit 140 may be configured to receive an enable signal en (en0, en1, ..., en1) obtained by address decoding based on the write address. 15 The output terminal CKG of each clock gating unit 140 can be configured to output an enable clock signal enclk (enclk0, enclk1, . . . , enclk ) to the clock control terminal G of a corresponding latch unit 120. 15 The memory device 100 may further include or be coupled to an address decoding unit 130 configured to perform address decoding on a write address to generate enable signals en0, en1, ..., en 15These enable signals are fed into the clock gating units 1400, 1401, ..., 140 15 Combined with the input clock signal clk to generate corresponding enable clock signals enclk0, enclk1, ..., enclk 15 , thereby controlling the corresponding latch units 1200, 1201, ..., 120 15 For example, assuming that the write address corresponds to the latch unit 1200, the enable signal en0 is configured to be combined with the input clock signal clk to generate the enable clock signal enclk0 so that the clock control terminal G of the latch unit 1200 is signal-inverted so that the write data wd is written into the latch unit 1200, and the enable signals en1, ..., en 15 is configured to be combined with the input clock signal clk to generate enable clock signals enclk1, ..., enclk 15 So that the latch units 1201, ..., 120 15 The clock control terminal G does not flip the signal so that the write data wd is not written into the latch units 1201, ..., 120 15 .

[0048] In some embodiments, the clock gating unit 140 may include a latch and an AND gate. For example, referring to FIG5 , a non-limiting implementation of the clock gating unit 140 is shown. As shown in FIG5 , the clock gating unit 140 includes a latch 142 and an AND gate 144. Latch 142 receives an enable signal en and also receives an input clock signal clk and inverts it to obtain an inverted input clock signal clki. AND gate 144 receives the input clock signal clk and the enable latch signal enl output by latch 142, and outputs an enable clock signal enclk. FIG6 shows example waveforms of various signals of the clock gating unit 140 of FIG5 .

[0049] In other embodiments, the clock gating unit 140 may include a latch and an OR gate. For example, referring to FIG7 , another non-limiting implementation of the clock gating unit 140 is shown. As shown in FIG7 , the clock gating unit 140 includes a latch 142 and an OR gate 146. Inverters (or, NOT gates) 1482 and 1484 are also provided at the two input ends of the OR gate 146. The latch 142 receives the enable signal en and also receives the input clock signal clk and inverts it to obtain an inverted input clock signal clki. The inverter 1482 inverts the enable latch signal enl output by the latch 142 to obtain an inverted enable latch signal enli. The inverter 1484 inverts the input clock signal clk to obtain an inverted input clock signal clki. The OR gate 146 receives the inverted input clock signal clki and the inverted enable latch signal enli and outputs the enable clock signal enclk. FIG. 8 shows example waveforms of various signals of the clock gating unit 140 of FIG. 7 .

[0050] In yet other embodiments, clock gating unit 140 may include only an AND gate. For example, referring to FIG. 9 , another non-limiting implementation of clock gating unit 140 is shown. As shown in FIG. 9 , clock gating unit 140 includes only an AND gate 144. AND gate 144 receives an input clock signal clk and an enable signal en, and outputs an enable clock signal enclk.

[0051] As can be seen from Figures 5, 7, and 9, the circuit implementation of clock gating unit 140 is much simpler than that of multiplexer unit 11 in Figure 3. In particular, even if clock gating unit 140 employs latch 142, the latch can be selected to have a bit width of 1 bit. Compared to multiplexer unit 11, which requires the same bit width as latch unit 12, clock gating unit 140 consumes much less area and power. Therefore, compared to storage device 10 in Figure 3, storage device 100 in Figure 4 can have simplified data write logic, occupy less area, and consume less power.

[0052] Furthermore, due to the enable clock signal enclk generated by the clock gating unit 140, during a write operation, only the clock control terminal G of the latch unit 120 corresponding to the write address undergoes a signal inversion, while the clock control terminal G of the latch unit 120 not corresponding to the write address does not undergo a signal inversion. Therefore, the memory device 100 of FIG. 4 can have reduced inversion power consumption compared to the memory device 10 of FIG. 3 , thereby achieving lower total chip power consumption.

[0053] It is worth noting that when performing a write operation, each clock gating unit 1400, 1401, ..., 140 15The clock terminal CK is also flipping, which also results in a certain amount of power consumption. In contrast, Figure 10 shows a storage device 200 according to other embodiments of the present disclosure. This device can further reduce the signal flip rate and thus power consumption by arranging multiple levels of clock gating units. As shown in Figure 10, the storage device 200 includes a storage module 210 and a clock gating module 240.

[0054] The memory module 210 includes a plurality of latch units 2200, 2201, ..., 220 15 (Herein, sometimes collectively referred to as latch units 220). Each latch unit 220 may have an input terminal D, an output terminal Q, and a clock control terminal G, and may be assigned an address. These latch units 220 may be arranged in the form of an array (e.g., a one-dimensional array, a two-dimensional array, etc.). Although sixteen latch units are shown in Figure 10, this is merely exemplary and not restrictive, and the present disclosure may be applicable to storage devices including any suitable number of latch units. The input terminal D of each latch unit 220 may be configured to receive write data wd.

[0055] The clock gating module 240 includes a first-stage clock gating unit 244 and latch units 2200, 2201, ..., 220 15 The second-stage clock gating unit 242 is located between the first-stage clock gating unit 244. As shown in FIG10 , the first-stage clock gating unit 244 may include a plurality of clock gating units 2440, 2441, ..., 2443 (sometimes collectively referred to as clock gating units 244 in this document), and the second-stage clock gating unit 242 may include a plurality of clock gating units 2420, 2421, ..., 242 15 (Herein, sometimes collectively referred to as clock gating unit 242.) Each clock gating unit in the first-stage clock gating unit 244 is configured to receive the input clock signal clk and the enable signal en' (en'0, ..., en'3) obtained by decoding the first address of the write address, and output the enable clock signal enclk' (enclk'0, ..., enclk'3) to the corresponding clock gating unit in the second-stage clock gating unit 242. Each clock gating unit in the second-stage clock gating unit 242 is configured to receive the enable clock signal enclk' (enclk'0, ..., enclk'3) output by the corresponding clock gating unit in the first-stage clock gating unit 244 and the enable signal en (en0, en1, ..., en1) obtained by decoding the second address of the write address. 15 ), and to the latch units 2200, 2201, ..., 220 15 The corresponding latch unit in the output enables the clock signal enclk (enclk0, enclk1, ..., enclk15 ).

[0056] In the example shown in FIG. 10 , the clock gating units 2420 , 2421 , . . . , 242 15 Respectively with latch units 2200, 2201, ..., 220 15 The clock gating unit 2440 is coupled to the clock gating units 2420, 2421, 2422, and 2423 and further coupled to the latch units 2200, 2201, 2202, and 2203. The clock gating unit 2441 is coupled to the clock gating units 2424, 2425, 2426, and 2427 and further coupled to the latch units 2204, 2205, 2206, and 2207. The clock gating unit 2442 is coupled to the clock gating units 2428, 2429, and 2420. 10 , 242 11 Then, the latch units 2208, 2209, and 220 10 , 220 11 The clock gating unit 2443 is coupled to the clock gating unit 242 12 , 242 13 , 242 14 , 242 15 Then, the latch unit 220 12 , 220 13 , 220 14 , 220 15 Each clock gating unit 242, 244 may have a clock terminal CK, an enable terminal EN, and an output terminal CKG. The clock terminal CK is used to receive the input clock signal clk or the enable clock signal output by the previous clock gating unit. The enable terminal EN is used to receive the enable signal obtained by address decoding based on the write address. The output terminal CKG is used to output the enable clock signal generated by the clock gating unit. The circuit implementation of the clock gating units 242, 244 may be similar to the various circuit implementations of the clock gating unit 140 described above with reference to Figures 5 to 9, and will not be further described here.

[0057] The memory device 100 may further include or be coupled to an address decoding unit 230 configured to perform address decoding on a write address. The address decoding unit 230 may be configured to perform a first address decoding on the write address to generate enable signals en'0, ..., en'3, which are fed into the first-stage clock gating units 2440, ..., 2443 to be combined with the input clock signal clk to generate corresponding enable clock signals enclk'0, ..., enclk'3, thereby controlling the corresponding second-stage clock gating units 2420, 2421, ..., 242 15The address decoding unit 230 can also be configured to perform a second address decoding on the write address to generate enable signals en0, en1, ..., en 15 These enable signals are fed into latch units 2200, 2201, ..., 220 15 Combined with the corresponding enable clock signals enclk'0, ..., enclk'3 to generate corresponding enable clock signals enclk0, enclk1, ..., enclk 15 , thereby controlling the corresponding latch units 2200, 2201, ..., 220 15 Whether the signal inversion occurs at the clock control terminal G.

[0058] In this document, for the convenience of description, the latch unit corresponding to the write address may be referred to as the target latch unit, and the latch unit not corresponding to the write address may be referred to as the non-target latch unit. Thus, the enable signal (en'0, ..., en'3) obtained by decoding the first address based on the write address may be configured so that the enable clock signal output by the clock gating unit not coupled to the target latch unit in the first-stage clock gating unit 244 causes the clock terminal CK of the clock gating unit coupled to the clock gating unit in the second-stage clock gating unit 242 to not undergo a signal flip, and the enable clock signal output by the clock gating unit coupled to the target latch unit in the first-stage clock gating unit 244 causes the clock terminal CK of the clock gating unit coupled to the clock gating unit in the second-stage clock gating unit 242 to undergo a signal flip. The enable signal (en0, en1, ..., en3) obtained by decoding the second address based on the write address 15 ) can be configured to cause a signal inversion to occur at the clock control terminal G of the target latch unit and a signal inversion to occur at the clock control terminal G of the non-target latch unit, thereby writing the write data wd into the target latch unit but not writing the write data wd into the non-target latch unit.

[0059] For example, in FIG10 , assuming that the target latch unit is the latch unit 2200, the enable signal en'0 can be a high level (e.g., 1) so that the clock terminals CK of the clock gating units 2420, 2421, 2422, and 2423 are respectively flipped (turn on the clock for one cycle), and the enable signals en'1, en'2, and en'3 can be a low level (e.g., 0) so that the clock gating units 2424, 2425, ..., 2426 are turned off. 15 The respective clock terminals CK do not experience signal inversion (clock is off). 15The respective clock terminals CK do not undergo signal inversion, so the enable clock signals enclk4, enclk5, ..., enclk outputted by the output terminals CKG are 15 It can be low level (eg, 0) to make the latch units 2204, 2205, ..., 220 15 The respective clock control terminals G do not undergo signal inversion (clock is turned off). In addition, the enable signal en0 can be at a high level (e.g., 1) to cause the clock control terminal G of the latch unit 2200 to undergo signal inversion (turn on the clock for one cycle), while the enable signals en1, en2, and en3 can be at a low level (e.g., 0) to cause the respective clock control terminals G of the latch units 2201, 2202, and 2203 to undergo signal inversion (clock is turned off). In this way, although the latch units 2200, 2201, ..., 220 15 The input terminals D of the latch units 2200 and 2201 receive the write data wd, but since only the clock control terminal G of the latch unit 2200 undergoes a signal inversion, the write data wd will only be written into the latch unit 2200 and will not be written into the latch units 2201, 2202, ..., 220 15 .

[0060] Similarly, if the write data wd is to be written into a latch unit 2200 (1200), the storage device 200 has only eight clock gating units (clock gating units 2420, 2421, 2422, 2423, 2440, 2441, 2442, 2443) at which the clock terminal CK will have a signal inversion, while the storage device 100 has sixteen clock gating units (clock gating units 1400, 1401, ..., 1402). 15 ) will experience signal toggle at the clock terminal CK of the memory device 200. Therefore, when performing a write operation, the memory device 200 has a significantly lower signal toggle rate and, therefore, significantly lower toggle power consumption compared to the memory device 100, thereby reducing the total power consumption of the chip. Furthermore, although the number of clock gating units in the memory device 200 is increased compared to the memory device 100, as previously mentioned, the circuit implementation of the clock gating units employed is simple and the area occupied is small. Therefore, the cost of this increase in number is acceptable compared to the benefits.

[0061] In some embodiments, the clock gating module 240 may further include one or more levels of clock gating units coupled between the first-level clock gating unit 244 and the second-level clock gating unit 242. Each clock gating unit in each level of the one or more levels of clock gating units may be configured to receive an enable clock signal output by a corresponding clock gating unit in an upper-level clock gating unit (close to the first-level clock gating unit 244) of the one or more levels of clock gating units and an enable signal obtained by decoding a corresponding address of a write address, and output the enable clock signal to a corresponding clock gating unit in a lower-level clock gating unit (close to the second-level clock gating unit 242) of the one or more levels of clock gating units. In this case, each clock gating unit in the first-level clock gating unit 244 is configured to receive an input clock signal and an enable signal obtained by decoding the first address based on the write address and output the enable clock signal to the corresponding clock gating unit in the uppermost clock gating unit in the one or more levels of clock gating units (directly coupled to the first-level clock gating unit 244), and each clock gating unit in the second-level clock gating unit 242 is configured to receive the enable clock signal output by the corresponding clock gating unit in the lowermost clock gating unit in the one or more levels of clock gating units (directly coupled to the second-level clock gating unit 242) and the enable signal obtained by decoding the second address based on the write address, and output the enable clock signal to the corresponding latch unit. For example, Figure 11 shows a clock gating module 240 (enable signal not shown) including three-level clock gating units, wherein the clock gating module 240 also includes a third-level clock gating unit 246 coupled between the first-level clock gating unit 244 and the second-level clock gating unit 242, which includes multiple clock gating units 2460, 2461,..., 2467.

[0062] The number of stages of the clock gating module 240 can be determined as follows. 15 can be hierarchically grouped, wherein the latch units 2200, 2201, ..., 220 15 The groups obtained by grouping at each level are obtained by grouping the latch units 2200, 2201, ..., 220 15 In this case, the number of stages of the clock gating units included in the clock gating module 240 may correspond to the latch units 2200, 2201, ..., 220 15 The number of the clock gating units included in each level of the clock gating unit in the clock gating module 240 may also correspond to the number of the latch units 2200, 2201, ..., 220 15 The number of groups obtained by grouping at the corresponding level.

[0063] For example, referring to FIG. 10 , the latch units 2200 , 2201 , . . . , 220 15 Can be grouped into two levels. At the higher level (first level), latch units 2200, 2201, ..., 220 15 The latch units 2200, 2201, 2202 and 2203 are divided into four groups, the first group includes latch units 2204, 2205, 2206 and 2207, the third group includes latch units 2208, 2209 and 2200. 10 , 220 11 , the fourth group includes latch unit 220 12 , 220 13 , 220 14 , 220 15 ). At the lower level (second level), latch units 2200, 2201, ..., 220 15 Divided into 16 groups (each group includes 2200, 2201, ..., 220 15 In view of the latch units 2200, 2201, ..., 220 15 The clock gating module 240 is grouped into two levels, and may include two levels of clock gating units, namely, a first-level clock gating unit 244 (corresponding to the first level, including four clock gating units) and a second-level clock gating unit 242 (corresponding to the second level, including sixteen clock gating units). In the case of FIG. 11 , the latch units 2200, 2201, ..., 220 15 The three-level grouping further includes latch units 2200, 2201, ..., 220 at the middle level (third level) compared to FIG. 10. 15 In view of this, the clock gating module 240 of Figure 11 may include three levels of clock gating units, that is, further includes a third level clock gating unit 246 (corresponding to the third level, including eight clock gating units).

[0064] It can be understood that, although in the exemplary cases of FIG. 10 and FIG. 11 , the latch units 2200 , 2201 , . . . , 220 15 The latch units 2200, 2201, ..., 220 are equally divided at each level, but this is not meant to be limiting. 15The number of latch units included in each group obtained by grouping at this level can be the same or different. In other words, the division is not particularly limited, as long as the group obtained by grouping the latch units at each level is obtained by further dividing the group obtained by grouping the latch units at the previous level.

[0065] Each clock gating unit in each stage of the clock gating unit in the clock gating module 240 can be connected to the latch units 2200, 2201, ..., 220 15 The corresponding group of latch units obtained by grouping at the corresponding level are directly or indirectly coupled. For example, as shown in FIG10 , each clock gating unit in the first level clock gating unit 244 is connected to the latch units 2200, 2201, ..., 220 through the clock gating units of other levels in the clock gating module 240. 15 The corresponding group of latch units obtained by the first level grouping is coupled, and each clock gating unit in the second level clock gating unit 242 is coupled to the latch units 2200, 2201, ..., 220 15 The corresponding group of latch units obtained by grouping at the second level is coupled. In some embodiments as shown in FIG. 10 , the latch units 2200, 2201, . . . , 220 15 Each group obtained by grouping at the second level includes a latch unit. Accordingly, each clock gating unit in the second-level clock gating unit 242 is coupled to a latch unit; latch units 2200, 2201, ..., 220 15 Each group obtained by grouping at the first level includes four latch units. Accordingly, each clock gating unit in the first-level clock gating unit 244 is coupled to four latch units via clock gating units at other levels in the clock gating module 240. If a first clock gating unit (e.g., clock gating unit 2440) included in the first-level clock gating unit 244 is coupled to a second clock gating unit (e.g., clock gating unit 2420) included in the second-level clock gating unit 242, then a corresponding group of latch units (e.g., latch units 2200, 2201, 2202, 2203) coupled to the first clock gating unit (e.g., clock gating unit 2440) includes four latch units coupled to the second clock gating unit (e.g., clock gating unit 2420). A corresponding group of latch units (e.g., latch unit 2200) coupled to the clock gating unit 2420), that is, the grouping of latch units corresponding to the second clock gating unit (e.g., clock gating unit 2420) at the second level (e.g., latch unit 2200) is a subgroup of the grouping of latch units corresponding to the first clock gating unit (e.g., clock gating unit 2440) at the first level (e.g., latch units 2200, 2201, 2202, 2203, etc.).

[0066] The enable signal received by each clock gating unit in each level of the clock gating unit in the clock gating module 240 may be obtained by decoding the address corresponding to the corresponding level based on the write address. 15 The address of each latch unit in includes different parts corresponding to different levels. The addresses of latch units in the same group at the same level may have the same part, for example.

[0067] In some examples, when the address is binary, if the groups obtained by grouping the latch units at the second level each include one latch unit (a total of sixteen groups) and the groups obtained by grouping the latch units at the first level each include four latch units (a total of four groups), then the first address decoding corresponding to the first level of the write address may be associated with the remaining bits of the write address except for the lowest two bits, and the second address decoding corresponding to the second level of the write address may be associated with the lowest two bits of the write address. For example, referring to FIG. 10 , assuming that the latch units 2200, 2201, ..., 220 15 The addresses of the latch units 2200, 2201, 2202, and 2203 are respectively assigned from 0000 to 0011 (they belong to the same group at the first level, and the two most significant bits of the addresses are both 00), the addresses of the latch units 2204, 2205, 2206, and 2207 are respectively assigned from 0100 to 0111 (they belong to the same group at the first level, and the two most significant bits of the addresses are both 01), and the addresses of the latch units 2208, 2209, and 2200 are respectively assigned from 0100 to 0111 (they belong to the same group at the first level, and the two most significant bits of the addresses are both 01). 10 , 220 11 The address range is 1000 to 1011 (they belong to the same group in the first level, and the highest two digits of the address are both 10), the latch unit 220 12 , 220 13 ,2204,220 15The address range is 1100 to 1111 (they belong to the same group at the first level, and the two most significant bits of the address are both 11). Therefore, when the write address is 0000 (the target latch unit is latch unit 2200), the first address decoding corresponding to the first level of the write address can be based on the two most significant bits of the write address 00, thereby making the enable signal en'0 for the clock gating unit 2440 high, and making the enable signals en'1, en'2, and en'3 for the clock gating units 2441, 2442, and 2443 low, thereby only turning on the clock terminals CK of the clock gating units 2420, 2421, 2422, and 2423. Next, the second address decoding corresponding to the second level of the write address can be based on the lowest two bits 00 of the write address, so that the enable signal en0 for the clock gating unit 2420 is high, and the enable signals en1, en2, and en3 for the clock gating units 2421, 2422, and 2423 are low, thereby only turning on the clock control terminal G of the latch unit 2200.

[0068] Similarly, in other examples, when the address is binary, if the groups obtained by grouping the latch units at the second level each include one latch unit (a total of sixteen groups) and the groups obtained by grouping the latch units at the first level each include eight latch units (a total of two groups), then the first address decoding corresponding to the first level of the write address may be associated with the remaining bits of the write address except for the lowest three bits, and the second address decoding corresponding to the second level of the write address may be associated with the lowest three bits of the write address. For example, assuming that the latch units 2200, 2201, ..., 220 15 The addresses 0000 to 1111 are assigned respectively, wherein the latch units 2200, 2201, ..., 2207 are grouped into one group at the first level and have an address range of 0000 to 0111 (the highest bit of the address is 0), and the latch units 2208, 2209, ..., 220 15 The first level is divided into a group and has an address range of 1000 to 1111 (the highest bit of the address is 1).

[0069] It can be understood that for binary addresses, when the latch units are grouped into multiple levels, the address decoding corresponding to each level of the write address can be associated with the corresponding number of bits of the write address. "Several" means that it can be one or more. In some embodiments, especially when the latch units are equally divided at each level, the number of bits of the corresponding number of bits can be determined by the number of bits of the binary representation of the ratio of the number of groups obtained by grouping the latch units at this level to the number of groups obtained by grouping the latch units at the previous level. For the highest level, the previous level can be considered to be ungrouped, or the number of groups obtained by grouping the latch units at the previous level can be considered to be one.

[0070] For example, when the latch units are grouped in two levels, the number of bits of the binary representation of the number of groups (ratio to one) obtained by grouping the latch units in the first level determines that the first address decoding corresponding to the first level of the write address is associated with the highest bits of the write address, while the number of bits of the binary representation of the ratio of the number of groups obtained by grouping the latch units in the lower second level to the number of groups obtained by grouping the latch units in the first level determines that the second address decoding corresponding to the second level of the write address is associated with the lowest bits of the write address. For example, for the example in which the groups obtained by grouping the aforementioned latch units at the second level each include one latch unit (a total of sixteen groups) and the groups obtained by grouping at the first level each include eight latch units (a total of two groups): the number of groups obtained by grouping the latch units at the first level (the ratio to one) is 2, and its binary representation is 1 (the number of bits is 1), then the address decoding corresponding to the first level of the write address is associated with the highest bit of the write address; the ratio of the number of groups obtained by grouping the latch units at the second level to the number of groups obtained by grouping the latch units at the first level is 8, and its binary representation is 111 (the number of bits is 3), then the address decoding corresponding to the second level of the write address is associated with the lowest three bits of the write address. For another example, for the example in which the groups obtained by grouping the aforementioned latch units at the second level each include one latch unit (a total of sixteen groups) and the groups obtained by grouping the latch units at the first level each include four latch units (a total of four groups): the number of groups obtained by grouping the latch units at the first level (ratio to one) is 4, and its binary representation is 11 (the number of bits is 2), then the address decoding corresponding to the first level of the write address is associated with the highest two bits of the write address; the ratio of the number of groups obtained by grouping the latch units at the second level to the number of groups obtained by grouping the latch units at the first level is 4, and its binary representation is 11 (the number of bits is 2), then the address decoding corresponding to the second level of the write address is associated with the lowest two bits of the write address.

[0071] The above-described address configuration simplifies the address decoding logic. Of course, the address configuration is not limited to the above example, but can adopt any form suitable for addressing the target latch unit group at each level. Thus, the enable signal corresponding to the address decoding of each level based on the write address can be used to enable the clock gating unit in the corresponding first-level clock gating unit corresponding to the target latch unit group at that level.

[0072] 12 , in some embodiments, the storage module 210 further includes an additional latch unit 220 16 The clock gating module 240 also includes an additional clock gating unit 242 16 Additional latch unit 220 16 An address may be assigned to the additional clock gating unit 242, and its input terminal D is also configured to receive the write data. 16 With additional latch unit 22016 coupled, and configured to receive an input clock signal clk and an enable signal en obtained by address decoding based on a write address 16 , and to the additional latch unit 220 16 Output enable clock signal enclk 16 In such an embodiment, even after the highest level of grouping of the latch units in the storage module 210, there may still be a single latch unit. For example, after grouping the seventeen latch units into four groups, there may still be one latch unit left (as shown in FIG12 ). In this case, it is unnecessary and may even be disadvantageous to separately arrange multiple levels of clock gating units for the single latch unit. Therefore, a single clock gating unit can be directly used to control the data writing of the single latch unit, which is similar to each latch unit 120 and its corresponding clock gating unit 140 in FIG4 .

[0073] 13 and 14 , the storage device 200 may further include a trigger unit 310 and a clock source unit 320. The trigger unit 310 may be configured to output write data wd to the storage module 210 based on a received clock signal. The clock source unit 320 is coupled to the trigger unit 310 and the clock gating module 240, respectively, and is configured to provide an input clock signal clk. As shown in FIG14 , due to the presence of multiple clock gating units in the clock gating module 240, the enable clock signal enclk received by the target latch unit corresponding to the write address in the storage module 210 may be delayed (or "clock skew") relative to the input clock signal clk. This delay may cause timing issues between the output of wd by the trigger unit 310 and the writing of wd by the storage module 210, potentially leading to write failures. To this end, as shown in FIG13 , in some embodiments, the storage device 200 may further include a clock delay unit 330 coupled between the clock source unit 320 and the trigger unit 310. The clock delay unit 330 is configured to receive an input clock signal clk, delay the input clock signal clk based on the delay of the enable clock signal enclk received by the target latch unit in the storage module 210 relative to the input clock signal clk, and output the delayed input clock signal clkd to the flip-flop unit 310. As shown in FIG14 , there may be no clock skew or very little clock skew between the delayed input clock signal clkd and the enable clock signal enclk. The clock delay unit 320 may, for example, include one or more of the following: a clock buffer; an inverter. In some embodiments, the clock delay unit 320 may include a cascade of multiple clock buffers or inverters. When the flip-flop unit 310 is rising-edge triggered, the rising edge of the delayed input clock signal clkd may be closer to the rising edge of the enable clock signal enclk received by the target latch unit in the storage module 210 than to the rising edge of the input clock signal clk. When the flip-flop unit 310 is falling-edge triggered, the falling edge of the delayed input clock signal clkd can be closer to the falling edge of the enable clock signal enclk received by the target latch unit in the memory module 210 than the falling edge of the input clock signal clk. By providing the clock delay unit 330, the timing of the memory device 200 can be optimized, and the performance can be further improved.

[0074] In another aspect, the present disclosure further provides a system on chip, which may include the storage device according to any of the aforementioned embodiments. For example, such a system on chip may be implemented as various processors, controllers, and the like.

[0075] The present disclosure further provides, on another aspect, a computing device, which may include a system on a chip according to any of the foregoing embodiments. Examples of computing devices may include, but are not limited to, consumer electronic products, components of consumer electronic products, electronic test equipment, cellular communication infrastructure such as base stations, and the like. Examples of computing devices may include, but are not limited to, mobile phones such as smartphones, wearable computing devices such as smart watches or headphones, phones, televisions, computer monitors, computers, modems, handheld computers, laptop computers, tablet computers, personal digital assistants (PDAs), microwave ovens, refrigerators, in-vehicle electronic systems such as automotive electronic systems, stereo systems, DVD players, CD players, digital music players such as MP3 players, radios, portable cameras, cameras such as digital cameras, portable memory chips, washing machines, dryers, washer / dryers, peripheral devices, clocks, and the like. In addition, computing devices may include incomplete products.

[0076] The words "left," "right," "front," "back," "top," "bottom," "up," "down," "high," "low," and the like, if any, in the specification and claims, are used for descriptive purposes and are not necessarily intended to describe invariant relative positions. It should be understood that the words so used are interchangeable under appropriate circumstances such that the embodiments of the present disclosure described herein, for example, are capable of operation in orientations other than those illustrated or otherwise described herein. For example, features previously described as "above" other features could be described as "below" the other features when the apparatus in the accompanying drawings is turned over. The apparatus can also be otherwise oriented (rotated 90 degrees or in other orientations) and relative spatial relationships will be interpreted accordingly.

[0077] In the specification and claims, when an element is referred to as being "on," "attached," "connected," "coupled," or "in contact with," etc., another element, the element may be directly on, directly attached, directly connected, directly coupled, or directly in contact with the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being "directly" "on," "directly attached," "directly connected," "directly coupled," or "in direct contact with" another element, there will be no intervening elements. In the specification and claims, when a feature is arranged "adjacent" to another feature, it may mean that the feature has a portion that overlaps with the adjacent feature or a portion that is located above or below the adjacent feature.

[0078] As used herein, the word "exemplary" means "serving as an example, instance, or illustration," rather than as a "model" to be precisely copied. Any implementation described as exemplary is not necessarily to be construed as preferred or advantageous over other implementations. Furthermore, this disclosure is not to be bound by any expressed or implied theory presented in the technical field, background, summary, or detailed description.

[0079] As used herein, the term "substantially" is intended to encompass any minor variations due to design or manufacturing imperfections, device or component tolerances, environmental influences, and / or other factors. The term "substantially" also allows for deviations from a perfect or ideal condition due to parasitic effects, noise, and other practical considerations that may be present in actual implementations.

[0080] Additionally, terms such as "first," "second," and the like may also be used herein for reference purposes only and are not intended to be limiting. For example, the terms "first," "second," and other numerical terms referring to structures or elements do not imply a sequence or order unless the context clearly indicates otherwise.

[0081] It should also be understood that when the term “include / comprises” is used in this document, it indicates the presence of the specified features, integers, steps, operations, units and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, units and / or components and / or their combinations.

[0082] In addition, when used in this application, the words "herein," "above," "below," "hereunder," "supra," and words of similar meaning shall refer to this application as a whole and not to any particular portion of this application. Furthermore, unless expressly stated otherwise or otherwise understood in the context of use, conditional language used herein, such as "may," "might," "for example," "such as," and the like, is generally intended to express that certain embodiments include, while other embodiments do not include, certain features, elements, and / or states. Thus, such conditional language is generally not intended to imply that one or more embodiments require features, elements, and / or states in any way, or whether such features, elements, and / or states are included or performed in any particular embodiment.

[0083] In this disclosure, the term "provide" is used in a broad sense to cover all ways of obtaining an object, and thus "providing an object" includes but is not limited to "purchasing", "preparing / manufacturing", "arranging / setting up", "installing / assembling", and / or "ordering" an object, etc.

[0084] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the present disclosure. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0085] Those skilled in the art will appreciate that the boundaries between the above-described operations are merely illustrative. Multiple operations may be combined into a single operation, a single operation may be distributed among additional operations, and operations may be performed with at least partial overlap in time. Furthermore, alternative embodiments may include multiple instances of a particular operation, and the order of operations may be changed in various other embodiments. However, other modifications, variations, and substitutions are also possible. Aspects and elements of all of the embodiments disclosed above may be combined in any manner and / or in combination with aspects or elements of other embodiments to provide multiple additional embodiments. Therefore, this specification and the accompanying drawings should be regarded as illustrative, not restrictive. In fact, the novel devices, methods, and systems described herein may be embodied in a variety of other forms. Furthermore, various omissions, substitutions, and changes may be made to the form of the methods and systems described herein without departing from the spirit of the present disclosure. For example, although blocks are presented in a given arrangement, alternative embodiments may perform similar functions with different components and / or circuit topologies, and blocks may be deleted, moved, added, subdivided, combined, and / or modified. Each of these blocks may be implemented in a variety of different ways.

[0086] The various embodiments of the present disclosure may be described in a progressive manner, and the same or similar parts between the various embodiments may be referred to each other, and each embodiment focuses on the differences from other embodiments. In the present disclosure, descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present disclosure. In the present disclosure, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0087] Although some specific embodiments of the present disclosure have been described in detail by way of examples, those skilled in the art will appreciate that the above examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The various embodiments disclosed herein may be combined in any manner without departing from the spirit and scope of the present disclosure. Those skilled in the art will also appreciate that various modifications may be made to the embodiments without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A storage device, comprising: A storage module, comprising a plurality of latch units each assigned an address, wherein an input terminal of each latch unit in the plurality of latch units is configured to receive write data; as well as A clock gating module comprises a first-level clock gating unit and a second-level clock gating unit coupled between the plurality of latch units and the first-level clock gating unit, Among them, each clock gating unit in the first-level clock gating unit is configured to receive an input clock signal and an enable signal obtained by decoding a first address based on a write address and output an enable clock signal to a corresponding clock gating unit in the second-level clock gating unit, and each clock gating unit in the second-level clock gating unit is configured to receive an enable clock signal output by a corresponding clock gating unit in the first-level clock gating unit and an enable signal obtained by decoding a second address based on the write address and output an enable clock signal to a corresponding latch unit in the multiple latch units.

2. The storage device according to claim 1, wherein: The clock gating module further includes one or more levels of clock gating units coupled between the first level of clock gating units and the second level of clock gating units, each of the clock gating units in each level of the one or more levels of clock gating units being configured to receive an enable clock signal output by a corresponding clock gating unit in an upper level of the one or more levels of clock gating units and an enable signal obtained by decoding a corresponding address of a write address, and output an enable clock signal to a corresponding clock gating unit in a lower level of the one or more levels of clock gating units, Among them, each clock gating unit in the first-level clock gating unit is configured to receive an input clock signal and an enable signal obtained by decoding the first address based on the write address and output the enable clock signal to the corresponding clock gating unit in the uppermost clock gating unit in the one or more levels of clock gating units, and each clock gating unit in the second-level clock gating unit is configured to receive the enable clock signal output by the corresponding clock gating unit in the lowermost clock gating unit in the one or more levels of clock gating units and the enable signal obtained by decoding the second address based on the write address and output the enable clock signal to the corresponding latch unit in the multiple latch units.

3. The storage device according to claim 1 or 2, wherein: The plurality of latch units are grouped hierarchically, and the groups obtained by grouping the plurality of latch units at each hierarchical level are obtained by further dividing the groups obtained by grouping the plurality of latch units at the previous hierarchical level. The number of stages of the clock gating units included in the clock gating module corresponds to the number of the multiple latch units. the number of levels of grouping, and The number of clock gating units included in each level of clock gating units in the clock gating module corresponds to the number of groups obtained by grouping the multiple latch units at the corresponding level.

4. The storage device according to claim 3, wherein: The enable signal received by each clock gating unit in each level of clock gating units in the clock gating module is obtained based on address decoding corresponding to the corresponding level of the write address.

5. The storage device according to claim 4, wherein: The address of each of the plurality of latch units includes different parts corresponding to different levels, and wherein addresses of latch units within a same group at a same level have a same part.

6. The storage device according to claim 4 or 5, wherein: The address is binary, and wherein the address decoding corresponding to each level of the write address is associated with corresponding bits of the write address.

7. The storage device according to claim 6, wherein: The number of bits of the corresponding several bits is determined by the number of bits of the binary representation of the ratio between the number of groups obtained by grouping the multiple latch units at this level and the number of groups obtained by grouping the multiple latch units at the previous level.

8. The storage device according to claim 3, wherein: Each clock gating unit in the first-level clock gating unit is coupled to a corresponding group of latch units obtained by grouping the multiple latch units at the first level via other-level clock gating units in the clock gating module, and each clock gating unit in the second-level clock gating unit is coupled to a corresponding group of latch units obtained by grouping the multiple latch units at a second level lower than the first level.

9. The storage device according to claim 1, wherein: The storage module further comprises an additional latch unit assigned with an address, and an input end of the additional latch unit is configured to receive the write data; The clock gating module further includes an additional clock gating unit, which is coupled to the additional latch unit and configured to receive the input clock signal and an address decoded based on the write address. The enable signal is outputted to the additional latch unit and the enable clock signal is outputted to the additional latch unit.

10. The storage device according to claim 1, further comprising: a trigger unit configured to output the write data to the storage module based on the received clock signal; a clock source unit, coupled to the trigger unit and the clock gating module respectively, and configured to provide the input clock signal; as well as A clock delay unit is coupled between the clock source unit and the trigger unit, and is configured to receive the input clock signal and delay the input clock signal based on the delay of the enable clock signal received by the latch unit corresponding to the write address in the storage module relative to the input clock signal, and output the delayed input clock signal to the trigger unit.

11. The storage device according to claim 10, wherein: The clock delay unit includes one or more of the following: a clock buffer; an inverter.

12. The storage device according to claim 10, wherein: The trigger unit is rising edge triggered, and the rising edge of the delayed input clock signal is closer to the rising edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module than the rising edge of the input clock signal; or The trigger unit is falling-edge triggered, and the falling edge of the delayed input clock signal is closer to the falling edge of the enable clock signal received by the latch unit corresponding to the write address in the storage module than the falling edge of the input clock signal.

13. A system on chip, comprising the storage device according to any one of claims 1 to 12.

14. A computing device comprising the system on chip according to claim 13.

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