Caching method and apparatus for memory page table, storage medium, and computer program product

Abstract

The present application belongs to the technical field of computers, and discloses a caching method and apparatus for a memory page table, a storage medium, and a computer program product. The method comprises: a process applies, according to needs, for a memory page of a certain size, the size of the applied-for memory page not being limited to the page size of a page table of any level; correspondingly, a computing device can create, on the basis of application by the process and by merging page table entries, a memory page of a corresponding size for the process, and store, in a page table cache, a cache table entry obtained from merging. That is, by merging page table entries, a larger memory page is actively created from a source for the process, so that one cache table entry in the page table cache can cover a plurality of page table entries in a memory page table, thereby improving the hit rate of the page table cache, reducing page table walking, and lowering memory access delay and memory access overhead.

Description

Memory page table caching method, device, storage medium and computer program product

[0001] This application claims priority to Chinese patent application No. 202311230459.6 filed on September 21, 2023, entitled “Cache method, device, storage medium and computer program product for memory page table”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of computer technology, and in particular to a method, device, storage medium, and computer program product for caching a memory page table. Background Art

[0003] When accessing memory, processors often use virtual addresses (VAs). Using virtual addresses creates an address space much larger than the actual physical addresses (PAs). In the process of using virtual addresses for memory addressing, the virtual addresses must be converted to physical addresses, and then memory access is performed based on the physical addresses.

[0004] Among them, the virtual address includes a virtual page number (VPN) and an offset, and the physical address includes a physical page number (PPN) and an offset. One virtual page number corresponds to one physical page number, and one physical page number indicates one physical page. The offset in the virtual address is the same as the offset in the physical address.

[0005] In related technologies, a translation lookaside buffer (TLB) includes multiple cache entries. The TLB is also called a page table cache, and cache entries are also called entries. Each cache entry is used to store the mapping relationship between a virtual page number and a physical page number. When converting a virtual address to a physical address, the physical page number corresponding to the virtual page number in the virtual address is first searched from the TLB. If the search is successful (TLB hit), the physical address is determined based on the found physical page number and the offset in the virtual address. If the search fails (TLB miss), the page table (PT) is read from the memory, and the physical page number corresponding to the virtual page number in the virtual address is searched from each page table entry (PTE) in the page table to determine the physical address. The found mapping relationship is then stored as a cache entry in the TLB. This process is also called a page table walk (PTW). Each page table entry indicates the mapping relationship between a virtual page number and a physical page number.

[0006] However, a TLB cache entry only stores the mapping between a virtual page number and a physical page number. The TLB's storage space is limited, and the number of page table entries far outnumbers the number of cache entries in the TLB. Therefore, the physical pages that can be covered by the mapping stored in the TLB are limited, resulting in a low TLB hit rate. A TLB miss requires a time-consuming post-processing (PTW), which increases memory access latency and overhead. Therefore, improving the TLB hit rate has become a major concern.

[0007] Summary of the Invention

[0008] This application provides a memory page table caching method, device, storage medium, and computer program product that can increase the physical memory capacity covered by entries in the page table cache, thereby improving the page table cache hit rate, reducing page table walks, and lowering memory access latency and memory access overhead. The technical solution is as follows:

[0009] In a first aspect, a method for caching a memory page table is provided, the method comprising: obtaining a memory request of a target process, the memory request indicating a target page size, the target page size being larger than the page size of a first-level page table and smaller than the page size of a second-level page table, the first-level page table and the second-level page table being continuous two-level page tables; in response to the memory request, allocating N continuous virtual page numbers and N continuous physical page numbers to the target process, N being not less than the number of memory pages required by the target process; creating N page table entries in the memory page table based on the N physical page numbers and the N virtual page numbers, the N page table entries representing a mapping relationship between the N virtual page numbers and the N base pages, the N base pages being N physical pages corresponding one-to-one to the N physical page numbers, the size of the base page being equal to the page size of the first-level page table; merging the N page table entries into a first cache table entry, and storing the first cache table entry in the page table cache.

[0010] By merging page table entries, we proactively create larger memory pages for processes. This allows a single cache entry in the page table cache to cover multiple entries in the memory page table, improving the page table cache hit rate, reducing page table walks, and lowering memory access latency and overhead. Proactively creating large pages significantly increases the number of large pages, thereby increasing the number of cache entries that can be merged, significantly improving the page table cache hit rate.

[0011] Among them, allocating N consecutive virtual page numbers and N consecutive physical page numbers to the target process includes: determining the value of N based on the target page size and the size of the base page; determining N consecutive physical page numbers from unused physical page numbers based on the value of N, and determining N consecutive virtual page numbers based on the unused virtual address space; and allocating the determined N physical page numbers and N virtual page numbers to the target process.

[0012] Optionally, based on N physical page numbers and N virtual page numbers, N page table entries are created in the memory page table, including: determining the smallest physical page number among the N physical page numbers as the basic physical page number; generating a reference physical page number based on the basic physical page number; creating N page table entries in the memory page table, each of the N page table entries including a virtual page number among the N virtual page numbers, a reference physical page number and a tag bit, wherein the tag bit indicates that the corresponding page table entry is a mergeable item.

[0013] In order to facilitate the forward and reverse conversion between page numbers and improve performance, N can be limited to 2. x, x is a positive integer, and the base physical page number is divisible by N; this can be used as a condition for merging page table entries. Based on the base physical page number, generating a reference physical page number includes: determining that the value of the xth to the leftmost bit in the reference physical page number is equal to the value of the xth to the leftmost bit in the base physical page number, the values ​​of the 0th to x-2th to last bits are all the first value, and the value of the x-1th to last bit is the second value.

[0014] Considering that if the read and write attributes of pages are different, even if they are merged, the memory read and write performance of the process will be affected. Therefore, to ensure the performance of page table entry merging, the merging condition of page table entries also includes the same read and write attributes of the pages. For example, the read and write attributes of the N basic pages mentioned above are the same.

[0015] Merging N page table entries into a first cache table entry includes: obtaining a memory access request of a target process, the memory access request including a target virtual page number, and the target virtual page number being one of the N virtual page numbers; and merging the N page table entries into the first cache table entry in the process of determining a target physical page number corresponding to the target virtual page number.

[0016] As can be seen from the above, each of the N page table entries includes a virtual page number among the N virtual page numbers, and the N page table entries also include the same reference physical page number, which is generated based on the basic physical page number, and the basic physical page number is the smallest physical page number among the N physical page numbers; in the process of determining the target physical page number corresponding to the target virtual page number, the N page table entries are merged into a first cache table entry, including: in the process of determining the target physical page number corresponding to the target virtual page number, searching the memory page table for the page table entry where the target virtual page number is located to obtain the first page table entry; if the first page table entry is a mergeable item, determining the target parameter value based on the first page table entry, the target parameter value indicates the value size of N; generating a merged virtual page number based on the target parameter value and the target virtual page number, and determining the basic physical page number based on the reference physical page number in the first page table entry; generating a first cache table entry, the first cache table entry including the merged virtual page number, the basic physical page number and a tag bit, the tag bit in the first cache table entry indicating that the first cache table entry is a merged item.

[0017] The N page table entries all include a tag bit whose value is the first value, and the value of the penultimate x-1 bit in the reference physical page number is the second value, and the values ​​of the penultimate 0th to x-2th bits are all the first value, N=2 x, x is a positive integer, and x represents a target parameter value; determining the target parameter value based on the first page table entry includes: counting the number of bits whose value is the first value from the rightmost bit of the first binary string to the left until the first bit of the first binary string that is not the first value is counted from the right to the left, to obtain the target parameter value, wherein the first binary string refers to a binary string obtained by concatenating the tag bit at the end of the reference physical page number.

[0018] It can be seen that when N=2 x If both the base physical page number and the base virtual page number are divisible by N, and the value of the tag bit and the values ​​of the 0th to x-2th bits from the bottom of the reference physical page number are both the first value, then the processor does not need to waste additional storage space to record the number of merged items N and / or the parameter value x. The value of x can be determined by counting the number of bits of the first value in the low order bits of the first binary string. Knowing the value of x can determine the value of N. This design not only enables forward and reverse conversion between page numbers, but also eliminates the need to waste additional storage space.

[0019] Accordingly, a merged virtual page number is generated based on the target parameter value and the target virtual page number, including: determining that the values ​​of the xth to last bit to the leftmost bit in the merged virtual page number are equal to the values ​​of the xth to last bit to the leftmost bit in the target virtual page number, the values ​​of the 0th to x-2th to last bits are all first values, and the value of the xth to last bit is the second value; and determining the base physical page number based on the reference physical page number in the first page table entry, including: determining that the values ​​of the xth to last bit to the leftmost bit in the base physical page number are equal to the values ​​of the xth to last bit to the leftmost bit in the reference physical page number, and the values ​​of the 0th to x-1th to last bits are all first values.

[0020] After determining the base physical page number based on the reference physical page number in the first page table entry, the method further includes: determining a base virtual page number based on the target parameter value and the target virtual page number, where the base virtual page number is the smallest virtual page number among the N virtual page numbers; and determining a target physical page number based on the base physical page number, the target virtual page number, and the base virtual page number. In other words, the method translates the actual physical page number.

[0021] It should be understood that before searching the page table entry where the target virtual page number is located from the memory page table, it also includes: querying the page table cache based on the target virtual page number to determine whether the target virtual page number hits the page table cache; if the target virtual page number does not hit the page table cache, executing the step of searching the page table entry where the target virtual page number is located from the memory page table.

[0022] Among them, the page table cache is queried based on the target virtual page number to determine whether the target virtual page number hits the page table cache, including: querying the page table entry where the target virtual page number is located from the page table cache; if the page table entry where the target virtual page number is located is not queried from the page table cache, then based on the merge threshold and the target virtual page number, multiple candidate virtual page numbers are determined, and the merge threshold indicates the maximum number of page table entries that can be merged at one time; querying whether there is a page table entry corresponding to a first candidate virtual page number in the page table cache, the first candidate virtual page number being any candidate virtual page number among the multiple candidate virtual page numbers; if there is no page table entry corresponding to the first candidate virtual page number in the page table cache, it is determined that the target virtual page number does not hit the page table cache.

[0023] Optionally, based on the merge threshold and the target virtual page number, multiple candidate virtual page numbers are determined, including: determining that the value of the jth to last bit to the leftmost bit in the jth candidate virtual page number included in the multiple candidate virtual page numbers is equal to the value of the jth to last bit to the leftmost bit in the target virtual page number, j∈[1,X], X represents the merge threshold; when j>1, determining that the values ​​of the 0th to j-2th last bits in the jth candidate virtual page number are all the first value, and the value of the j-1th to last bit is the second value; when j=1, determining that the value of the j-1th to last bit in the jth candidate virtual page number is the second value.

[0024] It should be understood that during the address translation process, if a cache entry obtained by merging is stored in the page table cache, since the virtual page number in the cache entry is the merged virtual page number, and the processor does not know the number of merged entries corresponding to the cache entry at this time, the processor needs to first generate candidate virtual page numbers corresponding to any possible number of merged entries based on the above merge threshold, thereby obtaining multiple candidate virtual page numbers, and then query the page table cache to see if a candidate virtual page number can be hit. The multiple values ​​of j above indicate multiple possible numbers of merged entries.

[0025] As can be seen from the above, each candidate virtual page number in the multiple candidate virtual page numbers corresponds to a parameter value, and the parameter value corresponding to each candidate virtual page number indicates the number of merged items corresponding to the corresponding candidate virtual page number; after querying whether there is a page table entry corresponding to the first candidate virtual page number in the page table cache, the method also includes: if there is a page table entry corresponding to the first candidate virtual page number in the page table cache, then determining the parameter value corresponding to the first candidate virtual page number as the target parameter value; based on the target parameter value and the target virtual page number, determining the basic virtual page number, the basic virtual page number is the smallest virtual page number among the above N virtual page numbers; based on the basic physical page number, the target virtual page number and the basic virtual page number, determining the target physical page number.

[0026] Among them, if N = 2 x, x is a positive integer, and the base virtual page number is divisible by N. Then, based on the target parameter value and the target virtual page number, the base virtual page number is determined, including: determining that the value of the x-th last bit to the leftmost bit in the base virtual page number is equal to the value of the x-th last bit to the leftmost bit in the target virtual page number, and the values ​​of the 0th to x-1th last bits are all the first value, and x is equal to the target parameter value.

[0027] After determining the base physical page number and the base virtual page number, the processor can determine the target physical page number based on the base physical page number, the target virtual page number, and the base virtual page number. Specifically, determining the target physical page number based on the base physical page number, the target virtual page number, and the base virtual page number includes: determining a difference between the target virtual page number and the base virtual page number; and determining the sum of the difference and the base physical page number as the target physical page number.

[0028] Among them, the first value is 0 and the second value is 1.

[0029] Optionally, the method further includes: if a page table entry has been changed among the N page table entries, then based on the changed page table entry, deleting the first cache entry in the page table cache, and determining whether there are still M page table entries that can be merged among the N page table entries, where M is a positive integer greater than 2 and less than N; if it is determined that there are still M page table entries that can be merged among the N page table entries, then merging the M page table entries into a second cache entry, and storing the second cache entry in the page table cache. In other words, this solution can also disassemble the merged large page and re-merge the page table entries that can still be merged after the disassembly.

[0030] In a second aspect, a memory page table caching device is provided, wherein the device has the function of implementing the memory page table caching method described in the first aspect. The device includes one or more modules, each of which is configured to implement the memory page table caching method described in the first aspect.

[0031] In a third aspect, a computing device is provided, comprising a processor and a memory, wherein the memory is configured to store a program for executing the memory page table caching method provided in the first aspect, and to store data involved in implementing the memory page table caching method provided in the first aspect. The processor is configured to execute the program stored in the memory. The computing device may further comprise a communication bus for establishing a connection between the processor and the memory.

[0032] In a fourth aspect, a computer-readable storage medium is provided, wherein instructions are stored in the computer-readable storage medium, which, when executed on a computer, enables the computer to execute the memory page table caching method described in the first aspect.

[0033] In a fifth aspect, a computer program product comprising instructions is provided, which, when executed on a computer, enables the computer to execute the memory page table caching method described in the first aspect.

[0034] The technical effects obtained in the above-mentioned second, third, fourth and fifth aspects are similar to those obtained by the corresponding technical means in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] FIG1 is a schematic diagram of a page table hierarchy provided in an embodiment of the present application;

[0036] FIG2 is a schematic diagram of the structure of a computing device provided in an embodiment of the present application;

[0037] FIG3 is an architecture diagram of a processor provided in an embodiment of the present application;

[0038] FIG4 is a flow chart of a memory page table caching method provided in an embodiment of the present application;

[0039] FIG5 is a schematic diagram of creating a mergeable page table entry in Example 1 provided in an embodiment of the present application;

[0040] FIG6 is a schematic diagram of merging page table entries during the address translation process in Example 1 provided in an embodiment of the present application;

[0041] 7 is a schematic diagram of cache entries obtained by hit merging during the address translation process in Example 1 provided in an embodiment of the present application;

[0042] FIG8 is a schematic diagram of disassembling a large page in Example 1 provided in an embodiment of the present application;

[0043] FIG9 is a schematic diagram of creating a mergeable page table entry in Example 2 provided in an embodiment of the present application;

[0044] FIG10 is a schematic diagram of merging page table entries during the address translation process in Example 2 provided in an embodiment of the present application;

[0045] FIG11 is a schematic diagram of cache entries obtained by hit merging during address translation in Example 2 provided in an embodiment of the present application;

[0046] FIG12 is a schematic diagram of disassembling a large page in Example 2 provided in an embodiment of the present application;

[0047] FIG13 is a schematic diagram of creating a mergeable page table entry in Example 3 provided in an embodiment of the present application;

[0048] FIG14 is a schematic diagram of merging page table entries during the address translation process in Example 3 provided in an embodiment of the present application;

[0049] FIG15 is a schematic diagram of cache entries obtained by hit merging during the address translation process in Example 3 provided in an embodiment of the present application;

[0050] FIG16 is a schematic diagram of disassembling a large page in Example 3 provided in an embodiment of the present application;

[0051] FIG17 is a schematic structural diagram of a memory page table cache device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0052] In order to make the objectives, technical solutions and advantages of the embodiments of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0053] For ease of understanding, before explaining in detail the memory page table caching method provided in the embodiment of the present application, the terminology, background knowledge and implementation environment involved in the embodiment of the present application are first introduced.

[0054] First, the terms involved in the embodiments of the present application are introduced.

[0055] 1. Virtual page (VP) and physical page (PP)

[0056] In memory paging management, the virtual address space (or virtual memory) and the physical address space (or physical memory) are divided into multiple storage units of equal capacity. The storage units divided from the virtual address space are called virtual pages, and the storage units divided from the physical address space are called physical pages. Physical pages can also be called pages or page frames. The size (also called capacity) of virtual pages and physical pages is equal and usually fixed. For example, the size of a virtual page or physical page can be 4 kilobytes, 2 megabytes, or 1 gigabyte, etc.

[0057] 2. Physical address (VA)

[0058] A physical address is a unique memory address corresponding to a byte unit in memory. Under the paging mechanism, the operating system (OS) of a computing device can divide the physical address space into consecutive physical pages. A virtual address space is divided into multiple consecutive virtual pages. A physical address can uniquely identify a physical page.

[0059] The physical address includes a physical page number (PPN) and a physical page offset (PPO). The physical page number indicates the physical page where the physical address is located, and the physical page offset refers to the offset of the physical address relative to the starting address of the physical page where the physical address is located.

[0060] The physical page number is the high-order portion of the physical address, and the physical page offset is the low-order portion of the physical address. In other words, the physical page number is the left portion or the head of the physical address, and the physical page offset is the right portion or the tail of the physical address.

[0061] For example, taking a 32-bit operating system as an example, the physical address is in binary form of 32 bits, the physical page number is the upper 20 bits (i.e., bits 12 to 31) of the physical address, and the physical page offset is the lower 12 bits (i.e., bits 0 to 11) of the physical address.

[0062] 3. Virtual address (VA)

[0063] A virtual address is the logical address used by an application process to access memory. To enable multiple processes to run in parallel, the operating system allocates a private virtual address space to each process during initialization and maps each process's virtual address space to the corresponding physical address space. When multiple programs run simultaneously, each process corresponds to a different virtual address space, effectively residing in different physical address spaces. This ensures the normal execution of multiple programs. The computing device's operating system can use a paging mechanism to divide a virtual address space into multiple contiguous virtual pages. A virtual address uniquely identifies a virtual page.

[0064] A virtual address includes a virtual page number (VPN) and a virtual page offset (VPO). The virtual page number indicates the virtual page where the virtual address is located, and the virtual page offset refers to the offset of the virtual address relative to the starting address of the virtual page where the virtual address is located.

[0065] The virtual page number is the high-order portion of the virtual address, and the virtual page offset is the low-order portion of the virtual address. In other words, the virtual page number is the left portion or header of the virtual address, and the virtual page offset is the right portion or tail of the virtual address.

[0066] For example, taking a 32-bit operating system as an example, the virtual address is in binary form of 32 bits, the virtual page number is the upper 20 bits of the virtual address (i.e., bits 12 to 31), and the virtual page offset is the lower 12 bits of the virtual address (i.e., bits 0 to 11).

[0067] It should be noted that a virtual page number corresponds to a physical page number. For a pair of physical addresses and virtual addresses with a mapping relationship, there is a certain mapping relationship or conversion relationship between the physical page number included in the physical address and the virtual page number included in the virtual address, and the physical page offset included in the physical address is the same as the virtual page offset included in the virtual address.

[0068] 4. Page Table

[0069] A page table is a data structure in memory. The page table includes multiple page table entries, each of which indicates the mapping relationship between a virtual address and a physical address. For example, each page table entry includes a mapping relationship between a virtual page number and a physical page number. The computing device can determine the physical page corresponding to the virtual page where the virtual address is located based on the mapping relationship between the virtual page number and the physical page number, and then determine the physical address corresponding to the virtual address based on the virtual page offset. The page table can be divided into multiple levels. For example, the page table includes a first-level page table, a second-level page table, a third-level page table, and so on.

[0070] Please refer to Figure 1 to understand the page table and the size of the memory page. Figure 1 is a schematic diagram of a page table with a minimum page size of 4KB involved in an embodiment of the present application. The page table includes five levels, which are, from large to small in order of page size, the negative first-level page table (level-1 table, L-1 T), the level 0 page table (level 0 table, L0 T), the first-level page table (level 1 table, L1 T), the second-level page table (level 2 table, L2 T) and the third-level page table (level 3 table, L3 T). Among them, the negative first-level page table is the highest level page table, which contains the description information of all page tables, and the third-level page table is the lowest level page table, with a page size of 4KB. The third-level page table contains the description information of the physical page. In addition, the page size of the second-level page table is 2MB, and a second-level page table contains 512 third-level page tables. The second-level page table contains the description information and block description information of the third-level page table. The page size of the first-level page table is 1GB, and a first-level page table contains 512 second-level page tables. The first-level page table contains the description information and block description information of the second-level page table. The page size of the 0-level page table is 512G, and a 0-level page table contains 512 first-level page tables. The 0-level page table contains the description information and block description information of the first-level page table. It can be seen that the page size has been set in each level of the page table. In the embodiment of the present application, the page size of any level of the page table can be regarded as a basic page.

[0071] In a specific implementation, in addition to the minimum page size of 4KB shown in FIG1 , a minimum page size of 16KB or other sizes may also exist. Of course, the number of page table levels is not limited to the five levels shown in FIG1 , and the page table may also be divided into three or four levels. In other words, the embodiments of the present application do not limit the minimum unit of a page, that is, do not limit the size of a physical page, nor do they limit the number of page table levels.

[0072] 5. Page Table Cache

[0073] The page table cache is a high-speed cache on the processor, also known as TLB. The TLB cache contains some PTEs in the page table. That is, the page table cache includes multiple cache entries, each of which is used to store the mapping relationship indicated by the page table entry queried from the page table. The computing device stores the mapping relationship queried from the page table as a cache entry in the page table cache. Then, before the computing device queries the mapping relationship in the page table next time, it can first query the cache entry in the page table cache. If the computing device hits any cache entry in the page table cache, it obtains the mapping relationship stored in the cache entry without having to access the page table in the memory, which can save query time.

[0074] 6. Page table walk

[0075] If the computing device does not hit a cache entry in the page table cache, the computing device accesses the page table in the memory to query the mapping relationship in the page table and stores the queried mapping relationship as a cache entry in the page table cache. This process is called a page table walk.

[0076] 7. Superpage

[0077] A memory page that is larger than a base page. It can have a variety of sizes, not limited to the page size of any level of the page table. For example, a super page can be up to several megabytes. Super pages enable each cache entry in the TLB to map a large physical memory area into the virtual address space. This significantly increases TLB coverage, reduces TLB misses, and provides performance improvements for many applications. The embodiments of this application are implemented based on super pages.

[0078] 8. Process

[0079] An application's execution on a data set within a computing device is called an execution instance (or execution entity). A process is also the fundamental unit of resource allocation and scheduling within a computing device's operating system. Each process consists of various system resources, including a private virtual address space, data set, disk, and bandwidth. A process can be, for example, a running browser or chat window. A process can have multiple threads, such as a chat tool receiving and sending messages.

[0080] Next, the background knowledge involved in the embodiments of this application is introduced.

[0081] Modern systems on chips (SoCs) often use a memory management unit (MMU) to enhance memory utilization and provide programmers with an easy-to-program interface. The main function of the MMU is to provide isolation between the virtual address space and the physical address space. However, the SoC invoking the MMU incurs performance overhead because of the need for a post-processing (PTW) operation. To translate virtual addresses, the MMU accesses memory to obtain the PTE, a process known as a post-processing (PTW). The MMU caches the obtained PTE in the TLB, which can reduce the need to enable PTW. However, in the case of a high TLB miss rate, frequent PTWs can significantly degrade performance due to the need for frequent pauses during application execution. Therefore, it is necessary to improve the TLB hit rate and reduce the number of PTWs.

[0082] In traditional designs, page tables and TLBs operate at the page level. In other words, PTE and TLB entries contain information about a single page. Furthermore, PTW lookups result in single-page queries. Modern operating systems, on the other hand, typically allocate physical memory at the granularity of blocks (a set of contiguous free physical pages). To leverage this contiguousness and reduce PTWs, processor architectures typically define a finite set of page sizes. However, traditional designs have limitations in fully utilizing the OS-provided contiguousness. For example, suppose the OS allocates a 512KB physical block. If the machine architecture doesn't define a 512KB page size, the system treats the block as 128 separate 4KB pages. This lack of knowledge between the hardware and the OS results in the generation of many separate PTWs to retrieve multiple 4KB pages, rather than block-level address translation.

[0083] In other words, the page sizes supported by related systems are limited, making it difficult to flexibly allocate pages of various sizes based on application scenarios. Furthermore, TLB entries are limited. If each VPN-to-PPN mapping must correspond to a PTE, this can easily lead to TLB misses, which in turn lead to PTWs, increasing memory access latency and overhead.

[0084] Next, the implementation environment of this application is introduced.

[0085] It should be understood that the implementation environment described in the embodiments of the present application is intended to more clearly illustrate the technical solutions of the embodiments of the present application, and does not constitute a limitation on the technical solutions provided by the embodiments of the present application. Ordinary technicians in this field can know that with the evolution of system architecture and the emergence of new business scenarios, the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems.

[0086] 2 is a schematic diagram of a computing device according to an embodiment of the present application, wherein the computing device includes one or more processors 201 , a communication bus 202 , a memory 203 , and one or more communication interfaces 204 .

[0087] The processor 201 is a general-purpose central processing unit (CPU), a network processing processor (NP), a microprocessor, or one or more integrated circuits for implementing the solution of the present application, such as an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. Optionally, the PLD is a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0088] Communication bus 202 is used to transmit information between the above components. Optionally, communication bus 202 is divided into an address bus, a data bus, a control bus, etc. For ease of illustration, FIG2 shows only one thick line, but this does not mean that there is only one bus or one type of bus.

[0089] Optionally, the memory 203 is a read-only memory (ROM), a random access memory (RAM), an electrically erasable programmable read-only memory (EEPROM), an optical disc (including a compact disc read-only memory (CD-ROM), a compact disc, a laser disc, a digital versatile disc, a Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 203 exists independently and is connected to the processor 201 via the communication bus 202, or the memory 203 is integrated with the processor 201.

[0090] The communication interface 204 uses any transceiver-like device for communicating with other devices or communication networks. The communication interface 204 includes a wired communication interface and, optionally, a wireless communication interface. Examples of the wired communication interface include an Ethernet interface. Optionally, the Ethernet interface is an optical interface, an electrical interface, or a combination thereof. The wireless communication interface is a wireless local area network (WLAN) interface, a cellular network communication interface, or a combination thereof.

[0091] Optionally, in some embodiments, the computing device includes multiple processors, such as processor 201 and processor 205 shown in Figure 2. Each of these processors is a single-core processor or a multi-core processor. Optionally, a processor herein refers to one or more devices, circuits, and / or processing cores for processing data (such as computer program instructions).

[0092] In a specific implementation, as an embodiment, the computing device further includes an output device 206 and an input device 207. The output device 206 communicates with the processor 201 and can display information in a variety of ways. For example, the output device 206 is a liquid crystal display (LCD), a light emitting diode (LED) display device, a cathode ray tube (CRT) display device, or a projector. The input device 207 communicates with the processor 201 and can receive user input in a variety of ways. For example, the input device 207 is a mouse, a keyboard, a touch screen device, or a sensor device.

[0093] In some embodiments, the memory 203 is used to store program code 210 for executing the solution of the present application, and the processor 201 can execute the program code 210 stored in the memory 203. The program code includes one or more software modules, and the computing device can implement the memory page table caching method provided in the embodiment of the present application through the processor 201 and the program code 210 in the memory 203.

[0094] The method provided by the embodiment of the present application can be applied to a memory access scenario, which can also be referred to as a data read and write scenario. In the memory access scenario, before executing a memory access instruction, the computing device first extracts the target virtual address to be converted from the memory access instruction, then determines the target physical address corresponding to the target virtual address, and then performs memory access based on the target physical address. In other words, the memory access instruction carries the target virtual address, and by determining the target physical address corresponding to the target virtual address, memory access is performed based on the target physical address.

[0095] FIG3 is an architectural diagram of a processor provided in an embodiment of the present application. The processor is used to execute the memory page table caching method provided in an embodiment of the present application. Referring to FIG3 , the processor includes a CPU core, an MMU, a cache, and memory. Among them, the CPU core includes a software part (software), such as an operating system (OS). The MMU is a hardware circuit inside the processor. The MMU may include a page table cache (TLB). Of course, the page table cache may also be located in other locations in the processor besides the MMU. The following is an example of the TLB being located inside the MMU. In an embodiment of the present application, the MMU includes a TLB and a table walk unit (TWU).

[0096] Among them, the operating system belongs to the category of virtual address space, which is used to generate virtual addresses (VA) to be translated and send the VA to be translated to the MMU. The MMU is used to perform address translation, that is, to realize the conversion of virtual addresses to physical addresses (PA). The cache and memory belong to the category of physical address space, which are used to access the corresponding storage space based on PA.

[0097] Specifically, the processor core sends a memory access instruction to the MMU, which extracts the target VA to be converted from the memory access instruction and matches the target VA with the table entry in the TLB to determine whether the target VA hits the TLB. In the case where the target VA hits the TLB, the target PA corresponding to the target VA is determined based on the TLB, and then the data corresponding to the target PA is obtained from the cache. If the data is not in the cache, the data corresponding to the target PA is obtained from the memory. In the case where the target VA misses the TLB, the MMU queries the PT based on the target VA to determine the target PTE, which indicates the mapping relationship between the target VA and the target PA. In this way, the MMU can refresh the TLB based on the target PTE and determine the target PA corresponding to the target VA, and then obtain the data corresponding to the target PA from the cache. If the data is not in the cache, the data corresponding to the target PA is obtained from the memory.

[0098] Since the storage space of the TLB is limited and the number of PTEs in the PT is far greater than the number of entries in the TLB, the physical memory size that can be covered by the entries in the TLB is limited, which may cause TLB misses during the address translation process. In turn, walking through the page table when a TLB miss occurs will increase the memory access overhead.

[0099] Based on this, an embodiment of the present application provides a memory page table caching method, which can increase the page size that can be flexibly created by the OS, and the process can also apply for a certain size of memory page on demand, reducing the number of entries required by PTE in the TLB cache and reducing TLB misses, thereby reducing PTW overhead.

[0100] Next, we will introduce the memory page table caching method provided in the embodiment of the present application. It should be noted that the method is executed by a computing device, which can be a terminal device such as a computer, a mobile phone, or a server. In a specific implementation, the method can be executed by a processor in the computing device.

[0101] FIG4 is a flow chart of a memory page table caching method provided by an embodiment of the present application, which is applied to a computing device, specifically to a processor of the computing device. Referring to FIG4 , the method includes the following steps.

[0102] Step 401: Obtain a memory request of a target process, where the memory request indicates a target page size, where the target page size is larger than a page size of a first-level page table and smaller than a page size of a second-level page table, wherein the first-level page table and the second-level page table are two consecutive levels of page tables.

[0103] Since this solution can create large pages by merging page table entries, in order to realize the creation of large pages from the source, when a process requests memory, it can flexibly request pages of a certain size on demand, without being limited to pages of a certain level of page table size.

[0104] Taking the target process as an example, when the target process accesses memory, it generates a memory request that indicates the target page size. This target page size may not be equal to the page size of any level of the page table, but it can also be equal to the page size of a certain level of the page. Taking the page table partition shown in Figure 1 as an example, the target page size can be greater than 4KB and less than 2MB, for example, the target page size is 32KB. Alternatively, the target page size can be greater than 2MB and less than 1GB, for example, the target page size is 6MB.

[0105] Step 401 may be specifically executed by an operating system (OS) in a processor, that is, the operating system obtains a memory request of a target process.

[0106] Step 402: In response to the memory request, N consecutive virtual page numbers and N consecutive physical page numbers are allocated to the target process, where N is not less than the number of memory pages required by the target process.

[0107] It should be understood that page table entries that can be merged need to meet the merging conditions, and not all page table entries can be merged. In an embodiment of the present application, the merging conditions include continuous virtual page numbers and continuous physical page numbers. Based on this, the processor responds to the memory request of the target process and allocates N consecutive virtual page numbers and N consecutive physical page numbers to the target process. Among them, N is not less than the number of memory pages required by the target process. The number of memory pages required by the target process is determined based on the target page size.

[0108] In one implementation, the processor first determines the value of N based on the target page size and the base page size. Based on the value of N, the processor then determines N consecutive physical page numbers from unused physical page numbers and N consecutive virtual page numbers from unused virtual address space. The processor then allocates the determined N physical page numbers and N virtual page numbers to the target process. The base page size is equal to the page size of the first-level page table.

[0109] The processor may divide the target page size by the base page size to obtain a quotient and a remainder, and determine the value of N based on the quotient or the quotient and remainder. If the remainder is 0, the quotient represents the number of memory pages required by the target process. If the remainder is not 0, the quotient plus 1 represents the number of memory pages required by the target process.

[0110] In one implementation, the value of N can be a positive integer without any additional restrictions. In this case, if the remainder is 0, the processor determines that the value of N is equal to the quotient. If the remainder is not 0, the processor determines the value of N as the value obtained by adding 1 to the quotient.

[0111] Taking a 4KB base page as an example, assuming the target page size is 36KB, the quotient of 36 divided by 4 is 9, with a remainder of 0, so the processor determines N = 9. Assuming the target page size is 37KB, the quotient of 37 divided by 4 is 9, with a remainder of 1, so the processor determines N = 10.

[0112] In another implementation, the value of N has an additional restriction, which is N=2 x , x is a positive integer. In this case, the processor will not be less than the quotient and the value is equal to 2 x The minimum number is determined as the value of N.

[0113] Still taking the base page as an example, assuming the target page size is 32KB, the quotient of 32 divided by 4 is 8, 8=2 3 , then the processor determines that N = 8. Assuming the target page size is 48KB, the quotient of 48 divided by 4 is 12, 16 = 2 4 Is the smallest 2 that is not less than 12 x , then the processor determines that N=16.

[0114] In another implementation, the value of N is additionally limited to N=2C, where C is a positive integer. In this case, the processor determines the minimum number that is not less than the quotient and satisfies the value equal to 2C as the value of N.

[0115] Still taking the base page as an example, assuming that the target page size is 44KB, the quotient of 44 divided by 4 is 11, and 12=2×6 is the smallest 2C that is not less than 11, so the processor determines N=12.

[0116] In addition to the above implementations, the value of N may also have other limitations, which are not limited in the embodiments of the present application.

[0117] The above additional restriction on N can be used as a sub-condition in the merge condition of the page table entry. That is, in addition to the first sub-condition above (i.e., continuous virtual page numbers and continuous physical page numbers), the merge condition also includes a second sub-condition. The second sub-condition is an additional restriction on N. For example, the second sub-condition is N=2 x , x is a positive integer, or, the second sub-condition is N=2C, C is a positive integer.

[0118] In the specific implementation, considering that if the read and write attributes of the pages are different, even if they are merged, the read and write performance of the process to the memory will be affected after the merger, therefore, the merging condition also includes the same read and write attributes of the pages (i.e., the third sub-condition), that is, each page has read and write attributes, and pages with the same read and write attributes can be merged. For example, the read and write attributes of the N basic pages corresponding to the above-mentioned N consecutive physical page numbers are the same, then these N basic pages can be merged into a larger page. Among them, the same read and write attributes, for example, are all read-only pages, or are all read-write pages.

[0119] Of course, the merge condition may also include other sub-conditions. For example, the merge condition also includes a fourth sub-condition, which is that both the base physical page number and the base virtual page number can be divided by N, the base physical page number is the smallest physical page number among the N physical page numbers to be merged, and the base virtual page number is the smallest virtual page number among the N virtual page numbers to be merged. The fourth sub-condition can be when N=2 x In the case of , the sub-conditions need to be satisfied. The principle of such design can be understood through the embodiments below. Of course, the fourth sub-condition does not need to be related to the value of N.

[0120] It should be noted that the second and fourth sub-conditions are optional, while the first and third sub-conditions are basic conditions that must be met to ensure the reliability and performance of the solution.

[0121] As can be seen from the above, the processor can determine the value of N based on the second sub-condition in the merge condition, the target page size and the base page size, for example, N = 2 x Then, the processor determines N consecutive physical page numbers from the unused physical page numbers based on the other sub-conditions in the merge condition, and determines N consecutive virtual page numbers based on the unused virtual address space.

[0122] For example, based on the first sub-condition in the merge condition, the processor determines at least one group of physical page numbers from unused physical page numbers, each group of physical page numbers including multiple physical page numbers with consecutive page numbers and a number not less than N. Based on the third sub-condition, the processor determines at least one group of candidate physical page numbers from the at least one group of physical page numbers, each group of candidate physical page numbers including multiple physical page numbers corresponding to pages with the same read and write attributes. Finally, based on the fourth sub-condition, the processor determines the final N physical page numbers from the at least one group of candidate physical page numbers, the smallest of the N physical page numbers ultimately determined being divisible by N. Similarly, based on the first sub-condition in the merge condition, the processor determines at least one group of virtual page numbers from an unused virtual address space, each group of virtual page numbers including multiple virtual page numbers with consecutive page numbers and a number not less than N. Based on the fourth sub-condition, the processor determines the final N virtual page numbers from the at least one group of virtual page numbers, the smallest of the N virtual page numbers ultimately determined being divisible by N.

[0123] It should be understood that the embodiments of the present application do not limit the order in which the multiple sub-conditions in the merge condition must be met. For example, the processor can screen and determine the final N physical page numbers and N virtual page numbers in the order of the second sub-condition, the first sub-condition, the third sub-condition, and the fourth sub-condition introduced above, or it can screen in the order of the first sub-condition, the third sub-condition, the second sub-condition, and the fourth sub-condition. Alternatively, in a certain round of screening, physical page numbers that meet two or even three sub-conditions can be screened out at the same time, as long as the physical page numbers and virtual page numbers that meet all the sub-conditions in the merge condition can be finally screened out.

[0124] Step 403: Based on the N physical page numbers and the N virtual page numbers, create N page table entries in the memory page table, where the N page table entries represent the mapping relationship between the N virtual page numbers and the N base pages, which are the N physical pages that correspond one-to-one to the N physical page numbers.

[0125] After determining the N physical page numbers and N virtual page numbers allocated to the target process, the processor creates N page table entries in the memory page table. These N page table entries represent the mapping relationship between N base pages. These N base pages are N physical pages that correspond one-to-one to these N physical page numbers.

[0126] Each of the N page table entries includes a virtual page number and a reference physical page number among the N virtual page numbers. In other words, the N page table entries record the N virtual page numbers and also record the same N reference physical page numbers.

[0127] Optionally, in order to facilitate the subsequent identification that these N page table entries are mergeable items, the processor also sets a tag bit in each page table entry, and uses the tag bit to indicate whether the corresponding page table entry is a mergeable item. Of course, the processor may also not set the tag bit, but instead determine whether the page table entry is a mergeable item by checking whether the physical page number in a page table entry is the same as the physical page number in any adjacent page table entry. If the physical page number in a page table entry is the same as the physical page number in any adjacent page table entry, it means that these identical physical page numbers are the same reference physical page numbers, and multiple adjacent page table entries with the same reference physical page number are all mergeable items. If the physical page number in a page table entry is different from the physical page number in the adjacent page table entry, it means that the physical page number in this page table entry is a real physical page number, not a reference physical page number, and this page table entry is not a mergeable item.

[0128] Next, we will introduce the implementation process of the processor generating the reference physical page number.

[0129] In one implementation, the processor determines the smallest physical page number among the N physical page numbers as the base physical page number, and generates a reference physical page number based on the base physical page number. The processor then creates N page table entries in the memory page table. Each of the N page table entries includes a virtual page number from the N virtual page numbers, the reference physical page number, and a tag bit. The tag bit in the N page table entries indicates that the N page table entries are all mergeable.

[0130] Among them, when N=2 x , x is a positive integer, and the basic physical page number is divisible by N. The implementation process of the processor generating the reference physical page number based on the basic physical page number is as follows: determining that the value of the x-th to last bit to the leftmost bit in the reference physical page number is equal to the value of the x-th to last bit to the leftmost bit in the basic physical page number, the values ​​of the 0th to x-2th to last bits are all the first value, and the value of the x-1th to last bit is the second value.

[0131] Taking the first value as 0 and the second value as 1 as an example, if the base physical page number is recorded as Base PPN and the reference physical page number is recorded as PPN', the processor can first set PPN' = Base PPN, and then set PPN'[x-2:0] = 0 and PPN'[x-1] = 1. It should be understood that in the embodiment of the present application, the base physical page number and the reference physical page number are both represented by binary numbers.

[0132] For example, Figure 5 is a schematic diagram of creating a mergeable page table entry in Example 1 provided by an embodiment of the present application. Referring to Figure 5, in Example 1, the mergeable page table entry includes 4 page table entries, that is, N=4=2 2, x=2, the four virtual page numbers included in these four page table entries are 0b00000100, 0b00000101, 0b00000110, and 0b00000111, and the corresponding four physical page numbers are 0b00001000, 0b00001001, 0b00001010, and 0b00001011. Before setting these N page table entries as mergeable entries, the value of the tag bit M in these N page table entries is 1, indicating that these N page table entries have not been set as mergeable entries. After setting these N page table entries as mergeable entries, the value of the tag bit M in these N page table entries is 0, indicating that these N page table entries have been set as mergeable entries, and the physical page numbers in these N page table entries are all modified to the same reference physical page number according to the above method, which is 0b00001010.

[0133] In addition to the implementation method for determining the reference physical page number described above, the processor can also generate the reference physical page number using other methods. As long as the base physical page number can be derived from the reference physical page number, and the actual physical page number can be derived from the base physical page number during the address translation process, it will be sufficient. In other words, regardless of the implementation method, as long as the processor can perform forward and reverse conversion between page numbers based on the corresponding rules, it will be sufficient.

[0134] In addition, in the implementation described above, when N=2 x , when both the basic physical page number and the basic virtual page number are divisible by N, if the value of the tag bit and the value of the 0th to x-2th bits from the bottom in the reference physical page number are both the first value, then the processor does not need to waste additional storage space to record the number of merged items N and / or the parameter value x. The value of x can be determined later by counting the number of bits of the first value in the low order of the first binary string. Knowing the value of x can determine the value of N. The first binary string refers to the binary string obtained by splicing the tag bit at the end of the reference physical page number. The specific implementation method will be introduced later.

[0135] Of course, the processor can also use additional storage space to record the number of merged items N and / or the parameter value x. This can not only make it more direct to obtain the parameter value x and / or the number of merged items N later, but also make the value of the tag bit and the determination of the reference physical page number more flexible and diverse.

[0136] The above steps 402 and 403 are also specifically executed by the OS in the processor, that is, the OS searches for N physical page numbers and N virtual page numbers that meet the merging conditions, and creates the above N page table entries in the memory page table.

[0137] Step 404: Merge the N page table entries into a first cache entry, and store the first cache entry in the page table cache.

[0138] After creating N page table entries, the processor can execute step 404 in the subsequent address translation process, thereby improving the subsequent TLB hit rate. Step 404 is specifically executed by the MMU in the processor.

[0139] Next, the specific implementation process of merging these N page table entries into the first cache table entry will be introduced.

[0140] As mentioned above, when a process accesses memory, it generates a virtual address. The processor must translate this virtual address into a real physical address through the MMU, and then access the physical memory space based on the real physical address. The virtual address includes a virtual page number, and the physical address includes a physical page number. The address translation process primarily determines the physical page number based on the virtual page number. Next, using the target process accessing memory as an example, we will describe how to merge the N page table entries described above when the target process accesses memory space.

[0141] The processor obtains a memory access request from a target process, the memory access request including a target virtual page number, which is one of the N virtual page numbers. The processor determines a target physical page number corresponding to the target virtual page number and merges the N page table entries into a first cache entry. The target physical page number is the actual physical page number.

[0142] In one implementation, each of the N page table entries includes a virtual page number among the N virtual page numbers, and the N page table entries also include the same reference physical page number, which is generated based on the base physical page number, and the base physical page number is the smallest physical page number among the N physical page numbers. In the process of determining the target physical page number corresponding to the target virtual page number, the processor searches the memory page table for the page table entry where the target virtual page number is located to obtain the first page table entry. If the first page table entry is a mergeable item, the processor determines the target parameter value based on the first page table entry, and the target parameter value indicates the value of N. Then, the processor generates a merged virtual page number based on the target parameter value and the target virtual page number, determines the base physical page number based on the reference physical page number in the first page table entry, and then generates a first cache table entry. The first cache table entry includes the merged virtual page number, the base physical page number and a tag bit, and the tag bit in the first cache table entry indicates that the first cache table entry is a merged item.

[0143] Wherein, when each of the N page table entries also includes a tag bit, the processor determines that the first page table entry is a mergeable entry based on the value of the tag bit in the first page table entry. Wherein, the tag bit in the first page table entry is a first value, indicating that the first page table entry is a mergeable entry. Of course, regardless of whether each page table entry includes a tag bit, the processor can determine whether the first page table entry is a mergeable entry by checking whether the physical page number in the first page table entry is the same as the physical page number in any adjacent page table entry.

[0144] If the N page table entries all include a tag bit with the first value, and the values ​​of the last 0th to x-2th bits in the reference physical page number are all the first value, and the value of the last x-1th bit is the second value, N=2 x , x is a positive integer, x represents the target parameter value, then, the processor determines the target parameter value based on the first page table entry in the following manner: starting from the rightmost bit of the first binary string and counting to the left, the number of bits whose value is the first value is counted until the first bit of the first binary string that is not the first value is counted from the right to the left, to obtain the target parameter value, where the first binary string refers to a binary string obtained by concatenating the tag bit at the end of the reference physical page number.

[0145] Taking the first value as 0 and the second value (i.e., non-first value) as 1 as an example, assuming that the target virtual page number is 0b00000110 in Figure 5, then the first page table entry is the third mergeable entry in Figure 5, the reference physical page number in the first page table entry is 0b00001010, the tag bit M=0, the first binary string is 0b000010100, and the number of bits with a value of 0 is counted from the rightmost bit of the first binary string to the left until the first bit with a value of 1 from the right is counted. A total of two bits with a value of 0 are counted, so the target parameter value is 2, that is, x=2 is determined through statistics.

[0146] Of course, the processor can also count the number of bits with the first value starting from the rightmost bit of the reference physical page number to the left until the first bit other than the first value is counted from the right to the left in the reference physical page number, and then add 1 to the total number of 0s counted to obtain the target parameter value.

[0147] After determining the target parameter value, the processor may generate a merged virtual page number based on the target parameter value and the target virtual page number.

[0148] In one implementation, the processor determines that the values ​​of the xth to last bits to the leftmost bit in the merged virtual page number are equal to the values ​​of the xth to last bits to the leftmost bit in the target virtual page number, the values ​​of the 0th to x-2th to last bits are all the first value, and the value of the x-1th to last bit is the second value.

[0149] Still taking the first value as 0 and the second value as 1 as an example, if the target parameter value is recorded as x, the target virtual page number is recorded as Requested VPN, and the merged virtual page number is recorded as VPN', the processor can first set VPN'=Requested VPN, and then set VPN'[x-2:0]=0 and VPN'[x-1]=1.

[0150] For example, assuming that the target virtual page number is 0b00000110 in FIG. 5 , the virtual page number after merging is determined to be 0b00000110 according to the above method.

[0151] After determining the target parameter value, the processor can also determine a base physical page number based on the target parameter value and the reference physical page number. In one implementation, the processor determines that the value of the xth to the leftmost bit in the base physical page number is equal to the value of the xth to the leftmost bit in the reference physical page number, and that the values ​​of the 0th to x-1th to the last bits are both the first value, where x is equal to the target parameter value.

[0152] It should be understood that the implementation process of the processor determining the reference physical page number based on the basic physical page number in the process of creating the above-mentioned N mergeable page table entries matches, or is symmetrical to, or is inverse to, the implementation process of determining the basic physical page number based on the reference physical page number in the process of merging these N page table entries.

[0153] As can be seen above, the process of merging page table entries is performed during the address translation process. Therefore, after determining the base physical page number based on the reference physical page number in the first page table entry, the processor also determines the base virtual page number based on the target parameter value and the target virtual page number. The base virtual page number is the smallest virtual page number among the N virtual page numbers. The processor then determines the target physical page number based on the base physical page number, the target virtual page number, and the base virtual page number. The target physical page number is the actual physical page number obtained by translation.

[0154] When N=2 x , x is a positive integer, and the base virtual page number is divisible by N. The processor determines the implementation process of the base virtual page number based on the target parameter value and the target virtual page number as follows: determine that the value of the x-th last bit to the leftmost bit in the base virtual page number is equal to the value of the x-th last bit to the leftmost bit in the target virtual page number, and the values ​​of the 0th to x-1th last bits are all the first value, and x is equal to the target parameter value.

[0155] Still taking the first value as 0 and the second value as 1 as an example, if the target parameter value is recorded as x, the target virtual page number is recorded as Requested VPN, and the basic virtual page number is recorded as Base VPN, the processor can first set Base VPN = Requested VPN, and then set Base VPN[x-1:0] = 0.

[0156] After determining the base physical page number and the base virtual page number, the processor can determine the target physical page number based on the base physical page number, the target virtual page number, and the base virtual page number. Specifically, the processor determines the difference between the target virtual page number and the base virtual page number, and determines the sum of the difference and the base physical page number as the target physical page number.

[0157] For example, if the target physical page number is recorded as Real PPN, Real PPN=Base PPN+(Requested VPN-Base VPN).

[0158] The preceding article describes how the processor merges N page table entries into a first cache entry during address translation and determines the target physical page number. After obtaining the first cache entry, the processor stores it in the page table buffer (TLB), thereby improving the TLB hit rate during subsequent address translations.

[0159] As explained above, before searching the memory page table for the target virtual page number's page table entry, the processor first queries the page table cache based on the target virtual page number to determine if the target virtual page number has a hit in the page table cache. If the target virtual page number does not have a hit in the page table cache, the processor then searches the memory page table for the target virtual page number's page table entry.

[0160] Based on this, step 404 may be executed during the first translation of the target virtual address, i.e., the first cache entry has never been stored in the TLB. Alternatively, the first cache entry may have been stored in the TLB, but was deleted from the TLB due to low page heat or other reasons. In other words, the first cache entry is no longer included in the TLB during the current translation of the target virtual address. In this case, the processor may also be triggered to execute step 404.

[0161] Next, the complete process of address translation will be introduced.

[0162] After the processor obtains the memory access request of the target process, it first queries the page table entry where the target virtual page number is located from the page table cache. If the page table entry where the target virtual page number is located is not found from the page table cache, the processor determines multiple candidate virtual page numbers based on the merge threshold and the target virtual page number, and the merge threshold indicates the maximum number of page table entries that can be merged at one time. The processor queries the page table cache whether there is a page table entry corresponding to the first candidate virtual page number, and the first candidate virtual page number is any candidate virtual page number among the multiple candidate virtual page numbers. If the page table entry corresponding to the first candidate virtual page number does not exist in the page table cache, the processor determines that the target virtual page number does not hit the page table cache. Afterwards, the processor executes the above steps of searching the memory page table for the page table entry where the target virtual page number is located.

[0163] In one implementation, the processor determines the implementation process of multiple candidate virtual page numbers based on the merge threshold and the target virtual page number as follows: determine that the value of the jth to last bit to the leftmost bit of the jth candidate virtual page number included in the multiple candidate virtual page numbers is equal to the value of the jth to last bit to the leftmost bit of the target virtual page number, j∈[1,X], X represents the merge threshold; when j>1, determine that the values ​​of the 0th to j-2th last bits of the jth candidate virtual page number are all the first value, and the value of the j-1th to last bit is the second value; when j=1, determine that the value of the j-1th to last bit of the jth candidate virtual page number is the second value.

[0164] For example, taking the first value as 0 and the second value as 1, assuming the target virtual page number is 0b00000110 (ie 0b110) in FIG5, the merge threshold X=8, indicating that the maximum number of items that can be merged at one time is 2 8 =512. According to the above implementation, the processor can determine eight candidate virtual page numbers: 0b111, 0b110, 0b100, 0b1000, 0b10000, 0b1000000, 0b10000000. These eight candidate virtual page numbers correspond one-to-one to the eight values ​​of j, and these eight values ​​can be regarded as eight parameter values.

[0165] It should be understood that during the address translation process, if a merged cache entry is stored in the TLB, since the virtual page number in the cache entry is the merged virtual page number, and the processor does not know the number of merged entries corresponding to the cache entry, the processor needs to first generate candidate virtual page numbers corresponding to any possible number of merged entries based on the merge threshold, thereby obtaining multiple candidate virtual page numbers, and then query the TLB to see if a candidate virtual page number can be hit. The multiple values ​​of j above indicate multiple possible numbers of merged entries.

[0166] The specific implementation method for determining the candidate virtual page number described above is consistent with the specific implementation method for determining the merged virtual page number described above. For example, the merged virtual page number is determined by first setting VPN' = Requested VPN, then setting VPN'[x-2:0] = 0 and VPN'[x-1] = 1. Therefore, the candidate virtual page number is also determined by first setting Possible VPN' = Requested VPN, then setting Possible VPN'[j-2:0] = 0 and Possible VPN'[j-1] = 1. Where Possible VPN' represents the candidate virtual page number.

[0167] As can be seen from the above, each of the multiple candidate virtual page numbers corresponds to a parameter value, and the parameter value corresponding to each candidate virtual page number indicates the number of merged items corresponding to the corresponding candidate virtual page number. Based on this, after the processor queries the page table cache whether there is a page table entry corresponding to the first candidate virtual page number, if there is a page table entry corresponding to the first candidate virtual page number in the page table cache, indicating a TLB hit, the processor determines the parameter value corresponding to the first candidate virtual page number as the target parameter value. Then, the processor determines the base virtual page number based on the target parameter value and the target virtual page number, and the base virtual page number is the smallest virtual page number among the above N virtual page numbers. The processor determines the target physical page number based on the base physical page number, the target virtual page number and the base virtual page number, that is, translates the real physical page number. For the specific implementation method, please refer to the relevant introduction above, which will not be repeated here.

[0168] The embodiments of this application provide a pseudocode example of a processor performing address translation according to this solution, as shown below. In this pseudocode, VPN represents the target virtual page number to be translated, Entries represents entries in the TLB, and each entry includes a virtual page number and a tag bit M. VPN_p represents the candidate virtual page number, X represents the merge threshold, VPN_base represents the base virtual page number, PPN_base represents the base physical page number, and PPN represents the target physical page number to be translated.

[0169] From the above examples, it can be seen that when N=2 x, when the basic physical page number and the basic virtual page number are divisible by N, by first setting PPN'=Base PPN and then setting PPN'[x-2:0]=0 and PPN'[x-1]=1, setting M=0 to indicate a mergeable item, M=1 to indicate a non-mergeable item, first setting VPN'=Requested VPN and then setting VPN'[x-2:0]=0 and VPN'[x-1]=1, first setting Base VPN=Requested VPN and then setting Base VPN[x-1:0]=0, and so on, a series of operations can be performed, which not only does not increase the storage space required for the page table entry, but also reduces the difficulty of merging the page table entries and the difficulty of subsequently deriving the real physical page number.

[0170] The above introduces the implementation process of the processor to create large pages from the source. Optionally, in a specific implementation, the processor can also scan the memory page table to find mergeable page table entries (i.e., meet the merge conditions), set the mergeable page table entries as mergeable entries, and then in the subsequent process of address translation of the virtual page number in any page table entry set as the mergeable entry, merge these page table entries into a third cache table entry, and store the third cache table entry in the page table cache.

[0171] Among them, the processor can scan the memory page table periodically through the OS, or scan the memory page table under event triggering. The processor can set the scanned mergeable page table entry as a mergeable item in a manner consistent with the principle of generating N page table entries above. For example, the processor modifies the tag bit in the mergeable page table entry from the second value to the first value, and modifies the physical page numbers in the mergeable page table entry to the same reference physical page number. Among them, the tag bit is the second value, indicating that the corresponding page table entry is not set as a mergeable item, and the tag bit is the first value, indicating that the corresponding page table entry is set as a mergeable item. The specific implementation method is similar to the implementation method of generating N page table entries above, and will not be repeated here.

[0172] It's worth noting that compared to the processor passively scanning the memory page table to discover mergeable page table entries, the processor proactively creates huge pages for processes at the source, resulting in more merged table entries and significantly improving the TLB hit rate. Simply put, proactively creating huge pages is more effective than passively discovering mergeable pages.

[0173] In addition, the embodiment of the present application also provides a method for updating the merged cache entries, which will be introduced below.

[0174] Taking the N page table entries as an example, if a page table entry among the N page table entries is changed, the processor deletes the first cache entry in the page table cache based on the changed page table entry and determines whether there are M page table entries that can be merged among the N page table entries, where M is a positive integer greater than 2 and less than N. If it is determined that there are M page table entries that can be merged among the N page table entries, the processor merges the M page table entries into a second cache entry and stores the second cache entry in the page table cache.

[0175] Among them, when a virtual page number among the above-mentioned N virtual page numbers is swapped out, or in other possible situations, it will cause a page table entry in the above-mentioned N page table entries to be changed. In this case, the above-mentioned N page table entries no longer meet the merging conditions, and the merged large page needs to be decomposed. Therefore, the processor needs to delete the first cache table entry in the page table cache, delete the page table entry where the swapped-out virtual page number is located among the N page table entries, and set the remaining page table entries among the N page table entries to non-mergeable entries, such as changing the tag bit in the remaining page table entries from the first value to the second value.

[0176] Optionally, the processor may further determine, based on the merging condition, whether there are M mergable page table entries among the remaining page table entries. If there are M mergable page table entries among the remaining page table entries, the processor merges the M page table entries into a second cache entry according to the specific implementation described above, and stores the second cache entry in the page table cache.

[0177] Optionally, the processor further stores all the remaining page table entries except the M page table entries in the page table cache, and these page table entries are all non-mergeable page table entries.

[0178] Next, please explain this solution with examples 1 to 3.

[0179] Example 1: Take the 4KB minimum page, the third-level page table, and the merging of four pages as an example. Please refer to Figures 5 to 8 for understanding.

[0180] Referring to Figure 5, the OS creates or discovers four pages that can be merged by scanning the memory page table, and sets the four page table entries corresponding to these four pages as mergeable entries. Among them, these four page table entries meet the merge conditions, and the merge conditions include the first to fourth sub-conditions mentioned above. The four virtual page numbers included in these four page table entries are 0b00000100, 0b00000101, 0b00000110, and 0b00000111, and the corresponding four physical page numbers are 0b00001000, 0b00001001, 0b00001010, and 0b00001011. Before setting these four page table entries as mergeable entries, the value of the tag bit M in these four page table entries is 1, indicating that these four page table entries have not yet been set as mergeable entries. After setting these four page table entries as mergeable entries, the value of the tag bit M in these four page table entries is 0, indicating that these four page table entries have been set as mergeable entries, and the physical page numbers in these four page table entries are all modified to the same reference physical page number, which is 0b00001010. In addition, 0b00000100 of these four virtual page numbers is the base virtual page number, and 0b00001000 of these four physical page numbers is the base physical page number.

[0181] Referring to Figure 6, taking the target virtual page number Requested VPN (Req_VPN) = 0b110 as an example, the MMU first queries the TLB and determines a TLB miss (neither the target virtual page number nor the candidate virtual page number hits. The specific implementation process is described above and will not be repeated here). Then, based on the Requested VPN, the MMU queries the corresponding page table entry from the memory page table. Since the tag bit M in this page table entry is 0, indicating that the page table entry is a mergeable entry, the MMU determines the target parameter value x = 2 by counting the number of 0 bits (see above for the specific implementation method). Based on x and the reference physical page number PPN' in the page table entry, the base physical page number Base PPN = 0b1000 is derived. Based on x and the Requested VPN, the base virtual page number Base VPN = 0b100 is derived. The MMU then derives the target physical page number Real PPN = Base PPN + (Requested VPN - Base VPN) = 0b1000 + (0b110 - 0b100) = 0b1010. In FIG6 , TLBE represents a TLB entry.

[0182] After deriving the basic physical page number, the MMU also determines the merged virtual page number VPN'=0b00000110 based on the basic virtual page number and x, and stores the first cache table entry in the page table cache. The first cache table entry includes the merged virtual page number, the basic physical page number and the tag bit. The value of the tag bit in the first cache table entry is 0, indicating that the first cache table entry is a merged entry.

[0183] Referring to Figure 7 , during the subsequent address translation process, still taking the target virtual page number Requested VPN = 0b110 as an example, the MMU first queries the TLB for the cache entry containing the Requested VPN and determines that the TLB misses the Requested VPN. Then, based on the Requested VPN and the merge threshold (X = 8), the MMU generates eight candidate virtual page numbers: possibleVPN' = [0b111, 0b110, 0b100, 0b10000, 0b100000, 0b1000000, 0b10000000]. The MMU queries each candidate virtual page number in turn, ultimately finding the first cache entry in the TLB containing the candidate virtual page number 0b110.

[0184] Referring to Figure 8, when the virtual page number 0b101 is swapped out, the OS needs to decompose the large page corresponding to the first cache table entry. Specifically, the OS deletes the first cache table entry, modifies the tag bits of the corresponding four page table entries in the memory page table to 1, and deletes the page table entry where the virtual page number 0b101 is located. The OS finds that the two page table entries where the virtual page numbers 0b110 and 0b111 are located can still be merged, so the OS merges the two page table entries in the above manner. Specifically, the OS modifies the tag bits in the two page table entries in the memory page table to 0, and modifies the physical page numbers in the two page table entries to the reference physical page number 0b1011, and redetermines the basic physical page number and the merged virtual page number corresponding to the two page table entries. The OS inserts the second cache table entry and the fourth cache table entry into the TLB. The second cache entry is a cache entry obtained by merging the two page table entries. The second cache entry stores the correspondence between the newly determined merged virtual page number 0b00000111 and the underlying physical page number 0b00001010. The tag bit in the second cache entry is 0. The fourth cache entry is the page table entry other than the two page table entries among the four page table entries that can no longer be merged. The fourth cache entry stores the correspondence between the virtual page number 0b00000100 and the physical page number 0b00001000. The tag bit in the fourth cache entry is 1.

[0185] Example 2: Take the 4KB minimum page, the second-level page table, and the merging of two pages as an example. Please refer to Figures 9 to 12 for understanding.

[0186] Referring to Figure 9, the OS creates or discovers two mergeable pages by scanning the memory page table, and sets the two page table entries corresponding to these two pages as mergeable entries. Among them, these two page table entries meet the merge conditions, and the merge conditions include the first to fourth sub-conditions mentioned above. The two virtual page numbers included in these two page table entries are 0b00000100 and 0b00000101, and the corresponding two physical page numbers are 0b00001000 and 0b00001001. Before setting these two page table entries as mergeable entries, the value of the tag bit M in these two page table entries is 1, indicating that these two page table entries have not yet been set as mergeable entries. After setting these two page table entries as mergeable entries, the value of the tag bit M in these two page table entries is 0, indicating that these two page table entries have been set as mergeable entries, and the physical page numbers in these two page table entries are both modified to the same reference physical page number, which is 0b00001001. In addition, 0b00000100 of these two virtual page numbers is the base virtual page number, and 0b00001000 of these two physical page numbers is the base physical page number.

[0187] Referring to Figure 10 , taking the target virtual page number Requested VPN = 0b101 as an example, the MMU first queries the TLB and determines a TLB miss (neither the target virtual page number nor the candidate virtual page number hits. The specific implementation process is described above and will not be repeated here). The MMU then queries the corresponding page table entry from the memory page table based on the Requested VPN. Since the tag bit M in this page table entry is 0, indicating that the page table entry is a mergeable entry, the MMU determines the target parameter value x = 1 by counting the number of 0 bits (see above for the specific implementation method). Based on x and the reference physical page number PPN' in the page table entry, the MMU derives the base physical page number Base PPN = 0b1000. Based on x and the Requested VPN, the MMU derives the base virtual page number Base VPN = 0b100. The MMU then derives the target physical page number Real PPN = Base PPN + (Requested VPN - Base VPN) = 0b1000 + (0b101 - 0b100) = 0b1001.

[0188] After deriving the basic physical page number, the MMU also determines the merged virtual page number VPN'=0b00000101 based on the basic virtual page number and x, and stores the first cache table entry in the page table cache. The first cache table entry includes the merged virtual page number, the basic physical page number and the tag bit. The value of the tag bit in the first cache table entry is 0, indicating that the first cache table entry is a merged entry.

[0189] Referring to Figure 11 , during the subsequent address translation process, taking Requested VPN = 0b100 as an example, the MMU first queries the TLB for the cache entry containing the Requested VPN and determines that the TLB misses the Requested VPN. Then, based on the Requested VPN and the merge threshold (X = 8), the MMU generates eight candidate virtual page numbers: possibleVPN' = [0b101, 0b110, 0b100, 0b10000, 0b100000, 0b1000000, 0b10000000]. The MMU queries each candidate virtual page number in turn, ultimately finding the first cache entry in the TLB containing the candidate virtual page number 0b101.

[0190] Referring to Figure 12, when the virtual page number 0b101 is swapped out, the OS needs to decompose the large page corresponding to the first cache table entry. Specifically, the OS deletes the first cache table entry, modifies the tag bits of the corresponding two page table entries in the memory page table to 1, and deletes the page table entry where the virtual page number 0b101 is located. The OS finds that the remaining page table entry cannot be merged further, then determines the real physical page number 0b1001 corresponding to the virtual page number in this page table entry based on the remaining page table entry, and caches the fourth cache table entry in the TLB. The fourth cache table entry stores the correspondence between the virtual page number 0b00000100 and the physical page number 0b00001001, and the tag bit in the fourth cache table entry is 1.

[0191] Example 3: Take the smallest page of 16KB, the third-level page table, and the merging of 8 pages as an example. Please refer to Figures 13 to 16 for understanding.

[0192] Referring to Figure 13, the OS creates or discovers eight pages that can be merged by scanning the memory page table, and sets the eight page table entries corresponding to these eight pages as mergeable entries. These eight page table entries meet the merge conditions, which include the first to fourth sub-conditions mentioned above. The 8 virtual page numbers included in these 8 page table entries are 0b00010000, 0b000010001, 0b00010010, 0b00010011, 0b00010100, 0b000010101, 0b00010110, 0b00010111, and the corresponding 8 physical page numbers are 0b00001000, 0b00001001, 0b00001010, 0b00001011, 0b00001100, 0b00001101, 0b00001110, 0b00001111. Before setting these 8 page table entries as mergeable items, the value of the tag bit M in these 8 page table entries is 1, indicating that these 8 page table entries have not yet been set as mergeable items. After setting these eight page table entries as mergeable entries, the value of the tag bit M in these eight page table entries is 0, indicating that these eight page table entries have been set as mergeable entries, and the physical page numbers in these eight page table entries are all modified to the same reference physical page number, which is 0b00001100. In addition, 0b00010000 of these eight virtual page numbers is the base virtual page number, and 0b00001000 of these eight physical page numbers is the base physical page number.

[0193] Referring to FIG14 , taking the target virtual page number Requested VPN = 0b10101 as an example, the MMU first queries the TLB and determines that the TLB misses (both the target virtual page number and the candidate virtual page number miss. The specific implementation process is described above and will not be repeated here). Then, the MMU queries the corresponding page table entry from the memory page table based on Requested VPN. Since the tag bit M in the page table entry is 0, it indicates that the page table entry is a mergeable entry. Therefore, the MMU determines the target parameter value x = 3 by counting the number of 0 bits (see above for the specific implementation method), and derives the base physical page number Base PPN = 0b1000 based on x and the reference physical page number PPN' in the page table entry. Based on x and Requested VPN, the MMU derives the base virtual page number Base VPN = 0b10000. Then, the MMU derives the target physical page number Real PPN=Base PPN+(Requested VPN-Base VPN)=0b1000+(0b10101-0b10000)=0b1101.

[0194] After deriving the basic physical page number, the MMU also determines the merged virtual page number VPN'=0b00010100 based on the basic virtual page number and x, and stores the first cache table entry in the page table cache. The first cache table entry includes the merged virtual page number, the basic physical page number and the tag bit. The value of the tag bit in the first cache table entry is 0, indicating that the first cache table entry is a merged entry.

[0195] Referring to Figure 15 , during the subsequent address translation process, taking Requested VPN = 0b10010 as an example, the MMU first searches the TLB for the cache entry containing Requested VPN and determines that the TLB misses Requested VPN. Then, based on Requested VPN and the merge threshold (X = 10), the MMU generates 10 candidate virtual page numbers: possibleVPN' = [0b10001, 0b10010, 0b10100, 0b11000, 0b10000, 0b1000000, 0b10000000, 0b100000000, 0b1000000000]. The MMU searches each candidate virtual page number in turn and ultimately finds the first cache entry in the TLB containing candidate virtual page number 0b10100.

[0196] Referring to Figure 16, when the virtual page number 0b10010 is swapped out, the OS needs to decompose the large page corresponding to the first cache table entry. Specifically, the OS deletes the first cache table entry, modifies the tag bits of the corresponding 8 page table entries in the memory page table to 1, and deletes the page table entry where the virtual page number 0b10010 is located. The OS finds that the two page table entries where the virtual page numbers 0b10000 and 0b10001 are located can still be merged, so the OS merges these two page table entries in the above manner, and the four page table entries where the virtual page numbers 0b00010100, 0b000010101, 0b00010110, and 0b00010111 are located can also be merged, so the OS also merges these two page table entries in the above manner.

[0197] Specifically, for the two page table entries that can still be merged, the OS modifies the tag bits in the two page table entries in the memory page table to 0, and modifies the physical page numbers in the two page table entries to the reference physical page number 0b1001, and redetermines the basic physical page numbers and merged virtual page numbers corresponding to the two page table entries. The OS inserts a second cache table entry and a fourth cache table entry into the TLB. The second cache table entry is the cache table entry obtained by merging the two page table entries. The second cache table entry stores the correspondence between the redetermined merged virtual page number 0b00010001 and the basic physical page number 0b00001000, and the tag bit in the second cache table entry is 0. The fourth cache table entry is the page table entry that can no longer be merged among the eight page table entries. The fourth cache table entry stores the correspondence between the virtual page number 0b00010011 and the physical page number 0b00001011, and the tag bit in the fourth cache table entry is 1.

[0198] For the four page table entries that can still be merged, the OS modifies the tag bits in the four page table entries in the memory page table to 0, and modifies the physical page numbers in the four page table entries to the reference physical page number 0b1110, and redetermines the basic physical page numbers and merged virtual page numbers corresponding to the four page table entries. The OS inserts a second cache table entry into the TLB. The second cache table entry is the cache table entry obtained by merging the above four page table entries. The second cache table entry stores the correspondence between the redetermined merged virtual page number 0b00010110 and the basic physical page number 0b00001100, and the tag bit in the second cache table entry is 0.

[0199] In summary, in the embodiments of the present application, a process can request a memory page of a certain size on demand. The size of the requested memory page is not limited to the page size of any first-level page table. Accordingly, the computing device can create a memory page of the corresponding size for the process by merging page table entries based on the process's request, and store the merged cache entry in the TLB. In other words, by merging page table entries, a larger memory page is proactively created for the process from the source, allowing a single TLB cache entry to cover multiple page table entries in the memory page table, thereby improving the TLB hit rate, reducing PTW, and lowering memory access latency and memory access overhead.

[0200] In the specific implementation, the process can request a memory page of more flexible size from the OS through the newly added programming interface. The OS creates large memory pages from the source, specifically marking the mergeable page table entries when creating page table entries. In this way, the MMU only needs to merge the page table entries according to the tag bits during the address translation process. The operation of the MMU is relatively simple, that is, the computing power requirements of the hardware are relatively low. This solution also specifically designs the merging conditions of the page table entries and the page table conversion method of VPN and PPN, so that the MMU and OS can deduce the merged page size and the basic physical page number, thereby obtaining the basic pages that make up the large page. In addition, the OS can also decompose the large page according to the changes in PTE, and automatically insert the re-merged cache table entries in the TLB.

[0201] FIG17 is a schematic diagram of the structure of a memory page table cache device 1700 provided in an embodiment of the present application. The device 1700 can be implemented by software, hardware, or a combination of both to form part or all of a computing device, such as the computing device shown in FIG2 . For example, the device can form part or all of a processor, such as the processor shown in FIG3 . Referring to FIG17 , the device includes: an acquisition module 1701, an allocation module 1702, a page table entry creation module 1703, and a page table entry merging module 1704.

[0202] An acquisition module 1701 is configured to acquire a memory request of a target process, where the memory request indicates a target page size, where the target page size is larger than a page size of a first-level page table and smaller than a page size of a second-level page table, where the first-level page table and the second-level page table are two consecutive levels of page tables.

[0203] an allocation module 1702 for allocating N consecutive virtual page numbers and N consecutive physical page numbers to a target process in response to a memory request, where N is not less than the number of memory pages required by the target process;

[0204] A page table entry creation module 1703 is configured to create N page table entries in a memory page table based on the N physical page numbers and the N virtual page numbers. The N page table entries represent a mapping relationship between the N virtual page numbers and N base pages. The N base pages are N physical pages that correspond one-to-one to the N physical page numbers. The size of the base pages is equal to the page size of the first-level page table.

[0205] The page table entry merging module 1704 is configured to merge the N page table entries into a first cache entry and store the first cache entry in the page table cache.

[0206] Optionally, the allocation module 1702 includes:

[0207] A first determination submodule is used to determine the value of N based on the target page size and the base page size;

[0208] A second determining submodule is configured to determine N consecutive physical page numbers from unused physical page numbers based on the value of N, and to determine N consecutive virtual page numbers based on the unused virtual address space;

[0209] The allocation submodule is used to allocate the determined N physical page numbers and N virtual page numbers to the target process.

[0210] Optionally, the page table entry creation module 1703 includes:

[0211] A third determining submodule is configured to determine the smallest physical page number among the N physical page numbers as the basic physical page number;

[0212] A generation submodule, for generating a reference physical page number based on the basic physical page number;

[0213] A submodule is created to create the N page table entries in the memory page table, each of the N page table entries including a virtual page number among the N virtual page numbers, a reference physical page number and a tag bit, wherein the tag bit indicates that the corresponding page table entry is a mergeable item.

[0214] Optionally, N=2 x , x is a positive integer, and the basic physical page number is divisible by N;

[0215] Generate submodules specifically for:

[0216] Determine that the values ​​of the xth to the leftmost bit in the reference physical page number are equal to the values ​​of the xth to the leftmost bit in the base physical page number, the values ​​of the 0th to x-2th last bits are all the first value, and the value of the x-1th to last bit is the second value.

[0217] Optionally, the page table entry merging module 1704 includes:

[0218] An acquisition submodule is used to obtain a memory access request of a target process, where the memory access request includes a target virtual page number, where the target virtual page number is one of the N virtual page numbers;

[0219] The merging submodule is configured to merge the N page table entries into a first cache table entry in the process of determining the target physical page number corresponding to the target virtual page number.

[0220] Optionally, each of the N page table entries includes one virtual page number among the N virtual page numbers, and the N page table entries also include the same reference physical page number, where the reference physical page number is generated based on a base physical page number, and the base physical page number is the smallest physical page number among the N physical page numbers;

[0221] The merge submodule is specifically used for:

[0222] In the process of determining the target physical page number corresponding to the target virtual page number, searching the memory page table for a page table entry where the target virtual page number is located to obtain a first page table entry;

[0223] If the first page table entry is a mergeable entry, determining a target parameter value based on the first page table entry, where the target parameter value indicates a value of N;

[0224] generating a merged virtual page number based on the target parameter value and the target virtual page number, and determining a base physical page number based on the reference physical page number in the first page table entry;

[0225] A first cache entry is generated, where the first cache entry includes a merged virtual page number, a basic physical page number, and a tag bit, and the tag bit in the first cache entry indicates that the first cache entry is a merged entry.

[0226] Optionally, each of the N page table entries further includes a tag bit whose value is the first value, and the value of the penultimate x-1 bit in the reference physical page number is the second value, and the values ​​of the penultimate 0th to x-2th bits are all the first value, N=2 x , x is a positive integer, x represents the target parameter value;

[0227] The merge submodule is specifically used for:

[0228] The target parameter value is obtained by counting the number of bits with the first value from the rightmost bit of the first binary string to the left until the first bit of the first binary string that is not the first value is counted from the right to the left. The first binary string refers to the binary string obtained by concatenating the tag bit at the end of the reference physical page number.

[0229] Optionally, the merge submodule is specifically used to:

[0230] Determine that the value of the xth to the leftmost bit in the merged virtual page number is equal to the value of the xth to the leftmost bit in the target virtual page number, the values ​​of the 0th to x-2th to the last bits are all the first value, and the value of the x-1th to the last bit is the second value;

[0231] Determining a base physical page number based on a reference physical page number in the first page table entry includes:

[0232] It is determined that the values ​​of the xth to leftmost bits in the base physical page number are equal to the values ​​of the xth to leftmost bits in the reference physical page number, and the values ​​of the 0th to x-1th bits in the last are all the first value.

[0233] Optionally, the merging submodule is further specifically used for:

[0234] After determining the base physical page number based on the reference physical page number in the first page table entry, determining the base virtual page number based on the target parameter value and the target virtual page number, the base virtual page number being the smallest virtual page number among the N virtual page numbers;

[0235] Based on the base physical page number, the target virtual page number, and the base virtual page number, a target physical page number is determined.

[0236] Optionally, the merging submodule is further specifically used for:

[0237] Before searching the page table entry where the target virtual page number is located from the memory page table, querying the page table cache based on the target virtual page number to determine whether the target virtual page number hits the page table cache;

[0238] If the target virtual page number does not hit the page table cache, the step of searching the memory page table for the page table entry where the target virtual page number is located is performed.

[0239] Optionally, the merge submodule is specifically used to:

[0240] Query the page table entry where the target virtual page number is located from the page table cache;

[0241] If the page table entry where the target virtual page number is located is not found from the page table cache, multiple candidate virtual page numbers are determined based on a merge threshold and the target virtual page number, where the merge threshold indicates the maximum number of page table entries that can be merged at one time;

[0242] querying whether there is a page table entry corresponding to a first candidate virtual page number in a page table cache, where the first candidate virtual page number is any one of the multiple candidate virtual page numbers;

[0243] If the page table entry corresponding to the first candidate virtual page number does not exist in the page table cache, it is determined that the target virtual page number does not hit the page table cache.

[0244] Optionally, the merge submodule is specifically used to:

[0245] Determine that a value from the jth to the leftmost bit of a j-th candidate virtual page number included in the multiple candidate virtual page numbers is equal to a value from the jth to the leftmost bit of the target virtual page number, j∈[1,X], where X represents a merge threshold;

[0246] When j>1, it is determined that the values ​​of the 0th to j-2th last bits in the jth candidate virtual page number are all the first value, and the value of the j-1th last bit is the second value;

[0247] When j=1, the value of the j-1th last bit in the jth candidate virtual page number is determined to be the second value.

[0248] Optionally, each candidate virtual page number among the multiple candidate virtual page numbers corresponds to a parameter value, and the parameter value corresponding to each candidate virtual page number indicates the number of merge items corresponding to the corresponding candidate virtual page number;

[0249] The merge submodule is also specifically used for:

[0250] After querying whether there is a page table entry corresponding to the first candidate virtual page number in the page table cache, if there is a page table entry corresponding to the first candidate virtual page number in the page table cache, determining the parameter value corresponding to the first candidate virtual page number as the target parameter value;

[0251] Determine a base virtual page number based on the target parameter value and the target virtual page number, where the base virtual page number is the smallest virtual page number among the N virtual page numbers.

[0252] Based on the base physical page number, the target virtual page number, and the base virtual page number, a target physical page number is determined.

[0253] Optionally, N=2 x , x is a positive integer, and the basic virtual page number is divisible by N;

[0254] The merge submodule is specifically used for:

[0255] Determine that the values ​​of the xth to leftmost bits in the base virtual page number are equal to the values ​​of the xth to leftmost bits in the target virtual page number, and the values ​​of the 0th to x-1th bits from the bottom are all first values, and x is equal to the target parameter value.

[0256] Optionally, the merge submodule is specifically used to:

[0257] Determine the difference between the target virtual page number and the base virtual page number;

[0258] The sum of the difference value and the base physical page number is determined as the target physical page number.

[0259] Optionally, the first value is 0 and the second value is 1.

[0260] Optionally, the apparatus 1700 further includes:

[0261] a cache entry deletion module, configured to, if a changed page table entry exists among the N page table entries, delete the first cache entry in the page table cache based on the changed page table entry, and determine whether there are M page table entries that can be merged among the N page table entries, where M is a positive integer greater than 2 and less than N;

[0262] The cache table entry changing module is configured to merge the M page table entries into a second cache table entry if it is determined that there are still M page table entries that can be merged in the N page table entries, and store the second cache table entry in the page table cache.

[0263] Optionally, the read and write attributes of the N basic pages are the same.

[0264] In an embodiment of the present application, a process can request a memory page of a certain size on demand. The size of the requested memory page is not limited to the page size of any level-one page table. Accordingly, the computing device can create a memory page of the corresponding size for the process by merging page table entries based on the process's request, and store the merged cache entry in the TLB. In other words, by merging page table entries, a larger memory page is proactively created for the process from the source, allowing a single TLB cache entry to cover multiple page table entries in the memory page table, thereby improving the TLB hit rate, reducing PTW, and lowering memory access latency and memory access overhead.

[0265] It should be noted that the memory page table caching device provided in the above embodiment only uses the division of the above functional modules as an example to illustrate when caching the memory page table. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the memory page table caching device provided in the above embodiment and the memory page table caching method embodiment are based on the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0266] In the above embodiments, all or part of the embodiments can be implemented by software, hardware, firmware, or any combination thereof. When implemented using software, all or part of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of the present application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via a wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) method. The computer-readable storage medium can be any available medium that can be accessed by a computer, or a data storage device such as a server or data center that includes one or more available media integrated therein. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, or a magnetic tape), an optical medium (e.g., a digital versatile disc (DVD)), or a semiconductor medium (e.g., a solid state disk (SSD)). It is worth noting that the computer-readable storage medium mentioned in the embodiments of the present application may be a non-volatile storage medium, in other words, a non-transient storage medium.

[0267] It should be understood that the "at least one" mentioned herein refers to one or more, and "a plurality of" refers to two or more. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is merely a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in order to facilitate a clear description of the technical solutions of the embodiments of the present application, in the embodiments of the present application, words such as "first" and "second" are used to distinguish between identical or similar items with substantially the same functions and effects. Those skilled in the art will understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0268] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.) and signals involved in the embodiments of this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data need to comply with the relevant laws, regulations and standards of relevant countries and regions.

[0269] The above description is an embodiment provided for this application and is not intended to limit this application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of this application should be included in the scope of protection of this application.

Claims

1. A memory page table cache method, characterized in that: The method comprises: Obtaining a memory request of a target process, wherein the memory request indicates a target page size, wherein the target page size is larger than a page size of a first-level page table and smaller than a page size of a second-level page table, wherein the first-level page table and the second-level page table are continuous two-level page tables; In response to the memory request, allocating N consecutive virtual page numbers and N consecutive physical page numbers to the target process, where N is not less than the number of memory pages required by the target process; Based on the N physical page numbers and the N virtual page numbers, N page table entries are created in a memory page table, wherein the N page table entries represent a mapping relationship between the N virtual page numbers and N base pages, wherein the N base pages are N physical pages corresponding one-to-one to the N physical page numbers, and a size of the base page is equal to a page size of the first-level page table; The N page table entries are merged into a first cache table entry, and the first cache table entry is stored in a page table cache.

2. The method according to claim 1, characterized in that The allocating N consecutive virtual page numbers and N consecutive physical page numbers to the target process includes: Determine the value of N based on the target page size and the base page size; Based on the value of N, determine N consecutive physical page numbers from unused physical page numbers, and determine N consecutive virtual page numbers based on unused virtual address space; The determined N physical page numbers and N virtual page numbers are allocated to the target process.

3. The method according to claim 1 or 2, characterized in that The creating N page table entries in the memory page table based on the N physical page numbers and the N virtual page numbers includes: Determine the smallest physical page number among the N physical page numbers as the basic physical page number; Based on the basic physical page number, generating a reference physical page number; The N page table entries are created in the memory page table, each of the N page table entries includes a virtual page number among the N virtual page numbers, the reference physical page number and a tag bit, and the tag bit indicates that the corresponding page table entry is a mergeable item.

4. The method according to claim 3, characterized in that N=2 x , x is a positive integer, and the basic physical page number is divisible by N; The step of generating a reference physical page number based on the basic physical page number includes: Determine that the values ​​of the xth to last bit to the leftmost bit in the reference physical page number are equal to the values ​​of the xth to last bit to the leftmost bit in the base physical page number, the values ​​of the 0th to x-2th to last bits are all first values, and the value of the x-1th to last bit is the second value.

5. The method according to any one of claims 1 to 4, characterized in that: The merging of the N page table entries into a first cache table entry includes: Obtaining a memory access request of the target process, wherein the memory access request includes a target virtual page number, and the target virtual page number is one of the N virtual page numbers; In the process of determining the target physical page number corresponding to the target virtual page number, the N page table entries are merged into the first cache table entry.

6. The method according to claim 5, characterized in that Each of the N page table entries includes a virtual page number among the N virtual page numbers, and the N page table entries also include the same reference physical page number, where the reference physical page number is generated based on a basic physical page number, and the basic physical page number is the smallest physical page number among the N physical page numbers; In the process of determining the target physical page number corresponding to the target virtual page number, merging the N page table entries into the first cache table entry includes: In the process of determining the target physical page number corresponding to the target virtual page number, searching the memory page table for a page table entry where the target virtual page number is located to obtain a first page table entry; If the first page table entry is a mergeable entry, a target parameter value is determined based on the first page table entry, the target parameter value indicating the The value of N; Generate a merged virtual page number based on the target parameter value and the target virtual page number, and determine the basic physical page number based on the reference physical page number in the first page table entry; The first cache table entry is generated, wherein the first cache table entry includes the merged virtual page number, the basic physical page number and a tag bit, and the tag bit in the first cache table entry indicates that the first cache table entry is a merged entry.

7. The method according to claim 6, characterized in that The N page table entries all include a tag bit whose value is the first value, and the value of the penultimate x-1 bit in the reference physical page number is the second value, and the values ​​of the penultimate 0th to x-2th bits are all the first value, and N=2 x , x is a positive integer, and x represents the target parameter value; The determining the target parameter value based on the first page table entry includes: The target parameter value is obtained by counting the number of bits whose value is the first value from the rightmost bit of the first binary string to the left until the first bit that is not the first value from the right to the left in the first binary string is counted, where the first binary string refers to the binary string obtained by concatenating the tag bit with the tail of the reference physical page number.

8. The method according to claim 7, characterized in that The generating a merged virtual page number based on the target parameter value and the target virtual page number includes: Determine that the value of the xth to last bit to the leftmost bit in the merged virtual page number is equal to the value of the xth to last bit to the leftmost bit in the target virtual page number, the value of the 0th to x-2th to last bit is the first value, and the value of the x-1th to last bit is the second value; The determining the basic physical page number based on the reference physical page number in the first page table entry includes: It is determined that the values ​​of the xth to the leftmost bit in the base physical page number are equal to the values ​​of the xth to the leftmost bit in the reference physical page number, and the values ​​of the 0th to x-1th to the last bits are all the first values.

9. The method according to any one of claims 6 to 8, characterized in that: After determining the basic physical page number based on the reference physical page number in the first page table entry, the method further includes: Based on the target parameter value and the target virtual page number, determining a basic virtual page number, the basic virtual page number being the smallest virtual page number among the N virtual page numbers; The target physical page number is determined based on the base physical page number, the target virtual page number, and the base virtual page number.

10. The method according to any one of claims 6 to 9, characterized in that: Before searching the memory page table for the page table entry where the target virtual page number is located, the method further includes: Querying the page table cache based on the target virtual page number to determine whether the target virtual page number hits the page table cache; If the target virtual page number does not hit the page table cache, the step of searching the memory page table for a page table entry where the target virtual page number is located is performed.

11. The method according to claim 10, characterized in that The querying the page table cache based on the target virtual page number to determine whether the target virtual page number hits the page table cache includes: Query the page table entry where the target virtual page number is located from the page table cache; If the page table entry where the target virtual page number is located is not found from the page table cache, multiple candidate virtual page numbers are determined based on a merge threshold and the target virtual page number, wherein the merge threshold indicates a maximum number of page table entries that can be merged at one time; querying whether there is a page table entry corresponding to a first candidate virtual page number in the page table cache, where the first candidate virtual page number is any one of the multiple candidate virtual page numbers; If the page table entry corresponding to the first candidate virtual page number does not exist in the page table cache, it is determined that the target virtual page number does not hit the page table cache.

12. The method according to claim 11, characterized in that The determining of a plurality of candidate virtual page numbers based on the merge threshold and the target virtual page number includes: Determine that the value from the jth to last bit to the leftmost bit in the jth candidate virtual page number included in the multiple candidate virtual page numbers is equal to the value from the jth to last bit to the leftmost bit in the target virtual page number, where j∈[1,X], and X represents the merge threshold; When j>1, determine that the values ​​of the 0th to j-2th last bits in the jth candidate virtual page number are all the first value, and the value of the j-1th last bit is the second value; When j=1, the value of the j-1th last bit in the jth candidate virtual page number is determined to be the second value.

13. The method according to claim 11 or 12, characterized in that Each of the plurality of candidate virtual page numbers corresponds to a parameter value, and the parameter value corresponding to each candidate virtual page number indicates the number of merge items corresponding to the corresponding candidate virtual page number; After querying whether there is a page table entry corresponding to the first candidate virtual page number in the page table cache, the method further includes: If a page table entry corresponding to the first candidate virtual page number exists in the page table cache, determining the parameter value corresponding to the first candidate virtual page number as the target parameter value; Based on the target parameter value and the target virtual page number, determining a basic virtual page number, the basic virtual page number being the smallest virtual page number among the N virtual page numbers; The target physical page number is determined based on the base physical page number, the target virtual page number, and the base virtual page number.

14. The method according to claim 9 or 13, characterized in that N=2 x , x is a positive integer, and the basic virtual page number is divisible by N; The determining of the basic virtual page number based on the target parameter value and the target virtual page number includes: Determine that the value of the xth to the leftmost bit in the base virtual page number is equal to the value of the xth to the leftmost bit in the target virtual page number, and the values ​​of the 0th to x-1th to last bits are all first values, and x is equal to the target parameter value.

15. The method according to claim 9, 13 or 14, characterized in that: The determining the target physical page number based on the basic physical page number, the target virtual page number and the basic virtual page number includes: Determining a difference between the target virtual page number and the base virtual page number; The sum of the difference value and the base physical page number is determined as the target physical page number.

16. The method according to any one of claims 1 to 15, characterized in that: The method further comprises: If there is a changed page table entry among the N page table entries, then based on the changed page table entry, the first cache table entry in the page table cache is deleted, and it is determined whether there are still M page table entries that can be merged among the N page table entries, where M is a positive integer greater than 2 and less than N; If it is determined that there are still M page table entries that can be merged among the N page table entries, the M page table entries are merged into a second cache table entry, and the second cache table entry is stored in the page table cache.

17. A memory page table cache device, characterized in that: The device comprises: An acquisition module, configured to acquire a memory application of a target process, wherein the memory application indicates a target page size, wherein the target page size is larger than a page size of a first-level page table and smaller than a page size of a second-level page table, wherein the first-level page table and the second-level page table are continuous two-level page tables; an allocation module, configured to allocate N consecutive virtual page numbers and N consecutive physical page numbers to the target process in response to the memory request, wherein N is not less than the number of memory pages required by the target process; A page table entry creation module, configured to create N page table entries in a memory page table based on the N physical page numbers and the N virtual page numbers, wherein the N page table entries represent a mapping relationship between the N virtual page numbers and N base pages, wherein the N base pages are N physical pages corresponding one-to-one to the N physical page numbers, and a size of the base page is equal to a page size of the first-level page table; The page table entry merging module is used to merge the N page table entries into a first cache table entry and store the first cache table entry in a page table cache.

18. The device according to claim 17, characterized in that The allocation module comprises: A first determination submodule, used to determine the value of N based on the target page size and the base page size; The second determination submodule is used to determine N consecutive physical page numbers from unused physical page numbers based on the value of N. and determining N consecutive virtual page numbers based on the unused virtual address space; The allocation submodule is used to allocate the determined N physical page numbers and N virtual page numbers to the target process.

19. The device according to claim 17 or 18, characterized in that The page table entry creation module includes: A third determining submodule, configured to determine the smallest physical page number among the N physical page numbers as the basic physical page number; A generating submodule, used for generating a reference physical page number based on the basic physical page number; A creation submodule is used to create the N page table entries in the memory page table, each of the N page table entries includes a virtual page number among the N virtual page numbers, the reference physical page number and a tag bit, and the tag bit indicates that the corresponding page table entry is a mergeable item.

20. The device according to claim 19, characterized in that N=2 x , x is a positive integer, and the basic physical page number is divisible by N; The generation submodule is specifically used for: Determine that the values ​​of the xth to last bit to the leftmost bit in the reference physical page number are equal to the values ​​of the xth to last bit to the leftmost bit in the base physical page number, the values ​​of the 0th to x-2th to last bits are all first values, and the value of the x-1th to last bit is the second value.

21. The device according to any one of claims 17 to 20, characterized in that The page table entry merging module comprises: An acquisition submodule, configured to acquire a memory access request of the target process, wherein the memory access request includes a target virtual page number, and the target virtual page number is one of the N virtual page numbers; The merging submodule is used to merge the N page table entries into the first cache table entry in the process of determining the target physical page number corresponding to the target virtual page number.

22. The device according to claim 21, characterized in that Each of the N page table entries includes a virtual page number among the N virtual page numbers, and the N page table entries also include the same reference physical page number, where the reference physical page number is generated based on a basic physical page number, and the basic physical page number is the smallest physical page number among the N physical page numbers; The merging submodule is specifically used for: In the process of determining the target physical page number corresponding to the target virtual page number, searching the memory page table for a page table entry where the target virtual page number is located to obtain a first page table entry; If the first page table entry is a mergeable entry, determining a target parameter value based on the first page table entry, where the target parameter value indicates a value of N; Generate a merged virtual page number based on the target parameter value and the target virtual page number, and determine the basic physical page number based on the reference physical page number in the first page table entry; The first cache table entry is generated, wherein the first cache table entry includes the merged virtual page number, the basic physical page number and a tag bit, and the tag bit in the first cache table entry indicates that the first cache table entry is a merged entry.

23. The device according to claim 22, characterized in that The N page table entries all include a tag bit whose value is the first value, and the value of the penultimate x-1 bit in the reference physical page number is the second value, and the values ​​of the penultimate 0th to x-2th bits are all the first value, and N=2 x , x is a positive integer, and x represents the target parameter value; The merging submodule is specifically used for: The target parameter value is obtained by counting the number of bits whose value is the first value from the rightmost bit of the first binary string to the left until the first bit that is not the first value from the right to the left in the first binary string is counted, where the first binary string refers to the binary string obtained by concatenating the tag bit with the tail of the reference physical page number.

24. The device according to claim 23, characterized in that The merging submodule is specifically used for: Determine that the value of the xth to last bit to the leftmost bit in the merged virtual page number is equal to the value of the xth to last bit to the leftmost bit in the target virtual page number, the value of the 0th to x-2th to last bit is the first value, and the value of the x-1th to last bit is the second value; The determining the basic physical page number based on the reference physical page number in the first page table entry includes: It is determined that the values ​​of the xth to the leftmost bit in the base physical page number are equal to the values ​​of the xth to the leftmost bit in the reference physical page number, and the values ​​of the 0th to x-1th to the last bits are all the first values.

25. The device according to any one of claims 22 to 24, characterized in that The merging submodule is also specifically used for: After determining the basic physical page number based on the reference physical page number in the first page table entry, determining a basic virtual page number based on the target parameter value and the target virtual page number, the basic virtual page number being the smallest virtual page number among the N virtual page numbers; The target physical page number is determined based on the base physical page number, the target virtual page number, and the base virtual page number.

26. The device according to any one of claims 22 to 25, characterized in that The merging submodule is also specifically used for: Before searching the page table entry where the target virtual page number is located from the memory page table, querying the page table cache based on the target virtual page number to determine whether the target virtual page number hits the page table cache; If the target virtual page number does not hit the page table cache, the step of searching the memory page table for a page table entry where the target virtual page number is located is performed.

27. The device according to claim 26, characterized in that The merging submodule is specifically used for: Query the page table entry where the target virtual page number is located from the page table cache; If the page table entry where the target virtual page number is located is not found from the page table cache, multiple candidate virtual page numbers are determined based on a merge threshold and the target virtual page number, wherein the merge threshold indicates a maximum number of page table entries that can be merged at one time; querying whether there is a page table entry corresponding to a first candidate virtual page number in the page table cache, where the first candidate virtual page number is any one of the multiple candidate virtual page numbers; If the page table entry corresponding to the first candidate virtual page number does not exist in the page table cache, it is determined that the target virtual page number does not hit the page table cache.

28. A computing device, characterized in that The computing device includes a processor and a memory; The memory is used to store computer programs; The processor is configured to execute the computer program to implement the method according to any one of claims 1 to 16.

29. A computer-readable storage medium, characterized in that: The storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 16 are implemented.

30. A computer program product, characterized in that The computer program product stores computer instructions, and when the computer instructions are executed by a processor, the steps of the method according to any one of claims 1 to 16 are implemented.

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