Heterogeneous computing system and server system

Abstract

Provided in the present application are a heterogeneous computing system and a server system. The heterogeneous computing system comprises a plurality of terminal devices; a processor, configured to determine whether a target terminal device among the plurality of terminal devices is in a reset-requiring state, upon determining that the target terminal device is in said state, intercept an interrupt signal reported by the target terminal device to a root complex, and enable the target terminal device to send a device identifier to the root complex, and upon reception of storage completion information sent by the root complex, reset the target terminal device and send reset completion information to the root complex; and a root complex, configured to receive a device identifier, store corresponding current state information on the basis of the device identifier, send storage completion information to the processor when storing the current state information is completed, and, send the current state information to the target terminal device upon reception of reset completion information. Therefore, the present application solves the problem of main units being unable to operate normally due to PCIe device failures.

Description

Heterogeneous computing systems and server systems

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the China Patent Office on September 19, 2023, with application number 2023112076176 and application name “Heterogeneous Computing System and Server System,” the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments of the present application relate to the field of computers, and more specifically, to a heterogeneous computing system and a server system. Background Art

[0004] As the performance of heterogeneous computing systems improves, users are demanding increasingly diverse functionalities. Consequently, the PCIe (Peripheral Component Interconnect Express) devices that implement these functions are also becoming increasingly diverse. Different heterogeneous computing systems are configured with different PCIe devices, each with its own distinct functionality. If a particular PCIe device fails, it can disrupt the corresponding heterogeneous computing system functionality or cause the system to crash, forcing the host system to reset and potentially leading to serious problems such as loss of important data. Therefore, when a PCIe device fails in a system, how to detect and address the failure is a critical issue.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a heterogeneous computing system and a server system to at least solve the problem in the related art that a host cannot operate normally due to a PCIe device failure.

[0007] According to one embodiment of the present application, a heterogeneous computing system is provided, comprising: a plurality of terminal devices; a processor, communicatively connected to the plurality of terminal devices, the processor being configured to determine whether a target terminal device among the plurality of terminal devices is in a state requiring reset, and when it is determined that the target terminal device is in a state requiring reset, intercepting an interrupt signal reported by the target terminal device to a root complex, and causing the target terminal device to send a device identification to the root complex, the processor being further configured to, when receiving storage completion information sent by the root complex, reset the target terminal device and send reset completion information to the root complex; a root complex, respectively connected to the plurality of terminal devices, the root complex being configured to receive a device identification, store current status information corresponding to the device identification according to the device identification, send the storage completion information to the processor when the current status information is stored, and establish a connection with the reset target terminal device and send the current status information to the target terminal device when the reset completion information is received.

[0008] In an exemplary embodiment, the processor is further configured to: start the counting function of the watchdog timer corresponding to each terminal device, and clear the watchdog timer corresponding to the terminal device when receiving a dog feeding signal sent by the terminal device; determine whether the count value of the watchdog timer corresponding to the target terminal device exceeds a threshold; when the count value of the watchdog timer corresponding to the target terminal device exceeds the threshold, determine that the target terminal device is faulty and determine that the target terminal device is in a state that needs to be reset.

[0009] In an exemplary embodiment, the processor is further configured to: when it is determined that the target terminal device is faulty, turn off the counting function of the watchdog timer corresponding to the target terminal device; and after sending the reset completion information to the root complex, restore the counting function of the watchdog timer corresponding to the target terminal device.

[0010] In an exemplary embodiment, the terminal device is also configured to send a heartbeat signal to the processor once every first predetermined time period, and the processor is further configured to: determine whether the heartbeat signal sent by each terminal device is received every first predetermined time period; if no heartbeat signal is received, determine that the terminal device that has not received the heartbeat signal is the target terminal device, and determine that the target terminal device has failed and is in a state that needs to be reset.

[0011] In an exemplary embodiment, the processor is further configured to: determine whether a reset request message of the operating system of the target terminal device is received, wherein the reset request message is information generated by the operating system after the software of the target terminal device is updated, and the reset request message is used to request to reset the target terminal device; when the reset request message is received, determine that the target terminal device is in a state that requires reset.

[0012] In an exemplary embodiment, the reset request information is generated by the operating system in response to a predetermined operation acting on the human-computer interaction interface. The predetermined operation is an operation that feeds back the inquiry information displayed on the human-computer interaction interface. The inquiry information is generated by the basic input and output system and sent to the operating system when the software of the target terminal device is updated. The inquiry information is used to inquire whether the operating system should be reset after the software is updated.

[0013] In an exemplary embodiment, the processor is further configured to: intercept error report information sent by the target terminal device to the root complex, the error report information including an interrupt signal, a device identifier, an error type, an error address, and an error source; mask the interrupt signal in the error report information, the error report information after masking the interrupt signal constitutes masked information; and send the masked information to the root complex.

[0014] In an exemplary embodiment, the processor is further configured to: after intercepting the error report information sent by the target terminal device to the root complex, generate an error log according to the device identification, error type, error address, and error source.

[0015] In an exemplary embodiment, the processor is further configured to: after resetting the target terminal device, determine whether the target terminal device is in a state requiring reset; if it is determined that the target terminal device is in a state requiring reset, control the corresponding number of consecutive resets of the target terminal device to be counted once; if it is determined that the target terminal device is not in a state requiring reset, control the number of consecutive resets to be cleared; determine whether the number of consecutive resets is greater than or equal to a predetermined threshold; if it is determined that the number of consecutive resets is greater than or equal to the predetermined threshold, not intercept the interrupt signal.

[0016] In an exemplary embodiment, the root complex is further configured to reset in response to an interrupt signal if the interrupt signal is received.

[0017] In an exemplary embodiment, the processor is further configured to: intercept the interrupt signal when it is determined that the target terminal device is in a state requiring reset and the number of consecutive resets corresponding to the target terminal device is less than a predetermined threshold.

[0018] In an exemplary embodiment, the processor is further configured to do one of the following: control the target terminal device to reset; and restore register status information corresponding to the downstream port of the target terminal device to an initial state.

[0019] In an exemplary embodiment, the current state information includes configuration space information, a BAR (Base Address Register) space mapping relationship, and memory space information of the target terminal device.

[0020] In an exemplary embodiment, the root complex is further configured to: store configuration space information, BAR space mapping relationship, and memory space information corresponding to the device identifier in a hard disk according to the device identifier.

[0021] In an exemplary embodiment, the root complex is further configured to: scan the reset target terminal device according to the device identification to restore the communication connection with the target terminal device; read the current status information from the hard disk through the memory; and send the read current status information to the target terminal device.

[0022] In an exemplary embodiment, the root complex is further configured to: disconnect from the target terminal device when the current state information is stored.

[0023] In an exemplary embodiment, the root complex is communicatively connected to each terminal device via a PCIe link.

[0024] In an exemplary embodiment, the root complex is further configured to: scan the PCIe link using a depth-first search algorithm to allocate an address space to each terminal device before storing the current status information according to the device identification.

[0025] In an exemplary embodiment, the terminal device includes: a system on a chip, which is configured to run one of the Orin (an NVIDIA Jetson series computing module, mainly used for autonomous driving) platform and the NV (an NVIDIA Jetson series computing module, such as used in edge computing boxes) platform.

[0026] In one exemplary embodiment, the processor includes a baseboard management controller.

[0027] According to another embodiment of the present application, a server system is provided, including any heterogeneous computing system.

[0028] By adopting the embodiment of the present application, when the processor determines that the target terminal device needs to be reset due to a fault or upgrade, etc., it intercepts the interrupt signal reported by the target terminal device to the root complex, thereby preventing the root complex from receiving the interrupt signal and causing the root complex to be abnormal or even down and reset, thereby ensuring that the root complex can continue to operate normally during the fault handling process; and the processor does not intercept the device identification sent by the target device to the root complex, so that the root complex stores the status information of the target terminal device corresponding to the device identification, notifies the processor after the storage is completed, and the processor resets the target terminal device. After the reset is completed, the root complex restores its status information, thereby ensuring that the data of the target terminal device will not be lost during the fault handling process. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] FIG1 is a schematic structural diagram of a heterogeneous computing system according to an embodiment of the present application;

[0030] FIG2 is another structural diagram of a heterogeneous computing system according to an embodiment of the present application;

[0031] FIG3 is a flowchart of a fault handling process for a heterogeneous computing system according to an embodiment of the present application.

[0032] The above drawings include the following reference numerals:

[0033] 30. Terminal device; 31. Root complex; 32. Processor; 33. PCIe switch device. DETAILED DESCRIPTION

[0034] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] It should be noted that the terms "first", "second", etc. in the description, claims and drawings of this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0036] In this embodiment, a heterogeneous computing system is provided. FIG1 is a schematic diagram of the structure of a heterogeneous computing system according to an embodiment of the present application. As shown in FIG1 , the heterogeneous computing system includes:

[0037] Multiple terminal devices (End point) 30;

[0038] Alternatively, the terminal device may be any suitable type of device. For example, the terminal device may be a PCIe device, or a system-on-chip configured to run the Orin platform (an NVIDIA Jetson series computing module, primarily used for autonomous driving) or the NV platform (an NVIDIA Jetson series computing module, such as used in edge computing boxes).

[0039] a processor 32, communicatively connected to a plurality of terminal devices, the processor being configured to determine whether a target terminal device among the plurality of terminal devices is in a state requiring reset, and if it is determined that the target terminal device is in a state requiring reset, intercepting an interrupt signal reported by the target terminal device to a root complex, and causing the target terminal device to send a device identification to the root complex; and further configured to, if a storage completion message is received from the root complex, reset the target terminal device and send a reset completion message to the root complex;

[0040] Optionally, the target terminal device may be any one of a plurality of terminal devices. The state requiring reset includes a state requiring reset due to a fault and may also include a state requiring reset due to a software upgrade. The storage completion information is used to indicate that the storage of the current state information is complete.

[0041] The root complex 31 is connected to multiple terminal devices respectively. The root complex is configured to receive a device identification, store the current status information corresponding to the device identification according to the device identification, and send the storage completion information to the processor when the current status information is stored. When the reset completion information is received, the root complex establishes a connection with the reset target terminal device and sends the current status information to the target terminal device.

[0042] Optionally, the root complex may be a server host. When the target terminal device is in a state requiring reset, it will generate fault information and an interrupt signal to trigger an interrupt processing process. The interrupt signal may easily cause abnormal interruption or even reset of the root complex service.

[0043] Through the system, the processor determines whether the target terminal device is in a state that needs to be reset; when it is determined that the target terminal device is in a state that needs to be reset, the processor intercepts the interrupt signal reported by the target terminal device to the root complex, which will cause the target terminal device to send its corresponding device identification to the root complex. The root complex stores the current status information of the target terminal device corresponding to the device identification according to the device identification, and when the storage is completed, sends the storage completion information to the processor to trigger the processor to reset the target terminal device and repair the target terminal device. Thereafter, the reset completion information of the target terminal device is sent to the root complex, so that the root complex establishes a connection with the reset target terminal device and restores the status information of the target terminal device. Compared with the problem in the related art that the host cannot operate normally due to PCIe device failure, the processor in the present application intercepts the interrupt signal reported by the target terminal device to the root complex when determining that the target terminal device needs to be reset due to failure or upgrade, so as to avoid the root complex receiving the interrupt signal and causing the root complex to be abnormal or even down and reset, thereby ensuring that the root complex can continue to operate normally during the fault handling process; and the processor does not intercept the device identification sent by the target device to the root complex, so that the root complex stores the status information of the target terminal device corresponding to the device identification, notifies the processor after the storage is completed, and the processor resets the target terminal device. After the reset is completed, the root complex restores its status information, thereby ensuring that the data of the target terminal device will not be lost during the fault handling process.

[0044] In one optional solution, the processor is further configured to: activate the counting function of the watchdog timer corresponding to each terminal device, and upon receiving a watchdog feeding signal from the terminal device, clear the watchdog timer corresponding to the terminal device; determine whether the count value of the watchdog timer corresponding to the target terminal device exceeds a threshold; and, if the count value of the watchdog timer corresponding to the target terminal device exceeds the threshold, determine that the target terminal device has failed and that the target terminal device is in a state requiring a reset. By setting the watchdog timer and monitoring whether the terminal device is feeding the watchdog regularly, the processor can more accurately and promptly determine whether each terminal device has failed, thereby achieving fault location.

[0045] In order to achieve normal monitoring of multiple terminal devices, the processor is further configured to: establish communication connections with the multiple terminal devices before starting the counting function of the watchdog timer corresponding to each terminal device.

[0046] In addition to monitoring the status of the terminal device in the above manner, in other embodiments, the device status of the terminal device is bound to a heartbeat signal, and the terminal device is further configured to send a heartbeat signal to the processor every first predetermined period of time. The processor can also be configured to: determine whether the heartbeat signal sent by each terminal device is received every first predetermined period of time; if the heartbeat signal is not received, determine that the terminal device that did not receive the heartbeat signal is the target terminal device, and determine that the target terminal device has a fault and is in a state that needs to be reset. The processor monitors whether the terminal device has a fault through the timed heartbeat signal, and can more accurately and timely determine whether each terminal device has a fault, thereby achieving fault location.

[0047] Furthermore, the processor is configured to, upon determining that a target terminal device has failed, disable the counting function of the watchdog timer corresponding to the target terminal device. This prevents the watchdog timer from frequently reporting errors during fault handling. The processor is further configured to, after sending a reset completion message to the root complex, restore the counting function of the watchdog timer corresponding to the target terminal device. This allows continued monitoring of the target terminal device after it has recovered.

[0048] In addition to a state requiring a reset due to a fault, a state requiring a reset due to a software upgrade may also be a state requiring a reset. To monitor this state requiring a reset, in some exemplary embodiments of the present application, the processor is further configured to: determine whether a reset request message from the operating system (OS) of the target terminal device has been received, wherein the reset request message is information generated by the operating system after the software of the target terminal device has been updated, and the reset request message is used to request the reset of the target terminal device; upon receiving the reset request message, determine that the target terminal device is in a state requiring a reset. In this embodiment, the processor determines whether it is in a state requiring a reset by determining whether a reset request message proactively initiated by the target terminal device has been received.

[0049] Optionally, the reset request message is generated by the operating system in response to a predetermined operation performed on the human-computer interaction interface, wherein the predetermined operation is an operation that returns a query message displayed on the human-computer interaction interface. The query message is generated and sent by the Basic Input Output System (BIOS) to the operating system when the software of the target terminal device is updated. The query message is used to inquire whether to reset the operating system after the software update. In this embodiment, the terminal device performs a software upgrade via the BIOS. After the upgrade is complete, the BIOS sends a reset query message to the terminal device's operating system. The operating system displays the query message to relevant personnel via the human-computer interaction interface, so that if the relevant personnel selects to reset through the predetermined operation, the operating system generates a reset request message in response to the predetermined operation.

[0050] Optionally, the predetermined operation can be any operation method acting on the human-computer interaction interface, such as single-click, double-click, long press, and slide, and the predetermined operation represents an operation to reset the operating system. In addition, if the relevant personnel chooses not to reset the operating system through the operating system, or if the relevant personnel does not perform any operation within the second predetermined time period, the operating system does not generate a reset request message.

[0051] To avoid the problem of host downtime or reset caused by terminal device failure, according to some embodiments of the present application, the processor is further configured to: intercept error report information sent by the target terminal device to the root complex, the error report information including an interrupt signal, device identification, error type, error address, and error source; shield the interrupt signal in the error report information, and the error report information after shielding the interrupt signal constitutes shielded information; and send the shielded information to the root complex. By shielding the interrupt signal in the error report information and sending it to the root complex, the root complex can receive other error report information in addition to the interrupt signal, which makes it easier for the root complex to know the terminal device that has an error and store the corresponding data.

[0052] Optionally, the masked information is used to trigger the root complex to store current status information of the target terminal device where the error occurs.

[0053] To facilitate subsequent fault tracing, in another embodiment, the processor is further configured to: after intercepting the error report information sent by the target terminal device to the root complex, generate an error log according to the device identification, error type, error address and error source.

[0054] In actual applications, the PCIe bus supports Advanced Error Reporting (AER), which can detect and report bus faults and device errors in a timely manner, improving the stability and reliability of the PCIe architecture. Correspondingly, some system anomalies will cause the system to restart or software repair. When an error occurs in a PCIe device, such as a transmission error or bus error during data transmission, the device will send an error report message to the location indicated by the AER working mechanism. The AER mechanism will record the received error report message, including information such as the error type, error address, and error source. The AER mechanism will pass the error report message to the operating system so that the system can perform appropriate error handling. It can also pass the error message to the BIOS for processing. The operating system can handle the error, such as restarting the PCIe device or repairing the fault through software to maintain system stability.

[0055] In some optional embodiments, the processor is further configured to: after resetting the target terminal device, determine whether the target terminal device is in a state requiring reset; if it is determined that the target terminal device is in a state requiring reset, control the number of consecutive resets corresponding to the target terminal device to be counted once; if it is determined that the target terminal device is not in a state requiring reset, control the number of consecutive resets to be cleared; determine whether the number of consecutive resets is greater than or equal to a predetermined threshold; if it is determined that the number of consecutive resets is greater than or equal to the predetermined threshold, not intercept the interrupt signal. Accordingly, the root complex is further configured to reset in response to the interrupt signal upon receiving the interrupt signal. Since in actual applications, the types of terminal device failures include recoverable failures and unrecoverable failures, and some unrecoverable failures cannot be repaired by reset, the processor of this embodiment, if the target terminal device is still in a state requiring reset after being reset multiple times, indicates that the reset cannot repair the failure of the target terminal device, and in this case, the target terminal device is no longer reset and the interrupt signal is no longer intercepted. In this way, the root complex can receive the interrupt signal and restart and reset, ensuring high fault handling efficiency of the heterogeneous computing system while ensuring data processing security of the heterogeneous computing system.

[0056] If the number of consecutive resets is less than a predetermined threshold, it indicates that the target terminal device may still be repaired through reset. In this case, the processor is further configured to intercept the interrupt signal if it determines that the target terminal device is in a state requiring reset and the number of consecutive resets corresponding to the target terminal device is less than the predetermined threshold. This prevents the root complex from receiving the interrupt signal, causing abnormalities or even downtime and reset, thereby ensuring that the root complex can continue to operate normally during the fault handling process.

[0057] In order to achieve flexible resetting of the target terminal device, in an exemplary embodiment, the processor is further configured to do one of the following: control the target terminal device to be reset; and restore register status information corresponding to the downstream port of the target terminal device to an initial state.

[0058] In an embodiment of the present application, the current state information includes the target terminal device's configuration space information, BAR space mapping relationship, and memory space information. When the target terminal device is in a state requiring a reset, the root complex stores the target terminal device's configuration space information, BAR space mapping relationship, and memory space information, thereby avoiding the loss of current operating data after the target terminal device is reset.

[0059] In an exemplary embodiment of the present application, the root complex is further configured to: store configuration space information, BAR space mapping relationships, and memory space information corresponding to the device identifier on a hard disk based on the device identifier. When the target terminal device is in a state requiring a reset, the root complex stores the configuration space information, BAR space mapping relationships, and memory space information of the target terminal device, thereby avoiding the problem of losing the current operating data of the target terminal device after the reset.

[0060] To ensure data security during troubleshooting, some optional solutions further configure the root complex to: scan the reset target terminal device based on its device identifier to restore communication with the target terminal device; read current status information from the hard disk via memory; and send the read current status information to the target terminal device. In this embodiment, when restoring connection with the target terminal device, the root complex first reads the data to be restored from the hard disk into memory, and then sends this data from memory to the target terminal device, thereby restoring data on the reset target terminal device.

[0061] Optionally, the root complex is further configured to: disconnect from the target terminal device when the current state information is stored, thereby isolating the target terminal device that needs to be restarted.

[0062] The root complex may use any appropriate type of communication link to establish a communication connection with each terminal device. In this application, each terminal device is a PCIe device, and the root complex is communicated with each terminal device via a PCIe link.

[0063] The root complex is also configured to scan the PCIe links using a depth-first search algorithm to allocate address space to each end device before storing current status information based on the device's identity. The root complex performs a PCI (Peripheral Component Interconnect) scan of PCIe end devices to allocate address space to each end device and establish a PCIe link connection with each end device.

[0064] In actual application, the processor can be any suitable type of processor, such as a CPU (Central Processing Unit), an MCU (Microcontroller Unit), etc. In this application, the processor includes a baseboard management controller (BMC). The processor is a baseboard management controller.

[0065] Optionally, the terminal device includes: a system on chip, the system on chip being configured to run one of the Orin platform and the NV platform.

[0066] Optionally, as a heterogeneous computing platform, a heterogeneous computing system is a computing system that integrates different computing resources (such as CPU, GPU (Graphics Processing Unit, graphics processor), FPGA (Field Programmable Gate Array, ASIC (Application Specific Integrated Circuit, application-specific integrated circuit), etc.), and uses different resources to achieve high-efficiency applications. Among them, NVIDIA's Jetson is a low-power AI (Artificial Intelligence) computing platform that can support high-performance machine learning, computer vision and graphics processing applications. The Jetson computing platform is a system on chip (SoC), which includes computing resources such as NVIDIA GPU and ARM CPU to achieve rapid deployment and intelligent applications. NVIDIA's Jetson platform supports both the deployment of a single computing node and the configuration of its PCIe bus resources as terminal device mode (i.e., PCIe End Point mode) to form a system with stronger computing resources. Compared with computing nodes interconnected by Ethernet, the system that uses the PCIe bus to interconnect the host computing node (Host) and heterogeneous computing nodes (Jetson) has lower data transmission latency, so that the multi-node computing platform can achieve higher performance.

[0067] In another embodiment, as shown in FIG2 , the heterogeneous computing system further includes a PCIe switch device 33 , and the root complex is connected to the plurality of terminal devices 30 via the PCIe switch device 33 .

[0068] Optionally, the root complex is integrated into the server host. In actual application, the heterogeneous computing platform based on the server host Host and SoC (configured as a PCIe terminal device) has a technical problem of PCIe terminal device failure caused by SoC running the operating system and algorithm software, which is limited by the general characteristics of the PCIe bus architecture, and thus causes the entire computing platform to shut down or restart. In particular, when multiple SoCs serve as PCIe EP (Endpoint, terminal device), the redundancy reliability of the entire computing platform is doubled. Based on the results of system experimental tests, it was found that the failure of the computing platform caused by PCIe bus hardware is much lower than the system shutdown or restart caused by SoC running system and software. Therefore, the heterogeneous computing system of the present application is proposed.

[0069] For example, if the processor is a BMC, the terminal device and BMC are connected via GPIO to implement heartbeat detection. A pulse (heartbeat) frequency can be set based on the actual system requirements, for example, every 1 second. The terminal device binds its device status to the heartbeat signal, allowing the BMC to clearly identify the status of the terminal device node. A communication link is established between the BMC and the host, through which information about the faulty terminal device is fed back.

[0070] As shown in Figure 3, the host performs a PCI scan on the terminal device, assigns a bus number to the terminal device based on the DFS (Depth-First Search) algorithm, and completes the configuration of the configuration space. When the terminal device fails, the BMC only records the error type, error address, error source and other information in the AER, and masks the interrupt signal. At the same time, the host stores the configuration space information, BAR space mapping, memory space information and other related data of the failed terminal device on the hard disk. After the host processes the information of the failed terminal device stored in the memory, it notifies the BMC. At this time, the BMC initiates a restart control of the failed terminal device node. After the restart is complete, it notifies the BMC and notifies the host through the BMC. The host then re-initiates a PCI scan command for the restarted terminal device node, regains the node, and restores the relevant information of the previously failed terminal device.

[0071] According to another aspect of the present application, a server system is further provided, and the server system includes any heterogeneous computing system.

[0072] The server system includes any heterogeneous computing system, through which the processor intercepts the interrupt signal reported by the target terminal device to the root complex when determining that the target terminal device needs to be reset due to a fault or upgrade, etc., to prevent the root complex from receiving the interrupt signal and causing the root complex to be abnormal or even down and reset, thereby ensuring that the root complex can continue to operate normally during the fault handling process; and the processor does not intercept the device identification sent by the target device to the root complex, so that the root complex stores the status information of the target terminal device corresponding to the device identification, notifies the processor after the storage is completed, and the processor resets the target terminal device. After the reset is completed, the root complex restores its status information, thereby ensuring that the data of the target terminal device will not be lost during the fault handling process, thereby ensuring the operational reliability of the server system.

[0073] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM (Read-Only Memory, Read-Only Memory) / RAM (Random Access Memory, Random Access Memory), a magnetic disk, or an optical disk), and includes a number of instructions for enabling a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods of each embodiment of the present application.

[0074] It should be noted that each module can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: all modules are located in the same processor; or, each module is located in different processors in any combination.

[0075] For examples in this embodiment, reference may be made to the examples described in the embodiments and exemplary implementations, and this embodiment will not be described in detail here.

[0076] Obviously, those skilled in the art should understand that the modules or steps of the present application described above can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed across a network composed of multiple computing devices, they can be implemented using program code executable by the computing device, and thus, they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be fabricated into separate integrated circuit modules, or multiple modules or steps can be fabricated into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0077] The above description is merely a preferred embodiment of the present application and is not intended to limit the present application. Various modifications and variations are possible for those skilled in the art. Any modifications, equivalent substitutions, improvements, etc. made within the principles of the present application shall be included within the scope of protection of the present application.

Claims

1. A heterogeneous computing system, characterized in that: include: Multiple terminal devices; a processor, communicatively connected with the plurality of terminal devices, the processor being configured to determine whether a target terminal device among the plurality of terminal devices is in a state requiring reset, and in the case of determining that the target terminal device is in the state requiring reset, intercepting an interrupt signal reported by the target terminal device to the root complex, and causing the target terminal device to send a device identification to the root complex, and the processor being further configured to reset the target terminal device and send reset completion information to the root complex in the case of receiving storage completion information sent by the root complex; The root complex is connected to multiple terminal devices respectively, and the root complex is configured to receive the device identification, store the current status information corresponding to the device identification according to the device identification, and send the storage completion information to the processor when the storage of the current status information is completed. When the reset completion information is received, a connection is established with the reset target terminal device and the current status information is sent to the target terminal device.

2. The system according to claim 1, characterized in that The processor is further configured to: Starting the counting function of the watchdog timer corresponding to each of the terminal devices, and clearing the watchdog timer corresponding to the terminal device when receiving a dog feeding signal sent by the terminal device; Determine whether a count value of a watchdog timer corresponding to the target terminal device exceeds a threshold; When the count value of the watchdog timer corresponding to the target terminal device exceeds a threshold value, it is determined that the target terminal device fails, and it is determined that the target terminal device is in the state that needs to be reset.

3. The system according to claim 2, characterized in that The processor is further configured to: In the case where it is determined that the target terminal device fails, turning off the counting function of the watchdog timer corresponding to the target terminal device; After sending the reset completion information to the root complex, the counting function of the watchdog timer corresponding to the target terminal device is restored.

4. The system according to claim 1, characterized in that The terminal device is further configured to send a heartbeat signal to the processor once every first predetermined time period, and the processor is further configured to: Determining whether the heartbeat signal sent by each of the terminal devices is received every the first predetermined time period; In the case where the heartbeat signal is not received, it is determined that the terminal device that has not received the heartbeat signal is the target terminal device, and it is determined that the target terminal device fails and is in the state that needs to be reset.

5. The system according to claim 1, characterized in that The processor is further configured to: Determining whether reset request information of the operating system of the target terminal device is received, wherein the reset request information is information generated by the operating system after the software of the target terminal device is updated, and the reset request information is used to request to reset the target terminal device; When the reset request information is received, it is determined that the target terminal device is in the state requiring reset.

6. The system according to claim 5, characterized in that The reset request information is generated by the operating system in response to a predetermined operation acting on the human-computer interaction interface, the predetermined operation is an operation of feeding back the inquiry information displayed on the human-computer interaction interface, the inquiry information is generated by the basic input and output system and sent to the operating system when the software of the target terminal device is updated, and the inquiry information is used to inquire whether the operating system should be reset after the software is updated.

7. The system according to claim 1, characterized in that The processor is further configured to: intercepting error report information sent by the target terminal device to the root complex, the error report information including the interrupt signal, the device identifier, the error type, the error address and the error source; Shielding the interrupt signal in the error report information, so that the error report information after shielding the interrupt signal constitutes shielded information; The masked information is sent to the root complex.

8. The system according to claim 7, characterized in that The processor is further configured to: after intercepting the error report information sent by the target terminal device to the root complex, generate an error log according to the device identification, the error type, the error address and the error source.

9. The system according to any one of claims 1 to 8, characterized in that The processor is further configured to: After resetting the target terminal device, determining whether the target terminal device is in the state requiring resetting; When it is determined that the target terminal device is in the state that needs to be reset, controlling the number of consecutive resets corresponding to the target terminal device to be counted once; When it is determined that the target terminal device is not in the state requiring reset, controlling the number of consecutive resets to be reset to zero; Determining whether the number of consecutive resets is greater than or equal to a predetermined threshold; If it is determined that the number of consecutive resets is greater than or equal to the predetermined threshold, the interrupt signal is not intercepted.

10. The system according to claim 9, characterized in that The root complex is further configured to reset in response to the interrupt signal if the interrupt signal is received.

11. The system according to claim 9, characterized in that The processor is further configured to: When it is determined that the target terminal device is in the state requiring reset and the number of consecutive resets corresponding to the target terminal device is less than the predetermined threshold, the interrupt signal is intercepted.

12. The system according to any one of claims 1 to 8, characterized in that The processor is further configured to do one of the following: Controlling the target terminal device to reset; The register status information corresponding to the downstream port of the target terminal device is restored to an initial state.

13. The system according to any one of claims 1 to 8, characterized in that The current status information includes the configuration space information, base address register BAR space mapping relationship and memory space information of the target terminal device.

14. The system according to any one of claims 1 to 8, characterized in that The root complex is also configured to: According to the device identification, the configuration space information, the BAR space mapping relationship and the memory space information corresponding to the device identification are stored in the hard disk.

15. The system according to claim 14, characterized in that The root complex is also configured to: Scanning the reset target terminal device according to the device identification to restore the communication connection with the target terminal device; Reading the current status information from the hard disk through the memory; The read current status information is sent to the target terminal device.

16. The system according to any one of claims 1 to 8, characterized in that The root complex is also configured to: When the current status information is stored, the connection with the target terminal device is disconnected.

17. The system according to any one of claims 1 to 8, characterized in that The root complex is connected to each of the terminal devices through a high-speed serial computer expansion bus standard PCIe link.

18. The system according to claim 17, characterized in that The root complex is also configured to: Before storing the current status information according to the device identification, the PCIe link is scanned using a depth-first search algorithm to allocate an address space to each of the terminal devices.

19. The system according to any one of claims 1 to 8, characterized in that The terminal device includes: a system on a chip, and the system on a chip is configured to run one of an Orin platform and an NV platform.

20. The system according to any one of claims 1 to 8, characterized in that The processor includes a baseboard management controller.

21. A server system, characterized in that: A heterogeneous computing system comprising any one of claims 1 to 20.

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