Semiconductor product and semiconductor device

Abstract

This semiconductor product is composed of a chiplet architecture and comprises: an interposer having a relay wiring structure; a first semiconductor device having a first circuit for performing first signal processing; and a second semiconductor device having a second circuit for performing second signal processing. The semiconductor product has a capacitor circuit and includes a third semiconductor device adjacent to the first and second semiconductor devices. The first, second, and third semiconductor devices are connected to a first surface of the interposer. The capacitor circuit is electrically connected to the first and second semiconductor devices via a plurality of relay wires provided in the relay wiring structure. By providing the capacitor circuit outside the first and second semiconductor devices, a capacitor for suppressing noise according to the frequency band of noise can be arranged in an appropriate position while suppressing an increase in cost.

Description

Semiconductor products and semiconductor equipment

[0001] The present invention relates to semiconductor products and semiconductor devices.

[0002] In order to suppress power supply noise in a semiconductor device and operate the semiconductor device at high speed and stability, a capacitor element may be placed close to the semiconductor device. For example, a semiconductor chip and a capacitor chip are placed side by side on a substrate, and the pads of the semiconductor chip and the pads of the capacitor chip are connected to each other via terminals provided on the substrate by bonding wires. Alternatively, the pads of the semiconductor chip and the pads of the capacitor chip are connected to the substrate via bumps, and are then connected to each other via the substrate.

[0003] When a semiconductor chip and a capacitor chip are stacked on a substrate, for example, the pads of the semiconductor chip and the pads of the capacitor chip are connected to each other by bonding wires via terminals provided on the substrate. Alternatively, the pads of the semiconductor chip and the pads of the capacitor chip are connected to each other via bumps. In addition, a capacitor component having a through conductor connecting the substrate and the semiconductor chip may be provided between the substrate and the semiconductor chip.

[0004] In the so-called 2.5-dimensional packaging technology, an interposer is disposed on a substrate, and a plurality of semiconductor chips are arranged side by side on the interposer, and the plurality of semiconductor chips are connected to each other via the interposer.

[0005] JP 2001-035990 A JP 2006-041061 A JP 2007-318049 A U.S. Patent Application Publication No. 2010 / 0123215 U.S. Patent Application Publication No. 2022 / 0059452 JP 2017-228647 A JP 2018-182027 A

[0006] In semiconductor products in which multiple semiconductor devices are arranged side by side on an interposer, no method has been proposed for placing capacitors in appropriate positions to suppress noise according to the noise frequency band while suppressing increases in cost.

[0007] The present invention has been made in consideration of the above points, and aims to place capacitors that suppress noise in appropriate positions according to the frequency band of the noise while suppressing increases in costs in semiconductor products in which multiple semiconductor devices are arranged side by side on an interposer.

[0008] In one aspect of the present invention, a semiconductor product is a semiconductor product configured using a chiplet architecture, and includes an interposer having a relay wiring structure, a first semiconductor device having a first circuit for performing first signal processing and connected to a first surface of the interposer, a second semiconductor device having a second circuit for performing second signal processing and connected to the first surface of the interposer, and a third semiconductor device having a capacitor circuit and connected to the first surface of the interposer adjacent to the first semiconductor device and the second semiconductor device, wherein the capacitor circuit is electrically connected to the first semiconductor device and the second semiconductor device via a plurality of relay wirings provided in the relay wiring structure, respectively.

[0009] According to the disclosed technology, in a semiconductor product in which multiple semiconductor devices are arranged side by side on an interposer, capacitors that suppress noise according to the noise frequency band can be placed in appropriate positions while suppressing increases in cost.

[0010] 10 is a plan view showing a first embodiment of a semiconductor package. FIG. 11 is a cross-sectional view showing an example of a cross-section along line XX' of the semiconductor package of FIG. 1. FIG. 12 is a cross-sectional view showing another example of a cross-section along line XX' of the semiconductor package of FIG. 1. FIG. 13 is a cross-sectional view showing an example of a cross-section of another semiconductor package. FIG. 14 is a plan view showing an example of an improvement of an existing semiconductor package. FIG. 15 is a plan view showing another example of an improvement of an existing semiconductor package. FIG. 16 is a plan view showing a second embodiment of a semiconductor package. FIG. 17 is a plan view showing an embodiment of a capacitor chiplet. FIG. 18 is a plan view showing an example of connecting the capacitor chiplet of FIG. 8 to multiple chiplets. FIG. 19 is a diagram showing an example of connecting power lines and ground lines between the capacitor chiplet of FIG. 9 and multiple chiplets.

[0011] Hereinafter, embodiments will be described with reference to the drawings. Hereinafter, a symbol indicating a signal is also used to indicate a signal line or a signal terminal. A symbol indicating a power supply is also used to indicate a power supply line or a power supply terminal to which a power supply potential is supplied, or a ground line or a ground terminal to which a ground potential is supplied.

[0012] 1 shows a first embodiment of a semiconductor package. The semiconductor package 101 shown in FIG. 1 includes a buildup substrate BUBRD, an interposer INTP, and a stiffener STIF disposed on the buildup substrate BUBRD. The semiconductor package 101 also includes chiplets CPLT1, CPLT2, CPLT3, CPLT4, and CPLT5 disposed on the interposer INTP, and capacitor chiplets CCPLT1 and CCPLT2.

[0013] Hereinafter, when the chiplets CPLT1 to CPLT5 are described without distinction, they will also be simply referred to as chiplets CPLT. When the capacitor chiplets CCPLT1 and CCPLT2 are described without distinction, they will also be simply referred to as capacitor chiplets CCPLT.

[0014] Each chiplet CPLT has a circuit for performing signal processing. The capacitor chiplets CCPLT1 and CCPLT2 include a capacitor circuit, are arranged in a vacant area on the interposer INTP where no chiplets CPLT are arranged, and include a plurality of electrically isolated capacitor elements. By arranging the capacitor chiplets CCPLT1 and CCPLT2 in the vacant area on the interposer INTP, it is possible to eliminate steps of the chiplets CPLT on the interposer INTP and make them flat. This makes it possible to flatten the surface of a molding material that covers the chiplets CPLT and the capacitor chiplets CCPLT and is arranged on the build-up substrate BUBRD.

[0015] The semiconductor package 101 is an example of a semiconductor product configured using a chiplet architecture. The build-up substrate BUBRD is an example of a package substrate. For example, each chiplet CPLT is an example of a first semiconductor device having a first circuit that performs first signal processing, or a second semiconductor device having a second circuit that performs second signal processing. Each capacitor chiplet CCPLT is an example of a third semiconductor device adjacent to the first semiconductor device and the second semiconductor device.

[0016] An underfill UDF is filled between the buildup substrate BUBRD and the interposer INTP. The stiffener STIF is attached in an annular shape to the outer periphery of the buildup substrate BUBRD, and functions as a ring to prevent the buildup substrate BUBRD from warping.

[0017] On the interposer INTP, chiplets CPLT1 and CPLT2 are arranged adjacent to each other in the X direction, and capacitor chiplets CCPLT1, CPLT3, and CCPLT2 are arranged adjacent to each other in the X direction. Also, on the interposer INTP, chiplets CPLT4 and CPLT5 are arranged adjacent to each other in the X direction. The capacitor chiplet CCPLT1 and the chiplet CPLT3 are adjacent to the chiplets CPLT1 and CPLT4 in the Y direction. The chiplet CPLT3 and the capacitor chiplet CCPLT2 are adjacent to the chiplets CPLT2 and CPLT5 in the Y direction.

[0018] The solid lines shown between the chiplets CPLT1, CPLT2, CPLT4, CPLT5 and the chiplet CPLT3 indicate a signal line WS1 provided within the interposer INTP. The signal line WS1 is provided in a relay wiring layer within the interposer INTP. The number of signal lines WS1 is not limited to that shown in FIG. 1. The solid lines shown between the chiplets CPLT1, CPLT3, CPLT4 and the capacitor chiplet CCPLT1 indicate a power supply line WP1. The solid lines shown between the chiplets CPLT2, CPLT5 and the capacitor chiplet CCPLT2 indicate a power supply line WP1.

[0019] Since each chiplet CPLT and each capacitor chiplet CCPLT are connected via the interposer INTP, the wiring resistance can be reduced compared to when they are connected via the build-up board BUBRD.

[0020] The power supply line WP1 is provided in a relay wiring layer within the interposer INTP and includes, for example, a power supply line and a ground line. That is, the capacitor elements of the capacitor circuits included in each capacitor chiplet CCPLT are electrically connected to the chiplet CPLT via the power supply line and the ground line. The signal line WS1 is an example of relay wiring that electrically connects the chiplets CPLT. The power supply line WP1 is an example of relay wiring that electrically connects the chiplet CPLT and the capacitor chiplet CCPLT.

[0021] Each capacitor chiplet CCPLT only includes a capacitor circuit including a capacitor element connected to a power supply line and a ground line. Because each capacitor chiplet CCPLT is connected only to a power supply line and a ground line and not to a signal line, it does not include a processing circuit such as a logic circuit or an analog circuit that receives an input signal, operates, and outputs an output signal. That is, each capacitor chiplet CCPLT only includes a capacitor circuit, which is a passive element, and does not include an active circuit that performs signal processing. In other words, each capacitor chiplet CCPLT does not independently perform active signal processing to generate an output signal from an input signal. In addition to the capacitor element, the capacitor circuit may also include other passive elements, such as an electrostatic discharge (ESD) protection element.

[0022] The reference numerals (1) to (5) shown in the capacitor chiplet CCPLT1 are examples of capacitor circuit blocks having capacitor elements. The reference numerals (1), (3), and (4) shown in the capacitor chiplet CCPLT1 indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT1, CPLT3, and CPLT4, respectively, via the power line WP1. The reference numerals (2) and (5) shown in the capacitor chiplet CCPLT2 indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT2 and CPLT5, respectively, via the power line WP1. Each capacitor element functions as a decoupling capacitor for the circuit within the chiplet CPLT to which it is connected via the power line WP1.

[0023] In this way, by sharing each capacitor chiplet CCPLT arranged in the free space among multiple chiplets CPLT, it is possible to connect a capacitor circuit of an appropriate size located near each chiplet CPLT to each chiplet CPLT, thereby making it possible to appropriately suppress power supply noise according to the operating frequency, function, etc. of each chiplet CPLT.

[0024] At least one of the chiplets CPLTs is manufactured using a process rule having finer processing accuracy than the process rule used to manufacture the capacitor chiplet CCPLT. For example, the capacitor chiplet CCPLT can be manufactured using a manufacturing process that is several generations older than the manufacturing process for the chiplet CPLT. Therefore, the manufacturing cost of the capacitor chiplet CCPLT can be lower than that of the chiplet CPLT. Furthermore, compared to when a capacitor element is provided within the chiplet CPLT instead of the capacitor chiplet CCPLT, the chip size of the chiplet CPLT can be reduced and the yield, which is the rate of non-defective chiplets CPLT, can be improved, thereby reducing the manufacturing cost of the chiplet CPLT and the semiconductor package 101.

[0025] Fig. 2 shows an example of a cross section taken along line XX' of the semiconductor package 101 in Fig. 1. Fig. 2 shows an example of a system SYS1 including the semiconductor package 101 connected to a printed circuit board PCB via LSI (Large-Scale Integration) balls BALL.

[0026] In the interposer INTP, the surface facing the chiplets CPLT and capacitor chiplets CCPLT is an example of a first surface, and the surface facing the buildup substrate BUBRD is an example of a second surface. In the buildup substrate BUBRD, the surface facing the interposer INTP is an example of a third surface, and the surface facing the printed circuit board PCB is an example of a fourth surface.

[0027] Hereinafter, the surfaces of the interposer INTP, the buildup substrate BUBRD, and the printed circuit board PCB on the side of the chiplets CPLT and the capacitor chiplets CCPLT may be referred to as the "front surface."Furthermore, the surfaces of the interposer INTP, the buildup substrate BUBRD, and the printed circuit board PCB opposite the chiplets CPLT and the capacitor chiplets CCPLT may be referred to as the "back surface."

[0028] Each chiplet CPLT and capacitor chiplet CCPLT are connected to the interposer INTP via, for example, bumps BMP1. For example, the bumps BMP1 are microbumps or the like, and are arranged at a pitch of several tens of microns. The power supply terminal and ground terminal of the chiplet CPLT connected to the bumps BMP1 are connected to the power supply terminal and ground terminal of the capacitor chiplet CCPLT via power supply lines WP1 formed in the interposer INTP, respectively. The bumps BMP1 are an example of a first bump or a second bump.

[0029] The signal terminals of each chiplet CPLT are connected to the signal terminals of other chiplets CPLT or to the bumps BMP2 via signal lines WS1 (FIG. 1) (not shown) formed in the interposer INTP. The power supply terminals and ground terminals of each chiplet CPLT are connected to the bumps BMP2 via power supply lines WP1 (not shown) in the interposer INTP.

[0030] For example, the bumps BMP2 are C4 (Controlled Collapse Chip Connection) bumps or Cu pillars, and are arranged at a pitch of about 150 microns to 200 microns. The bumps BMP2 are an example of a third bump.

[0031] The buildup board BUBRD has a buildup layer BUL1 provided on the interposer INTP side, a buildup layer BUL2 provided on the printed circuit board PCB side, and a core layer CRL provided between the buildup layers BUL1 and BUL2. The buildup layers BUL1 and BUL2 have one or more wiring layers. Although not particularly limited, the thickness of the buildup board BUBRD is, for example, approximately 0.5 mm to 2 mm.

[0032] For example, bumps BMP2 electrically connected to the power supply terminal and ground terminal of the chiplet CPLT, respectively, are connected to vias VIA (penetrating electrodes) provided through the buildup layers BUL1, BUL2 and core layer CRL of the buildup substrate BUBRD. A pair of vias VIA connected to the power supply terminal and ground terminal, respectively, are connected to a pair of terminals of a capacitor CAP21 or a capacitor CAP22, such as a ceramic capacitor, arranged on the back surface of the buildup substrate BUBRD.

[0033] In the example shown in Figure 2, a capacitor CAP31 connected to a power supply line and a ground line is arranged on the front surface of the printed circuit board PCB. A capacitor CAP32 connected to a power supply line and a ground line is arranged on the back surface of the printed circuit board PCB. The capacitors CAP31 and CAP32 are ceramic capacitors or the like. The capacitors CAP31 and CAP32 are connected to the power supply line, the ground line and an LSI ball BALL via wiring in a wiring layer provided on the printed circuit board PCB, and are connected to any one of the power supply terminal and the ground terminal of the chiplet CPLT. The LSI ball BALL is an example of an external connection terminal.

[0034] For example, the capacitor chiplet CCPLT functions as a decoupling capacitor that suppresses power supply noise in the GHz band, which is a frequency band from 1 GHz to several tens of GHz. For example, the capacitors CAP21 and CAP22 function as decoupling capacitors that suppress power supply noise in a frequency band from several tens of MHz to several hundred MHz. Note that the distance between the capacitor chiplet CCPLT1 and the chiplet CPLT3 and the distance between the capacitor chiplet CCPLT2 and the chiplet CPLT3 are shorter than the distance between the capacitors CAP21 and CAP22 and the chiplet CPLT3.

[0035] For example, the capacitors CAP31 and CAP32 function as decoupling capacitors that suppress power supply noise in a frequency band from several MHz to several tens of MHz. The capacitors CAP21, CAP22, CAP31, and CAP32 are an example of a capacitor device.

[0036] FIG. 3 shows another example of a cross section of the semiconductor package 101 of FIG. 1 taken along line XX'. The same elements as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The configuration and structure of the semiconductor package 101 of FIG. 3 are the same as those of the semiconductor package 101 of FIG. 2, except that a capacitor CAP23, such as a ceramic capacitor, is disposed on the build-up substrate BUBRD. For example, the capacitor CAP23 is a ceramic capacitor or the like, and functions as a decoupling capacitor that suppresses power supply noise in a frequency band of several hundred MHz. The capacitor CAP23 is an example of a capacitor device.

[0037] For example, the capacitor CAP23 is connected to the power supply terminal and ground terminal of the chiplet CPLT3 via the power supply line WP2, the bump BMP2, the interposer INTP, and the bump BMP1 provided on the buildup layer BUL1. The capacitor CAP23 arranged on the surface of the buildup substrate BUBRD is arranged to avoid the underfill UDF, and therefore cannot be arranged in a position closer to the interposer INTP than the underfill UDF. In contrast, the capacitor chiplets CCPLT1 and CCPLT2 are arranged on the interposer INTP.

[0038] Therefore, the distance between the capacitor CAP23 and the chiplet CPLT3 is longer than the distance between the capacitor chiplet CCPLT1 and the chiplet CPLT3 and the distance between the capacitor chiplet CCPLT2 and the chiplet CPLT3. In other words, the length of the power supply line and the ground line connecting the capacitor CAP23 and the chiplet CPLT3 is longer than the length of the power supply line and the ground line connecting the capacitor chiplet CCPLT1 and the chiplet CPLT3 and the length of the power supply line and the ground line connecting the capacitor chiplet CCPLT2 and the chiplet CPLT3. Therefore, it is difficult to make the capacitor CAP23 arranged on the surface of the build-up board BUBRD function as a decoupling capacitor that suppresses power supply noise in the GHz band.

[0039] FIG. 4 shows an example of a cross section of another semiconductor package. The same elements as those in FIG. 2 are designated by the same reference numerals, and detailed description thereof will be omitted. The semiconductor package 102 in FIG. 4 has chiplets CPLT6 and CPLT7, but does not have the capacitor chiplets CCPLT1 and CCPLT2 and interposer INTP of FIG. 2. The chiplets CPLT6 and CPLT7 are connected to each other via signal lines WS2 and bumps BMP2 provided on the buildup layer BUL1. The printed circuit board PCB to which the buildup board BUBRD is connected operates as a system SYS2.

[0040] Capacitor CAP23 arranged on buildup substrate BUBRD is connected to the power supply terminal and ground terminal of chiplet CPLT6 via power line WP2 and bump BMP2 in buildup layer BUL1. Similarly, capacitor CAP24 arranged on buildup substrate BUBRD is connected to the power supply terminal and ground terminal of chiplet CPLT7 via power line WP2 and bump BMP2 in buildup layer BUL1. The other configurations and structures of semiconductor package 102 are similar to those of semiconductor package 101 in FIG. 2 .

[0041] The semiconductor package 102 does not have an interposer INTP and capacitor chiplets CCPLT1 and CCPLT2 including capacitor circuits arranged on the interposer INTP. Therefore, for example, decoupling capacitors that suppress power supply noise in the GHz band are mounted inside the chiplets CPLT6 and CPLT7. In this case, compared to when the capacitor chiplets CCPLT1 and CCPLT2 are arranged on the interposer INTP, the chip sizes of the chiplets CPLT6 and CPLT7 become larger and the yield decreases, resulting in an increase in the manufacturing costs of the chiplets CPLT and the semiconductor package 102.

[0042] Fig. 5 shows an example of an improvement to an existing semiconductor package. For the sake of simplicity, Fig. 5 shows only the interposer INTP and elements arranged on the interposer INTP. Elements that are the same as those in Fig. 1 are given the same reference numerals, and detailed descriptions thereof will be omitted.

[0043] The existing semiconductor package 103 has chiplets CPLT1-CPLT5 and dummy chiplets DMY1 and DMY2 arranged on an interposer INTP. The dummy chiplets DMY1 and DMY2 are an example of a dummy semiconductor device. The dummy chiplets DMY1 and DMY2 are arranged in a vacant area on the interposer INTP to eliminate steps on the interposer INTP. For example, adjacent chiplets CPLT are connected by a signal line WS1.

[0044] The dummy chiplets DMY1 and DMY2 have terminals for mechanically or electrically connecting to the interposer INTP via bumps BMP1 (not shown), but do not perform any signal processing. For example, the dummy chiplets DMY1 and DMY2 may have dummy circuits, but do not input or output signals to or from the outside of the dummy chiplets DMY1 and DMY2.

[0045] Semiconductor package 101 is formed by replacing dummy chiplets DMY1 and DMY2 of semiconductor package 103 with capacitor chiplets CCPLT1 and CCPLT2, each including a capacitor circuit. Semiconductor package 101 is an example of a semiconductor product configured using chiplet architecture. By replacing dummy chiplets DMY1 and DMY2 with capacitor chiplets CCPLT1 and CCPLT2, it is possible to connect an appropriate-sized capacitor circuit to each chiplet CPLT1-CPLT5 without forming a decoupling capacitor within each chiplet CPLT1-CPLT5. As a result, it is possible to suppress power supply noise in the GHz band.

[0046] Furthermore, since the formation areas of the decoupling capacitors in the chiplets CPLT1-CPLT5 can be replaced with formation areas of active elements such as transistors, it is possible to suppress an increase in chip size and improve the processing function of the chiplets CPLT1-CPLT5. Furthermore, by replacing the dummy chiplets DMY1 and DMY2 with the capacitor chiplets CCPLT1 and CCPLT2, it is possible to maintain the flatness of the upper surfaces of the chiplets CPLT and capacitor chiplets CCPLT. As a result, the surface of the molding material can be made flat.

[0047] The semiconductor package 104 is formed by replacing the dummy chiplet DMY1 of the semiconductor package 103 with a capacitor chiplet CCPLT1 including a capacitor circuit. The semiconductor package 104 is an example of a semiconductor product configured using a chiplet architecture.

[0048] For example, the semiconductor package 104 is an example of a configuration in which the operating frequencies of the chiplets CPLT2 and CPLT5 are lower than the operating frequencies of the other chiplets CPLT1, CPLT3, and CPLT4, making it less likely that power supply noise in the GHz band will occur. By replacing the dummy chiplet DMY1 with the capacitor chiplet CCPLT1, it is possible to connect appropriate-sized capacitor circuits to each of the chiplets CPLT1, CPLT3, and CPLT4. As a result, it is possible to suppress power supply noise in the GHz band in each of the chiplets CPLT1, CPLT3, and CPLT4. Meanwhile, because noise generation can be suppressed in the chiplets CPLT2 and CPLT5 without the capacitor chiplet CCPLT2, the dummy chiplet DMY2 is disposed directly on the interposer INTP.

[0049] When there is a vacant area on the interposer INTP where no chiplets CPLT and capacitor chiplets CCPLT are arranged, the surface of the molding material can be made flat by arranging dummy chiplets DMY in the vacant area.

[0050] FIG. 6 shows another example of an improvement to an existing semiconductor package. For simplicity of explanation, FIG. 5 shows only the interposer INTP and elements disposed on the interposer INTP. The existing semiconductor package 105 has chiplets CPLT8, CPLT9, CPLT10, and CPLT11 and dummy chiplets DMY3, DMY4, and DMY5 disposed on the interposer INTP. For example, similar to the semiconductor package 103 of FIG. 5, adjacent chiplets CPLT are connected by a signal line WS1.

[0051] Semiconductor package 106 is formed by replacing dummy chiplets DMY3-DMY5 of semiconductor package 105 with capacitor chiplets CCPLT3-CCPLT5, each including a capacitor circuit. Capacitor chiplets CCPLT3-CCPLT5 have different sizes, and the sizes of the capacitor circuits included therein are also different. Semiconductor package 106 is an example of a semiconductor product configured using a chiplet architecture.

[0052] Hereinafter, when the chiplets CPLT8-CPLT11 are described without distinction, they will also be simply referred to as chiplets CPLT. When the capacitor chiplets CCPLT3-CCPLT5 are described without distinction, they will also be simply referred to as capacitor chiplets CCPLT. Each capacitor element of the capacitor circuit of each capacitor chiplet CCPLT3-CCPLT5 functions as a decoupling capacitor for the circuit within the chiplet CPLT to which it is connected via the power line WP1.

[0053] Each chiplet CPLT is an example of a first semiconductor device having a first circuit that performs first signal processing, or a second semiconductor device having a second circuit that performs second signal processing. Each capacitor chiplet CCPLT is an example of a third semiconductor device adjacent to the first semiconductor device and the second semiconductor device. Dummy chiplets DMY3-DMY5 are examples of dummy semiconductor devices.

[0054] The reference numerals (8) to (11) shown in the capacitor chiplet CCPLT3 are examples of capacitor circuit blocks having capacitor elements. The reference numerals (8) and (9) shown in the capacitor chiplet CCPLT3 indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT8 and CPLT9, respectively, via the power line WP1. The reference numerals (9) and (11) shown in the capacitor chiplet CCPLT4 indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT9 and CPLT11, respectively, via the power line WP1. The reference numerals (8) and (10) shown in the capacitor chiplet CCPLT5 indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT8 and CPLT10, respectively, via the power line WP1.

[0055] For example, in semiconductor package 106, chiplet CPLT8 may be connected to multiple capacitor chiplets CCPLT3 and CCPLT5. Similarly, chiplet CPLT9 may be connected to multiple capacitor chiplets CCPLT3 and CCPLT4.

[0056] This allows a capacitor circuit of an appropriate size to be connected to each chiplet CPLT 8, CPLT 9, even when capacitor chiplets CCPLT of various different sizes are formed in an area on the interposer INTP where no chiplets CPLT are formed. As a result, power supply noise in the GHz band can be appropriately suppressed according to the operating frequency, function, etc. of each chiplet CPLT 8, CPLT 9.

[0057] Semiconductor package 107 can be formed by replacing dummy chiplets DMY3 and DMY4 of semiconductor package 105 with capacitor chiplets CCPLT3 and CCPLT4 including capacitor circuits. Semiconductor package 107 is an example of a semiconductor product configured using a chiplet architecture.

[0058] 5 , semiconductor package 107 is an example of a configuration in which the operating frequency of chiplet CPLT10 is lower than the operating frequencies of the other chiplets CPLT8, CPLT9, and CPLT11, making it less likely for power supply noise in the GHz band to occur. By replacing dummy chiplets DMY3 and DMY4 with capacitor chiplets CCPLT3 and CCPLT4, capacitor circuits of appropriate sizes can be connected to each chiplet CPLT8, CPLT9, and CPLT11. As a result, power supply noise in the GHz band can be suppressed in each chiplet CPLT8, CPLT9, and CPLT11. Meanwhile, chiplet CPLT10 can suppress noise generation without capacitor chiplet CCPLT5, so dummy chiplet DMY5 is left in place.

[0059] As described above, in the first embodiment of the semiconductor package, a capacitor chiplet CCPLT including only a capacitor circuit is arranged adjacent to a plurality of chiplets CPLT on the interposer INTP. The plurality of chiplets CPLT are connected to a plurality of capacitor circuit blocks in the capacitor chiplet CCPLT via power lines and ground lines in the interposer INTP. This allows the capacitor chiplet CCPLT arranged in an area on the interposer INTP where no chiplets CPLT are arranged to function as a decoupling capacitor for the plurality of chiplets CPLT.

[0060] Furthermore, since the chiplets CPLT and the capacitor chiplets CCPLT are connected via the interposer INTP, the wiring resistance can be reduced compared to when they are connected via the build-up substrate BUBRD. Since the capacitor chiplets CCPLT can be arranged near the chiplets CPLT, the capacitor chiplets CCPLT can function as a decoupling capacitor that suppresses power supply noise in the GHz band.

[0061] A capacitor chiplet CCPLT including only a capacitor circuit can be manufactured using, for example, a manufacturing process several generations older than the manufacturing process for the chiplet CPLT, thereby reducing manufacturing costs compared to the chiplet CPLT. Furthermore, because a decoupling capacitor does not need to be included in the chiplet CPLT, the chip size of the chiplet CPLT can be reduced, and the yield of the chiplet CPLT can be improved, thereby reducing manufacturing costs for the chiplet CPLT and the semiconductor packages 101, 104, 106, and 107. As a result, semiconductor packages 101, 104, 106, and 107 having decoupling capacitors that suppress power supply noise in the GHz band can be formed at low manufacturing costs.

[0062] For example, the capacitor chiplets CCPLT are arranged in place of the dummy chiplets DMY in an empty area on the interposer INTP where the chiplets CPLT are not arranged, thereby suppressing steps on the interposer INTP and flattening the surface of the molding material, and the capacitor chiplets CCPLT can function as a decoupling capacitor that suppresses power supply noise in the GHz band.

[0063] By sharing the capacitor chiplet CCPLT arranged in the free space among multiple chiplets CPLT, it is possible to connect an appropriate sized capacitor circuit arranged near each chiplet CPLT to each chiplet CPLT, thereby appropriately suppressing power supply noise according to the operating frequency, function, etc. of each chiplet CPLT.

[0064] When there is a vacant area on the interposer INTP where no chiplets CPLT and capacitor chiplets CCPLT are arranged, the surface of the molding material can be made flat by arranging dummy chiplets DMY in the vacant area.

[0065] A capacitor CAP connected to the power supply line VDD and the ground line VSS is disposed on one or both of the buildup board BUBRD that connects the interposer INTP and the printed circuit board PCB to which the buildup board BUBRD is connected. Therefore, the capacitor chiplets CCPLT and the capacitor CAP can suppress power supply noise in multiple frequency bands.

[0066] As described above, in a semiconductor package in which a plurality of chiplets CPLT are arranged side by side, the capacitor chiplets CCPLT and the capacitors CAP can be arranged in appropriate positions according to the noise frequency band while suppressing increases in cost, thereby forming semiconductor packages 101, 104, 106, and 107 that can appropriately suppress power supply noise in each frequency band.

[0067] 7 shows a second embodiment of the semiconductor package. Elements similar to those in the first embodiment are designated by the same reference numerals, and detailed descriptions thereof will be omitted. For simplicity of explanation, FIG. 7 also shows only the interposer INTP and elements disposed on the interposer INTP.

[0068] 1 and 2, the semiconductor package 108 shown in Fig. 7 has a build-up board BUBRD (not shown) on which an interposer INTP is arranged. The build-up board BUBRD is mounted on a printed circuit board PCB (not shown), and the semiconductor package 108 operates as a system. The semiconductor package 108 is an example of a semiconductor product configured using a chiplet architecture.

[0069] 7, the area in which the chiplets CPLT12 and CPLT13 are arranged is rectangular and does not have a step where the dummy chiplet DMY is arranged. Therefore, when capacitor chiplets CCPLT6-CCPLT9 including capacitor circuits that function as decoupling capacitors are required, the capacitor chiplets CCPLT6-CCPLT9 are arranged around the chiplets CPLT12 and CPLT13. The solid line between the chiplet CPLT12 and the chiplet CPLT13 indicates the signal line WS1.

[0070] Hereinafter, when there is no need to distinguish between the chiplets CPLT12 and CPLT13, they will also be simply referred to as the chiplet CPLT. When there is no need to distinguish between the capacitor chiplets CCPLT6-CCPLT9, they will also be simply referred to as the capacitor chiplets CCPLT.

[0071] Each chiplet CPLT is an example of a first semiconductor device having a first circuit for performing first signal processing, or a second semiconductor device having a second circuit for performing second signal processing. Each capacitor chiplet CCPLT is an example of a third semiconductor device adjacent to the first semiconductor device and the second semiconductor device.

[0072] Capacitor chiplet CCPLT6 is connected to chiplets CPLT12 and CPLT13. Capacitor chiplet CCPLT7 is connected to chiplet CPLT12. Capacitor chiplet CCPLT8 is connected to chiplet CPLT13. Capacitor chiplet CCPLT9 is connected to chiplets CPLT12 and CPLT13.

[0073] As in Figures 5 and 6, the reference numerals (12) and (13) shown in the capacitor chiplets CCPLT6 and CCPLT9, respectively, are examples of capacitor circuit blocks having capacitor elements, and indicate capacitor circuit blocks including capacitor elements connected to the chiplets CPLT12 and CPLT13, respectively, via the power supply line WP1.

[0074] If there is no step on which to place the dummy chiplet DMY and a decoupling capacitor for suppressing power supply noise in the GHz band is required, a capacitor element may be formed in the chiplets CPLT12 and CPLT13. However, if a capacitor element is formed in the chiplets CPLT12 and CPLT13 that are manufactured using a process rule with fine processing accuracy, the chip size increases, the yield decreases, and as a result, the chip cost increases.

[0075] Therefore, in the semiconductor package 108, capacitor chiplets CCPLT6-CCPLT9 are arranged on the interposer INTP separately from the chiplets CPLT12 and CPLT13. In this case, by arranging the capacitor chiplets CCPLT6-CCPLT9 around the chiplets CPLT12 and CPLT13 in a plan view, it is possible to minimize the propagation delay time of signals between the chiplets CPLT12 and CPLT13. By arranging the capacitor chiplets CCPLT6-CCPLT9 around the chiplets CPLT12 and CPLT13 in a plan view, the size of the interposer INTP increases. However, since the capacitor chiplets CCPLT can be manufactured using a manufacturing process that is several generations older than the manufacturing process for the chiplets CPLT, for example, the manufacturing cost can be lower than that of the chiplets CPLT, and therefore an increase in the total cost of the semiconductor package 108 can be suppressed.

[0076] As described above, the second embodiment of the semiconductor package can also achieve the same effects as the first embodiment of the semiconductor package. For example, capacitor chiplets CCPLT that can be manufactured using an older manufacturing process than the chiplets CPLT can be arranged on the interposer INTP. This allows the capacitor chiplets CCPLT to be arranged near the chiplets CPLT while reducing manufacturing costs, and the capacitor chiplets CCPLT can function as a decoupling capacitor that suppresses power supply noise in the GHz band.

[0077] Furthermore, in the second embodiment of the semiconductor package, when there is no step between the plurality of chiplets CPLT arranged on the interposer INTP for arranging the dummy chiplets DMY, the capacitor chiplets CCPLT are arranged around the chiplets CPLT. This makes it possible to suppress the generation of power supply noise in the GHz band and to suppress an increase in the total cost of the semiconductor package 108 compared to the case where a capacitor element is formed inside the chiplet CPLT.

[0078] As described above, in the semiconductor package 108 in which a plurality of chiplets CPLT are arranged side by side, the capacitor chiplets CCPLT and the capacitor CAP (not shown) can be arranged in appropriate positions according to the frequency band of the noise while suppressing an increase in cost, thereby making it possible to appropriately suppress power supply noise in each frequency band.

[0079] FIG. 8 shows one embodiment of a capacitor chiplet. The capacitor chiplet CCPLT shown in FIG. 8 is an example of a semiconductor device and has a capacitor circuit including nine capacitor groups CAPG0-CAPG8. That is, the capacitor circuit of the capacitor chiplet CCPLT includes nine capacitor groups CAPG0-CAPG8, and the capacitor groups CAPG0-CAPG8 are an example of a capacitor circuit block having capacitor elements. Like the capacitor chiplet CPLT shown in FIG. 1, etc., each capacitor group CAPG0-CAPG8 only has a capacitor circuit including capacitor elements connected only to power lines and ground lines. Each capacitor group CAPG0-CAPG8 is connected only to power lines and ground lines and is not connected to signal lines, and therefore does not include processing circuits such as logic circuits or analog circuits that receive input signals, operate, and output output signals. That is, each capacitor group CAPG0-CAPG8 only includes capacitor circuits, which are passive elements, and does not include active circuits that perform signal processing. In other words, each of the capacitor groups CAPG0-CAPG8 does not have the function of independently performing active signal processing to generate an output signal from an input signal. Note that the capacitor circuit may include other passive elements, such as electrostatic discharge (ESD) protection elements, in addition to the above-mentioned capacitor elements.

[0080] In the following description, when there is no need to distinguish between the capacitor groups CAPG0 to CAPG8, they will also be simply referred to as the capacitor group CAPG. The capacitor groups CAPG0 to CAPG8 each have independent power supply terminals VDD0 to VDD8 and ground terminals VSS0 to VSS8.

[0081] Each capacitor group CAPG may include, for example, a metal-oxide-metal (MOM) capacitor having a pair of comb-shaped opposing electrodes, one of which is electrically connected to a power supply line VDD and the other of which is electrically connected to a ground line VSS. The MOM capacitor is an example of a capacitor element. The MOM capacitors may be formed in multiple wiring layers. In this case, a capacitor can be formed between wiring layers by interchanging the patterns of the power supply line VDD and the ground line VSS in adjacent wiring layers. Each capacitor group CAPG may also be formed by a metal-insulator-metal (MIM) capacitor or a gate capacitance of a transistor, or may be a combination of a MOM capacitor, a MIM capacitor, and a gate capacitance of a transistor.

[0082] Fig. 9 shows an example of connecting the capacitor chiplet CCPLT of Fig. 8 to multiple chiplets CPLT. For example, in Fig. 9, a semiconductor package 109 on which the capacitor chiplet CCPLT of Fig. 8 is mounted has chiplets CPLT-A, CPLT-B, and CPLT-C connected to the capacitor chiplet CCPLT. The semiconductor package 109 is an example of a semiconductor product configured using a chiplet architecture.

[0083] Hereinafter, when the chiplets CPLT-A, CPLT-B, and CPLT-C are described without distinction, they will also be simply referred to as chiplets CPLT. Each chiplet CPLT is an example of a first semiconductor device having a first circuit that performs first signal processing, or a second semiconductor device having a second circuit that performs second signal processing. The capacitor chiplet CCPLT is an example of a third semiconductor device adjacent to the first semiconductor device and the second semiconductor device.

[0084] The chiplet CPLT-A is connected to the capacitor elements of the capacitor groups CAPG3, CAPG4, CAPG6, and CAPG7 (capacitor circuit blocks) via a power supply line VDDA and a ground line VSSA formed on the interposer INTP (not shown). The capacitor elements of the capacitor groups CAPG3, CAPG4, CAPG6, and CAPG7 (capacitor circuit blocks) function as decoupling capacitors for the circuits within the chiplet CPLT-A and suppress power supply noise in the GHz band.

[0085] The power supply line VDDA is electrically connected to the power supply terminals VDD3, VDD4, VDD6, and VDD7 of the capacitor groups CAPG3, CAPG4, CAPG6, and CAPG7. The ground line VSSA is electrically connected to the ground terminals VSS3, VSS4, VSS6, and VSS7 of the capacitor groups CAPG3, CAPG4, CAPG6, and CAPG7.

[0086] The chiplet CPLT-B is connected to the capacitor elements of the capacitor groups CAPG0 and CAPG1 (capacitor circuit block) via a power supply line VDDB0 and a ground line VSSB0 formed on the interposer INTP (not shown). Furthermore, the chiplet CPLT-B is connected to the capacitor elements of the capacitor group CAPG2 (capacitor circuit block) via a power supply line VDDB1 and a ground line VSSB1 formed on the interposer INTP (not shown).

[0087] The capacitor elements of the capacitor groups CAPG0 and CAPG1 (capacitor circuit blocks) function as decoupling capacitors for the circuit to which the power supply line VDDB0 and ground line VSSB0 in the chiplet CPLT-B are connected. The capacitor elements of the capacitor group CAPG2 (capacitor circuit block) function as decoupling capacitors for the circuit to which the power supply line VDDB1 and ground line VSSB1 in the chiplet CPLT-B are connected.

[0088] The power supply line VDDB0 is electrically connected to the power supply terminals VDD0 and VDD1 of the capacitor groups CAPG0 and CAPG1. The ground line VSSB0 is electrically connected to the ground terminals VSS0 and VSS1 of the capacitor groups CAPG0 and CAPG1. The power supply line VDDB1 is electrically connected to the power supply terminal VDD2 of the capacitor group CAPG2. The ground line VSSB1 is electrically connected to the ground terminal VSS2 of the capacitor group CAPG2.

[0089] The chiplet CPLT-C is connected to the capacitor elements of the capacitor groups CAPG5 and CAPG8 (capacitor circuit blocks) via a power supply line VDDC and a ground line VSSC formed on the interposer INTP (not shown). The capacitor elements of the capacitor groups CAPG5 and CAPG8 (capacitor circuit blocks) function as decoupling capacitors for the circuits within the chiplet CPLT-C.

[0090] The power supply line VDDC is electrically connected to the power supply terminals VDD5 and VDD8 of the capacitor groups CAPG5 and CAPG8. The ground line VSSC is electrically connected to the ground terminals VSS5 and VSS8 of the capacitor groups CAPG5 and CAPG8.

[0091] The power supply lines VDDA, VDDB0, VDDB1, and VDDC and the ground lines VSSA, VSSB0, VSSB1, and VSSC are relay wirings corresponding to the power supply line WP1 shown in FIG. 1 and other figures. Hereinafter, when the power supply lines VDDA, VDDB0, VDDB1, and VDDC are described without distinction, they will also be simply referred to as the power supply line VDD. When the ground lines VSSA, VSSB0, VSSB1, and VSSC are described without distinction, they will also be simply referred to as the ground line VSS.

[0092] Each of the capacitor groups CAPG3, CAPG4, CAPG6, CAPG7 and the capacitor groups CAPG0, CAPG1 is an example of a subset of the plurality of capacitor groups CAPG (capacitor circuit blocks). Also, each of the capacitor groups CAPG2, CAPG5, CAPG8 is an example of a subset of the plurality of capacitor groups CAPG (capacitor circuit blocks). Each of the power supply line VDDA / ground line VSSA, the power supply line VDDB0 / ground line VSSB0, the power supply line VDDB1 / ground line VSSB1, and the power supply line VDDC / ground line VSSC is an example of a subset of the plurality of relay wirings.

[0093] Fig. 10 shows an example of the connection of the power supply line VDD and the ground line VSS between the capacitor chiplet CCPLT and the plurality of chiplets CPLT in Fig. 9. The connection relationship of the power supply line VDD and the ground line VSS shown in Fig. 10 is the same as that in Fig. 9.

[0094] As described above, the embodiment of the capacitor chiplet can also achieve the same effects as the first embodiment of the semiconductor package. For example, the capacitor chiplet CCPLT, which can be manufactured using a process rule of an older generation than the chiplet CPLT, can be arranged on the interposer INTP. This reduces manufacturing costs and allows the capacitor chiplet CCPLT to be arranged near the chiplet CPLT, allowing the capacitor chiplet CCPLT to function as a decoupling capacitor that suppresses power supply noise in the GHz band.

[0095] Furthermore, in one embodiment of the capacitor chiplet, the capacitor circuit of the capacitor chiplet CCPLT is divided into a plurality of capacitor groups CAPG (capacitor circuit blocks), and the number of capacitor groups CAPG corresponding to the operating frequency, function, etc. of the chiplet CPLT is connected to each chiplet CPLT. This makes it possible to connect a capacitor circuit of an appropriate size to each chiplet CPLT, and to appropriately suppress power supply noise according to the operating frequency, function, etc. of each chiplet CPLT.

[0096] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0097] 101, 102, 103, 104 Semiconductor package 105, 106, 107, 108 Semiconductor package BALL LSI ball BMP1, BMP2 Bump BUBRD Build-up substrate BUL1, BUL2 Build-up layer CAP21-CAP23 Capacitor CAP31, CAP32 Capacitor CAPG0-CAPG8 Capacitor group CCPLT1-CCPLT9 Capacitor chiplet CPLT-A, CPLT-B, CPLT-C Chiplet CPLT1-CPLT13 Chiplet CRL Core layer DMY1-DMY5 Dummy chiplet INTP Interposer PCB Printed circuit board STIF Stiffener UDF Underfill VDDA, VDDB0, VDDB1, VDDC Power supply lines VIA Via VSSA, VSSB0, VSSB1, VSSC Ground lines WP1 Power supply line WS1 Signal line

Claims

1. A semiconductor product configured with a chiplet architecture, comprising: an interposer having an interconnection structure; a first semiconductor device having a first circuit performing a first signal processing and connected to a first surface of the interposer; a second semiconductor device having a second circuit performing a second signal processing and connected to the first surface of the interposer; and a third semiconductor device having a capacitor circuit and connected to the first surface of the interposer adjacent to the first semiconductor device and the second semiconductor device, wherein the capacitor circuit is electrically connected to the first semiconductor device and the second semiconductor device via a plurality of interconnections provided in the interconnection structure.

2. The semiconductor product according to claim 1, wherein at least one of the first semiconductor device and the second semiconductor device is manufactured by a process rule having a finer processing accuracy than the process rule used to manufacture the third semiconductor device.

3. The semiconductor product according to claim 1, further comprising a dummy semiconductor device that is connected to said first surface of said interposer and does not perform any signal processing.

4. The semiconductor product according to claim 1, wherein said capacitor circuit is electrically connected to a power supply terminal and a ground terminal of said first semiconductor device and said second semiconductor device via said relay wiring structure.

5. The semiconductor product described in claim 4, wherein the capacitor circuit includes at least a first capacitor element and a second capacitor element, the first capacitor element functions as a decoupling capacitor for the first circuit of the first semiconductor device, and the second capacitor element functions as a decoupling capacitor for the second circuit of the second semiconductor device.

6. The semiconductor product according to claim 5, wherein the decoupling capacitor is configured to suppress power supply noise in the GHz range.

7. The semiconductor product of claim 1, wherein the capacitor circuit includes a plurality of capacitor circuit blocks each having a capacitor element, a first subset of the plurality of capacitor circuit blocks being electrically connected to a power supply terminal and a ground terminal of the first semiconductor device via a first subset of the plurality of relay wirings, and a second subset of the plurality of capacitor circuit blocks being electrically connected to a power supply terminal and a ground terminal of the second semiconductor device via a second subset of the plurality of relay wirings.

8. The semiconductor product according to claim 7, wherein each of the plurality of capacitor circuit blocks is connected to a pair of a power supply line and a ground line that are different from each other.

9. The semiconductor product of claim 7, wherein the first subset of the plurality of capacitor circuit blocks functions as a decoupling capacitor for the first circuit of the first semiconductor device, and the second subset of the plurality of capacitor circuit blocks functions as a decoupling capacitor for the second circuit of the second semiconductor device.

10. The semiconductor product according to claim 1, wherein said third semiconductor device does not have a function of independently executing active signal processing for generating an output signal in response to an input signal.

11. The semiconductor product according to claim 1, wherein said third semiconductor device is composed only of passive elements including a capacitor element included in said capacitor circuit.

12. The semiconductor product according to claim 1, further comprising a package substrate having a third surface connected to a second surface of the interposer different from the first surface, and having an external connection terminal on a fourth surface different from the third surface.

13. The semiconductor product of claim 12, wherein the first semiconductor device is connected to the first surface of the interposer via a first bump having a first size, the second semiconductor device is connected to the first surface of the interposer via a second bump having the first size, and the package substrate is connected to the second surface of the interposer via a third bump having a second size larger than the first size.

14. The semiconductor product of claim 12, further comprising a capacitor device connected to either the third surface or the fourth surface, or to both the third surface and the fourth surface, of the package substrate, wherein a distance between the third semiconductor device and the first semiconductor device and a distance between the third semiconductor device and the second semiconductor device are each shorter than a distance between the capacitor device and the interposer.

15. The semiconductor product of claim 1, wherein the first semiconductor device, the second semiconductor device, and the third semiconductor device are each a chiplet.

16. A semiconductor device having a capacitor circuit including a plurality of capacitor circuit blocks each having a capacitor element and connected to different pairs of power supply lines and ground lines, and which does not have the function of independently performing active signal processing to generate an output signal in response to an input signal.

17. The semiconductor device according to claim 16, which is constituted only by passive elements including the capacitor element included in the capacitor circuit.

18. The semiconductor device according to claim 16, wherein said capacitor circuit is electrically connected to a power supply terminal and a ground terminal of at least one other semiconductor device.

19. The semiconductor device according to claim 18, wherein the capacitor element included in the capacitor circuit functions as a decoupling capacitor for a circuit included in the other semiconductor device.

20. The semiconductor device according to claim 19, wherein the decoupling capacitor is configured to suppress power supply noise in the GHz band.

21. The semiconductor device of claim 16, wherein a first subset of the plurality of capacitor circuit blocks is electrically connected to a power supply terminal and a ground terminal of a first semiconductor device among the other semiconductor devices, and a second subset of the plurality of capacitor circuit blocks is electrically connected to a power supply terminal and a ground terminal of a second other semiconductor device different from the first semiconductor device among the other semiconductor devices.

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