Measurement circuit and semiconductor integrated circuit

Abstract

A measurement circuit according to the present invention includes a first switch circuit that switches the connection between respective emitter nodes of first and second bipolar transistors and a voltage measurement node supplied with a voltage to be measured, and a differential input of an analog-to-digital conversion circuit. By switching the connection of the first switch circuit according to a plurality of measurement modes for measuring a plurality of types of physical quantities, respectively, it is possible to suppress a decrease in the accuracy of the measurement value of each of the physical quantities measured according to the measurement mode.

Description

Measuring circuit and semiconductor integrated circuit

[0001] The present invention relates to a measurement circuit and a semiconductor integrated circuit.

[0002] Conventionally, thermometer circuits for measuring silicon junction temperatures have been integrated into semiconductor integrated circuits in some cases. For example, in processors for PCs and servers, mobile SoCs (System on Chip), and the like, temperatures are detected using thermometer circuits integrated on silicon dies (see, for example, Patent Documents 1 and 2).

[0003] Temperature information indicating the temperature measured by the thermometer circuit is used to control clock frequencies, compensate for the temperature characteristics of RF (Radio Frequency) circuits that are highly temperature sensitive, etc. Furthermore, in systems installed in vehicles and the like that require reliability, the temperature information is used, for example, to monitor whether the temperatures of devices included in the system are within an allowable range.

[0004] Furthermore, in order to improve power efficiency, a dynamic voltage and frequency scaling (DVFS) technique is known that dynamically controls the power supply voltage in addition to the clock frequency. SoCs and the like that apply the DVFS technique measure voltage using, for example, a voltmeter circuit integrated on the device, and control the power supply voltage based on the measured voltage value.

[0005] Also, a technique is known in which a voltmeter circuit is integrated on a device by using part of a thermometer circuit integrated on the device (see, for example, Patent Document 9).

[0006] JP 2015-190799 A, International Publication No. 2018 / 211554, JP 2010-170470 A, JP 2011-186744 A, JP 2014-016860 A, JP 2013-55450 A, JP 2016-111563 A, JP 2019-095271 A, U.S. Patent Application Publication No. 2018 / 0292271 Specification, U.S. Patent Application Publication No. 2023 / 0140251 Specification, JP 2017-198523 A

[0007] Akira Yukawa, "Oversampling A-D Conversion Technology", Nikkei BP, 1990 Richard Schreier and Gabor C. Temes, Takao Waho and Akira Yasuda, "Introduction to Delta-Sigma Analog-Digital Converters", Maruzen, 2007

[0008] One or more sets of thermometer circuits and voltmeter circuits may be integrated into various semiconductor integrated circuits such as SoCs. For example, if multiple CPU (Central Processing Unit) cores are integrated into a single silicon die that functions as a semiconductor integrated circuit and temperature and voltage are measured for each CPU core, the number of thermometer circuits and voltmeter circuits increases in proportion to the number of CPU cores.

[0009] By sharing part of the thermometer circuit and the voltmeter circuit, the circuit area becomes smaller than when the thermometer circuit and the voltmeter circuit are provided separately. However, no specific method has been proposed to prevent a decrease in the accuracy of the temperature and voltage measurements when the thermometer circuit and the voltmeter circuit share part of the circuit.

[0010] The present invention has been made in consideration of the above points, and aims to suppress a decrease in the accuracy of the measurement values ​​of each physical quantity when a common circuit is used to measure each of multiple types of physical quantities according to a measurement mode.

[0011] In one aspect of the present invention, the measurement circuit includes a first field effect transistor and a first bipolar transistor connected via a first node between a first power supply line and a second power supply line, a second field effect transistor and a second bipolar transistor connected via a second node between the first power supply line and a second power supply line, an analog-to-digital conversion circuit that converts an analog voltage indicating a difference between a voltage at a first differential input node and a voltage at a second differential input node into a digital output value using the voltage at the first node as a reference voltage and outputs the digital output value, and a first switch circuit that is provided between a voltage measurement node to which the voltage to be measured is supplied, an input node including the first node and the second node, and an output node including the first differential input node and the second differential input node, and that switches a connection between the input node and the output node according to a plurality of measurement modes for measuring each of a plurality of types of physical quantities.

[0012] According to the disclosed technology, when a common circuit is used to measure each of a plurality of physical quantities according to a measurement mode, it is possible to suppress a decrease in the accuracy of the measurement values ​​of each physical quantity.

[0013] 11 is a circuit diagram showing an example of a thermometer circuit. FIG. 12 is a circuit diagram showing an example of a voltmeter circuit. FIG. 13 is a circuit diagram showing an example of a measurement circuit in the first embodiment. FIG. 14 is a timing diagram showing an example of the operation of the measurement circuit of FIG. 3. FIG. 15 is a circuit diagram showing an example of a measurement circuit in the second embodiment. FIG. 16 is a circuit diagram showing an example of a measurement circuit in the third embodiment. FIG. 17 is a timing diagram showing an example of the operation of the measurement circuit of FIG. 6. FIG. 18 is a circuit diagram showing an example of a measurement circuit in the fourth embodiment. FIG. 19 is a timing diagram showing an example of the operation of the measurement circuit of FIG. 8. FIG. 19 is a circuit diagram showing an example of a measurement circuit in the fifth embodiment. FIG. 19 is a timing diagram showing an example of the operation timing of the measurement circuit of FIG. 10, which is different from that of FIG. 9. FIG. 19 is a circuit diagram showing an example of the operational amplifiers and switches of FIGS. 8 and 10. FIG. 19 is a circuit diagram showing an example of a main part of a measurement circuit in the sixth embodiment. FIG. 20 is a block diagram showing an example of a semiconductor integrated circuit in which any of the measurement circuits of the above-mentioned embodiments is mounted.

[0014] Hereinafter, embodiments will be described with reference to the drawings. In the following, a symbol indicating a signal is also used to indicate a signal line, a signal terminal, or a signal node. A symbol indicating a voltage is also used to indicate a voltage line, a voltage terminal, or a voltage node to which a voltage is supplied.

[0015] Fig. 1 shows an example of a thermometer circuit. Note that Fig. 1 shows the minimum elements required to measure temperature. The thermometer circuit 10 shown in Fig. 1 includes P-channel MOS (Metal Oxide Semiconductor) transistors M1 and M2, PNP transistors Q1 and Q2, a resistor R1, an operational amplifier AMP, an analog-to-digital converter (ADC), and an arithmetic circuit OPC.

[0016] Hereinafter, the PNP transistors Q1 and Q2 will also be simply referred to as transistors Q1 and Q2, and the P-channel MOS transistors M1 and M2 will also be simply referred to as transistors M1 and M2. The analog-to-digital conversion circuit ADC will also be simply referred to as ADC.

[0017] The transistors M1 and Q1 are connected in series between the power supply line VDD and the ground line GND via a node VBE1. The gate of the transistor M1 is connected to the output terminal of the operational amplifier AMP via a feedback node FB. The base of the transistor Q1 is connected to the ground line GND. A node VBE1 connected between the drain of the transistor M1 and the emitter of the transistor Q1 is connected to the negative input of the operational amplifier AMP, the positive input terminal VIP of the ADC, and the reference voltage terminal VREF of the ADC.

[0018] The transistor M2, resistor R1, and transistor Q2 are connected in series between the power supply line VDD and the ground line GND via nodes V1 and VBE2, which are nodes at both ends of the resistor R1. The gate of the transistor M2 is connected to the output terminal of the operational amplifier AMP via a feedback node FB. The base of the transistor Q2 is connected to the ground line GND. A node V1, which is connected to the drain of the transistor M2 and one end of the resistor R1, is connected to the + input of the operational amplifier AMP. A node VBE2, which is connected to the other end of the resistor R1 and the emitter of the transistor Q2, is connected to the negative input terminal VIM of the ADC.

[0019] The symbols x15 and x1 next to transistors M1 and M2 indicate that the channel width of transistor M1 is 15 times that of transistor M2. The symbols 15xI and I next to transistors Q1 and Q2 indicate that the emitter current of transistor Q1 is 15 times that of transistor Q2.

[0020] The power supply line VDD is an example of a first power supply line, and the ground line GND is an example of a second power supply line. The node VBE1 is an example of a first node, and the node VBE2 is an example of a second node. The node V1 is an example of a third node. The transistor M1 is an example of a first field effect transistor, and the transistor M2 is an example of a second field effect transistor. The transistor Q1 is an example of a first bipolar transistor, and the transistor Q2 is an example of a second bipolar transistor.

[0021] The positive input terminal VIP is an example of a first differential input node, and the negative input terminal VIM is an example of a second differential input node. The operational amplifier AMP is an example of a comparison circuit that receives the voltages of the nodes VBE1 and V1 at its differential input node, compares them, and outputs a voltage indicating the comparison result to the gates of the transistors M1 and M2.

[0022] In the thermometer circuit 10, the drain current of transistor M1 is supplied to the emitter of transistor Q1. The drain current of transistor M2 is supplied to the emitter of transistor Q2 via resistor R1. The operational amplifier AMP operates as a negative feedback circuit, and if the gain of the operational amplifier AMP is sufficiently large, the voltages VBE1 and V1 stabilize at approximately the same potential.

[0023] If the base-emitter voltage (forward voltage of PN junction) of a BJT (Bipolar Junction Transistor) is VBE, VBE is expressed by the following equation (1): VBE=Veg-a·T (1)

[0024] In equation (1), Veg represents the bandgap voltage of silicon, T represents absolute temperature, and a represents the temperature coefficient of the voltage VBE. Here, Veg is known to be approximately 1.2 V, and the value of a is known to be approximately 2 mV / °C. Therefore, when T = 300 K, VBE is approximately 600 mV. Equation (1) indicates that VBE has a negative proportionality coefficient with respect to temperature.

[0025] The relationship between the emitter current IE and the voltage VBE of the BJT is expressed by equation (2). In equation (2), I0 is a constant proportional to the emitter area of ​​the BJT, q is the electron charge, and k is the Boltzmann constant. IE = I0 exp{q VBE / (k T)} (2)

[0026] As described above, the negative feedback control of the operational amplifier AMP causes the input voltages VBE1 and V1 of the operational amplifier AMP to converge to the same potential. The transistors M1 and M2 share a gate and source, and the channel width of the transistor M1 is 15 times the channel width of the transistor M2. Therefore, if the drain current of the transistor M2 is I, the drain current of the transistor M1 is 15×I. Therefore, from equation (2), equations (3) and (4) can be obtained. 15×I=I0·exp{q·VBE1 / (k·T)} (3) I=I0·exp{q·VBE2 / (k·T)} (4)

[0027] Dividing equation (3) by equation (4) gives equation (5). If VBE1-VBE2=ΔVBE, equation (5) can be expressed as equation (6). 15=exp{q·VBE1 / (k·T)-q·VBE2 / (k·T)} (5) ΔVBE=k·T / (q·ln15) (6)

[0028] From equation (6), ΔVBE is expressed as the product of the thermal voltage k·T / q and the logarithm of the current ratio of the transistors Q1 and Q2, and has a positive proportionality coefficient with respect to the temperature.

[0029] The relationship between the input and output of the ADC is expressed by equation (7). In equation (7), Dout represents the digital output value output from the ADC. The ADC outputs the ratio of the difference between the positive input voltage VIP and the negative input voltage VIM to the reference voltage VREF as the digital output value Dout to the arithmetic circuit OPC. The arithmetic circuit OPC performs an arithmetic operation to calculate the temperature of the thermometer circuit 10 based on the digital output value Dout, and outputs the calculated temperature as a temperature measurement value Tread (arithmetic operation result). Dout = (VIP - VIM) / VREF (7)

[0030] The positive input terminal VIP and the negative input terminal VIM of the ADC are connected to the nodes VBE1 and VBE2, respectively, and the reference voltage terminal VREF is connected to the node VBE1, so that equation (7) can be expressed as equation (8): Dout=(VBE1-VBE2) / VBE1=ΔVBE / VBE1 (8)

[0031] By substituting equations (1) and (6) into equation (8), equation (9) is obtained: Dout = {k T / (q ln15)} / (Veg - a T) (9)

[0032] The numerator of equation (9) has a positive proportionality coefficient with respect to the temperature T, and the denominator of equation (9) has a negative proportionality coefficient with respect to the temperature T. Since the temperature T appears in the numerator and denominator of equation (9), it is not suitable to use the measured value of the digital output value Dout as the temperature measured value Tread indicating the temperature. Therefore, as shown in equation (3) of Patent Document 1, the mathematical model of the thermometer circuit 10 is given by equation (10). In equation (10), A, B, and g are constants. Tread=A+B·ΔVBE / (VBE1+g·ΔVBE) (10)

[0033] Extracting the denominator of the second term on the right side of equation (10) gives equation (11): VBE1+g·ΔVBE (11)

[0034] As explained in equation (1), VBE1 has a negative proportionality coefficient of -a (approximately -2 mV / °C) with respect to temperature. As shown in equation (6), ΔVBE has a positive proportionality coefficient of k / (q ln15) ≈ +233 μV / °C with respect to temperature. Therefore, if g is set to 2 mV / 233 μV ≈ 8.6, equation (11) can be made constant with respect to temperature. If g is set to 8.6, the denominator of the second term on the right-hand side of equation (10) becomes constant, so the temperature measurement value Tread can be made proportional to the temperature.

[0035] Here, the output voltage value Dout output by the ADC is expressed by the above-mentioned equation (8). Therefore, by dividing the numerator and denominator of the second term of equation (10) by VBE1, it can be transformed into equation (12). Tread = A + B (ΔVBE / VBE1) / {1 + g (ΔVBE / VBE1)} = A + B Dout / (1 + g Dout) (12)

[0036] Based on the model of equation (12), ΔVBE / VBE1 is the digital output value Dout of the ADC (equation (8)). Therefore, the arithmetic circuit OPC can directly calculate the temperature as the measured temperature value Tread by applying the digital output value Dout output from the ADC and constants A, B, and g to equation (12). Note that the constants A, B, and g can be calculated in advance by measuring the temperature characteristics of the BJT.

[0037] Figure 2 shows an example of a voltmeter circuit. For example, when dynamically controlling a power supply voltage within a semiconductor integrated circuit, a voltmeter circuit for measuring the power supply voltage may be integrated into the semiconductor integrated circuit. In Figure 2, the same circuit elements as those in Figure 1 are assigned the same reference numerals. However, the electrical characteristics of elements with the same reference numerals in Figures 1 and 2 are not necessarily the same.

[0038] 2 includes PNP transistors Q1 and Q2, resistors R1, R2, and R3, an operational amplifier AMP, and an ADC. Although not particularly limited, the resistance values ​​of the resistors R1, R2, and R3 are set to, for example, 100 kΩ, 1 MΩ, and 200 kΩ, respectively.

[0039] Resistor R1 and transistor Q1 are connected in series between the reference voltage line VREF and the ground line GND via node VBE1. The base of transistor Q1 is connected to the ground line GND. Node VBE1 is connected to the negative input of operational amplifier AMP. Resistors R2, R3 and transistor Q2 are connected in series between the reference voltage line VREF and the ground line GND. Resistors R2, R3 are connected via node V1, and resistor R3 and transistor Q2 are connected via node VBE2. The base of transistor Q2 is connected to the ground line GND. Node V1 is connected to the positive input of operational amplifier AMP.

[0040] The I displayed near resistor R2 indicates the emitter current of transistor Q2, and 10×I displayed near resistor R1 indicates that the emitter current of transistor Q1 is 10 times the emitter current I of transistor Q2. The ×1 and ×10 attached to transistors Q1 and Q2, respectively, indicate that the emitter area of ​​transistor Q2 is 10 times that of transistor Q1.

[0041] In the voltmeter circuit 20 shown in FIG. 2 , the circuits excluding the ADC operate as a bandgap circuit that generates a reference voltage VREF. The bandgap circuit has a function of generating a constant reference voltage VREF (e.g., 1.2 V) that is independent of temperature. Bandgap circuits are disclosed in Patent Documents 3, 4, and 5.

[0042] The reference voltage VREF is supplied to the ADC as its reference voltage. The ADC calculates the ratio between the reference voltage and the input voltage VIN and outputs a digital output value Dout indicating the input voltage VIN. Because the reference voltage VREF is constant over temperature, the ADC can output the input voltage VIN received at the positive input terminal VIP as a digital output value Dout that is independent of temperature.

[0043] 2, if the voltage gain of the operational amplifier AMP is sufficiently large, the input voltages VBE1 and V1 of the amplifier AMP will be approximately equal, and the circuit will be stable. Therefore, if the resistance values ​​of the resistors R1 and R2 are designed to be, for example, 1:10 (100 kΩ and 1 MΩ), the magnitude of the currents flowing through the transistors Q1 and Q2 will be 10:1.

[0044] For example, if the emitter area of ​​transistor Q2 is 10 times that of transistor Q1, and the base-emitter voltages of transistors Q1 and Q2 are represented by VBE1 and VBE2, respectively, then equations (13) and (14) can be obtained from equation (2): 10×I=I0·exp{q·VBE1 / (k·T)} (13) I=10×I0·exp{q·VBE2 / (k·T)} (14)

[0045] Dividing equation (13) by equation (14) gives equation (15), and expressing VBE1-VBE2 in equation (15) as ΔVBE gives equation (16): 100=exp{q k T (VBE1-VBE2)} (15) ΔVBE=k T / q ln100 (16)

[0046] That is, the difference ΔVBE between the base-emitter voltages of transistors Q1 and Q2 is expressed as the product of the logarithm (ln100) of the current density ratio 100 of transistors Q1 and Q2 and the thermal voltage k·T / q. Since voltages V1 and VBE1 are equal to each other and ΔVBE is equal to the potential difference across resistor R3, a current expressed as ΔVBE / R3 flows through resistors R2 and R3. Therefore, if the potential difference across resistor R2 is VR2, the current flowing through resistor R2 is expressed as VR2 / R2, which is equal to ΔVBE / R3, and thus equation (17) is obtained: VR2=ΔVBE·(R2 / R3) (17)

[0047] VR2 is represented by "VREF-V1", and the voltages VBE1 and V1 are equal to each other. Therefore, the potential of the reference voltage VREF is represented by V1+VR2=VBE1+VR2, and is expressed by equation (18) using equation (17): VREF=VBE1+ΔVBE(R2 / R3) (18)

[0048] The first term VBE1 on the right side of equation (18) is the forward voltage of the PN junction, and as shown in equation (1), it has a negative temperature dependency that decreases with increasing temperature. On the other hand, the second term ΔVBE on the right side of equation (18) increases in proportion to temperature, as shown in equation (16). Therefore, by appropriately selecting the ratio R2 / R3 of the resistance values ​​R2 and R2, it is possible to design a voltmeter circuit 20 that generates a voltage VREF that is independent of temperature. The value of voltage VREF at this time is 1.2 V, which corresponds to the bandgap voltage of silicon.

[0049] In the thermometer circuit 10 of Fig. 1 and the voltmeter circuit 20 of Fig. 2, the ADC is shown as a block, but for the purpose of measuring DC voltages such as temperature or power supply voltage, an ADC known as a delta-sigma type is suitable. Delta-sigma type ADCs are disclosed in Patent Document 6, Non-Patent Document 1, and Non-Patent Document 2.

[0050] FIG. 3 shows an example of a measurement circuit in the first embodiment. The measurement circuit 100 shown in FIG. 3 adds a switch circuit SW1 and a control circuit CNTL to the thermometer circuit 10 of FIG. 1 , and has both the functions of the thermometer circuit 10 of FIG. 1 and the functions of the voltmeter circuit 20 of FIG. 2 . The control circuit CNTL is an example of a switch control circuit. Note that the control circuit CNTL may be disposed external to the measurement circuit 100. For example, the measurement circuit 100 is mounted on a semiconductor integrated circuit and measures the temperature of the semiconductor integrated circuit and the voltage (e.g., power supply voltage) used in the semiconductor integrated circuit. The temperature and voltage are examples of physical quantities. The measurement circuit 100 may also be used to control DVFS of the semiconductor integrated circuit.

[0051] The switch circuit SW1 is connected to the nodes VBE1 and VBE2, the input voltage line VIN, the ground line GND, and the positive and negative input terminals VIP and VIM of the ADC. When a control signal CNT1 from the control circuit CNTL indicates the temperature measurement mode, the switch circuit SW1 connects the positive input terminal VIP to the node VBE1 and connects the negative input terminal VIM to the node VBE2.

[0052] In this case, the measurement circuit 100 has the same circuit configuration as the thermometer circuit 10 in Fig. 1, and the calculation circuit OPC outputs a measured temperature value Tread indicating the temperature of the measurement circuit 100 as the measurement result. That is, the calculation circuit OPC applies g set based on the above-mentioned equation (11) to equation (10), thereby suppressing a decrease in the accuracy of the measured temperature value Tread measured in the temperature measurement mode. The temperature measurement mode is an example of a first measurement mode.

[0053] When the control signal CNT1 from the control circuit CNTL indicates a voltage measurement mode, the switch circuit SW1 connects the positive input terminal VIP to the input voltage line VIN and the negative input terminal VIM to the ground line GND. In this case, the measurement circuit 100 operates as a voltmeter circuit, and outputs a measured voltage Dvin indicating the input voltage VIN from the calculation circuit OPC as a measurement result. The ground line GND is an example of a fixed voltage node, and the ground voltage GND supplied to the ground line GND is an example of a fixed voltage.

[0054] The switch circuit SW1 is an example of a first switch circuit. In the switch circuit SW1, the nodes VBE1, VBE2, the input voltage line VIN, and the ground line GND are connected to one another and are an example of an input node, and the nodes VIP and VIM are connected to one another and are an example of an output node. The input voltage line VIN is an example of a voltage measurement node to which the voltage to be measured is supplied.

[0055] When the control signal CNT1 indicates the voltage measurement mode, the switch circuit SW1 connects the positive input terminal VIP to the input voltage line VIN and the negative input terminal VIM to the ground line GND. The voltage measurement mode is an example of a second measurement mode. Here, the ground voltage GND is supplied to the negative input terminal VIM of the ADC, and the voltage VBE1 is supplied to the reference voltage terminal VREF of the ADC. Therefore, the digital output value Dout output by the ADC is VIP / VBE1, which can be expressed by equation (19) by reflecting equation (1). Dout=VIP / (Veg-aT) (19)

[0056] Since the denominator on the right side of equation (19) has a negative temperature coefficient, the digital output value Dout does not correspond to the input voltage VIN. For example, even if the input voltage VIN does not change, the digital output value Dout increases as the temperature increases.

[0057] In this embodiment, the measurement circuit 100 measures the temperature in the temperature measurement mode, and then measures the voltage in the voltage measurement mode. The arithmetic circuit OPC then uses the temperature measurement value Tread acquired in the temperature measurement mode to perform temperature compensation on the digital output value Dout of the input voltage VIN converted by the ADC.

[0058] For example, the arithmetic circuit OPC cancels the temperature coefficient of the denominator by multiplying the digital output value Dout indicating the input voltage VIN by "Veg-a·Tread." If the digital value corresponding to the input voltage VIN is the input voltage value Dvin and the temperature measurement value Tread is T, the input voltage value Dvin is expressed by equation (20), and the input voltage value Dvin indicating the input voltage VIN supplied to the positive input voltage VIP of the ADC can be obtained. However, it is assumed that the temperature measurement value Tread is sufficiently accurate. The first term on the right side of equation (20) is the digital output value Dout as shown in equation (19).

[0059] Dvin=VIP / (Veg-a・T)×(Veg-a・Tread) =VIP / (Veg-a・T)×(Veg-a・T) VIP‥(20)

[0060] Here, the constant a used in "Veg-a Tread" is approximately 2 mV / °C, as explained in equation (1). More precisely, it is reasonable to make it consistent with the constant used when measuring the temperature. In the temperature measurement explained in Figure 1, the constant g was set so that equation (11) would be constant with respect to temperature, and was used to calculate the temperature. By substituting the right-hand side of equation (1) into the first term of equation (11) and the right-hand side of equation (6) into the second term of equation (11), equation (21) is derived. Veg-a T + g k T / (q ln15) = constant ... (21)

[0061] Since equation (21) is constant, a can be expressed as "g·k / (q·ln15)". Here, g is the value used for temperature measurement described in FIG. 1. k is the Boltzmann constant, q is a constant indicating the charge of an electron, and ln15 is a constant.

[0062] Therefore, by substituting the temperature measurement value Tread obtained in the temperature measurement mode, the digital output value Dout, and the constants a and Veg into the first line of equation (20), the arithmetic circuit OPC can calculate the temperature-independent voltage measurement value Dvin, which corresponds to the input voltage VIN. As a result, it is possible to suppress a decrease in the accuracy of the voltage measurement value Dvin measured in the voltage measurement mode. The digital output value Dout indicates the input voltage VIN received at the positive input terminal VIP during the voltage measurement mode, and is expressed as "VIP / (Veg-aT)".

[0063] Fig. 4 shows an example of the operation timing of the measurement circuit 100 in Fig. 3. The operation shown in Fig. 4 is realized by the operation of each circuit in the measurement circuit 100, such as the ADC and the arithmetic circuit OPC, under the control of the control circuit CNTL. The measurement circuit 100 measures temperature and voltage in that order.

[0064] The control circuit CNTL first outputs a low-level control signal CNT1 to the switch circuit SW1, switching the switch circuit SW1 to a temperature measurement mode in which the switch circuit SW1 connects its positive input terminal VIP to a node VBE1 and its negative input terminal VIM to a node VBE2.

[0065] The ADC operates in response to the falling edge of the control signal CNT1 and outputs a digital output value Dout corresponding to the input voltages VIP and VIM. When the arithmetic operation circuit OPC receives a low-level control signal CNT1, it calculates a temperature measurement value Tread from the digital output value Dout output from the ADC and outputs the calculated temperature measurement value Tread.

[0066] Next, the control circuit CNTL outputs a high-level control signal CNT1 to the switch circuit SW1, switching the switch circuit SW1 to a voltage measurement mode in which the switch circuit SW1 connects the positive input terminal VIP to the input voltage line VIN and the negative input terminal VIM to the ground line GND.

[0067] The ADC operates in response to the rising edge of the control signal CNT1 and outputs a digital output value Dout corresponding to the input voltages VIP and VIM. When the arithmetic operation circuit OPC receives a high-level control signal CNT1, it calculates a voltage measurement value Dvin based on the digital output value Dout output from the ADC and outputs the calculated voltage measurement value Dvin.

[0068] In the measurement circuit 100 of Fig. 3, the analog calculations realized by the bandgap circuit in Fig. 2 can be replaced with digital calculations. That is, in the measurement circuit 100, the main calculations are performed numerically using digital values ​​after AD conversion, which makes it less susceptible to changes in characteristics due to manufacturing errors and temperature changes in the measurement circuit 100, and allows for definitive measurement results.

[0069] In contrast, the voltmeter circuit 20 shown in FIG. 2 is provided with a bandgap circuit that generates a constant reference voltage VREF with respect to temperature, and the ADC generates a digital output value Dout using the reference voltage VREF. The bandgap circuit is an analog arithmetic circuit that adds R2 / R3 times the voltage difference ΔVBE, which has a positive temperature coefficient, to a voltage VBE1, which has a negative temperature coefficient, as shown in equation (18). Each element used in the analog arithmetic has variations due to manufacturing errors, and its characteristics change as the temperature changes. Therefore, the arithmetic operation shown in equation (18) is uncertain, with the results varying slightly depending on the individual differences (manufacturing errors) of the voltmeter circuit 20 and the temperature.

[0070] As described above, in the first embodiment, the arithmetic circuit OPC executes different calculations in the temperature measurement mode and the voltage measurement mode to calculate the temperature measurement value Tread and the voltage measurement value Dvin, respectively. This makes it possible to suppress a decrease in the accuracy of the temperature measurement value Tread and the voltage measurement value Dvin measured using the common measurement circuit 100, even when the electrical characteristics of the elements included in the measurement circuit 100 vary due to manufacturing errors, etc.

[0071] 1 and the voltmeter circuit 20 of FIG. 2 can be realized by a single measurement circuit 100, so the circuit area of ​​the measurement circuit 100 that measures temperature and voltage can be smaller than the sum of the circuit areas of the two circuits that measure temperature and voltage, respectively. When multiple measurement circuits 100 are mounted on a semiconductor integrated circuit, the greater the number of measurement circuits 100 mounted, the greater the area reduction effect can be.

[0072] Fig. 5 shows an example of a measurement circuit according to the second embodiment. Elements that are the same as or similar to those in Fig. 3 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. Fig. 5 has the same circuit configuration as Fig. 3, except that the configuration and function of a switch circuit SW1 that selects a voltage to be supplied to the ADC differs from those of the switch circuit SW1 in Fig. 3.

[0073] In the measurement circuit 102 shown in Figure 5, the positive input terminal VIP of the ADC is connected to a node VBE1. A switch circuit SW1 connects a node VBE2 or an input voltage line VIN to a negative input terminal VIM of the ADC. When a control signal CNT1 from the control circuit CNTL indicates a temperature measurement mode, the switch circuit SW1 connects the negative input terminal VIM to the node VBE2. In this case, the measurement circuit 102 has the same circuit configuration as the thermometer circuit 10 of Figure 1, and the measurement circuit 102 can obtain a temperature measurement value Tread.

[0074] When the control signal CNT1 indicates the voltage measurement mode, the switch circuit SW1 connects the negative input terminal VIM to the input voltage line VIN. The digital output value Dout output from the ADC in the voltage measurement mode is expressed by equation (22), which reflects equation (1) in equation (7): Dout=(Veg-a.T-VIN) / (Veg-a.T) (22)

[0075] Assume that the measured temperature value Tread calculated in the temperature measurement mode is sufficiently accurate, and Tread = T. In this case, by moving the denominator on the right side of equation (22) to the left side, replacing the input voltage VIN with the measured voltage value Dvin, and rewriting it as an equation for the measured voltage value Dvin, equation (23) is obtained. Dvin = (Dout - 1) x (Veg - a * Tread) = {(Veg - a * T - VIN) / (Veg - a * T) - 1} x (Veg - a * Tread) = {1 - VIN / (Veg - a * T) - 1} x (Veg - a * Tread) = -VIN (23)

[0076] As a result, an input voltage value Dvin that does not depend on temperature can be obtained according to the voltage value VIN. The calculation circuit OPC can calculate the temperature-independent input voltage value Dvin that corresponds to the input voltage VIN by substituting the digital output value Dout, the temperature measurement value Tread obtained in the temperature measurement mode, and the constants Veg and a into the first line of equation (23). Note that in equation (23), the input voltage VIN and the measured voltage Dvin have opposite signs, so the calculation circuit OPC inverts the sign of the measured voltage Dvin calculated using equation (23) and outputs it. The operation timing of the measurement circuit 102 shown in FIG. 5 is the same as that shown in FIG. 4.

[0077] As described above, the second embodiment can also achieve the same effects as the first embodiment. For example, the arithmetic circuit OPC executes different calculations in the temperature measurement mode and the voltage measurement mode to calculate the temperature measurement value Tread and the voltage measurement value Dvin, respectively. This makes it possible to suppress a decrease in the accuracy of the temperature measurement value Tread and the voltage measurement value Dvin measured using the common measurement circuit 102, even when the electrical characteristics of the elements included in the measurement circuit 102 vary due to manufacturing errors or the like.

[0078] 1 and the functions of the voltmeter circuit 20 of FIG. 2 can be realized by a single measurement circuit 102, so the circuit area of ​​the measurement circuit 102 that measures temperature and voltage can be made smaller than the sum of the circuit areas of the thermometer circuit 10 and the voltmeter circuit 20. Furthermore, in the second embodiment, the circuit size of the switch circuit SW1 can be made smaller than the circuit size of the switch circuit SW1 of the measurement circuit 100 of FIG. 3, thereby making it possible to further reduce the circuit area.

[0079] FIG. 6 shows an example of a measurement circuit according to the third embodiment. Elements that are the same as or similar to those in FIG. 5 are designated by the same reference numerals, and detailed descriptions thereof will be omitted. The measurement circuit 104 shown in FIG. 6 has transistors M30, M31, M32, and M33 arranged in place of the transistors M1 and M2 in FIG. 5, and includes a switch circuit SW2 that switches the connection between the transistors M30-M33 and the nodes VBE1 and V1. The transistors M30-M33 are an example of a third field-effect transistor. The switch circuit SW2 is an example of a second switch circuit.

[0080] The output node of the preamplifier AMP is connected to the gates of transistors M30-M33 via a feedback node FB. The control circuit CNTL outputs a control signal CNT1 that controls the switch circuit SW1, as well as a control signal CNT2 that controls the switch circuit SW2. The control signal CNT2 is also supplied to the ADC and the arithmetic circuit OPC. The other components of the measurement circuit 104 are similar to those of the measurement circuit 102 shown in FIG. 5. Hereinafter, when the transistors M30, M31, M32, and M33 are not to be distinguished from one another, they will also be referred to as transistor M3.

[0081] In the measurement circuit 100 shown in FIG. 3 and the measurement circuit 102 shown in FIG. 5 described above, the channel widths of the transistors M1 and M2 are set to a ratio of 15:1 in order to determine the current ratio of the transistors Q1 and Q2, and it is expected that the ratio of 15:1 will be accurate when calculating the temperature.

[0082] Therefore, for example, if the current ratio of transistors Q1 and Q2 changes from 15:1 due to manufacturing variations in transistors M1 and M2, an error occurs in the temperature measurement value Tread. Furthermore, if the ratio changes from 15:1, an error also occurs in the voltage measurement value Dvin, which is calculated based on the expectation that the temperature measurement value Tread is accurate.

[0083] 6 uses a switch circuit SW2 to connect three of the same-sized transistors M3 to the transistor Q1, and connects the remaining transistor M3 to the transistor Q2. In other words, the switch circuit SW2 switches the combination of the transistors M3 connected to the transistors Q1 and Q2.

[0084] In order to achieve the same current ratio of 15:1 between transistors Q1 and Q2 in measuring circuit 104 of Fig. 6 as that of measuring circuits 100 and 102 of Fig. 3 and Fig. 5, it is desirable to provide 16 transistors M3, connect 15 of the 16 transistors M3 to transistor Q1, and connect the remaining transistor M3 to transistor Q2. However, in Fig. 6, for the sake of simplicity, four transistors M3 are provided, and the current ratio between transistors Q1 and Q2 is set to 3:1.

[0085] The switch circuit SW2 has switches S0-S3 connected to transistors M30-M33. For example, the control circuit CNTL outputs a 4-bit control signal CNT2 to the switch circuit SW2 to control the switches S0-S3. One bit of the 4-bit control signal CNT2 is set to "1" and the remaining three bits are set to "0."

[0086] A "0" shown in switch circuit SW2 indicates that transistor M3 is connected to transistor Q1. A "1" shown in switch circuit SW2 indicates that transistor M3 is connected to transistor Q2. This allows the emitter current ratio of transistors Q1 and Q2 to be constantly maintained at 3:1 while switching transistor M3 connected to transistors Q1 and Q2.

[0087] FIG. 7 shows an example of the operation timing of the measurement circuit of FIG. 6. Detailed description of operations that are the same as or similar to those of FIG. 4 will be omitted. The operation in the voltage measurement mode is the same as that of FIG. 4. During the temperature measurement mode in which the control signal CNT1 is set to a low level, the control circuit CNTL of FIG. 6 sequentially changes the logic level of the control signal CNT2. The control circuit CNTL sequentially switches three of the four transistors M3 connected to transistor Q1 and one of the transistors M3 connected to transistor Q2.

[0088] The four bits shown in the control signal CNT2 shown in Fig. 7 correspond to transistors M30, M31, M32, and M33 from the right. The transistor M3 corresponding to a bit value of "0" is connected to the transistor Q1, and the transistor M3 corresponding to a bit value of "1" is connected to the transistor Q2. In Fig. 7, "0001" of the control signal CNT2 output first indicates the state of the switch circuit SW2 in Fig. 6.

[0089] The voltages BVBE1 and VBE2 generated at the nodes VBE1 and VBE2 change due to slight differences in the electrical characteristics of the transistor M3 connected to the transistors Q1 and Q2. The ADC generates a digital output value Dout every time the logic level of the control signal CNT2 switches.

[0090] The ADC operates in synchronization with the transition edge of the control signal CNT2 and outputs a digital output value Dout corresponding to the input voltages VIP and VIM. The arithmetic circuit OPC acquires the digital output value Dout a predetermined delay time after the transition edge of the control signal CNT2 and integrates the acquired digital output value Dout. The arithmetic circuit OPC then calculates the average of the four integrated digital output values ​​Dout and outputs the calculated average as the temperature measurement value Tread. Because the arithmetic circuit OPC only needs to calculate the average of the digital output values ​​Dout, this can be achieved by numerical calculation.

[0091] For example, suppose that due to manufacturing variations in transistors M30-M33, the drain current of transistor M30 is 1.1×, and the drain current of transistors M31-M33 is 1×. In this case, the current ratio of transistors Q1 and Q2 is 1.1:3 with the first control signal CNT2 (=0001), and 1:3.1 with each of the second to fourth control signals CNT2 (=0010, 0100, 1000).

[0092] Adding the four ratios on the left and right sides, respectively, results in a ratio of (1.1 + 1 + 1 + 1):(3 + 3.1 + 3.1 + 3.1) = 1:3. Therefore, by switching switches S0-S3 and averaging the digital output value Dout measured four times, it is possible to eliminate the effects of variations in the electrical characteristics of transistors M30-M33.

[0093] As a result, it is possible to cancel errors in the temperature measurement value Tread caused by manufacturing variations in the transistors M30-M33. Furthermore, in the subsequent voltage measurement mode, it is possible to prevent manufacturing variations in the transistors M30-M33 from affecting the voltage measurement value Dvin calculated using the temperature measurement value Tread.

[0094] It is known that the variation in the electrical characteristics of MOS transistors is relatively large as the channel area becomes smaller. Therefore, in the measurement circuits 100 and 102 shown in FIGS. 3 and 5, which calculate the temperature measurement value Tread from a single digital output value Dout, the total area of ​​the channels of transistors M1 and M2, which determine the current ratio of transistors Q1 and Q2, must be sufficiently larger than the total area of ​​the channel of transistor M3. In other words, in the measurement circuit 104 shown in FIG. 5, the total area of ​​transistor M3 can be made smaller than the total area of ​​transistors M1 and M2 shown in FIGS. 3 and 5.

[0095] The switch circuit SW1 of the measurement circuit 104 shown in Fig. 6 may be replaced with the switch circuit SW1 shown in Fig. 3. In this case, the operation is the same as in Fig. 7, and it is possible to suppress the influence of variations in the electrical characteristics of the transistor M3 on the temperature measurement value Tread and the voltage measurement value Dvin.

[0096] In the measurement circuit 104 shown in FIG. 6, the current ratio of transistors Q1 and Q2 has been described as 3:1, but the current ratio can be set arbitrarily. The larger the current ratio, the larger the voltage ΔVBE (=VBE1-VBE2). Therefore, it is desirable to increase the current ratio in order to improve measurement accuracy.

[0097] On the other hand, increasing the current ratio increases the number of transistors M3 included in the measurement circuit 104 and the number of switches included in the switch circuit SW2, thereby increasing the circuit size. Furthermore, the number of combinations connected to the transistors Q1 and Q2 increases, lengthening the measurement time. Therefore, the number of transistors M3 is determined by considering the balance between the measurement accuracy, circuit size, and measurement time requirements. For example, if the total area of ​​the transistors M30-M33 and the switch circuit SW2 can be made smaller than the total area of ​​the transistors M1 and M2 in FIG. 5, the size of the measurement circuit 104 can be made smaller than the size of the measurement circuit 102 in FIG. 5.

[0098] As described above, the third embodiment can also achieve the same effects as the first and second embodiments. Furthermore, in the third embodiment, in the temperature measurement mode, by sequentially switching the multiple transistors M3 connected to the transistors Q1 and Q2, it is possible to cancel errors in the temperature measurement value Tread caused by manufacturing variations in the transistor M3. Furthermore, in the subsequent voltage measurement mode, it is possible to prevent manufacturing variations in the transistor M3 from affecting the voltage measurement value Dvin calculated using the temperature measurement value Tread. As a result, it is possible to further prevent a decrease in the accuracy of the temperature measurement value Tread and the voltage measurement value Dvin measured using the common measurement circuit 104.

[0099] FIG. 8 shows an example of a measurement circuit according to the fourth embodiment. Elements identical or similar to those in FIG. 6 are designated by the same reference numerals, and detailed description thereof will be omitted. The measurement circuit 106 shown in FIG. 8 has a configuration similar to that of the measurement circuit 104 in FIG. 6, except that the operational amplifier AMP has a differential output, and switch circuits SW3 and SW4 controlled by a control signal CNT3 are connected to the input and output of the operational amplifier AMP, respectively. The control signal CNT3 is generated by a control circuit CNTL. The switch circuit SW3 is an example of a third switch circuit, and the switch circuit SW4 is an example of a fourth switch circuit.

[0100] 8, the offset voltage of the operational amplifier AMP can be canceled by switching the polarity of the differential input and the polarity of the differential output of the operational amplifier AMP using the control signal CNT3. The operational amplifier AMP is an example of a comparison circuit that receives and compares the voltages of nodes VBE1 and V1 at differential input nodes IN- and IN+, and outputs voltages indicating the comparison results to differential output nodes OUT- and OUT+.

[0101] Figure 9 shows an example of the operation timing of the measurement circuit 106 in Figure 8. Detailed description of operations that are the same as or similar to those in Figure 7 will be omitted. The operation in the voltage measurement mode is the same as that in Figure 7. During the temperature measurement mode in which the control signal CNT1 is set to a low level, the control circuit CNTL in Figure 8 sets the logic level of the control signal CNT3 to a low level and a high level in sequence.

[0102] While the control signal CNT3 is at low level, the switch circuit SW3 connects the node VBE1 to the negative input (IN-) of the operational amplifier AMP and connects the node V1 to the positive input (IN+) of the operational amplifier AMP. Also, while the control signal CNT3 is at low level, the switch circuit SW4 connects the output OUT- of the operational amplifier AMP to the feedback node FB.

[0103] While the control signal CNT3 is at a high level, the switch circuit SW3 connects the node VBE1 to the + input of the operational amplifier AMP and connects the node V1 to the - input of the operational amplifier AMP. Also, while the control signal CNT3 is at a high level, the switch circuit SW4 connects the output OUT+ of the operational amplifier AMP to the feedback node FB.

[0104] The "normal" shown in the control signal CNT3 indicates that the node VBE1 is connected to the negative input of the operational amplifier AMP, the node V1 is connected to the positive input of the operational amplifier AMP, and the output OUT- of the operational amplifier AMP is connected to the feedback node FB. The "reverse" shown in the control signal CNT3 indicates that the node VBE1 is connected to the positive input of the operational amplifier AMP, the node V1 is connected to the negative input of the operational amplifier AMP, and the output OUT+ of the operational amplifier AMP is connected to the feedback node FB.

[0105] The negative input (IN-) of the operational amplifier AMP is an example of a third differential input node, the positive input (IN+) of the operational amplifier AMP is an example of a fourth differential input node, the output OUT- of the operational amplifier AMP is an example of a first differential output node, and the output OUT+ of the operational amplifier AMP is an example of a second differential output node.

[0106] The control circuit CNTL also sequentially changes the logic level of the control signal CNT2 during each of the low-level period and high-level period of the control signal CNT3, similarly to Fig. 8. Then, the control circuit CNTL sequentially switches three of the four transistors M3 connected to the transistor Q1, and sequentially switches one of the transistors M3 connected to the transistor Q2.

[0107] In the temperature measurement mode, the ADC outputs the digital output value Dout four times each during the "forward" period and the "reverse" period of the control signal CNT3 to the arithmetic circuit OPC. The arithmetic circuit OPC integrates the digital output values ​​Dout received eight times from the ADC, calculates the average of the eight integrated digital output values ​​Dout, and outputs the calculated average as the temperature measurement value Tread.

[0108] In the voltage measurement mode, the arithmetic circuit OPC calculates the temperature measurement value Tread using the averaged digital output value Dout. This allows the measurement circuit 106 to calculate the temperature measurement value Tread in which the manufacturing variations of the transistors M30-M33 and the offset voltage of the operational amplifier AMP are canceled out. Furthermore, in the subsequent voltage measurement mode, the temperature measurement value Tread can be used to calculate the voltage measurement value Dvin in which the manufacturing variations of the transistors M30-M33 and the offset voltage of the operational amplifier AMP are canceled out.

[0109] As described above, the fourth embodiment can also achieve the same effects as the first to third embodiments. Furthermore, in the fourth embodiment, it is possible to calculate the temperature measurement value Tread and the voltage measurement value Dvin in which the manufacturing variations of the transistors M30-M33 and the offset voltage of the operational amplifier AMP are canceled out. As a result, it is possible to further suppress the deterioration in the accuracy of the temperature measurement value Tread and the voltage measurement value Dvin measured using the common measurement circuit 106. Note that the switch circuits SW3 and SW4 may be arranged at the input and output of the operational amplifier AMP in FIGS. 3 and 5, respectively.

[0110] 10 shows an example of a measurement circuit according to the fifth embodiment. Elements that are the same as or similar to those in FIG. 8 are given the same reference numerals, and detailed description thereof will be omitted. The measurement circuit 108 shown in FIG. 10 has a configuration similar to that of the measurement circuit 106 in FIG. 8, except that a switch circuit SW5 controlled by a control signal CNT3 is disposed between nodes VBE1, VBE2 and transistors Q1, Q2. The switch circuit SW5 is an example of a fifth switch circuit.

[0111] While the control signal CNT3 is at low level, the switch circuit SW5 connects the node VBE1 to the transistor Q1 and the node VBE2 to the transistor Q2. While the control signal CNT3 is at high level, the switch circuit SW5 connects the node VBE1 to the transistor Q2 and the node VBE2 to the transistor Q1.

[0112] The operation timing of the measurement circuit 108 shown in Fig. 10 is the same as the operation timing of the measurement circuit 106 shown in Fig. 9. However, during the "normal" period of the control signal CNT3, the node VBE1 is connected to the transistor Q1, and the node VBE2 is connected to the transistor Q2. During the "reverse" period of the control signal CNT3, the node VBE1 is connected to the transistor Q2, and the node VBE2 is connected to the transistor Q1.

[0113] As a result, in the temperature measurement mode, it is possible to cancel differences in electrical characteristics caused by manufacturing errors of the transistors Q1 and Q2, and to cancel the input-referred offset of the operational amplifier AMP caused by differences in the electrical characteristics of the transistors Q1 and Q2. The measurement circuit 108 shown in Figure 10 can cancel almost all major errors during temperature measurement, and therefore can achieve even more accurate temperature and voltage measurements than the measurement circuit 106 in Figure 8.

[0114] Figure 11 shows an example of operation timing in the measurement circuit 108 of Figure 10 that differs from that of Figure 9. Detailed description of operations that are the same as or similar to those of Figure 9 will be omitted. Figure 11 is the same as the operation timing of Figure 9, except that the control signal CNT3 changes between low and high levels in the voltage measurement mode.

[0115] During the voltage measurement mode, the ADC outputs a digital output value Dout to the arithmetic circuit OPC during the "forward" period and the "reverse" period of the control signal CNT3. The arithmetic circuit OPC integrates the digital output value Dout received twice from the ADC during the voltage measurement mode, calculates the average of the two integrated digital output values ​​Dout, and outputs the calculated average as the voltage measurement value Dvin. This makes it possible to cancel the offset of the operational amplifier AMP that occurs not only when measuring the temperature but also when measuring the input voltage VIN.

[0116] As described above, the fifth embodiment can also achieve the same effects as the first to fourth embodiments. Furthermore, the fifth embodiment can cancel the offset of the operational amplifier AMP that occurs not only when measuring temperature but also when measuring the input voltage VIN. As a result, it is possible to further suppress a decrease in the accuracy of the measured voltage Dvin measured using the common measurement circuit 108. Note that the switch circuit SW5 may be disposed between the transistors M1 and M2 and the transistors Q1 and Q2 in FIGS. 3 and 5.

[0117] 12 shows an example of the operational amplifier AMP and switch circuits SW3 and SW4 of FIGS. 8 and 10. When the control signal CNT3 is low level ("0"), the switch circuit SW3 connects the node VBE1 to the input IN- of the operational amplifier AMP and connects the node V1 to the input IN+ of the operational amplifier AMP. When the control signal CNT3 is high level ("1"), the switch circuit SW3 connects the node VBE1 to the input IN+ of the operational amplifier AMP and connects the node V1 to the input IN- of the operational amplifier AMP.

[0118] When the control signal CNT3 is at a low level ("0"), the switch circuit SW4 connects the output OUT- of the operational amplifier AMP to the feedback node FB. When the control signal CNT3 is at a high level ("1"), the switch circuit SW4 connects the output OUT+ of the operational amplifier AMP to the feedback node FB.

[0119] The operational amplifier AMP includes P-channel MOS transistors MP0, MP1, MP2, MP3, and MP4, N-channel MOS transistors MN0, MN1, MN2, and MN3, and a switch circuit SW6. The switch circuit SW6 is an example of a sixth switch circuit. Hereinafter, the P-channel MOS transistors MP0, MP1, MP2, MP3, and MP4 will also be simply referred to as transistors MP0, MP1, MP2, MP3, and MP4. The N-channel MOS transistors MN0, MN1, MN2, and MN3 will also be simply referred to as transistors MN0, MN1, MN2, and MN3.

[0120] The transistors MP2, MN2, and MN0 are connected in series between the power supply line VDD and the ground line GND. The transistors MP3, MN3, and MN1 are connected in series between the power supply line VDD and the ground line GND. The gates of the transistors MP2 and MP3 are connected via the switch circuit SW6 to the output OUT+, which is the drain of the transistors MP2 and MN2, or to the output OUT-, which is the drain of the transistors MP3 and MN3.

[0121] When the control signal CNT3 is at a low level ("0"), the switch circuit SW6 connects the gates of transistors MP2 and MP3 to the output OUT+, and when the control signal CNT3 is at a high level ("1"), connects the gates of transistors MP2 and MP3 to the output OUT-. The gates of transistors MN2 and MN3 are set to a predetermined voltage that provides electrical continuity between the source and gate of each of transistors MN2 and MN3. The gates of transistors MN0 and MN1 are set to a predetermined voltage that provides electrical continuity between the source and gate of each of transistors MN0 and MN1.

[0122] The source of transistor MP4 is connected to the power supply line VDD, the gate is set to a predetermined voltage that causes conduction between the source and gate of transistor MP4, and the drain is connected to the sources of transistors MP0 and MP1. The gate of transistor MP0 is connected to input IN-, and the drain is connected to node ND0, which is the source of transistor MN2 and the drain of transistor MN0. The gate of transistor MP1 is connected to input IN+, and the drain is connected to node ND1, which is the source of transistor MN3 and the drain of transistor MN1. Transistors MP0 and MP1 operate as a single-stage amplifier with a common source pair folded back.

[0123] Since the transistors M33-M30 shown in FIG. 10 etc. operate as a source-grounded amplifier (single-stage amplifier), it is desirable that the operational amplifier AMP shown in FIG. 12 be a single-stage amplifier using transistors MP0 and MP1 from the viewpoint of negative feedback stability.

[0124] The offset voltage of the operational amplifier AMP shown in Figure 12 is mainly caused by mismatches between the three combinations of transistors MP0 and MP1, transistors MP2 and MP3, and transistors MN0 and MN1. When the gate-source potentials of transistors MP0 and MP1 are the same, the drain currents of transistors MP0 and MP1 should ideally be the same, but manufacturing variations in transistors MP0 and MP1 cause current differences. Mismatches between the pair of transistors MP2 and MP3 and the pair of transistors MN0 and MN1 also cause offset voltages.

[0125] Therefore, in the operational amplifier AMP shown in Figure 12, measurements are performed using two settings: one where the control signal CNT3 is set to a low level ("0"), and one where the control signal CNT3 is set to a high level ("1"). The offset voltage of the operational amplifier AMP when the control signal CNT3 is set to a low level ("0") and when the control signal CNT3 is set to a high level ("1") has the same value but different polarity. Therefore, the effect of the offset can be canceled out by taking the average of the two measurements.

[0126] FIG. 13 shows an example of the main components of a measurement circuit in the sixth embodiment. In FIGS. 3, 5, 6, 8, and 10, the input voltage VIN is directly supplied to the input node of the ADC. The ADC used in the above-described embodiments is used to measure DC voltages, so a ΔΣ architecture is suitable. When a ΔΣ ADC is used, there are restrictions, such as the input voltage (VIP-VIM) being limited to a range of −0.8×VREF to +0.8×VREF.

[0127] Considering this restriction in the measurement circuit 100 of Figure 3 and the measurement circuit 102 of Figure 5, when the temperature T is 300 K and VBE is 0.6 V, the measurable range of the input voltage VIN by the ACD is 0 V to 0.48 V (= 0.6 V x 0.8) in the measurement circuit 100. In the measurement circuit 102, VIN is 0.12 V (= 0.6 V - 0.6 V x 0.8) to 1.08 V (= 0.6 V + 0.6 V x 0.8). These measurable ranges may not be sufficient depending on the application of the measurement circuit.

[0128] Therefore, by dividing the input voltage VIN using a voltage divider circuit and supplying the resulting divided voltage to the ADC, the measurable voltage range can be further expanded. In the example of applying a voltage divider circuit to the measurement circuit 100 of FIG. 3 shown in FIG. 13(a), resistors 3R and 3R with a resistance ratio of 3:1 are connected in series between the input voltage line VIN and the ground line GND via node VIN2, and node VIN2 is connected to the positive input terminal VIP of the ADC. This allows the applied voltage VIN2 of the ADC to be scaled by 1 / 4. For example, in the measurement circuit 100 of FIG. 3, the allowable input voltage range of the input voltage VIN is 0 V to 0.48 V, but in FIG. 13(a), the allowable input voltage range of the input voltage VIN can be expanded to 0 V to 1.92 V.

[0129] 5 , resistors R and R with a resistance ratio of 1:1 are connected in series between the input voltage line VIN and the ground line GND via a node VIN2, and the node VIN2 is connected to the negative input terminal VIM of the ADC. For example, by applying the voltage divider circuit of FIG. 13( b) to the measurement circuit 102 of FIG. 5 , the lower limit of the allowable input voltage range can be set to 0.24 V (= (0.6 - 0.6 × 0.8) × 2) and the upper limit of the allowable input voltage range can be set to 2.16 V (= (0.6 V + 0.6 V × 0.8) × 2).

[0130] Note that the method for scaling the input voltage range of the input voltage VIN is not limited to the voltage divider circuit using resistors shown in Fig. 13. For example, if the ADC is a switched capacitor ΔΣ type, the input sensitivity can be changed by switching the ratio between the sampling capacitance and the reference capacitance.

[0131] FIG. 14 shows an example of a semiconductor integrated circuit incorporating one of the measurement circuits of the above-described embodiments. For example, the semiconductor integrated circuit 200 shown in FIG. 14 is a multi-core processor formed on a silicon die and including multiple core circuits, with each core circuit incorporating one of the measurement circuits of the above-described embodiments. For example, each core circuit is a CPU core that executes instructions to perform calculations. Note that while FIG. 14 shows an example in which the semiconductor integrated circuit 200 has eight core circuits (#0-#7), the number of core circuits is not limited to eight, as long as there is more than one.

[0132] The measurement circuit of each core circuit outputs a measured temperature value Tread and a measured voltage value Dvin. An example of the measured temperature value Tread and the measured voltage value Dvin measured by the measurement circuit of each core circuit is shown in FIG. 14 as the measurement results. The measured temperature value Tread and the measured voltage value Dvin output from the measurement circuit of each core circuit are supplied to, for example, a voltage frequency control circuit mounted on the semiconductor integrated circuit 200.

[0133] For example, the voltage frequency control circuit outputs a voltage control signal VCNT to a voltage generation circuit (not shown) that generates a power supply voltage to be supplied to each core circuit based on a temperature measurement value Tread received from each core circuit. The voltage frequency control circuit also outputs a frequency control signal FCNT to a phase-locked loop (PLL) circuit (not shown) that adjusts the frequency of the clock supplied to each core circuit based on a voltage measurement value Dvin received from each core circuit. The voltage frequency control circuit then variably controls the frequency of the clock and the power supply voltage supplied to each of the multiple core circuits.

[0134] For example, the voltage generation circuit and the PLL circuit are mounted on the semiconductor integrated circuit 200. For example, the voltage frequency control circuit may implement DVFS, which dynamically controls the power supply voltage and clock frequency, for each core circuit. Note that the voltage frequency control circuit may control either the clock frequency or the power supply voltage.

[0135] Although the present invention has been described above based on the embodiments, the present invention is not limited to the requirements shown in the above embodiments. These requirements can be changed without departing from the spirit of the present invention, and can be appropriately determined depending on the application form.

[0136] 10 Thermometer circuit 20 Voltmeter circuit 100, 102, 104, 106, 108 Measuring circuit 200 Semiconductor integrated circuit AMP Operational amplifier CNT1, CNT2, CNT3 Control signal CNTL Control circuit Dout Digital output value Dvin Input voltage value FB Feedback node M0, M1 Transistor OPC Arithmetic circuit Q1, Q2 R1, R2, R3 Resistor S0, S1, S2, S3 Switch SW1, SW2, SW3, SW4, SW5, SW6 Switch circuit Tread Temperature measurement value V1 Node VBE1, VBE2 Node VIN Input voltage

Claims

1. A measurement circuit comprising: a first field effect transistor and a first bipolar transistor connected between a first power supply line and a second power supply line via a first node; a second field effect transistor and a second bipolar transistor connected between the first power supply line and a second power supply line via a second node; an analog-to-digital conversion circuit that converts an analog voltage indicating a difference between a voltage at a first differential input node and a voltage at a second differential input node into a digital output value using the voltage at the first node as a reference voltage and outputs the digital output value; and a first switch circuit that is provided between a voltage measurement node to which a voltage to be measured is supplied, an input node including the first node and the second node, and an output node including the first differential input node and the second differential input node, and that switches a connection between the input node and the output node in accordance with a plurality of measurement modes for measuring each of a plurality of types of physical quantities.

2. The measurement circuit of claim 1, wherein the first switch circuit, when the measurement mode is a first measurement mode, connects the first node and the second node to the first differential input node and the second differential input node, respectively, and, when the measurement mode is a second measurement mode, connects the voltage measurement node and a fixed voltage node to which a fixed voltage is supplied to the first differential input node and the second differential input node, respectively.

3. The measurement circuit of claim 1, wherein the first switch circuit connects the second node to the second differential input node when the measurement mode is a first measurement mode, and connects the voltage measurement node to the second differential input node when the measurement mode is a second measurement mode, and the first differential input node is connected to the first node regardless of the measurement mode.

4. The measurement circuit according to any one of claims 1 to 3, further comprising: a calculation circuit that uses the digital output value output from the analog-to-digital conversion circuit to perform a different calculation for each of the measurement modes, and outputs a value indicating a physical quantity corresponding to the measurement mode.

5. The measurement circuit according to claim 2 or 3, wherein the first measurement mode is a temperature measurement mode in which a temperature is measured based on a digital output value output from the analog-digital conversion circuit, and the second measurement mode is a voltage measurement mode in which a voltage is measured based on a digital output value output from the analog-digital conversion circuit.

6. The measurement circuit according to claim 5, further comprising a second switch circuit connected between the first field effect transistor and the second field effect transistor and the first bipolar transistor and the second bipolar transistor, the first field effect transistor and the second field effect transistor being arranged as a plurality of third field effect transistors, the number of which is three or more, and in the temperature measurement mode, a combination of the third field effect transistors connected to the first bipolar transistor and the second bipolar transistor is switched by the second switch circuit.

7. The measurement circuit according to claim 5, further comprising: a comparator circuit that receives and compares the voltage at the first node and the voltage at the second node at a third differential input node and a fourth differential input node, and outputs a voltage indicating a comparison result to a first differential output node and a second differential output node; a third switch circuit that is connected between the first node and the second node and the third differential input node and the fourth differential input node, and switches the connections of the first node and the second node and the third differential input node and the fourth differential input node; and a fourth switch circuit that connects either the first differential output node or the second differential output node to a feedback node connected to the gate of the first field effect transistor and the gate of the second field effect transistor, and wherein the connections of the third switch circuit and the fourth switch circuit are switched in the temperature measurement mode and the voltage measurement mode.

8. The measurement circuit according to claim 5, further comprising a fifth switch circuit connected between the first field effect transistor and the second field effect transistor and the first bipolar transistor and the second bipolar transistor, for switching connections between the first field effect transistor and the second field effect transistor and the first bipolar transistor and the second bipolar transistor, wherein the connection of the fifth switch circuit is switched in the temperature measurement mode and the voltage measurement mode.

9. The measurement circuit according to claim 6, further comprising a calculation circuit that uses the digital output values ​​output from the analog-digital conversion circuit to execute a different calculation for each of the measurement modes and outputs a value indicating a physical quantity corresponding to the measurement mode, wherein the calculation circuit calculates an average value of the digital output values ​​output from the analog-digital conversion circuit each time the connection is switched, and outputs the calculation result as a temperature measurement value or a voltage measurement value.

10. The measurement circuit according to claim 7, further comprising a calculation circuit that uses the digital output values ​​output from the analog-digital conversion circuit to execute a different calculation for each of the measurement modes and outputs a value indicating a physical quantity corresponding to the measurement mode, wherein the calculation circuit calculates an average value of the digital output values ​​output from the analog-digital conversion circuit each time the connection is switched, and outputs the calculation result as a temperature measurement value or a voltage measurement value.

11. The measurement circuit according to claim 8, further comprising a calculation circuit that uses the digital output values ​​output from the analog-digital conversion circuit to execute a different calculation for each of the measurement modes and outputs a value indicating a physical quantity corresponding to the measurement mode, wherein the calculation circuit calculates an average value of the digital output values ​​output from the analog-digital conversion circuit each time the connection is switched, and outputs the calculation result as a temperature measurement value or a voltage measurement value.

12. The measurement circuit of claim 1, further comprising a comparison circuit that compares the voltage of the first node with the voltage of the second node and outputs a voltage indicating the comparison result to the gate of the first field effect transistor and the gate of the second field effect transistor.

13. The measurement circuit of claim 12, further comprising a resistor connected between said second field effect transistor and said second node, and said comparison circuit compares the voltage at said first node with a voltage generated at a third node between said second field effect transistor and said resistor.

14. The measurement circuit according to claim 1, further comprising a voltage divider circuit that divides the voltage of the object to be measured to generate a divided voltage and supplies the generated divided voltage as the voltage of the voltage measurement node.

15. The measurement circuit according to claim 1, further comprising a switch control circuit that controls the first switch circuit to switch the connection between the input node and the output node in accordance with the measurement mode.

16. A semiconductor integrated circuit comprising: a measurement circuit according to claim 1; and a core circuit that performs calculation processing in response to a physical quantity that is measured by said measurement circuit and corresponds to said measurement mode.

17. The semiconductor integrated circuit according to claim 16, wherein the first switch circuit, when the measurement mode is a first measurement mode, connects the first node and the second node to the first differential input node and the second differential input node, respectively, and, when the measurement mode is a second measurement mode, connects the voltage measurement node and a fixed voltage node to which a fixed voltage is supplied to the first differential input node and the second differential input node, respectively.

18. The semiconductor integrated circuit according to claim 16, wherein the first switch circuit, when the measurement mode is a first measurement mode, connects the second node to the second differential input node, and, when the measurement mode is a second measurement mode, connects the voltage measurement node to the second differential input node, and the first differential input node is connected to the first node regardless of the measurement mode.

19. The semiconductor integrated circuit according to any one of claims 16 to 18, further comprising: an arithmetic circuit that uses the digital output value output from the analog-to-digital conversion circuit to execute a different arithmetic operation for each of the measurement modes, and outputs a value indicating a physical quantity corresponding to the measurement mode.

20. A semiconductor integrated circuit as claimed in any one of claims 16 to 18, further comprising a voltage frequency control circuit that variably controls a frequency of a clock supplied to the core circuit and a power supply voltage, the voltage frequency control circuit adjusting either the clock frequency or the power supply voltage, or both the clock frequency and the power supply voltage, based on a physical quantity corresponding to the measurement mode measured by the measurement circuit.

21. The semiconductor integrated circuit according to any one of claims 16 to 18, comprising a plurality of said core circuits, said measurement circuit being provided in each of said plurality of said core circuits.

22. A semiconductor integrated circuit as claimed in any one of claims 16 to 18, further comprising a voltage frequency control circuit that variably controls a clock frequency and a power supply voltage supplied to each of the multiple core circuits, the voltage frequency control circuit adjusting either the clock frequency or the power supply voltage, or both the clock frequency and the power supply voltage, based on a physical quantity corresponding to the measurement mode measured by the multiple measurement circuits.

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