Semiconductor device

Abstract

This semiconductor device comprises: a silicon carbide layer that includes a first silicon carbide region of a first conductivity type, a second silicon carbide region of a second conductivity type, and a third silicon carbide region of the first conductivity type, and that has a first surface and a second surface; a first gate electrode and a second gate electrode that extend in a first direction; a first electrode located on the first surface side and including a first portion that is in contact with the second silicon carbide region and the third silicon carbide region at locations between the first gate electrode and the second gate electrode, and a second portion that is provided in the first direction of the first portion and is in contact with the first silicon carbide region at a location between the first gate electrode and the second gate electrode; and a second electrode on the second surface side. When the first conductivity-type impurity concentrations are indicated by a logarithmic scale, the distribution of the first conductivity-type impurity concentrations in a direction from the first surface toward the second surface of the third silicon carbide region includes a plurality of inflection points on the side closer to the first surface relative to a first position at which the maximum impurity concentration is shown in the distribution.

Description

Semiconductor Devices

[0001] FIELD An embodiment of the present invention relates to a semiconductor device.

[0002] Silicon carbide is a material used in semiconductor devices. Compared to silicon, silicon carbide has excellent physical properties, such as a band gap approximately three times larger, a breakdown field strength approximately ten times larger, and a thermal conductivity approximately three times larger. By utilizing these properties, it is possible to realize, for example, a metal oxide semiconductor field effect transistor (MOSFET) that has high breakdown voltage, low loss, and is capable of operating at high temperatures.

[0003] A vertical MOSFET using silicon carbide has a pn junction diode as a built-in diode. For example, the MOSFET is used as a switching element connected to an inductive load. In this case, the pn junction diode allows a reflux current to flow even when the MOSFET is in the off state.

[0004] However, when a return current is passed through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy. The growth of stacking faults in the silicon carbide layer causes a problem of increased on-resistance of the MOSFET. The increased on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET. For example, by providing a unipolar operating Schottky Barrier Diode (SBD) as a built-in diode in the MOSFET, stacking faults in the silicon carbide layer can be suppressed.

[0005] Japanese Patent Application Laid-Open No. 2020-47680

[0006] An object of the present invention is to provide a semiconductor device that allows an increase in on-current.

[0007] The semiconductor device of the embodiment is a silicon carbide layer having a first surface and a second surface opposite to the first surface, the semiconductor device comprising: a first silicon carbide region of a first conductivity type having a region in contact with the first surface; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction parallel to the first surface; and a second silicon carbide region of a second conductivity type provided between the second silicon carbide region and the first surface and extending in the first direction, the second silicon carbide region having a first conductivity type impurity concentration equal to or greater than the first conductivity type impurity concentration of the first silicon carbide region. a silicon carbide layer including a third silicon carbide region of a first conductivity type having a higher impurity concentration than the first conductivity type; a first gate electrode extending in the first direction and facing the second silicon carbide region and the third silicon carbide region; a second gate electrode extending in the first direction and provided in a second direction perpendicular to the first direction with respect to the first gate electrode and facing the second silicon carbide region and the third silicon carbide region; a first gate insulating layer provided between the second gate electrode and the second silicon carbide region; a second gate insulating layer provided between the second gate electrode and the third silicon carbide region; a first electrode provided on the first surface side of the silicon carbide layer, the first electrode including: a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; and a second portion provided between the first gate electrode and the second gate electrode and in the first direction of the first portion and in contact with the region of the first silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer, wherein a distribution of a concentration of first conductivity type impurities in a direction from the first surface to the second surface of the third silicon carbide region includes a plurality of inflection points on the first surface side of a first position at which the distribution exhibits a maximum impurity concentration when the concentration of first conductivity type impurities is expressed on a logarithmic scale.

[0008] 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment; a schematic top view of a semiconductor device according to a first embodiment; an enlarged schematic cross-sectional ... top view of a semiconductor device according to a first embodiment; a diagram showing an impurity concentration distribution of a semiconductor device according to a first embodiment; an equivalent circuit diagram of a semiconductor device according to a first embodiment; a diagram for explaining a problem of the semiconductor device according to the first embodiment; a diagram showing an impurity concentration distribution of a semiconductor device according to a comparative example; a diagram showing an impurity concentration distribution of a semiconductor device according to a modification of the first embodiment; a diagram showing an impurity concentration distribution of a semiconductor device according to a second embodiment; a diagram showing an impurity concentration distribution of a semiconductor device according to a modification of the second embodiment.

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described may be omitted as appropriate.

[0010] In the following description, n ＋ , n, n － and p ＋ , p, p － When there are notations, these notations indicate the relative level of impurity concentration in each conductivity type. ＋ has a relatively higher n-type impurity concentration than n, － indicates that the n-type impurity concentration is relatively lower than that of n. ＋ has a relatively higher p-type impurity concentration than p － indicates that the p-type impurity concentration is relatively lower than that of p. ＋ shape, n － The type is simply n-type, p-type ＋ shape, p － The form is sometimes simply referred to as p-form.

[0011] The impurity concentration can be measured, for example, by secondary ion mass spectrometry (SIMS). The relative level of the impurity concentration can also be determined from the level of the carrier concentration obtained, for example, by scanning capacitance microscopy (SCM). Distances such as the width and depth of the impurity region can be determined, for example, by SIMS. Distances such as the width and depth of the impurity region can also be determined, for example, from SCM images or scanning electron microscope (SEM) images. The thickness of the insulating layer can also be measured, for example, on SIMS, SEM, or transmission electron microscope (TEM) images.

[0012] In this specification, the "p-type impurity concentration" of a p-type silicon carbide region means the net p-type impurity concentration obtained by subtracting the n-type impurity concentration of that region from the p-type impurity concentration of that region. Also, the "n-type impurity concentration" of an n-type silicon carbide region means the net n-type impurity concentration obtained by subtracting the p-type impurity concentration of that region from the n-type impurity concentration of that region.

[0013] Unless otherwise specified in the specification, the impurity concentration in a particular region means the maximum impurity concentration in that region.

[0014] (First Embodiment) A semiconductor device of a first embodiment includes a silicon carbide layer having a first surface and a second surface opposite to the first surface, the silicon carbide layer including: a first silicon carbide region of a first conductivity type having a region in contact with the first surface; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction parallel to the first surface; and a third silicon carbide region of the first conductivity type provided between the second silicon carbide region and the first surface, extending in the first direction, the third silicon carbide region having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; a first gate electrode extending in the first direction and facing the second silicon carbide region and the third silicon carbide region; and a second gate electrode extending in the first direction and extending in a second direction parallel to the first surface and perpendicular to the first direction with respect to the first gate electrode. a second gate electrode facing the second and third silicon carbide regions; a first gate insulating layer provided between the second and third silicon carbide regions and the first gate electrode; a second gate insulating layer provided between the second and third silicon carbide regions and the second gate electrode; a first electrode provided on the first surface side of the silicon carbide layer, the first electrode including: a first portion provided between the first gate electrode and the second gate electrode and in contact with the second and third silicon carbide regions; and a second portion provided between the first gate electrode and the second gate electrode and in a first direction of the first portion and in contact with the first silicon carbide region; and a second electrode provided on the second surface side of the silicon carbide layer. The distribution of the first conductivity type impurity concentration in the direction from the first surface toward the second surface of the third silicon carbide region includes, when the first conductivity type impurity concentration is expressed on a logarithmic scale, a plurality of inflection points on the first surface side of a first position where the distribution shows a maximum impurity concentration.

[0015] The semiconductor device of the first embodiment is a planar-gate vertical MOSFET 100 using silicon carbide. The MOSFET 100 of the first embodiment is, for example, a double implantation MOSFET (DIMOSFET) in which a body region and a source region are formed by ion implantation. The MOSFET 100 of the first embodiment also includes an SBD as a built-in diode.

[0016] The following description will be given taking as an example a case where the first conductivity type is n-type and the second conductivity type is p-type. The MOSFET 100 is a vertical n-channel MOSFET that uses electrons as carriers.

[0017] Fig. 1 is a schematic cross-sectional view of the semiconductor device of the first embodiment. Fig. 2 is a schematic top view of the semiconductor device of the first embodiment. Fig. 2 is a schematic view showing patterns of a gate electrode and a source electrode on the top surface of a silicon carbide layer. Fig. 1 is a cross-sectional view taken along line AA' in Fig. 2.

[0018] 3, 4, and 5 are enlarged schematic cross-sectional views of the semiconductor device of the first embodiment. FIG. 6 is an enlarged schematic top view of the semiconductor device of the first embodiment. FIG. 6 is a diagram showing a pattern of a semiconductor region on the surface of a silicon carbide layer. FIG. 3 is a BB' cross-sectional view of FIG. 6. FIG. 4 is a CC' cross-sectional view of FIG. 6. FIG. 5 is a DD' cross-sectional view of FIG. 6.

[0019] The MOSFET 100 includes a silicon carbide layer 10, a source electrode 12 (first electrode), a drain electrode 14 (second electrode), a gate insulating layer 16, a gate electrode 18, and an interlayer insulating layer 20. The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The source electrode 12 includes a contact electrode portion 12x (first portion) and a diode electrode portion 12y (second portion). The gate insulating layer 16 includes a first gate insulating layer 16a, a second gate insulating layer 16b, and a third gate insulating layer 16c. The gate electrode 18 includes a first gate electrode 18a, a second gate electrode 18b, and a third gate electrode 18c.

[0020] In the silicon carbide layer 10, n ＋ The drain region 22, n － a p-type drift region 24 (first silicon carbide region), a p-type body region 26 (second silicon carbide region), and an n-type ＋ The p-type body region 26 includes a p-type low concentration region 26 a and a p-type source region 30 (third silicon carbide region). ＋ The high concentration region 26b includes a shaped region 26b.

[0021] The drift region 24 includes a JBS region 24x (region) and a JFET region 24y. JBS is an abbreviation for Junction Barrier Schottky. JFET is an abbreviation for Junction Field Effect Transistor.

[0022] The silicon carbide layer 10 is provided between the source electrode 12 and the drain electrode 14. The silicon carbide layer 10 is single-crystal SiC. The silicon carbide layer 10 is, for example, 4H—SiC.

[0023] The silicon carbide layer 10 has a first surface ("F1" in FIG. 1) and a second surface ("F2" in FIG. 1). Hereinafter, the first surface F1 may be referred to as the front surface, and the second surface F2 may be referred to as the back surface. The first surface F1 is located on the source electrode 12 side of the silicon carbide layer 10. The second surface F2 is located on the drain electrode 14 side of the silicon carbide layer 10. The first surface F1 and the second surface F2 face each other. Hereinafter, "depth" means the depth in the direction from the first surface toward the second surface.

[0024] The first direction and the second direction are parallel to the first plane F1, and the second direction is perpendicular to the first direction.

[0025] The first plane F1 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (0001) plane. The second plane F2 is, for example, a plane inclined at an angle of 0 to 8 degrees with respect to the (000-1) plane. The (0001) plane is called the silicon plane. The (000-1) plane is called the carbon plane.

[0026] n ＋ The drain region 22 is provided on the back surface side of the silicon carbide layer 10. The drain region 22 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drain region 22 is, for example, 1×10 １８ cm －３ 1x10 or more ２１ cm －３ The following is the result.

[0027] n － The n-shaped drift region 24 is provided between the drain region 22 and the first face F1. －A n-shaped drift region 24 is provided between the source electrode 12 and the drain electrode 14. － A drift region 24 of a semiconductor conductor is provided between the gate electrode 18 and the drain electrode 14 .

[0028] n － The n-type drift region 24 is provided on the drain region 22. The drift region 24 contains, for example, nitrogen (N) as an n-type impurity. The n-type impurity concentration of the drift region 24 is lower than the n-type impurity concentration of the drain region 22. The n-type impurity concentration of the drift region 24 is, for example, 4×10 １４ cm －３ 5x10 or more １７ cm －３ The thickness of the drift region 24 is, for example, not less than 3 μm and not more than 150 μm.

[0029] The drift region 24 includes JBS regions 24x. The JBS regions 24x are in contact with the first face F1. The JBS regions 24x are surrounded by the body region 26.

[0030] The JBS region 24x contacts the diode electrode portion 12y of the source electrode 12. The JBS region 24x functions as the cathode region of the SBD.

[0031] The drift region 24 includes a JFET region 24y. The JFET region 24y is in contact with the first face F1. The JFET region 24y is sandwiched between two body regions 26 in the second direction.

[0032] The JFET region 24y faces the gate electrode 18. The JFET region 24y functions as a path for an on-current when the MOSFET 100 is in an on-state.

[0033] The p-type body region 26 is provided between the drift region 24 and the first face F1. The body region 26 extends in a first direction. The body region 26 functions as a channel region of the MOSFET 100.

[0034] The body region 26 contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the body region 26 is, for example, 5×10 １６ cm －３ 5x10 or more ２０cm －３ The following is the result.

[0035] The depth of the body region 26 is, for example, not less than 0.4 μm and not more than 2 μm.

[0036] The body region 26 is in contact with the source electrode 12. The body region 26 is in contact with the contact electrode portion 12x of the source electrode 12. The body region 26 is electrically connected to the source electrode 12. The contact between the body region 26 and the source electrode 12 is, for example, an ohmic contact. The body region 26 is fixed to the potential of the source electrode 12.

[0037] A portion of the body region 26 contacts the first face F1. A portion of the body region 26 faces the gate electrode 18. A portion of the body region 26 becomes a channel region of the MOSFET 100. The gate insulating layer 16 is sandwiched between the portion of the body region 26 and the gate electrode 18.

[0038] The body region 26 includes a p-type low concentration region 26a and a p ＋ The high concentration region 26b includes a shaped region 26b.

[0039] A portion of the low concentration region 26 a contacts the first face F1. A portion of the low concentration region 26 a faces the gate electrode 18. A portion of the low concentration region 26 a becomes a channel region of the MOSFET 100. The gate insulating layer 16 is sandwiched between the portion of the low concentration region 26 a and the gate electrode 18.

[0040] The low concentration region 26a contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the low concentration region 26a is, for example, 5×10 １６ cm －３ 5x10 or more １８ cm －３ The following is the result.

[0041] The high concentration region 26b is provided between the low concentration region 26a and the first face F1. The high concentration region 26b contacts the source electrode 12. The high concentration region 26b contacts the contact electrode portion 12x of the source electrode 12.

[0042] The p-type impurity concentration of the high concentration region 26b is higher than the p-type impurity concentration of the low concentration region 26a.

[0043] The high-concentration region 26b contains, for example, aluminum (Al) as a p-type impurity. The p-type impurity concentration of the high-concentration region 26b is, for example, 1×10 １９ cm －３ 5x10 or more ２０ cm －３ The following is the result.

[0044] The depth of the high concentration region 26b is, for example, not less than 0.2 μm and not more than 0.7 μm.

[0045] n ＋ A source region 30 having a shape similar to that of the body region 26 is provided between the body region 26 and the first face F1.

[0046] The source region 30 contains, for example, phosphorus (P) or nitrogen (N) as an n-type impurity. The n-type impurity concentration of the source region 30 is higher than the n-type impurity concentration of the drift region 24.

[0047] The n-type impurity concentration of the source region 30 is, for example, 1×10 １９ cm －３ 1x10 or more ２０ cm －３ The depth of the source region 30 is shallower than the depth of the body region 26. The depth of the source region 30 is, for example, not less than 0.1 μm and not more than 0.4 μm.

[0048] The source region 30 is in contact with the source electrode 12. The source region 30 is in contact with the contact electrode portion 12x of the source electrode 12. The source region 30 is electrically connected to the source electrode 12. The contact between the source region 30 and the source electrode 12 is, for example, an ohmic contact. The source region 30 is fixed to the potential of the source electrode 12.

[0049] The source region 30 is formed by, for example, performing multiple ion implantations of n-type impurities at different acceleration energies.

[0050] 7 is a diagram showing the impurity concentration distribution of the semiconductor device of the first embodiment. Fig. 7 is a diagram showing the distribution of n-type impurity concentration in the depth direction of the source region 30. In Fig. 7, the position of zero depth corresponds to the position of the first plane F1. In Fig. 7, the n-type impurity concentration on the vertical axis is expressed on a logarithmic scale.

[0051] The distribution of the n-type impurity concentration in the source region 30 shows a maximum impurity concentration at a first position P1. The depth of the first position P1 showing the maximum impurity concentration is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1 showing the maximum impurity concentration is, for example, 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0052] The distribution of the n-type impurity concentration in the source region 30 has two inflection points closer to the first face F1 than the first position P1. The two inflection points are a first inflection point IP1 and a second inflection point IP2. The position of the first inflection point IP1 is deeper than the position of the second inflection point IP2. The position of the first inflection point IP1 is closer to the first position P1 than the position of the second inflection point IP2.

[0053] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0054] The n-type impurity concentration at the first inflection point IP1 is higher than the n-type impurity concentration at the second inflection point IP2, and is, for example, 1.5 to 10 times the n-type impurity concentration at the second inflection point IP2.

[0055] The depth of the second inflection point IP2 is, for example, 0.15 μm or less.

[0056] The n-type impurity concentration at the second inflection point IP2 is, for example, 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0057] 7, the distribution of the n-type impurity concentration in the source region 30 has a first peak PK1 and a second peak PK2. The first peak PK1 is located at a first position P1. The second peak PK2 is located at a second position P2. The second position P2 is located between the first position P1 and the first plane F1.

[0058] The depth of the first position P1 is, for example, 0.15 μm or more, and the depth of the second position P2 is, for example, 0.1 μm or less.

[0059] The first conductivity type impurity concentration at the second peak PK2 is lower than the n-type impurity concentration at the first peak PK1. The n-type impurity concentration at the first peak PK1 is, for example, 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The first conductivity type impurity concentration at the second peak PK2 is, for example, 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0060] The graph of the distribution of the n-type impurity concentration in the depth direction of the source region 30 as shown in FIG. 7 can be obtained, for example, by fitting the logarithmic values ​​of the measured values ​​of the n-type impurity concentration in the depth direction of the source region 30 with a high-order function using depth as a variable.

[0061] The gate electrode 18 is provided on the first face F1 side of the silicon carbide layer 10. The gate electrode 18 extends in a first direction. A plurality of the gate electrodes 18 are arranged parallel to one another in a second direction. The gate electrode 18 faces the JFET region 24y, the body region 26, and the source region 30 on the first face F1.

[0062] The first gate electrode 18a extends in a first direction and faces the JFET region 24y, the body region 26, and the source region 30 on the first face F1.

[0063] The second gate electrode 18b extends in a first direction. The second gate electrode 18b is provided in a second direction relative to the first gate electrode 18a. The second gate electrode 18b faces the JFET region 24y, the body region 26, and the source region 30 on the first face F1.

[0064] The third gate electrode 18c extends in a first direction. The third gate electrode 18c is provided in a second direction relative to the second gate electrode 18b. The second gate electrode 18b is provided between the first gate electrode 18a and the third gate electrode 18c. The third gate electrode 18c faces the JFET region 24y, the body region 26, and the source region 30 on the first face F1.

[0065] The gate electrode 18 is a conductive layer, and is, for example, polycrystalline silicon containing p-type impurities or n-type impurities.

[0066] The gate insulating layer 16 is provided between the gate electrode 18 and the JFET region 24y, the body region 26, and the source region 30. The first gate insulating layer 16a is provided between the first gate electrode 18a and the JFET region 24y, the body region 26, and the source region 30. The second gate insulating layer 16b is provided between the second gate electrode 18b and the JFET region 24y, the body region 26, and the source region 30. The third gate insulating layer 16c is provided between the third gate electrode 18c and the JFET region 24y, the body region 26, and the source region 30.

[0067] The gate insulating layer 16 includes, for example, silicon oxide. The gate insulating layer 16 includes, for example, a silicon oxide layer. For example, a high-dielectric-constant insulating material can be applied to the gate insulating layer 16. Furthermore, for example, a stacked structure of a silicon oxide layer and a high-dielectric-constant insulating layer can be applied to the gate insulating layer 16.

[0068] The thickness of the gate insulating layer 16 is, for example, not less than 30 nm and not more than 100 nm.

[0069] The interlayer insulating layer 20 is provided on the gate electrode 18. The interlayer insulating layer 20 is provided between the gate electrode 18 and the source electrode 12.

[0070] The interlayer insulating layer 20 electrically separates the gate electrode 18 from the source electrode 12. The interlayer insulating layer 20 includes, for example, silicon oxide. The interlayer insulating layer 20 is, for example, a silicon oxide layer.

[0071] The source electrode 12 is provided on the first face F1 side of the silicon carbide layer 10. The source electrode 12 is in contact with the silicon carbide layer 10. The source electrode 12 is in contact with the body region 26 and the source region 30.

[0072] The source electrode 12 includes a contact electrode portion 12x and a diode electrode portion 12y.

[0073] The contact electrode portion 12x is provided between two gate electrodes 18. For example, the contact electrode portion 12x is provided between the first gate electrode 18a and the second gate electrode 18b. The contact electrode portion 12x is in contact with the body region 26 and the source region 30.

[0074] For example, the interface between the contact electrode portion 12 x and the body region 26 is located closer to the second face F2 than the first face F1 in a third direction perpendicular to the first face F1. For example, the contact electrode portion 12 x contacts the source region 30 in the second direction.

[0075] The diode electrode portion 12y is provided between two gate electrodes 18. For example, the diode electrode portion 12y is provided between the first gate electrode 18a and the second gate electrode 18b. The diode electrode portion 12y is provided in the first direction of the contact electrode portion 12x.

[0076] The contact electrode portions 12x and the diode electrode portions 12y are alternately and repeatedly arranged in the first direction between the same two gate electrodes 18.

[0077] The diode electrode portion 12y is in contact with the JBS region 24x of the drift region 24. The diode electrode portion 12y functions as the anode electrode of the SBD.

[0078] In the MOSFET 100, the diode electrode portion 12y and the contact electrode portion 12x are adjacent to each other in the second direction. The arrangement of the contact electrode portion 12x and the diode electrode portion 12y in the first direction is shifted by a half period from the arrangement of the contact electrode portion 12x and the diode electrode portion 12y adjacent to each other in the second direction in the first direction.

[0079] In the MOSFET 100, the diode electrode portions 12y and the contact electrode portions 12x are arranged in a checkerboard pattern.

[0080] The source electrode 12 includes a metal silicide layer 12s and a metal layer 12m. The metal silicide layer 12s is provided between the silicon carbide layer 10 and the metal layer 12m.

[0081] The metal silicide layer 12s is in contact with the body region 26. The metal silicide layer 12s is in contact with the source region 30.

[0082] The metal silicide layer 12s includes, for example, nickel (Ni), titanium (Ti), or cobalt (Co), and is, for example, a nickel silicide layer, a titanium silicide layer, or a cobalt silicide layer.

[0083] The metal layer 12m includes a metal and has, for example, a stacked structure of a barrier metal film and a metal film.

[0084] The barrier metal film contains, for example, titanium (Ti), tungsten (W), or tantalum (Ta), and is, for example, a titanium film, a titanium nitride film, a tungsten nitride film, or a tantalum nitride film.

[0085] The metal film contains, for example, aluminum (Al), and is, for example, an aluminum film.

[0086] The contact electrode portion 12x includes a metal silicide layer 12s. When the contact electrode portion 12x includes the metal silicide layer 12s, ohmic contact is formed between the source electrode 12 and the body region 26, and between the source electrode 12 and the source region 30.

[0087] The diode electrode portion 12y includes, for example, a barrier metal film.

[0088] For example, when the diode electrode portion 12y includes a barrier metal film, a Schottky contact is formed between the source electrode 12 and the JBS region 24x.

[0089] The drain electrode 14 is provided on the second face F2 side of the silicon carbide layer 10. The drain electrode 14 is provided on the second face F2 of the silicon carbide layer 10. The drain electrode 14 is in contact with the second face F2.

[0090] The drain electrode 14 includes, for example, a metal or a metal-semiconductor compound, such as a nickel silicide layer, a titanium layer, a nickel layer, a silver layer, or a gold layer.

[0091] The drain electrode 14 is electrically connected to the drain region 22. The drain electrode 14 is in contact with the drain region 22, for example.

[0092] Next, the operation and effects of the MOSFET 100 of the first embodiment will be described.

[0093] 8 is an equivalent circuit diagram of the semiconductor device of the first embodiment. In MOSFET 100, a pn diode and an SBD are connected in parallel to the transistor as built-in diodes between source electrode 12 and drain electrode 14. The body region 26 is the anode region of the pn junction diode, and the drift region 24 is the cathode region of the pn junction diode. The source electrode 12 is the anode electrode of the SBD, and the JBS region 24x is the cathode region of the SBD.

[0094] For example, consider a case where MOSFET 100 is used as a switching element connected to an inductive load. When MOSFET 100 is off, an induced current caused by the inductive load may cause a voltage that is positive with respect to drain electrode 14 to be applied to source electrode 12. In this case, a forward current flows through the built-in diode. This state is also called a reverse conduction state.

[0095] If a MOSFET does not include an SBD, a forward current flows through the pn junction diode. The pn junction diode operates in a bipolar manner. When a return current flows through a bipolar pn junction diode, stacking faults grow in the silicon carbide layer due to carrier recombination energy. The growth of stacking faults in the silicon carbide layer causes a problem of an increase in the on-resistance of the MOSFET. The increase in the on-resistance of the MOSFET leads to a decrease in the reliability of the MOSFET.

[0096] The MOSFET 100 includes an SBD. The forward voltage (Vf) at which a forward current begins to flow through the SBD is lower than the forward voltage (Vf) of a pn junction diode. Therefore, the forward current flows through the SBD before the pn junction diode.

[0097] The forward voltage (Vf) of the SBD is, for example, not less than 1.0 V and not more than 2.0 V. The forward voltage (Vf) of the pn junction diode is, for example, not less than 2.0 V and not more than 3.0 V.

[0098] The SBD operates in a unipolar manner. Therefore, even if a forward current flows, stacking faults do not grow in silicon carbide layer 10 due to carrier recombination energy. This prevents an increase in the on-resistance of MOSFET 100, thereby improving the reliability of MOSFET 100.

[0099] 9 is an explanatory diagram of the problem of the semiconductor device of the first embodiment, and corresponds to FIG. 6 of the first embodiment.

[0100] 9 shows the current path of an on-current flowing near the first face F1 of MOSFET 100 during on-operation of MOSFET 100. The current path of the on-current is indicated by an arrow.

[0101] 9, in the second direction, there is no portion between the JBS regions 24x and the JFET region 24y where the contact electrode portion 12x and the source region 30 are in contact with each other. Therefore, as shown in FIG. 9, the on-current flows from the contact electrode portion 12x through the source region 30 in the first direction, and then flows into the JFET region 24y through the body region 26, which serves as a channel region.

[0102] When the electrical resistance of the source region 30 increases, the parasitic resistance of the MOSFET 100 increases, and the on-current of the MOSFET 100 decreases. In particular, when the distance between the contact electrode portions 12x adjacent in the first direction increases, the current path flowing in the first direction through the source region 30 becomes longer. Therefore, the increase in the parasitic resistance becomes significant, and the on-current of the MOSFET 100 decreases significantly.

[0103] Fig. 10 is a diagram showing the impurity concentration distribution of a semiconductor device of a comparative example. Fig. 10 is a diagram showing the distribution of n-type impurity concentration in the depth direction of source region 30. In Fig. 10, the position of zero depth corresponds to the position of first plane F1. In Fig. 10, the n-type impurity concentration on the vertical axis is expressed on a logarithmic scale.

[0104] 10, the distribution of the n-type impurity concentration of the semiconductor device of the comparative example is shown by a dotted line, and the distribution of the n-type impurity concentration of the semiconductor device of the first embodiment is also shown by a solid line.

[0105] 10 , the distribution of the n-type impurity concentration of the semiconductor device of the comparative example has a peak Pkx at a position Px. The distribution of the n-type impurity concentration of the semiconductor device of the comparative example shows a maximum impurity concentration at the position Px. The distribution of the n-type impurity concentration of the semiconductor device of the comparative example does not have an inflection point on the first face F1 side of the position Px.

[0106] In the semiconductor device of the comparative example, for example, if the n-type impurity concentration at the position Px is increased, the electrical resistance of the source region decreases, thereby reducing the parasitic resistance of the MOSFET and increasing the on-current of the MOSFET.

[0107] However, increasing the n-type impurity concentration in the source region increases the defect density in the source region, which defects are caused, for example, by the ion implantation of n-type impurities to form the source region.

[0108] In particular, when the n-type impurity concentration in the source region in contact with the gate insulating layer increases and the defect density increases, the reliability of the gate insulating layer above the source region decreases. When the defect density in the source region near the first face F1 increases, the reliability of the gate insulating layer above the source region decreases. Specifically, for example, the time-dependent dielectric breakdown (TDDB) characteristics of the gate insulating layer deteriorate.

[0109] The distribution of the n-type impurity concentration in the MOSFET 100 of the first embodiment has two inflection points closer to the first face F1 than the first position P1, which indicates the maximum impurity concentration. By having two inflection points in the distribution of the n-type impurity concentration, it is possible to form a low impurity concentration region of a predetermined width having an n-type impurity concentration equal to or greater than a predetermined concentration closer to the first face F1 than the first position P1.

[0110] In the MOSFET 100 of the first embodiment, the electrical resistance of the source region 30 is reduced by increasing the n-type impurity concentration at the first position P1. This reduces the parasitic resistance of the MOSFET 100 and increases the on-current of the MOSFET 100.

[0111] In the MOSFET 100 of the first embodiment, a low impurity concentration region of a predetermined width is provided closer to the first face F1 than the first position P1. Therefore, the n-type impurity concentration of the source region 30 in contact with the gate insulating layer 16 is low, and the defect density is reduced. In other words, the defect density of the source region 30 near the first face F1 is reduced. Therefore, the reliability of the gate insulating layer above the source region 30 is improved.

[0112] Furthermore, the low impurity concentration region provided in the MOSFET 100 of the first embodiment has two inflection points, thereby providing an n-type impurity concentration equal to or greater than a predetermined concentration. In other words, a constant level of n-type impurity concentration is maintained in the low impurity concentration region. This suppresses a decrease in the electrical resistance of the source region 30 near the first face F1. This reduces the parasitic resistance of the MOSFET 100, thereby increasing the on-current of the MOSFET 100.

[0113] According to the first embodiment, the source region 30 is provided with a low impurity concentration region of a predetermined width having an n-type impurity concentration equal to or greater than a predetermined concentration, closer to the surface than the position where the n-type impurity concentration is maximum, thereby realizing a MOSFET 100 that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0114] From the viewpoint of increasing the on-state current of the MOSFET 100, it is preferable that the maximum impurity concentration at the first point P1 is high. The n-type impurity concentration at the first point P1 is 3×10 １９ cm－３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0115] From the viewpoint of increasing the on-state current of MOSFET 100, the n-type impurity concentration at the first inflection point IP1 is preferably higher than the n-type impurity concentration at the second inflection point IP2.

[0116] From the viewpoint of increasing the on-state current of the MOSFET 100, it is preferable that the n-type impurity concentration at the second inflection point IP2 is high. The n-type impurity concentration at the second inflection point IP2 is 1×10 １９ cm －３ It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0117] The depth of the second inflection point IP2 is preferably shallow from the viewpoint of increasing the on-state current of MOSFET 100. The depth of the second inflection point IP2 is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0118] The depth of first position P1, which indicates the maximum impurity concentration, is preferably large from the viewpoint of improving the reliability of gate insulating layer 16 of MOSFET 100. The depth of first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0119] The depth of the first inflection point IP1 is preferably large from the viewpoint of improving the reliability of gate insulating layer 16 of MOSFET 100. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0120] From the viewpoint of improving the reliability of gate insulating layer 16 of MOSFET 100, it is preferable that the n-type impurity concentration at second inflection point IP2 is low. １９ cm －３ Preferably, it is 2×10 or less.１９ cm －３ More preferably, it is:

[0121] From the viewpoint of achieving both an increase in the on-state current of MOSFET 100 and an improvement in the reliability of gate insulating layer 16, the n-type impurity concentration at first inflection point IP1 is preferably 1.5 to 10 times, and more preferably 2 to 5 times, the n-type impurity concentration at second inflection point IP2.

[0122] From the viewpoint of increasing the on-state current of the MOSFET 100, it is preferable that the n-type impurity concentration at the first peak PK1 is high. The n-type impurity concentration at the first peak PK1 is 3×10 １９ cm －３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0123] From the viewpoint of increasing the on-state current of the MOSFET 100, it is preferable that the n-type impurity concentration at the second peak PK2 is high. The n-type impurity concentration at the second peak PK2 is 1×10 １９ cm －３ It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0124] The depth of second peak PK2 is preferably shallow from the viewpoint of increasing the on-state current of MOSFET 100. The depth of second peak PK2 is preferably 0.1 μm or less, and more preferably 0.08 μm or less.

[0125] The depth of first position P1 where first peak PK1 is provided is preferably large from the viewpoint of improving the reliability of gate insulating layer 16 of MOSFET 100. The depth of first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0126] From the viewpoint of improving the reliability of gate insulating layer 16 of MOSFET 100, the n-type impurity concentration at second peak PK2 is preferably low. １９ cm －３ Preferably, it is 2×10 or less. １９ cm －３ More preferably, it is equal to or greater than this.

[0127] (Variation) A semiconductor device according to a variation of the first embodiment differs from the semiconductor device according to the first embodiment in that the distribution of the first conductivity type impurity concentration in the direction from the first surface to the second surface of the third silicon carbide region includes four inflection points and three peaks.

[0128] 11 is a diagram showing the impurity concentration distribution of a semiconductor device according to a modification of the first embodiment. Fig. 11 is a diagram showing the distribution of n-type impurity concentration in the depth direction of the source region 30. In Fig. 11, the position of zero depth corresponds to the position of the first plane F1. In Fig. 11, the n-type impurity concentration on the vertical axis is expressed on a logarithmic scale.

[0129] The distribution of the n-type impurity concentration in the source region 30 shows a maximum impurity concentration at a first position P1. The depth of the first position P1 showing the maximum impurity concentration is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1 showing the maximum impurity concentration is, for example, 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0130] The distribution of the n-type impurity concentration in the source region 30 has four inflection points on the first face F1 side of the first position P1. The four inflection points are a first inflection point IP1, a second inflection point IP2, a third inflection point IP3, and a fourth inflection point IP4.

[0131] The position of the first inflection point IP1 is deeper than the position of the second inflection point IP2, which is deeper than the position of the third inflection point IP3, which is deeper than the position of the fourth inflection point IP4.

[0132] The first inflection point IP1 is located closest to the first position P1, and the fourth inflection point IP4 is located closest to the first plane F1.

[0133] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0134] The n-type impurity concentration at the first inflection point IP1 is higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4, and is, for example, 1.5 to 10 times the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0135] The depth of the fourth inflection point IP4 is, for example, 0.15 μm or less.

[0136] The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are, for example, 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0137] 11 , the distribution of the n-type impurity concentration in the source region 30 has a first peak PK1, a second peak PK2, and a third peak PK3. The first peak PK1 is located at a first position P1. The second peak PK2 is located at a second position P2. The third peak PK3 is located at a third position P3.

[0138] The second position P2 is located between the first position P1 and the first plane F1. The third position P3 is located between the second position P2 and the first plane F1.

[0139] The third peak PK3 is the peak closest to the first face F1.

[0140] The depth of the first position P1 is, for example, 0.15 μm or more, and the depth of the third position P3 is, for example, 0.1 μm or less.

[0141] The n-type impurity concentrations at the second peak PK2 and the third peak PK3 are lower than the n-type impurity concentration at the first peak PK1. The n-type impurity concentration at the first peak PK1 is 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The n-type impurity concentrations at the second peak PK2 and the third peak PK3 are 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0142] According to the modification of the first embodiment, similarly to the first embodiment, the source region 30 is provided with a low impurity concentration region of a predetermined width having an n-type impurity concentration equal to or greater than a predetermined concentration, on the surface side of the position where the n-type impurity concentration is maximum, thereby realizing a MOSFET that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0143] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the maximum impurity concentration at the first point P1 is high. The n-type impurity concentration at the first point P1 is 3×10 １９ cm －３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0144] From the viewpoint of increasing the on-current of the modified MOSFET, it is preferable that the n-type impurity concentration at the first inflection point IP1 be higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0145] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are high. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are 1×10 １９ cm －３It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0146] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, the depth of the fourth inflection point IP4 is preferably shallow, and is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0147] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first position P1 showing the maximum impurity concentration is large. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0148] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, the depth of the first inflection point IP1 is preferably large. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0149] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET of the modified example, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are low. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are 3×10 １９ cm －３ Preferably, it is 2×10 or less. １９ cm －３ More preferably, it is:

[0150] From the viewpoint of achieving both an increase in the on-state current of the MOSFET of the modified example and an improvement in the reliability of the gate insulating layer 16, the n-type impurity concentration at the first inflection point IP1 is preferably 1.5 to 10 times, and more preferably 2 to 5 times, the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0151] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the n-type impurity concentration at the first peak PK1 is high. The n-type impurity concentration at the first peak PK1 is 3×10 １９ cm －３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0152] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the n-type impurity concentrations at the second peak PK2 and the third peak are high. The n-type impurity concentrations at the second peak PK2 and the third peak are preferably 1×10 １９ cm －３ It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0153] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, the depth of the third peak PK3 is preferably shallow, preferably 0.1 μm or less, and more preferably 0.08 μm or less.

[0154] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, the depth of the first position P1 where the first peak PK1 is provided is preferably large. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0155] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET of the modified example, it is preferable that the n-type impurity concentrations at the second peak PK2 and the third peak PK3 are low. １９ cm －３ Preferably, it is 2×10 or less. １９ cm －３ More preferably, it is equal to or greater than this.

[0156] As described above, according to the first embodiment and its modifications, a MOSFET is realized that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0157] Second Embodiment A semiconductor device according to a second embodiment differs from the semiconductor device according to the first embodiment in that the distribution of the first conductivity type impurity concentration in the direction from the first surface to the second surface of the third silicon carbide region does not have multiple peaks. Hereinafter, some description of content that overlaps with the first embodiment may be omitted.

[0158] 12 is a diagram showing the impurity concentration distribution of the semiconductor device of the second embodiment. Fig. 12 is a diagram showing the distribution of n-type impurity concentration in the depth direction of the source region 30. In Fig. 12, the position of zero depth corresponds to the position of the first plane F1. In Fig. 12, the n-type impurity concentration on the vertical axis is expressed on a logarithmic scale.

[0159] The distribution of the n-type impurity concentration in the source region 30 shows a maximum impurity concentration at a first position P1. The depth of the first position P1 showing the maximum impurity concentration is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1 showing the maximum impurity concentration is, for example, 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0160] The distribution of the n-type impurity concentration in the source region 30 has two inflection points closer to the first face F1 than the first position P1. The two inflection points are a first inflection point IP1 and a second inflection point IP2. The position of the first inflection point IP1 is deeper than the position of the second inflection point IP2. The position of the first inflection point IP1 is closer to the first position P1 than the position of the second inflection point IP2.

[0161] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0162] The n-type impurity concentration at the first inflection point IP1 is higher than the n-type impurity concentration at the second inflection point IP2, and is, for example, 1.5 to 10 times the n-type impurity concentration at the second inflection point IP2.

[0163] The depth of the second inflection point IP2 is, for example, 0.15 μm or less.

[0164] The n-type impurity concentration at the second inflection point IP2 is, for example, 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0165] 12, the distribution of the n-type impurity concentration in the source region 30 has a first peak PK1. The first peak PK1 is located at a first position P1. The depth of the first position P1 is, for example, 0.15 μm or more.

[0166] According to the second embodiment, similarly to the first embodiment, the source region 30 is provided with a low impurity concentration region of a predetermined width having an n-type impurity concentration equal to or greater than a predetermined concentration, on the surface side of the position where the n-type impurity concentration is maximum, thereby realizing a MOSFET that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0167] From the viewpoint of increasing the on-state current of the MOSFET of the second embodiment, it is preferable that the maximum impurity concentration at the first position P1 is high. The n-type impurity concentration at the first position P1 is 3×10 １９ cm －３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0168] From the viewpoint of increasing the on-current of the MOSFET, the n-type impurity concentration at the first inflection point IP1 is preferably higher than the n-type impurity concentration at the second inflection point IP2.

[0169] From the viewpoint of increasing the on-current of the MOSFET, it is preferable that the n-type impurity concentration at the second inflection point IP2 is high. The n-type impurity concentration at the second inflection point IP2 is 1×10 １９ cm －３ It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0170] From the viewpoint of increasing the on-state current of the MOSFET, the depth of the second inflection point IP2 is preferably shallow, and is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0171] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable that the depth of the first position P1 showing the maximum impurity concentration is large. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0172] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable that the depth of the first inflection point IP1 is large. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0173] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET, it is preferable that the n-type impurity concentration at the second inflection point IP2 is low. １９ cm －３ Preferably, it is 2×10 or less. １９ cm －３ More preferably, it is:

[0174] From the viewpoint of achieving both an increase in the on-state current of the MOSFET and an improvement in the reliability of the gate insulating layer 16, the n-type impurity concentration at the first inflection point IP1 is preferably 1.5 to 10 times, and more preferably 2 to 5 times, the n-type impurity concentration at the second inflection point IP2.

[0175] (Variation) A semiconductor device according to a variation of the second embodiment differs from the semiconductor device according to the second embodiment in that the distribution of the first conductivity type impurity concentration in the direction from the first surface to the second surface of the third silicon carbide region includes four inflection points.

[0176] 13 is a diagram showing the impurity concentration distribution of a semiconductor device according to a modification of the second embodiment. Fig. 13 is a diagram showing the distribution of n-type impurity concentration in the depth direction of the source region 30. In Fig. 13, the position of zero depth corresponds to the position of the first plane F1. In Fig. 13, the n-type impurity concentration on the vertical axis is expressed on a logarithmic scale.

[0177] The distribution of the n-type impurity concentration in the source region 30 shows a maximum impurity concentration at a first position P1. The depth of the first position P1 showing the maximum impurity concentration is, for example, 0.15 μm or more. The n-type impurity concentration at the first position P1 showing the maximum impurity concentration is, for example, 3×10 １９ cm －３ 1x10 or more ２０ cm －３ The following is the result.

[0178] The distribution of the n-type impurity concentration in the source region 30 has four inflection points on the first face F1 side of the first position P1. The four inflection points are a first inflection point IP1, a second inflection point IP2, a third inflection point IP3, and a fourth inflection point IP4.

[0179] The position of the first inflection point IP1 is deeper than the position of the second inflection point IP2, which is deeper than the position of the third inflection point IP3, which is deeper than the position of the fourth inflection point IP4.

[0180] The first inflection point IP1 is located closest to the first position P1, and the fourth inflection point IP4 is located closest to the first plane F1.

[0181] The depth of the first inflection point IP1 is, for example, 0.15 μm or more.

[0182] The n-type impurity concentration at the first inflection point IP1 is higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4, and is, for example, 1.5 to 10 times the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0183] The depth of the fourth inflection point IP4 is, for example, 0.15 μm or less.

[0184] The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are, for example, 1×10 １９ cm －３ 3x10 or more １９ cm －３ The following is the result.

[0185] According to the modification of the second embodiment, similarly to the second embodiment, the source region 30 is provided with a low impurity concentration region of a predetermined width having an n-type impurity concentration equal to or greater than a predetermined concentration, on the surface side of the position where the n-type impurity concentration is maximum, thereby realizing a MOSFET that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0186] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the maximum impurity concentration at the first point P1 is high. The n-type impurity concentration at the first point P1 is 3×10 １９ cm －３ It is preferable that the ratio is 5×10 or more. １９ cm －３ More preferably, it is 8×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0187] From the viewpoint of increasing the on-current of the modified MOSFET, it is preferable that the n-type impurity concentration at the first inflection point IP1 be higher than the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0188] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, it is preferable that the n-type impurity concentration at the second inflection point IP2 is high. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are 1×10 １９ cm －３ It is preferable that the ratio is 2×10 or more. １９ cm －３ More preferably, it is equal to or greater than this.

[0189] From the viewpoint of increasing the on-state current of the MOSFET of the modified example, the depth of the fourth inflection point IP4 is preferably shallow, and is preferably 0.15 μm or less, and more preferably 0.1 μm or less.

[0190] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, it is preferable that the depth of the first position P1 showing the maximum impurity concentration is large. The depth of the first position P1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0191] From the viewpoint of improving the reliability of the gate insulating layer 16 of the modified MOSFET, the depth of the first inflection point IP1 is preferably large. The depth of the first inflection point IP1 is preferably 0.15 μm or more, and more preferably 0.2 μm or more.

[0192] From the viewpoint of improving the reliability of the gate insulating layer 16 of the MOSFET of the modified example, it is preferable that the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are low. The n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4 are 3×10 １９ cm －３ Preferably, it is 2×10 or less. １９ cm －３ More preferably, it is:

[0193] From the viewpoint of achieving both an increase in the on-state current of the MOSFET of the modified example and an improvement in the reliability of the gate insulating layer 16, the n-type impurity concentration at the first inflection point IP1 is preferably 1.5 to 10 times, and more preferably 2 to 5 times, the n-type impurity concentrations at the second inflection point IP2, the third inflection point IP3, and the fourth inflection point IP4.

[0194] As described above, according to the second embodiment and its modified example, a MOSFET is realized that can achieve both an increase in on-current and an improvement in the reliability of the gate insulating layer.

[0195] In the first and second embodiments, the number of inflection points is described as two or four, but the number of inflection points is not particularly limited as long as it is two or more. Also, in the first embodiment, the number of peaks is described as two or three, but the number of peaks is not particularly limited as long as it is two or more.

[0196] In the first and second embodiments, the case of 4H—SiC as the crystal structure of SiC has been described as an example, but the present invention can also be applied to devices using SiC with other crystal structures such as 6H—SiC, 3C—SiC, etc. Furthermore, it is also possible to apply a plane other than the (0001) plane to the surface of silicon carbide layer 10.

[0197] In the first and second embodiments, the first conductivity type is n-type and the second conductivity type is p-type, but it is also possible for the first conductivity type to be p-type and the second conductivity type to be n-type.

[0198] In the first and second embodiments, aluminum (Al) is used as an example of a p-type impurity, but boron (B) can also be used. Also, nitrogen (N) and phosphorus (P) are used as examples of n-type impurities, but arsenic (As), antimony (Sb), etc. can also be used.

[0199] The present invention can also be applied to an insulated gate bipolar transistor (IGBT).

[0200] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and modifications thereof are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims.

[0201] REFERENCE SIGNS LIST 10 silicon carbide layer 12 source electrode (first electrode) 12x contact electrode portion (first portion) 12y diode electrode portion (second portion) 14 drain electrode (second electrode) 16a first gate insulating layer 16b second gate insulating layer 18a first gate electrode 18b second gate electrode 24 drift region (first silicon carbide region) 24x JBS region (region) 26 body region (second silicon carbide region) 30 source region (third silicon carbide region) 100 MOSFET (semiconductor device) F1 first surface F2 second surface IP1 first inflection point P1 first position PK1 first peak

Claims

1. A silicon carbide layer having a first surface and a second surface opposite to the first surface, comprising: a first silicon carbide region of a first conductivity type having a region in contact with the first surface; a second silicon carbide region of a second conductivity type provided between the first silicon carbide region and the first surface and extending in a first direction parallel to the first surface; and a third silicon carbide region of a first conductivity type provided between the second silicon carbide region and the first surface, extending in the first direction, and having a first conductivity type impurity concentration higher than a first conductivity type impurity concentration of the first silicon carbide region; and a first gate electrode extending in the first direction and opposite to the second silicon carbide region and the third silicon carbide region. a second gate electrode extending in the first direction, provided in a second direction perpendicular to the first direction with respect to the first gate electrode, and facing the second silicon carbide region and the third silicon carbide region; a first gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the first gate electrode; a second gate insulating layer provided between the second silicon carbide region and the third silicon carbide region and the second gate electrode; a first electrode provided on the first surface side of the silicon carbide layer, the first electrode including: a first portion provided between the first gate electrode and the second gate electrode and in contact with the second silicon carbide region and the third silicon carbide region; and a second portion provided between the first gate electrode and the second gate electrode, in the first direction of the first portion and in contact with the region of the first silicon carbide region; a distribution of a first conductivity type impurity concentration in the third silicon carbide region in a direction from the first surface to the second surface includes a plurality of inflection points on a side of the first surface relative to a first position where the distribution exhibits a maximum impurity concentration when the first conductivity type impurity concentration is expressed on a logarithmic scale.

2. The semiconductor device according to claim 1, wherein a first conductivity type impurity concentration at a first inflection point that is closest to said first position among said plurality of inflection points is higher than first conductivity type impurity concentrations at other inflection points.

3. The semiconductor device according to claim 2, wherein the first conductivity type impurity concentration at the first inflection point is 1.5 to 10 times the first conductivity type impurity concentration at the other inflection points.

4. The semiconductor device according to claim 1, wherein the depth of said first position is 0.15 μm or more.

5. The semiconductor device according to claim 1, wherein a depth of a first inflection point, which is closest to said first position among said plurality of inflection points, is 0.15 μm or more.

6. The maximum impurity concentration is 3×10 １９ cm －３ 2. The semiconductor device according to claim 1.

7. The semiconductor device according to claim 1, wherein the depth of the inflection point closest to said first surface among said plurality of inflection points is 0.15 μm or less.

8. The n-type impurity concentration at an inflection point other than the first inflection point closest to the first position among the plurality of inflection points is 1×10 １９ cm －３ Above 3 x 10 １９ cm －３ 2. The semiconductor device according to claim 1, wherein:

9. The semiconductor device according to claim 1, wherein said distribution has a plurality of peaks including a first peak, said first peak being located at said first position.

10. A semiconductor device according to claim 9, wherein the depth of said first position is 0.15 μm or more, and the depth of a position at which a peak closest to said first surface among said plurality of peaks is provided is 0.1 μm or less.

11. The first conductivity type impurity concentration at the first peak is 3×10 １９ cm －３ Above 1 x 10 ２０ cm －３ the first conductivity type impurity concentration at a peak other than the first peak among the plurality of peaks is 1×10 １９ cm －３ Above 3 x 10 １９ cm －３ 10. The semiconductor device according to claim 9, wherein:

12. The semiconductor device according to claim 1, wherein the depth of said third silicon carbide region is 0.4 μm or less.

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