Semiconductor storage device, method for manufacturing semiconductor storage device, writing method, reading method, and storage system

Abstract

Provided is an SOT-MRAM capable of achieving high density by reducing circuit area. A memory cell array 10 of a semiconductor storage device 1000 includes memory cells 100 arranged in a matrix and each having a magnetic tunnel junction element. The semiconductor memory device 1000 includes: a shared read source line SRSL which is arranged in a column direction and to which terminals of read transistors of memory cells adjacent to each other in a row direction are connected; and bit lines BL0, BL1 which are arranged in a column direction and connected to the other electrodes of the magnetic tunnel junction elements. Read word lines RWL0, RWL1 are activated, either the bit lines or the shared read source line is activated, and a sense amplifier reads out stored data on the basis of a change in a current value of the lines / line which are / is not activated among the bit lines or the shared read source line.

Description

Semiconductor memory device, semiconductor memory device manufacturing method, writing method, reading method, and storage system

[0001] The present invention relates to a semiconductor memory device using a magnetic tunnel junction element, a manufacturing method for the semiconductor memory device, a writing method, a reading method, and a storage system.

[0002] (Background of magnetic random access memory)

[0003] A nonvolatile memory device using a magnetoresistive effect element (MRAM: Magnetic Random Access Memory or Magnetoresistive Random Access Memory) is attracting attention as a next-generation logic integrated circuit.

[0004] One such MRAM configuration is known as the Spin Transfer Torque (STT) MRAM. However, in STT-MRAM, a large voltage is applied across the device's tunnel oxide during write operations, resulting in a continuous trade-off between data retention, write endurance, and write speed. Thus, despite its maturity, STT-MRAM technology remains limited in its ability to meet the requirements of high-speed RAM applications, which require a combination of high speed, infinite endurance, and sufficient data retention.

[0005] As an MRAM configuration that can solve such problems, a three-terminal SOT (Spin Orbit Torque)-MRAM (Magnetic Random Access Memory) is known to be suitable for nonvolatile memories that require high-speed writing. For example, Patent Documents 1 and 2 disclose three-terminal SOT-MRAMs that are configured from a stack of a channel layer, a recording layer, a barrier layer, and a reference layer.

[0006] For example, the memory cell of the SOT-MRAM disclosed in Patent Document 1 is composed of a stack of a channel layer, a recording layer, a barrier layer, and a reference layer from the bottom, and has three terminals.

[0007] The channel layer is a conductive layer made of a heavy metal or the like, and is a region that generates a spin-orbit torque when a write current flows through this layer. The recording layer is made of a magnetic material, and is a magnetic layer whose magnetization M is variable between the +axis and -axis directions due to the spin-orbit torque generated by the write current flowing through the channel layer. The barrier layer is a non-magnetic layer made of a tunnel insulating layer.

[0008] The reference layer is made of a magnetic material, and the direction of the magnetization M is fixed.

[0009] When writing data to the SOT-MRAM, a voltage corresponding to the data to be written is applied between the second and third terminals, and a write current is passed through the channel layer. This causes a spin-orbit torque to act, and the direction of the magnetization M of the recording layer changes according to the direction of the write current. At this time, no current flows through the tunnel insulating layer.

[0010] When the magnetization M of the recording layer and the magnetization of the reference layer are oriented in the same direction (parallel state), the resistance between the reference layer and the recording layer is small. On the other hand, when the magnetization of the recording layer and the magnetization of the reference layer are oriented in opposite directions (antiparallel state), the resistance between the reference layer and the recording layer is relatively large. Data is assigned to the changing resistance value.

[0011] When reading data from the SOT-MRAM, a read voltage is applied between the first terminal and the second terminal or the third terminal, and data corresponding to the magnitude of the read current flowing through a magnetic tunnel junction (MTJ) consisting of a recording layer, a barrier layer, and a reference layer is output.

[0012] The above-described configuration of SOT-MRAM allows for the elimination of high voltage across the tunnel oxide of the device during writing.

[0013] The configuration disclosed in Patent Document 2 is such that even when the integration level is improved, the write current is suppressed and the decrease in read speed is prevented.

[0014] On the other hand, SOT-MRAM is a non-volatile memory technology that uses pure spin current due to the spin Hall effect as described above to perform high-speed writing. As one configuration for this, the use of topological insulators with a strong spin Hall effect is being considered to reduce the write current and power consumption.

[0015] Here, "topological insulators" refers to a group of materials that have an insulator-like state inside but a metallic conductive state on their surface.

[0016] The memory cell configuration of SOT-MRAM using such topological materials was formed by molecular beam epitaxial crystal growth method (Bi, Sb). ２ Te ３ A structure has also been proposed in which a topological insulator is placed as the bottom electrode, and a Ru (5 nm) intermediate layer with a crystalline structure similar to that of the topological insulator is used, on which a CoFeB (2.5 nm) / MgO (2 nm) / CoFeB (5 nm) MTJ is fabricated. In this case, a heat treatment at temperatures between 250°C and 300°C is reported to crystallize the CoFeB magnetic layer. It has been reported that a three-terminal SOT-MRAM device has been fabricated using this process (for example, see Non-Patent Document 1).

[0017] On the other hand, antiferromagnetic materials are attracting attention as a replacement for ferromagnetic materials in the hope of further improving the functionality of devices. Antiferromagnetic materials have the following advantages: (i) they do not produce stray magnetic fields, allowing for high-density devices with simple structures, (ii) their spin resonance frequency is higher at THz than that of ferromagnetic materials (GHz), enabling higher speeds, and (iii) they offer greater freedom in material selection.

[0018] However, because antiferromagnets do not have spontaneous magnetization, it is generally difficult to detect and control the spontaneous response resulting from the spin structure.

[0019] In contrast, the topological antiferromagnetic metal Mn ３ Sn is being actively researched as a candidate material for nonvolatile memory that will lead to the realization of terahertz electronic devices.

[0020] Mn ３Sn is an antiferromagnetic material in which a non-collinear spin structure, called the inverse 120-degree structure, appears at temperatures as high as 430 K. This antiferromagnetic spin structure exhibits a macroscopic broken time-reversal symmetry even in a zero-magnetization state, similar to the case of ferromagnetic order. This is due to the strongly ordered spin structure (cluster magnetic octupole) in which six spins, each consisting of three sublattices, are arranged in a two-layer kagome lattice.

[0021] Here, a "topological antiferromagnet" is a Weyl semimetal that exhibits a topological semimetal state in which the interior is semimetallic and the surface is metallic.

[0022] For example, the spin Hall effect, which converts electric current into spin current, has been studied mainly in transition metals with large spin-orbit coupling. However, the antiferromagnetic material Mn ３ The anomalous Hall effect was also observed in Sn, and furthermore, the "magnetic spin Hall effect" was observed in Mn stacked with a ferromagnetic material. ３ It has been reported that surface spin accumulation occurs on the surface of Sn, generating a spin torque on the magnetization of an adjacent ferromagnetic material (for example, Non-Patent Documents 2 and 3).

[0023] JP 2018-157108 A JP 2023-35644 A

[0024] https: / / www.titech.ac.jp / news / 2021 / 062339https: / / www.jst.go.jp / pr / announce / 20190117-2 / index.htmlhttps: / / www.jst.go.jp / pr / announce / 20151029-2 / index.html

[0025] As mentioned above, MRAM is a random access memory that is non-volatile and has excellent properties such as high speed operation and high durability. For these reasons, it is considered the leading candidate for a technology suitable for integrating non-volatile memory with integrated circuits.

[0026] Although SOT-MRAM can reduce the energy required for writing, it is necessary to form memory cells at a higher density in order to improve the storage capacity.

[0027] However, the current situation is that sufficient research has not been done on the circuit configuration required to realize high-density, high-capacity memories.

[0028] The present invention has been made to solve the above-mentioned problems, and has an object to provide a semiconductor memory device in an SOT-MRAM that can reduce the circuit area and achieve high density.

[0029] Another object of the present invention is to provide a method for writing and reading data in an SOT-MRAM, which is a semiconductor memory device that allows a reduction in circuit area.

[0030] Another object of the present invention is to provide a method for manufacturing an SOT-MRAM, which is a semiconductor memory device that can reduce the circuit area.

[0031] (Item 1)

[0032] According to one aspect of the present invention, a semiconductor memory device includes a memory cell array in which a plurality of memory cells are arranged in a matrix, each memory cell including a magnetic tunnel junction element having a first node and an internal node, and a first electrode connected to the internal node, a plurality of first interconnects arranged in a column direction of the memory cell array for supplying a write current to the first electrode, a plurality of second interconnects arranged in the column direction of the memory cell array for detecting a resistance value between the first node and the first electrode, and a plurality of third interconnects arranged in the column direction of the memory cell array for supplying a reference potential to the memory cell, wherein pairs of memory cells adjacent in a row direction of the memory cell array share either the first interconnect or the third interconnect as a shared interconnect.

[0033] Preferably, in the semiconductor memory device of the configuration of item 1, the first electrode has a second node and a third node, and the semiconductor memory device further includes write selection means for selectively conducting the write current between the second node and the third node of the selected memory cell to enable writing of data by spin-orbit torque, and read selection means for enabling detection of the resistance value between the first node and the second node of the selected memory cell.

[0034] Preferably, in the semiconductor memory device having the configuration of item 1 or 2, the shared wiring is a shared source line that is the third wiring for supplying the reference potential to the memory cells, and the read selection means includes a bit line among the first wirings that is commonly connected to the second nodes of the memory cells, a plurality of read word lines that are provided in the row direction of the memory cell array and that become active potential in response to row selection, and a pair of read transistors that are provided between the first node of one of the pair of memory cells and the shared wiring and between the first node of the other of the pair, respectively, and that become conductive in response to row selection by the read word line (item 4).

[0035] Preferably, in the semiconductor memory device having the configuration of any one of Items 2 and 3, the write selection means includes a bit line of the first wiring commonly connected to the second node of a plurality of the memory cells in the column direction, a plurality of write word lines arranged in the row direction of the memory cell array and set to an active potential in response to row selection, and a write transistor arranged between the second wiring and the third node and set to a conductive state in response to row selection by the write word line (Item 5).

[0036] Preferably, in the semiconductor memory device having the configuration of any one of Items 2 to 4, the shared wiring is a common bit line that is the first wiring for supplying the write current to the memory cell, and the write selection means includes a plurality of first word lines arranged in the row direction of the memory cell array and set to an active potential in response to row selection, a plurality of second word lines arranged in the row direction of the memory cell array and set to an active potential in response to row selection, a first transistor arranged between the second wiring and the third node and set to a conductive state in response to row selection by the first word line, and a second transistor arranged between the common bit line and the second node and set to a conductive state in response to row selection by the second word line (Item 6).

[0037] Preferably, in the semiconductor memory device having the configuration of item 5, the read selection means includes a read bit line among the third wirings that is commonly connected to the first nodes of a plurality of the memory cells in the column direction, and the second transistor is rendered conductive in a read operation in response to row selection by the second word line (item 7).

[0038] Preferably, in the semiconductor memory device having the configuration of any one of items 1 to 6, the first electrode is provided so that one surface thereof is commonly connected to each of the internal nodes of a plurality of memory cells adjacent in the column direction, the other surface of the first electrode opposite to the one surface has a first contact portion for enabling electrical connection with the first wiring and a second contact portion for enabling electrical connection with the second wiring, and the connection portion with the internal node on the one surface is located on a current path between the first contact portion and the second contact portion on the other surface (Item 8).

[0039] Preferably, in the semiconductor memory device having the configuration of any one of items 1 to 6, the first electrode is provided so that one surface thereof is commonly connected to each of the internal nodes of a pair of memory cells adjacent to each other in the column direction, and the other surface of the first electrode opposite to the one surface has a first contact portion for enabling electrical connection to either the first wiring or the second wiring, and a second contact portion for enabling electrical connection to the other of the first wiring or the second wiring, and either the first contact portion or the second contact portion is shared by the pair of memory cells (Item 9).

[0040] Preferably, in the semiconductor memory device having the configuration of item 8, a bottom surface on which the internal node of each of the magnetic tunnel junction elements of the pair of memory cells is provided has a major axis direction and a minor axis direction, and the magnetic tunnel junction elements are arranged so that the major axis direction is along a current path from one of the shared first contact portion and the shared second contact portion to the other of the shared first contact portion and the shared second contact portion (item 10).

[0041] According to another aspect of the present invention, a semiconductor memory device includes a memory cell array having a plurality of memory cells arranged in rows and columns on a semiconductor substrate, each memory cell including a magnetic tunnel junction element having a first node and an internal node, and a first electrode provided below the internal node and having a second node and a third node, write selection means for selectively conducting a write current between the second node and the third node of a selected memory cell to enable writing of data by spin-orbit torque, and read selection means for enabling detection of a resistance value between the first node and the second node of the selected memory cell, the read selection means including a plurality of read word lines provided in a row direction of the memory cell array and set to an active potential in response to row selection, read wiring provided above the memory cells along a column direction of the memory cell array for detecting the resistance value, and a read transistor provided between the first node and the read wiring and turned on in response to row selection by the read word line during a read operation (Item 11).

[0042] Preferably, in the semiconductor memory device having the configuration of item 10, the read transistor is a vertical MOS transistor formed above the first node. (Item 12)

[0043] Preferably, in the semiconductor memory device of item 10, the memory cell array and the read transistor are formed on a second semiconductor substrate, the write wiring and the write transistor for selecting the memory cell during writing are formed on a first semiconductor substrate different from the second semiconductor substrate, and the semiconductor memory device is formed by bonding the first semiconductor substrate and the second semiconductor substrate together (item 13).

[0044] According to another aspect of the present invention, there is provided a storage system including at least one semiconductor device according to any one of items 1 to 12, and further including a circuit that executes processing based on data stored in the semiconductor storage device. (Item 14)

[0045] According to yet another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, the method comprising: a lower layer manufacturing step of forming a write transistor on a semiconductor substrate by a complementary MOS transistor manufacturing method, the write transistor enabling opening and closing of a current path in a write operation, and forming a first wiring layer for supplying current in the write operation and a planarized first interlayer insulating film layer; a memory element manufacturing step of forming a magnetic tunnel junction element on the first interlayer insulating film layer to connect one terminal of the write transistor and forming a planarized second interlayer insulating film layer; and an upper layer manufacturing step of forming a read transistor, which is a vertical transistor, on the second interlayer insulating film layer to enable opening and closing of a current path to the other terminal of the magnetic tunnel junction element in a read operation, and forming a read wiring for performing a read operation via the current path (Item 15).

[0046] According to yet another aspect of the present invention, there is provided a method for manufacturing a semiconductor memory device, comprising a first semiconductor manufacturing step of forming, on a first semiconductor substrate by a complementary MOS transistor manufacturing method, a write transistor for enabling opening and closing of a current path in a write operation, forming a first wiring layer for supplying current in the write operation, forming a planarized first interlayer insulating film layer, and forming a first contact portion to the first wiring layer; and forming, on a second semiconductor substrate by a complementary MOS transistor manufacturing method, forming a read transistor, on a second semiconductor substrate by a complementary MOS transistor manufacturing method, forming a planarized second interlayer insulating film layer, and forming a first contact portion to the second interlayer insulating film. The method includes a second semiconductor manufacturing step of forming a magnetic tunnel junction element on an insulating film layer so that the read transistor and a first node are connected and the read transistor can open and close a current path to the first node during a read operation, forming a planarized third interlayer insulating film layer, and forming second contact portions of the first electrode of the magnetic tunnel junction element to the second node and the third node, and a bonding step of bonding an upper surface of the first semiconductor substrate and an upper surface of the second semiconductor substrate so that the first contact portion and the second contact portion are bonded to form a memory cell (Item 16).

[0047] According to yet another aspect of the present invention, there is provided a method for reading stored data in a semiconductor memory device, the semiconductor memory device comprising a memory cell array, the memory cell array including memory cells arranged in rows and each having a magnetic tunnel junction element, read transistors connected to one electrode of the magnetic tunnel junction element and switchable by a read word line arranged in a row direction, shared read source lines arranged in a column direction and connected to terminals of the read transistors of memory cells adjacent in the row direction, and bit lines arranged in the column direction and connected to the other electrode of the magnetic tunnel junction element, the method comprising the steps of activating the read word line and activating either the bit line or the shared read source line, and reading the stored data based on a change in a current value in the inactivated one of the bit line or the shared read source line.

[0048] According to yet another aspect of the present invention, there is provided a method for writing stored data in a semiconductor memory device, the semiconductor memory device comprising: a memory cell array; the memory cell array including memory cells arranged in rows and columns, each memory cell having a magnetic tunnel junction element and a first electrode for writing data to the magnetic tunnel junction element by spin-orbit torque; a write transistor connected to one terminal of the first electrode and switchable by a write word line provided in the row direction; a read transistor connected to the other terminal of the first electrode and switchable by a read word line provided in the row direction; and a write transistor connected to the other terminal of the first electrode and switchable by a read word line provided in the row direction, the write transistors being arranged in a column direction and being connected to the memory cells adjacent to each other in the row direction. the write word line and the read word line corresponding to the memory cell to be written are connected to an active potential; and the voltage value of the read bit line is set to an intermediate value between the active potential and the inactive potential, and a current is passed through the first electrode in a direction corresponding to the write data.

[0049] According to the configuration of the semiconductor memory device of the present invention, in the SOT-MRAM, the circuit area can be reduced and high density can be achieved.

[0050] Furthermore, according to the method for manufacturing a semiconductor memory device of the present invention, it is possible to manufacture an SOT-MRAM that can reduce the circuit area and increase the density.

[0051] More specifically, in an SOT-MRAM that can reduce the circuit area and increase the density, efficient data reading and writing becomes possible.

[0052] 1 is a diagram showing an overview of an MTJ element constituting a memory cell. FIG. 2 is a diagram showing a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM. FIG. 3 is a diagram showing the planar shape of bottom electrodes corresponding to MTJ elements adjacent in the column direction in the SOT-MRAM structure of the comparative example. FIG. 4 is a diagram showing an example of a cross-sectional structure of the circuit configuration of the MRAM of the comparative example when formed on a silicon substrate. FIG. 5 is a diagram showing control of the potential of each signal line in read operation and write operation of the comparative example. FIG. 6 is a conceptual diagram for explaining the configuration of a memory cell array 90 and a circuit for controlling read and write in a semiconductor memory device 9000 of the comparative example. FIG. 7 is a circuit diagram for explaining the circuit configuration of a memory cell array 10 and memory cells 100 in a semiconductor memory device 1000 of the first embodiment. FIG. 8 is a diagram showing control of the potential of each signal line in read operation and write operation in the first embodiment. FIG. 9 is a conceptual diagram for explaining the configuration of a memory cell array 10 and a circuit for controlling read and write in the semiconductor memory device 1000 of the first embodiment. FIG. 10 is a circuit diagram for explaining the circuit configuration of a memory cell array 20 and memory cells 200 in a semiconductor memory device 2000 of the second embodiment. FIG. 11 is a diagram showing control of the potential of each signal line in read operation and write operation in the second embodiment. FIG. 1 is a conceptual diagram for explaining the configuration of a memory cell array 20 and a circuit for controlling read and write in a semiconductor memory device 2000. FIG. 2 is a conceptual diagram for explaining a bottom electrode pattern of a third embodiment, to be compared with FIG. 3. FIG. 3 is a diagram showing a first modified example of the shape of the bottom electrode pattern of the third embodiment. FIG. 4 is a diagram showing a second modified example of the shape of the bottom electrode pattern of the third embodiment. FIG. 5 is a circuit diagram for explaining the configuration of a memory cell array 30 and a memory cell 300 of a semiconductor memory device 3000 of a fourth embodiment. FIG. 6 is a diagram showing control of the potential of each signal line in a read operation and a write operation of the fourth embodiment. FIG. 7 is a cross-sectional view showing a cross-sectional structure of a memory cell 300 of the fourth embodiment. FIG. 8 is a diagram showing an example of a method for manufacturing an element structure of a memory cell 300 of the fourth embodiment. FIG. 9 is a diagram showing an example of a method for manufacturing an element structure of a memory cell 300 of the fourth embodiment. FIG. 10 is a diagram showing an example of a method for manufacturing an element structure of a memory cell 300 of the fourth embodiment.FIG. 10 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 11 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 12 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 13 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 14 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 15 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment. FIG. 16 is a diagram showing an example of a manufacturing method for the element structure of the memory cell 300 according to the fourth embodiment.

[0053] The configuration of a semiconductor memory device according to an embodiment of the present invention will be described below. In the following embodiments, components and processing steps denoted by the same reference numerals are the same or equivalent, and unless necessary, their description will not be repeated. [Embodiment 1] (Comparative Example of MRAM Circuit Configuration)

[0054] Preferred embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In this specification and drawings, components having substantially the same functional configurations are designated by the same reference numerals, and their descriptions will not be repeated in principle.

[0055] FIG. 1 is a conceptual diagram showing the configuration of a magnetic tunnel junction element (hereinafter referred to as an "MTJ element") that constitutes a memory cell.

[0056] 1, the rectangle between node T2 and node T3 indicates the bottom electrode LEL, node T1 is the top electrode, node T2 is one end of the bottom electrode, and node T3 is the other end of the bottom electrode. Note that the "bottom electrode" here is an example of a "first electrode" along which a write current flows during a write operation of the SOT-MRAM. When the top-bottom structure of the MTJ element is inverted as described below, the top electrode provided on the internal node corresponds to the "first electrode."

[0057] An MTJ element is formed on the lower electrode LEL via an internal node Tint.

[0058] In FIG. 1, the MTJ element is simplified and represented as a variable resistor.

[0059] FIG. 2 is a circuit diagram of a comparative example for explaining the circuit configuration of an MRAM.

[0060] 2 shows an example of a schematic diagram of memory cells 900 in a memory array 90. This is only a portion of the memory cells, and in reality, many more memory cells and corresponding signal lines are arranged in both the row and column directions, but these are not shown in FIG.

[0061] 2, since the SOT-type MRAM is a three-terminal element, in principle, a transistor must be placed at each node as a select gate, which means that three transistors are required per memory cell.

[0062] The configuration of a memory cell 900 including an MTJ element MTJ00 will be described below as an example.

[0063] In contrast, as shown in FIG. 2, for example, by controlling the potential of one of the nodes (CTN002) with a select line that is selectively set to an active potential, it is possible to provide two select transistors per memory cell. That is, select transistors TR001 and TR003 are provided corresponding to nodes CTN001 and CTN003, respectively. The gate potential of select transistor TR001 is controlled by read word line RWL0, and the gate potential of transistor TR003 is controlled by write word line WWL0. With this configuration, one MTJ element, two select transistors, and three memory cell nodes can be provided per memory cell 900.

[0064] However, the number of elements is still large in the configuration shown in Fig. 2. In addition, since the read transistor TR001 needs to be provided on the semiconductor substrate, a vertical contact connection is required to connect the upper electrode of the MTJ element to the bottom silicon layer, as will be described later.

[0065] 3 is a diagram showing an example of the planar shape of the lower electrode LEL corresponding to the MTJ elements MTJ00 and MTJ10 in the region indicated by the symbol 2CH in the SOT-MRAM structure shown in FIG. 2, the positions of through-holes for connection from the lower surface side of the lower electrode LEL to the lower electrode LEL (portions connecting to the second node and the third node of the lower electrode via the through-holes are respectively referred to as "contact portions"), and the position of the lower surface of the MTJ element on the upper surface side of the lower electrode LEL. Therefore, FIG. 3 virtually shows the state in which the lower surfaces of the MTJ elements MTJ00 and MTJ10 are viewed from the lower surface side of the lower electrode LEL through the lower electrode LEL.

[0066] As shown in FIG. 3, through holes are located on both ends of the lower electrode LEL so that current flows directly below the MTJ elements MTJ00 and MTJ10.

[0067] In the following description, the term "MTJ element (magnetic tunnel junction element)" refers to an element having a structure in which two ferromagnetic layers sandwich a tunnel insulating film. The resistance to a current passing through this ferromagnetic layer / tunnel insulating film / ferromagnetic layer structure is small when the magnetic field directions of the two ferromagnetic layers are parallel, and large when they are antiparallel, due to the tunnel magnetoresistance effect.

[0068] In an MTJ element, the direction of one of the two magnetic layers sandwiching the tunnel insulating film is fixed. This magnetic layer is called the "pinned layer." The direction of the other magnetic layer can be changed to be parallel or anti-parallel to the magnetic field direction of the magnetic layer of the pinned layer, selectively setting the resistance of the MTJ element to either low or high. This magnetic layer is called the "free layer."

[0069] Although the stacked structure of the MTJ element shown in FIGS. 1 to 3 is not particularly limited, in each of the embodiments described later, for example, a stacked structure of CoFeB / MgO / CoFeB is formed as a conventional ferromagnetic layer / tunnel insulating film / ferromagnetic layer, and further, Mn is formed under the CoFeB on the free layer side. ３ The structure is such that Sn is provided. The Mn is provided under the CoFeB on the free layer side. ３ Preferably, the alloy is a non-collinear antiferromagnetic material, such as Sn, and has a chiral spin structure.

[0070] As mentioned above, the magnetic spin Hall effect ３ Surface spin accumulation occurs on the surface of Sn, which generates a spin torque on the magnetization of the adjacent ferromagnetic material. ３ Sn has a structure that assists the spin reversal of the CoFeB in the free layer. As a result, the current density required for the spin reversal can be reduced. This allows the advantages of the memory cell and memory array structures according to each embodiment to be further utilized.

[0071] The lower electrode of the MTJ element can be made of, for example, tungsten (W). However, the metal for the electrode is not limited to this. As for the antiferromagnetic material, any (non)collinear antiferromagnetic material that produces the anomalous Hall effect, such as Mn ３ The material of the ferromagnetic layer is not limited to CoFeB, and may be, for example, CoFe. The tunnel insulating film (barrier layer) may be made of AlO in addition to MgO. ｘ , TiO ｘ etc. may also be used.

[0072] Furthermore, the structure of the MTJ element is not particularly limited to the above configuration. For example, a non-collinear antiferromagnetic material (e.g., Mn ３ The MTJ element may have a structure in which Sn) is used as the free layer and / or the fixed layer.

[0073] FIG. 4 is a diagram showing an example of a cross-sectional structure when the circuit configuration of the MRAM shown in FIG. 2 is formed on a silicon substrate.

[0074] Referring to FIG. 4, a transistor TR003 and a transistor TR001 are formed on a silicon substrate.

[0075] Here, the process of forming a transistor is called the "front-end process." The multi-layer wiring process that follows the front-end process is called the "back-end process."

[0076] The source side of transistor TR003 is connected to column source line CSL0 via contact CL. Here, column source line CSL0 is formed, for example, by first layer wiring ML1. As will be described later, the potential of column source line CSL0 is selectively driven by a source line driver circuit.

[0077] The source side of transistor TR001 is connected to read source line RSL0 via contact CL. Here, read source line RSL0 is formed, for example, by first-layer wiring ML1 on a silicon substrate. As will be described later, the potential of read source line RSL0 is supplied to sense amplifier SA0 via a source line driver circuit, and data is read.

[0078] Although not shown, a multi-layer wiring made up of n layers is formed on the silicon substrate, and for example, the bit line BL0 is formed by the nth layer wiring, which is the top layer. A via hole VH is formed in the bit line BL0 to connect it to one node CTN002 of the lower electrode LEL.

[0079] In addition, the drain side of the transistor TR003 is connected to the wiring up to the nth layer via a contact CL and a plurality of via holes VH, and a via hole VH is formed on the wiring of the nth layer to connect to the other node CTN003 of the lower electrode LEL.

[0080] The second layer wiring to the (n-1)th layer wiring form, for example, a read word line, a write word line, and the like.

[0081] The above configuration is formed in the front-end and lower layer wiring process of silicon semiconductor.

[0082] That is, the process from forming a transistor on a silicon semiconductor substrate to the wiring process just before forming an MTJ element is called the "front-end / lower layer wiring process."

[0083] In the front-end lower layer wiring process, the surface of the lower insulating layer is desirably planarized by a polishing step using CMP (Chemical Mechanical Polishing) or the like.

[0084] In the multi-layer wiring in the front-end / lower layer wiring process, the connection with the source and drain of the transistor is made by forming plugs using a contact embedding technique such as tungsten, and for example, for the first layer wiring, a film of an aluminum alloy (AlSiCu, AlCu, etc.) may be formed by a PVD (Physical Vapor Deposition) method or the like, and then the wiring may be formed by processing it by dry etching.

[0085] Furthermore, the multilayer wiring technique may be a so-called "damascene technique." That is, after forming wiring grooves on an insulating film, wiring metal (e.g., Cu) is deposited by plating or the like, and the wiring metal is left only in the grooves by polishing using CMP (Chemical Mechanical Planarization) or the like, thereby forming multilayer wiring.

[0086] The damascene method can be either single damascene or dual damascene. When multilayer wiring is formed using the damascene method, a flat wiring structure can be obtained without the need for polishing the wiring metal to flatten the layers, making it easy to create multilayer fine wiring.

[0087] An MTJ element is formed in an upper layer wiring process on a silicon semiconductor substrate that has undergone a front-end / lower layer wiring process.

[0088] Specifically, the lower electrode LEL is formed in the upper layer of the via hole VH for connection to one node of the lower electrode LEL and the via hole VH for connection to the other node of the lower electrode LEL.

[0089] Furthermore, on the bottom electrode, as an MTJ element, Mn ３ After forming an Sn layer, a CoFeB layer as a free layer, an MgO layer as a barrier layer, a CoFeB layer as a pinned layer, a Ta layer, and a contact layer and etching them into the shape of an MTJ element, an upper electrode is formed and connected to the drain side of transistor TR001 via a contact in the upper layer wiring process and a multi-layer wiring layer in the front-end / lower layer wiring process.

[0090] Although not particularly limited, Mn ３ Regarding the method of forming the Sn layer, the sputtering method is disclosed in the following publicly known document: https: / / www.issp.u-tokyo.ac.jp / maincontents / docs / tayori59-1_Part4.pdf

[0091] Furthermore, an MTJ element having a CoFeB layer as a free layer, an MgO layer as a barrier layer, and a CoFeB layer as a pinned layer has been conventionally adopted as an MTJ element for MRAM.

[0092] To achieve this configuration, as described above, it is necessary to provide not only the write transistor TR003 but also the read transistor TR001 on the semiconductor substrate, and to provide a vertical contact connection to connect the upper electrode of the MTJ element to the drain of the bottom-most transistor TR001. Therefore, providing a read transistor TR001 for each memory cell increases the circuit area.

[0093] FIG. 5 is a diagram showing control of the potential of each signal line in read and write operations in a comparative example.

[0094] FIG. 6 is a conceptual diagram illustrating the configuration of a memory cell array 90 and circuits for controlling reading and writing in a semiconductor memory device 9000 of the comparative example.

[0095] First, referring to FIG. 6, the semiconductor memory device 9000 includes a memory cell array 90, a write decoder 9030 for controlling the reading and writing of data from each memory cell 900 in the memory cell array 90, a read decoder 9040, a source line driver 9010, a bit line driver 9020, and sense amplifiers SA0 to SA1.

[0096] In a write operation to the memory cell 900, the write decoder 9030 selects and activates the write word line WWL of the memory cell to be written.

[0097] In a read operation to the memory cell 900, the read decoder 9040 selects and activates the read word line RWL of the memory cell that is the target of reading.

[0098] When writing data to a selected memory cell, the bit line driver 9020 and source line driver 9010 select the bit line and column source line of the corresponding column (column selection) and switch the potentials of the bit line BL0 and column source line CSL0 to either a high potential (e.g., power supply potential (Vdd) level) or a low potential (e.g., ground potential (Gnd) level) to pass a current through the lower electrode LEL in a direction corresponding to the write data. The source line driver 9010 also controls the potential of the selected source line CSL0 to a low potential during reading. The sense amplifiers SA0-SA1 amplify the current flowing from the read source lines RSL0-RSL1 of the selected memory cell and output it as read data.

[0099] 5 and 6, the control of the potentials of the word lines, column source lines, read source lines, and bit lines during writing and reading will be described.

[0100] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected. (Writing Data "0")

[0101] First, when writing data "0" to a selected memory cell (Write-0 in FIG. 5), the write decoder 9030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). At this time, the read decoder 9040 sets the read word line RWL0 to an inactive potential (low potential, for example, ground potential GND).

[0102] In this state, the bit line driver 9020 sets the bit line BL0 to an active potential (high potential), and the source line driver 9010 sets the column source line CSL0 to an inactive potential (low potential). A current path is formed between the bit line BL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0, thereby injecting spins into the MTJ element MTJ00. (Writing data "1")

[0103] When data "1" is written to the selected memory cell (Write-1 in FIG. 5), the potential of the bit line BL0 and the potential of the column source line CSL0 are controlled in the opposite manner to when data "0" is written.

[0104] During the data write operation, in unselected memory cells (memory cells to which data is not written, shown as standby state (St-by) in FIG. 5), both the bit lines and column select lines are held at the inactive potential. (Data Read)

[0105] When reading data from a selected memory cell, the read decoder 9040 sets the read word line RWL0 to an active potential.

[0106] When the bit line driver 9020 sets the potential of the bit line BL of the selected column to an active potential, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the read source line RSL0 of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is "1" or "0." Therefore, the sense amplifier SA0 detects the current value of the read source line RSL0, thereby reading out data. (Semiconductor Memory Device of the Embodiment)

[0107] As described above, in the semiconductor memory device 9000 of the comparative example, as mentioned above, it is possible to reduce the number of select transistors per memory cell to 2. However, the select transistors are formed on the silicon substrate in the front-end process and are connected in the lower layer wiring process, so the circuit area is not sufficiently reduced.

[0108] Therefore, the following describes a circuit configuration that can reduce the circuit area in a semiconductor memory device having a memory cell array in which multiple memory cells are arranged in a matrix by sharing signal lines used for writing or reading between memory cells.

[0109] In the following, a memory cell having an MTJ element MTJ00 in the memory cell array will be described as an example of a selected memory cell.

[0110] That is, as described above, the MTJ element has an internal node connected to the first node CTN0001 and the bottom electrode LEL00. The bottom electrode also has a second node CTN002 and a third node CTN003 that are coupled to a signal line for causing a current to flow through the bottom electrode.

[0111] A plurality of first wirings for supplying a write current to the lower electrodes of the memory cells are provided in the column direction of the memory cell array, and a plurality of second wirings for detecting the resistance value between the first node CTN001 and the lower electrodes in a read operation are provided in the column direction of the memory cell array.

[0112] A plurality of third wirings for supplying a reference potential to the memory cells in the write operation and / or read operation are provided in the column direction of the memory cell array.

[0113] Here, the reference potential is a potential that serves as a reference when supplying a write current or detecting a read current in a write operation or a read operation, and is not particularly limited, but as will be described later, can be, for example, the power supply potential Vdd or an intermediate value of the power supply potential (Vdd / 2). However, the value of the reference potential can be changed depending on the circuit configuration, and is not limited to these values.

[0114] In the semiconductor memory device described below, a pair of memory cells adjacent to each other in the row direction of the memory cell array share either the first wiring or the third wiring as a shared wiring.

[0115] Each memory cell is provided with a select transistor, and in a write operation, a driver circuit (a write decoder and, if necessary, a read decoder) controls the gate potential of the select transistor of a selected memory cell via a corresponding word line, thereby selectively conducting a write current between the second node CTN002 and the third node CTN003 of the lower electrode, and writing data is performed by spin-orbit torque. The word lines are provided in the row direction of the memory cell array.

[0116] Furthermore, in a read operation, the driver circuit (a read decoder and, if necessary, a write decoder) controls the gate potential of the select transistor of the selected memory cell via the corresponding word line, thereby making it possible to detect the resistance value between the first node CTN001 and the second node CTN002 of the selected memory cell. The resistance value of the memory cell is detected by a sense amplifier via a second wiring provided corresponding to the selected memory cell, and data is read out. (Embodiment 1)

[0117] FIG. 7 is a circuit diagram for illustrating the circuit configuration of the memory cell array 10 and the memory cells 100 of the semiconductor memory device 1000 according to the first embodiment.

[0118] As in FIG. 2, FIG. 7 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row and column directions, they are not shown in FIG. 7.

[0119] FIG. 8 is a diagram showing control of the potential of each signal line in the read operation and the write operation according to the first embodiment.

[0120] FIG. 9 is a conceptual diagram for illustrating the configuration of memory cell array 10 and circuits for controlling reading and writing in semiconductor memory device 1000 according to the first embodiment.

[0121] Here again, the selected memory cell will be described by taking the memory cell 100 having the MTJ element MTJ00 in the memory cell array 10 as an example.

[0122] 7, a memory cell 100 having an MTJ element MTJ00 of the first embodiment shares a read source line SRSL with a memory cell having an MTJ element MTJ01 adjacent in the row direction via a read transistor TR001, thereby reducing the circuit area.

[0123] That is, in the memory cell array 10, the shared wiring is a shared read source line SRSL for supplying a reference potential to the memory cells.

[0124] 7 and 9, semiconductor memory device 1000 includes, as a configuration for selecting a memory cell from which reading is to be performed, bit lines BL0-BL1 arranged in the column direction of memory cell array 10 and commonly connected to second nodes of the memory cells, and a bit line driver 1020 for selectively driving the bit line potential. Semiconductor memory device 1000 also includes, as a configuration for selecting a memory cell from which reading is to be performed, a plurality of read word lines RWL0-RWL1 arranged in the row direction of memory cell array and set to an active potential in response to row selection, and a read decoder 1040 for selectively driving the potential of the corresponding read word lines RWL0-RWL1 in response to row selection. Furthermore, the semiconductor memory device 1000 includes pairs of read transistors TR001 to TR011, TR101 to TR111 that are provided between the first node of one of a pair of adjacent memory cells in the row direction and the read source line SRSL and between the first node of the other of the pair and the read source line SRSL, and that are turned on in response to row selection by a read word line.

[0125] The semiconductor memory device 1000 has a configuration for selecting a memory cell to be written, in which bit lines BL0-BL1 commonly connected to second nodes of the memory cells are arranged in the column direction of the memory cell array 10. The semiconductor memory device 1000 also has a bit line driver 1020 for selectively driving the potentials of these bit lines. The semiconductor memory device 1000 has a configuration for selecting a memory cell to be written, in which the semiconductor memory device 1000 has a plurality of write word lines WWL0-WWL1 arranged in the row direction of the memory cell array and set to an active potential in response to row selection, write transistors TR003, TR013, TR103, and TR113 whose gate potentials are controlled by the write word lines WWL0-WWL1, and a write decoder 1030 that selectively drives the potentials of the corresponding write word lines WWL0-WWL1 in response to row selection.

[0126] The other configuration is the same as that described with reference to FIG. 2, and therefore description thereof will not be repeated.

[0127] 8 and 9, the control of the potentials of the word lines, column source lines, common read source lines, and bit lines during writing and reading will be described.

[0128] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected. (Writing Data "0")

[0129] First, when writing data "0" to a selected memory cell (Write-0 in FIG. 8), the write decoder 1030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). At this time, the read decoder 1040 sets the read word line RWL0 to an inactive potential (low potential, for example, ground potential GND).

[0130] In this state, the bit line driver 1020 sets the bit line BL0 to an active potential (high potential), and the source line driver 1010 sets the column source line CSL0 to an inactive potential (low potential). A current path is formed between the bit line BL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0, thereby injecting spins into the MTJ element MTJ00. (Writing data "1")

[0131] When data "1" is written to the selected memory cell (Write-1 in FIG. 8), the potential of the bit line BL0 and the potential of the column source line CSL0 are controlled in the opposite manner to that in the case of data "0".

[0132] During the data write operation, in unselected memory cells (memory cells to which data is not written; in FIG. 8, these are shown as standby state (St-by)), both the bit lines and the column select lines are held at an inactive potential (low potential, for example, ground potential GND). (Data Read)

[0133] When reading data from a selected memory cell, the read decoder 1040 sets the read word line RWL0 to an active potential.

[0134] When the bit line driver 1020 sets the potential of the bit line BL0 of the selected column to an active potential, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the shared read source line SRSL of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is "1" or "0." Therefore, the sense amplifier SA detects the current value of the shared read source line SRSL, thereby reading out data.

[0135] 9, the memory cell column including the MTJ element MTJ00 and the memory cell column including the MTJ element MTJ01 share not only the shared read source line SRSL but also the sense amplifier SA. This also reduces the circuit area for the sense amplifier. (Data Read Procedure of First Embodiment)

[0136] As explained above, the data read procedure of the first embodiment can be summarized as follows.

[0137] In the configuration of the semiconductor memory device 1000, the read decoder 1040 activates the read word line corresponding to the selected memory cell, sets the bit line to an active potential, and sets the shared read source line to a non-active potential.

[0138] The sense amplifier SA reads out the stored data based on the change in the current value of the common read source line, which is at the inactive potential.

[0139] Alternatively, a sense amplifier SA may be arranged on the bit line driver side, and in a read operation, the bit line is set to an inactive potential, the shared read source line is set to an active potential, and the sense amplifier SA reads out stored data based on a change in the current value of the bit line (Embodiment 2).

[0140] FIG. 10 is a circuit diagram for illustrating the circuit configuration of the memory cell array 20 and the memory cells 200 of the semiconductor memory device 2000 according to the second embodiment.

[0141] As in FIG. 7, FIG. 10 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row and column directions, they are not shown in FIG. 10.

[0142] FIG. 11 is a diagram showing control of the potential of each signal line in the read operation and the write operation according to the second embodiment.

[0143] FIG. 12 is a conceptual diagram for explaining the configuration of the memory cell array 20 and circuits for controlling reading and writing in the semiconductor memory device 2000. In FIG.

[0144] Here again, the selected memory cell will be described by taking the memory cell 100 having the MTJ element MTJ00 in the memory cell array 10 as an example.

[0145] 10, a memory cell 200 having an MTJ element MTJ00 of the second embodiment shares a shared bit line SBL with a memory cell having an MTJ element MTJ01 adjacent in the row direction via read transistors TR002 and TR012, thereby reducing the circuit area.

[0146] That is, in the memory cell array 20, the shared wiring is a shared bit line SBL for supplying a write current to the memory cell during a write operation. As will be described later, the shared bit line SBL is set to an active potential by the bit line driver during a read operation.

[0147] 10 and 12, the semiconductor memory device 2000 includes, as a configuration for selecting a memory cell to be read, read bit lines RBL0-RBL1 arranged in the column direction of the memory cell array 10 and commonly connected to first nodes of the memory cells. The semiconductor memory device 2000 further includes sense amplifiers SA0-SA1 for detecting currents flowing through the bit lines RBL0-RBL1 during a read operation, and a bit line driver 2020 for driving the bit line potential from the ground potential to an intermediate potential (Vdd / 2, hereinafter referred to as the "intermediate potential") between the power supply potential and the ground potential, and for selectively driving the potential of the shared bit line SBL to an active potential Vdd. The semiconductor memory device 1000 includes, as a configuration for selecting a memory cell to be read, a plurality of read word lines RWL0-RWL1 arranged in the row direction of the memory cell array and set to an active potential in response to row selection, and a read decoder 2040 for selectively driving the potential of the corresponding read word lines RWL0-RWL1 in response to row selection. Furthermore, the semiconductor memory device 1000 includes a pair of read transistors TR002 to TR012, TR102 to TR112, which are provided between the second node of one of a pair of adjacent memory cells in the row direction and the bit line SBL, and between the second node of the other of the pair and the shared bit line SBL, and which are turned on in response to row selection by a read word line.

[0148] The semiconductor memory device 1000 includes, as a configuration for selecting memory cells to be written, a plurality of write word lines WWL0-WWL1 arranged in the row direction of the memory cell array 10 and set to an active potential in response to row selection, column source lines CSL0-CSL1 arranged in the column direction of the memory cell array 20, a source line driver 2010 for selectively driving the potentials of the column source lines CSL0-CSL1, and write transistors TR003-TR013, TR103-TR113 arranged between third nodes of the memory cells 200 and the corresponding column source lines and set to a conductive state in response to row selection by the write word lines WWL0-WWL1. Note that in the memory cell array 20, when a write operation is performed, the potentials of the read word lines RWL0-RWL1 also become an active potential in response to row selection by the read decoder 2040, and the read transistors TR002-TR012, TR102-TR112 are also selectively set to a conductive state.

[0149] The other configuration is the same as that described with reference to FIG. 2, and therefore description thereof will not be repeated.

[0150] 11 and 12, the control of the potentials of the word lines, column source lines, shared read source lines, and bit lines during writing and reading will be described.

[0151] In the following description, it is assumed that the memory cell corresponding to the MTJ element MTJ00 is selected. (Writing Data "0")

[0152] First, when writing data "0" to a selected memory cell (Write-0 in FIG. 11), the write decoder 2030 sets the write word line WWL0 to an active potential (high potential, for example, power supply potential Vdd). At this time, the read decoder 2040 sets the read word line RWL0 to an active potential (high potential, for example, power supply potential Vdd).

[0153] In this state, the bit line driver 1020 sets the shared bit line SBL to an active potential (high potential), the source line driver 1010 sets the column source line CSL0 to an inactive potential (low potential), and the source line driver 2010 drives the potential of the column source line CSL0 to an intermediate potential (Vdd / 2). A current path is formed between the shared bit line SBL0 and the column source line CSL0, and a current flows from the bit line BL0 to the column source line CSL0, thereby injecting spins into the MTJ element MTJ00. (Writing data "1")

[0154] When data "1" is written to the selected memory cell (Write-1 in FIG. 11), the potential of the shared bit line SBL and the potential of the column source line CSL0 are controlled in the opposite manner to that in the case of data "0".

[0155] During the data write operation, in the unselected memory cells (memory cells to which data is not written; in FIG. 8, the standby state (St-by)), both the shared bit lines and the column select lines are held at an inactive potential (low potential, for example, the ground potential GND). (Data Read)

[0156] When reading data from a selected memory cell, the read decoder 2040 sets the read word line RWL0 to an active potential.

[0157] When the bit line driver 2020 sets the potential of the shared bit line SBL of the selected column to an active potential and the potential of the read bit line RBL0 to an intermediate potential, a current flows through the MTJ element MTJ00, and a current corresponding to the resistance value of the MTJ element MTJ00 flows through the shared bit line SBL of the selected column. At this time, the resistance value changes depending on whether the data written to the memory cell is "1" or "0". Therefore, the sense amplifier SA0 detects the current value of the shared bit line SBL, thereby reading out data. (Data Read Procedure of Embodiment 2)

[0158] As explained above, the data read procedure of the second embodiment can be summarized as follows.

[0159] In the configuration of the semiconductor memory device 2000, a sense amplifier SA is arranged on the bit line driver side.

[0160] The read decoder 2040 activates the read word line corresponding to the selected memory cell, sets the shared bit line SBL to an active potential, and sets the read source line RBL0 to an intermediate potential.

[0161] The sense amplifier SA0 reads out the stored data based on the change in the current value of the read source line RBL0, which is at the intermediate potential. (Data Write Procedure of the Second Embodiment)

[0162] As explained above, the data writing procedure of the second embodiment can be summarized as follows.

[0163] The semiconductor memory device 2000 includes a write transistor connected to one terminal of the lower electrode of the MTJ element and switchable by a write word line arranged in the row direction, a read transistor connected to the other terminal of the lower electrode and switchable by a read word line arranged in the row direction, a shared bit line arranged in the column direction and connected to the read transistors of memory cells adjacent in the row direction so that a current path can be formed, a source line arranged in the column direction and connected to the other terminal of the lower electrode of each of the memory cells so that a current path can be formed by the write transistor and selectively set to an active potential, and read bit lines arranged in the column direction and connected to the upper electrodes of the MTJ elements, respectively.

[0164] The write decoder 2030 and the read decoder 2040 set the write word line and the read word line corresponding to the memory cell to be written to an active potential.

[0165] Next, the voltage value of the read bit line is set to an intermediate potential (an intermediate value between the activation potential and the inactivation potential), and a current is passed through the lower electrode in a direction corresponding to the write data (Embodiment 3).

[0166] Next, in a third embodiment, an example of the pattern of the bottom electrodes of memory cells adjacent in the column direction in the memory cell array described in the first or second embodiment will be described.

[0167] FIG. 13 is a conceptual diagram for explaining the lower electrode pattern of the third embodiment, and is to be compared with FIG.

[0168] In order to provide a common explanation for both embodiments 1 and 2, the multiple wirings arranged in the column direction of the memory cell array for supplying a write current to the lower electrode will be referred to as "first wirings," and the multiple wirings arranged in the column direction of the memory cell array for detecting the resistance value between the first node and the lower electrode will be referred to as "second wirings."

[0169] Similar to FIG. 3, FIG. 13 is a conceptual diagram showing the internal node side of the MTJ element when the MTJ element is viewed from the side of the lower electrode LEL opposite to the MTJ element, through the lower electrode LEL itself (assuming that the lower electrode LEL is transparent).

[0170] 13, one surface of the bottom electrode LEL is commonly connected to the internal nodes of the memory cells MTJ00 and MTJ10 adjacent to each other in the column direction. The bottom electrodes of the other memory cells adjacent to each other in the column direction also have a similar pattern.

[0171] The other surface of the lower electrode LEL, which faces the one surface, has a first through-hole portion for enabling electrical connection between either the first wiring or the second wiring and the third nodes CTN003 and CTN103, and a shared through-hole portion (which shares the second nodes CTN002 and CTN102; called the shared node SCN) for enabling electrical connection between the other of the first wiring or the second wiring and the lower electrode.

[0172] The connection portion with the internal node on one surface is disposed on the current path between the first through-hole portion and the shared through-hole portion on the other surface.

[0173] More specifically, one surface of the lower electrode LEL is commonly connected to each of the internal nodes of a pair of memory cells adjacent to each other in the column direction, and the other surface of the lower electrode has a through-hole portion for connection to a second node that is shared by the pair of memory cells.

[0174] 7 of the first embodiment, if the shape of the lower electrode in FIG. 13 is adopted, the lower electrode LEL00 and the lower electrode LEL10 will be formed as an integrated pattern. The through-hole portion of the lower electrode LEL00 to the second node CTN002 and the through-hole portion of the lower electrode LEL10 to the second node CTN102 connect the lower electrode and the bit line BL0 as the same via hole shared by the MTJ elements MTJ00 and MTJ10.

[0175] 13 is adopted in the configuration of the memory cell array of the second embodiment shown in Fig. 10, the lower electrode LEL00 and the lower electrode LEL10 are also formed as an integrated pattern. The through-hole portion of the lower electrode LEL00 to the second node CTN002 and the through-hole portion of the lower electrode LEL10 to the second node CTN102 are the same via holes shared by the MTJ elements MTJ00 and MTJ10, and connect the lower electrodes to the selection transistors TR002 and TR102.

[0176] 13, when forming via holes for contacting the second and third nodes of the bottom electrodes in each of the above-described embodiments, the via holes for contact can be shared between two adjacent MTJ elements. This allows the number of via holes per MTJ element to be 0.5. This allows the nodes of the bottom electrodes to be made more compact.

[0177] 13, which is different from FIG. 3, the shape of the lower electrode LEL is not rectangular but is approximately U-shaped. In this case, the current flowing between the node SCN and the node CTN003 (or 103) is bent, and the current density becomes non-uniform depending on the location. This non-uniformity causes variations in the spin direction in the MTJ element and also serves to facilitate the movement of spins during writing.

[0178] FIG. 14 is a conceptual diagram showing a lower electrode pattern according to a first modification of the third embodiment.

[0179] 12, the lower electrode LEL has a pattern in which one surface thereof is commonly connected to each of the internal nodes of a pair of memory cells adjacent to each other in the column direction. In contrast, FIG. 14 shows an example of a pattern in which the lower electrode LEL has one surface thereof commonly connected to each of the internal nodes of four memory cells adjacent to each other in the column direction. The through-hole portions of the second nodes of the four memory cells may be configured to share the same via hole.

[0180] As shown in FIG. 14 , when forming via holes for contacting the second and third nodes of the bottom electrode in each of the above embodiments, the via holes for contact can be shared among four adjacent MTJs. This allows the number of via holes per MTJ element to be reduced to 0.25. This allows the bottom electrode node to be made even more compact. Note that the number of MTJ elements sharing a node is not limited to four, and a configuration in which a node is shared by more MTJ elements is also possible.

[0181] 14, which is different from FIG. 3, the shape of the bottom electrode LEL is not a square but a series of approximately U-shapes. In this case, the current flowing between the bottom electrode LEL and the node CTN is bent, and the current density becomes non-uniform depending on the location. This non-uniformity causes variations in the spin direction in the MTJ element and also serves to facilitate the movement of spins during writing.

[0182] FIG. 15 is a diagram showing a second modified example of the shape of the lower electrode pattern according to the third embodiment.

[0183] 13 , the corners of the bottom electrode are chamfered, and the internal node of the MTJ element MTJ00 has a substantially elliptical shape and is provided so that its major axis direction runs from the through-hole portion of the bottom electrode LEL, which is connected to the third node CTN003, to the through-hole portion of the shared node SCN. Similarly, the internal node of the MTJ element MTJ10 has a substantially elliptical shape and is provided so that its major axis direction runs from the through-hole portion of the bottom electrode LEL, which is connected to the third node CTN103, to the through-hole portion of the shared node SCN.

[0184] That is, the bottom surface on which the internal nodes of each magnetic tunnel junction element of a memory cell pair are provided has a long axis direction and a short axis direction, and the magnetic tunnel junction elements are arranged so that their long axis direction is along the current path from one of the shared first through hole portion and second through hole portion to the other of the first through hole portion and second through hole portion.

[0185] With this configuration, the direction of the current flowing through the lower electrode LEL during data writing is along the internal node of the MTJ element, making it possible to improve the efficiency of data writing.

[0186] 15, when forming via holes for contacting the second and third nodes of the bottom electrode in each of the above-described embodiments, the via holes are shared between two adjacent MTJs, and further, a portion of the bottom electrode is chamfered, and the MTJ element is arranged along the direction between the contacts to the bottom electrode via holes. This allows the current to pass along the shape of the bottom of the MTJ element (the long axis direction of the approximately elliptical field). This further improves the efficiency of the spin-orbit torque.

[0187] The number of MTJ elements sharing a via hole is not limited to two, and may be greater than two.

[0188] FIG. 16 is a circuit diagram for illustrating the configuration of a memory cell array 30 and a memory cell 300 of a semiconductor memory device 3000 according to the fourth embodiment.

[0189] As in the first and second embodiments, FIG. 16 shows only a portion of the memory cells, and although in reality many more memory cells and corresponding signal lines are arranged in both the row and column directions, they are not shown in FIG.

[0190] The configuration of semiconductor memory device 3000 shown in FIG. 16 differs from the configuration of semiconductor memory device 1000 of the first embodiment shown in FIG. 7 in the following points.

[0191] First, when data is read from the MTJ element of a memory cell, read wiring RSL0 and RSL1 are provided as wiring above the MTJ element of the memory cell in order to detect the resistance value of the MTJ element in response to the memory cell being selected.

[0192] Furthermore, a read transistor that is turned on in response to row selection by a read word line is provided above the MTJ element between a first node of the MTJ element and the read wiring RSL0, and electrically connects the first node of the MTJ element to the read wiring RSL0 during a read operation. More specifically, the read transistor is a vertical transistor that can form a conductive channel in a direction substantially perpendicular to the main surface of the semiconductor substrate.

[0193] That is, the semiconductor memory device 3000 includes a memory cell array 30 in which a plurality of memory cells are arranged in a matrix on a semiconductor substrate, and each of the memory cells 300 includes an MTJ element having a first node and an internal node, and a lower electrode LEL provided below the internal node and having a second node and a third node.

[0194] In a write operation, the write transistor of a selected memory cell is rendered conductive, causing a write current to flow selectively between the second node and the third node of the MTJ element, and data is written by the spin-orbit torque.

[0195] In a read operation, the read transistor of the selected memory cell is rendered conductive, thereby making it possible to sense the resistance between the first and second nodes of the MTJ element.

[0196] In such a read operation, a configuration for selecting a memory cell and reading data includes a plurality of read word lines arranged in the row direction of the memory cell array and set to an active potential in response to row selection, and read wirings RSL0 and RSL1 arranged in the column direction of the memory cell array above the memory cells for detecting resistance values. Further, a read transistor is arranged between the first node and the corresponding read wiring, and is turned on in response to row selection by the read word line during a read operation.

[0197] The read transistor is a vertical MOS transistor formed above the first node of the MTJ element.

[0198] FIG. 17 is a diagram showing control of the potential of each signal line in the read operation and the write operation according to the fourth embodiment.

[0199] 5 during a write operation, the control of the potential of each signal line is the same as in FIG. 5, and therefore the description will not be repeated. During a read operation, a current is passed from RSL0 (Vdd) to BL0 (GND), and the resistance value is detected by a sense amplifier. (Example 1 of Cross-Sectional Structure of Semiconductor Memory Device 3000)

[0200] The cross-sectional structure of the semiconductor memory device 3000 and the manufacturing method thereof will be described below.

[0201] FIG. 18 is a cross-sectional view showing the cross-sectional structure of a memory cell 300 according to the fourth embodiment.

[0202] The memory cell 300 has a read transistor TR001 provided above the MTJ element. This eliminates the need to provide the transistor TR001 on the main surface side of the semiconductor substrate, and also eliminates the need for a connection structure using a vertical via hole from the first node of the MTJ element to the transistor TR001.

[0203] As shown in FIG. 18, the upper transistor (read transistor) is, but is not limited to, a MOS (Metal Oxide Semiconductor) transistor, for example.

[0204] On the other hand, a MOS transistor TR003 is provided as a write transistor on the main surface of the Si semiconductor substrate.

[0205] The source of the transistor TR003 is connected to the column source line CSL0.

[0206] The third node of the lower electrode of the MTJ element is connected to the source of the transistor TR003 through a via hole in the multilayer wiring.

[0207] The circuit and multilayer wiring on the Si semiconductor substrate including the transistor TR003 are manufactured by a normal Si semiconductor manufacturing process.

[0208] The lower electrode of the MTJ element and the MTJ element are formed in the upper layer after the "lower transistor and multilayer wiring" are formed.

[0209] Furthermore, a read transistor for opening and closing the connection between the first node of the MTJ element and the read wiring is formed in the upper layer of the MTJ element. (Method of Manufacturing the Semiconductor Memory Device 3000)

[0210] 19 to 33 are diagrams showing an example of a method for manufacturing the element structure of the memory cell 300 according to the fourth embodiment.

[0211] First, as shown in FIG. 19, the following steps before forming the lower electrode may be the same as the normal CMOS steps. The explanation of these steps will be omitted. 1) Front-end step (forming a component layer such as a transistor on a Si semiconductor substrate) 2) Step of forming multi-layer wiring such as wiring for connecting to the lower electrode of the MTJ element, wiring for supplying a write current, and word lines for controlling the gate potential of the select transistor.

[0212] Next, a lamination step 301 is carried out to form a laminated film of a magnetic MTJ element.

[0213] 19 is the same as the configuration of the MTJ element in the first and second embodiments. This configuration is merely an example, but as described above, ３By using a non-collinear antiferromagnetic material such as Sn to assist the spin flip of the CoFeB in the free layer, the energy required for spin flip can be further reduced. This reduces the current density, allowing the entire device to be further miniaturized. The lower electrode is made of a heavy metal such as W. The N-type semiconductor layer serves as the source / drain layer of the upper vertical transistor, which will be described later.

[0214] Such a vertical transistor does not necessarily have to be a so-called MOS transistor, and as long as it is a transistor capable of switching operation, it may be configured to control the conductance of an accumulation layer rather than by forming an inversion layer as in a MOS type.

[0215] In the following description, the N-type semiconductor layer is, for example, an N-type Si layer, and the transistor is a MOS transistor.

[0216] The method for growing the N-type Si layer is not particularly limited, but a conventional growth method such as a CVD (Chemical Vapor Deposition) method can be used. In addition, as shown in the following document, a method for growing the N-type Si layer using cyclopentasilane (CPS, C ５ H １０ Alternatively, a growth method such as applying a material such as silicon dioxide (SiO2) to the silicon substrate and then irradiating it with an excimer laser to form polycrystalline silicon may be used. However, as mentioned above, the growth method is not limited to these methods as long as it is a process that can form a transistor that can function as a switching element. Public literature: https: / / www.jstage.jst.go.jp / article / oubutsu / 88 / 1 / 88_26 / _pdf

[0217] Alternatively, for example, a process may be used in which an N-type Si layer, an intrinsic Si layer, and an N-type Si layer are epitaxially grown on another Si semiconductor substrate, and then a Ta layer is formed on the surface of the epitaxially grown N-type Si layer, and a stacked film of a magnetic MTJ element is formed on the semiconductor substrate up to the Ta layer, and the Ta layers are then bonded together by turning the substrate over, and the other Si semiconductor substrate is removed by polishing.

[0218] Next, as shown in Fig. 20, in step 302, a resist pattern is formed on the top of the N-type Si layer to form the MTJ element portion. Subsequently, as shown in Fig. 21, in step 303, the resist is used as a mask to perform etching by RIE (Reactive Ion Etching) or the like to pattern the MTJ element. Note that there are various process variations possible for patterning the MTJ element, such as reducing damage and taking care of side etching. Etching is stopped at the W surface of the lower electrode. Reactive Ion Etching

[0219] Next, as shown in FIG. 22, in step 304, the resist is removed, an interlayer insulating film (for example, a Si oxide film) is deposited by CVD or the like, and planarized by polishing such as CMP.

[0220] Next, as shown in FIG. 23, in step 305, the resist is patterned to form the shape of the lower electrode.

[0221] Next, as shown in FIG. 24, in step 306, a pattern for processing the lower electrode is formed using a resist mask, and the interlayer insulating film and the lower electrode are etched by RIE or the like.

[0222] Subsequently, as shown in FIG. 25, in step 307, the resist is removed.

[0223] Next, as shown in FIG. 26, in step 308, an interlayer insulating film is again deposited by CVD or the like and planarized by polishing.

[0224] Subsequently, as shown in FIG. 27, in step 309, a crystallized Si layer (channel layer of the transistor) and an N-type Si layer (source / drain layer of the transistor) are stacked by the growth method described above.

[0225] Next, as shown in FIG. 28, in step 310, the N-type Si layer deposited in step 309 and the crystallized Si layer in the channel region of the transistor are patterned (a resist step is not shown).

[0226] Subsequently, as shown in FIG. 29, in step 311, a gate insulating film and a gate electrode layer are laminated.

[0227] Next, as shown in FIG. 30, in step 312, the gate electrode film is etched by anisotropic etching such as RIE to form the gate electrode as a sidewall around the channel region.

[0228] Subsequently, as shown in FIG. 31, in step 313, an interlayer insulating film is deposited and then planarized by polishing.

[0229] Next, as shown in FIG. 32, in step 314, via holes are formed in the interlayer insulating film to connect to the source and drain of the upper transistor (read transistor).

[0230] 33, a metal wiring layer that will become the read wiring is formed in step 315. In this way, the element structure of the memory cell 300 is formed.

[0231] As described above, in forming the memory cell of the fourth embodiment, the following steps are carried out in order.

[0232] 1) A write transistor that enables opening and closing of a current path during a write operation is formed on a semiconductor substrate by a complementary MOS transistor manufacturing method, and a first wiring layer and a planarized first interlayer insulating film layer are formed to supply current during the write operation (lower layer manufacturing process).

[0233] 2) An MTJ element is formed on the first interlayer insulating film layer so as to connect one terminal of the write transistor, and a planarized second interlayer insulating film layer is formed (memory element forming step).

[0234] 3) A read transistor, which is a vertical transistor, is formed on the second interlayer insulating film layer so as to open and close a current path to the other terminal of the MTJ element during a read operation, and a read wiring for performing a read operation is formed via the current path (upper layer manufacturing process) (Modification of the semiconductor memory device 3000).

[0235] A modified example of the method for manufacturing the semiconductor memory device 3000 according to the fourth embodiment will be described below.

[0236] FIG. 34 is a cross-sectional view showing the cross-sectional structure of a memory cell 300' which is a modification of the semiconductor memory device 3000 according to the fourth embodiment.

[0237] The memory cell 300' has a read transistor TR001 provided above the MTJ element. This eliminates the need to provide the transistor TR001 on the main surface side of the semiconductor substrate, and also eliminates the need for a connection structure using a vertical via hole from the first node of the MTJ element to the transistor TR001.

[0238] As shown in FIG. 34, the upper transistor (read transistor) TR001 is provided by forming a MOS transistor on the second Si semiconductor substrate.

[0239] On the other hand, a MOS transistor TR003 is provided as a write transistor on the main surface of the first Si semiconductor substrate.

[0240] That is, in this modification, the memory cell array 30 in which the read transistor TR001 and the MTJ element are arranged is formed on a second semiconductor substrate, and the write wiring and the write transistor TR003 for selecting a memory cell during writing are formed on a first semiconductor substrate different from the second semiconductor substrate. The semiconductor memory device 3000 is formed by bonding the first semiconductor substrate and the second semiconductor substrate together. (Manufacturing Method of the Modified Semiconductor Memory Device 3000)

[0241] 35 to 37 are diagrams showing a method for manufacturing the element structure of a memory cell 300' according to a modification of the fourth embodiment.

[0242] As shown in FIG. 35, in step 301′, a transistor layer for realizing a desired circuit, including write transistors, and a multi-layer wiring layer for connecting components on the semiconductor substrate to enable circuit operation are formed on the second silicon substrate using CMOS process technology.

[0243] Although not particularly limited, write transistors, write word lines, column source lines, bit lines, etc. are formed on the second silicon substrate.

[0244] 36, in step 302', a read transistor TR001 is formed on the first silicon substrate by CMOS process technology. A multilayer film of an MTJ element is then formed above it, and the MT element is formed by repeating patterning and etching. The manufacturing method of the MTJ layer is not particularly limited, and may be the same as the above-described process for forming the MTJ element.

[0245] However, the order of lamination of the multilayer film constituting the MTJ element is reversed, unlike in Embodiments 1 and 2. The upper electrode layer of the multilayer film constituting the MTJ element becomes the "lower electrode," and is exposed at the bonding surface with the second silicon substrate.

[0246] Next, as shown in FIG. 37, the lower electrode LEL on the first silicon substrate is bonded to the contact surface of the upper wiring layer of the second silicon substrate, thereby forming a memory cell 300'.

[0247] That is, as explained above, in forming the memory cell of the fourth embodiment, the following steps are carried out in order.

[0248] 1) A write transistor for opening and closing a current path during a write operation is formed on a first semiconductor substrate by a complementary MOS transistor manufacturing method, a first wiring layer for supplying current during a write operation and a planarized first interlayer insulating film layer are formed, and a first contact portion to the first wiring layer is formed (first semiconductor manufacturing process).

[0249] 2) A read transistor is formed on a second semiconductor substrate by a complementary MOS transistor manufacturing method, a planarized second interlayer insulating film is formed, an MTJ element is formed on the second interlayer insulating film so that the read transistor and the first node are connected and the read transistor can open and close a current path to the first node during a read operation, and a planarized third interlayer insulating film is formed, followed by forming a second contact portion to the bottom electrode of the MTJ element (second semiconductor manufacturing process).

[0250] 3) The upper surface of the first semiconductor substrate and the upper surface of the second semiconductor substrate are bonded together so as to join the first contact portion and the second contact portion together, thereby forming a memory cell (bonding step).

[0251] Although the description has been given assuming that the lower surface of the lower electrode and the wiring layer are in direct contact with each other for bonding purposes, a via hole and a buried electrode filled in the via hole may be provided between them (example of a system including an MRAM described in each embodiment).

[0252] The semiconductor memory device formed in accordance with each of the above embodiments can be used as a memory device for a circuit that performs arithmetic processing of data.

[0253] For example, a central processing unit (CPU) has multiple levels of cache memory. For example, a hierarchical cache memory is typically provided, such as a level 1 (L1) primary cache memory, a level 2 (L2) secondary cache memory, a level 3 (L3) tertiary cache memory, and so on. In this case, cache memory has traditionally been implemented using static random access memory (SRAM). However, SRAM has drawbacks, such as low memory density (each memory cell is composed of six transistors) and relatively high standby power consumption (significant leakage current). Replacing SRAM with MRAM can reduce the silicon area per memory capacity and significantly reduce standby power consumption.

[0254] Therefore, for example, the semiconductor memory device of the MRAM according to each of the above-described embodiments can be employed as a last level cache such as an L3 cache or an L4 cache.

[0255] Furthermore, with the spread of new technologies such as AI, IoT, and 5G, there is a demand for high-speed, highly reliable memory solutions. Therefore, the applications of MRAM are not limited to the above, and it is expected that it will be used as a storage system in fields where high-speed, highly reliable memory is required, such as data storage in industrial automation systems, data storage in medical devices, and data centers.

[0256] According to the configuration of the semiconductor memory device of each embodiment as described above, in the SOT-MRAM, it is possible to reduce the circuit area and increase the density.

[0257] Furthermore, according to the method for manufacturing a semiconductor memory device of the embodiment, it is possible to manufacture an SOT-MRAM that can reduce the circuit area and increase the density.

[0258] More specifically, by employing the configuration of the semiconductor memory device according to each embodiment, efficient data reading and writing becomes possible in an SOT-MRAM that allows for a reduced circuit area and higher density.

[0259] Finally, while various embodiments of the present disclosure have been described, they are presented as examples and are not intended to limit the scope of the invention. The novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. Such embodiments and modifications are intended to be included within the scope and spirit of the invention, as well as within the scope of the inventions and their equivalents as defined in the claims.

[0260] Therefore, the embodiments disclosed herein are merely examples of configurations for specifically implementing the present invention, and do not limit the technical scope of the present invention. The technical scope of the present invention is defined by the claims, not by the description of the embodiments, and is intended to include modifications within the literal scope of the claims and within the scope of equivalent meanings.

[0261] 10, 20, 30 memory cell array, 100, 200, 300 memory cell, MTJ00, MTJ01, MTJ10, MTJ11 magnetic tunnel junction element, T1 first node of MTJ element, T2 second node of MTJ element, T3 third node of MTJ element, BL0, BL1 bit line, CSL0, CSL1 column source line, RSL0, RSL1 read source line, RSL0 shared source line, RWL0, RWL1 read word line, WWL0, WWL1 write word line, 1000, 2000, 3000 semiconductor memory device, 1010 source line driver, 1020 bit line driver, 1030 write decoder, 1040 read decoder.

Claims

1. A semiconductor memory device comprising: a memory cell array in which a plurality of memory cells are arranged in a matrix, each of the memory cells including: a magnetic tunnel junction element having a first node and an internal node; and a first electrode arranged to connect to the internal node; and a plurality of first wirings arranged in the column direction of the memory cell array for supplying a write current to the first electrode; a plurality of second wirings arranged in the column direction of the memory cell array for detecting a resistance value between the first node and the first electrode; and a plurality of third wirings arranged in the column direction of the memory cell array for supplying a reference potential to the memory cells, wherein pairs of memory cells adjacent in the row direction of the memory cell array share either the first wiring or the third wiring as a shared wiring.

2. A semiconductor memory device as claimed in claim 1, further comprising: write selection means for selectively conducting the write current between the second node and the third node of the selected memory cell, thereby enabling data to be written by spin-orbit torque; and read selection means for enabling detection of the resistance value between the first node and the second node of the selected memory cell.

3. A semiconductor memory device as recited in claim 2, wherein the shared wiring is a shared source line which is the third wiring for supplying the reference potential to the memory cells, and the read selection means includes: a bit line among the first wirings which is commonly connected to the second nodes of the memory cells; a plurality of read word lines which are provided in the row direction of the memory cell array and which become an active potential in response to row selection; and a pair of read transistors which are provided between the first node of one of the pairs of memory cells and the shared wiring and between the first node of the other of the pairs, respectively, and which become conductive in response to row selection by the read word line.

4. A semiconductor memory device as claimed in claim 3, wherein said write selection means includes: a bit line among said first wirings, commonly connected to said second node of a plurality of said memory cells in the column direction; a plurality of write word lines arranged in the row direction of said memory cell array and set to an active potential in response to row selection; and a write transistor arranged between said second wiring and said third node, and set to a conductive state in response to row selection by said write word line.

5. A semiconductor memory device as claimed in claim 2, wherein the shared wiring is a common bit line which is the first wiring for supplying the write current to the memory cells, and the write selection means includes: a plurality of first word lines arranged in the row direction of the memory cell array and which become an active potential in response to row selection; a plurality of second word lines arranged in the row direction of the memory cell array and which become an active potential in response to row selection; a first transistor arranged between the second wiring and the third node and which becomes conductive in response to row selection by the first word line; and a second transistor arranged between the common bit line and the second node and which becomes conductive in response to row selection by the second word line.

6. A semiconductor memory device as claimed in claim 5, wherein the read selection means includes a read bit line among the third wirings, which is commonly connected to the first nodes of a plurality of the memory cells in the column direction, and the second transistor is rendered conductive in response to row selection by the second word line during a read operation.

7. A semiconductor memory device as claimed in any one of claims 1 to 6, wherein the first electrode is provided such that one surface is commonly connected to each of the internal nodes of a plurality of memory cells adjacent in the column direction, the other surface opposite to the one surface of the first electrode has a first contact portion for enabling electrical connection with the first wiring and a second contact portion for enabling electrical connection with the second wiring, and the connection portion with the internal node on the one surface is arranged on a current path between the first contact portion and the second contact portion on the other surface.

8. A semiconductor memory device according to any one of claims 1 to 6, wherein the first electrode is provided such that one surface is commonly connected to each of the internal nodes of a pair of memory cells adjacent to each other in the column direction, the other surface of the first electrode opposite to the one surface has a first contact portion for enabling electrical connection to either the first wiring or the second wiring, and a second contact portion for enabling electrical connection to the other of the first wiring or the second wiring, and either the first contact portion or the second contact portion is shared by the pair of memory cells.

9. A semiconductor memory device as described in claim 8, wherein a bottom surface on which the internal node of each of the magnetic tunnel junction elements of the pair of memory cells is provided has a major axis direction and a minor axis direction, and the magnetic tunnel junction elements are arranged so that the major axis direction is along a current path from one of the shared first through hole portion and the shared second through hole portion to the other of the first through hole portion and the shared second through hole portion.

10. A semiconductor memory device comprising: a memory cell array having a plurality of memory cells arranged in a matrix on a semiconductor substrate, each of the memory cells including: a magnetic tunnel junction element having a first node and an internal node; and a first electrode provided under the internal node and having a second node and a third node; write selection means for selectively conducting a write current between the second node and the third node of a selected memory cell to enable writing of data by spin-orbit torque; and read selection means for enabling detection of a resistance value between the first node and the second node of a selected memory cell, the read selection means including: a plurality of read word lines provided in the row direction of the memory cell array and set to an active potential in response to row selection; read wiring provided above the memory cells along the column direction of the memory cell array for detecting the resistance value; and a read transistor provided between the first node and the read wiring and turned on in response to row selection by the read word line during a read operation.

11. The semiconductor memory device according to claim 10, wherein said read transistor is a vertical MOS transistor formed above said first node.

12. The semiconductor memory device according to claim 10, wherein the memory cell array and the read transistor are formed on a second semiconductor substrate, the write wiring and a write transistor for selecting the memory cell during writing are formed on a first semiconductor substrate different from the second semiconductor substrate, and the semiconductor memory device is formed by bonding the first semiconductor substrate and the second semiconductor substrate together.

13. A storage system comprising at least one semiconductor device according to claim 1 or 10, and further comprising a circuit for executing processing based on data stored in said semiconductor storage device.

14. A method for manufacturing a semiconductor memory device, comprising: a lower layer manufacturing process for forming a write transistor on a semiconductor substrate by a complementary MOS transistor manufacturing process, the write transistor enabling opening and closing of a current path in a write operation, and forming a first wiring layer for supplying current in the write operation and a planarized first interlayer insulating film layer; a memory element forming process for forming a magnetic tunnel junction element on the first interlayer insulating film layer to connect one terminal of the write transistor and forming a planarized second interlayer insulating film layer; and an upper layer manufacturing process for forming a read transistor, which is a vertical transistor, on the second interlayer insulating film layer, the magnetic tunnel junction element enabling opening and closing of a current path to the other terminal of the magnetic tunnel junction element in a read operation, and forming a read wiring for performing a read operation via the current path.

15. A method for manufacturing a semiconductor memory device, comprising: a first semiconductor manufacturing step of forming, on a first semiconductor substrate, a write transistor for enabling opening and closing of a current path in a write operation by a complementary MOS transistor manufacturing method, forming a first wiring layer for supplying current in the write operation and forming a planarized first interlayer insulating film layer, and forming a first contact portion to the first wiring layer; a second semiconductor manufacturing step of forming, on a second semiconductor substrate, a read transistor by a complementary MOS transistor manufacturing method, forming a planarized second interlayer insulating film layer, forming a magnetic tunnel junction element on the second interlayer insulating film layer such that the read transistor and a first node are connected and the read transistor is capable of opening and closing a current path to the first node in a read operation, forming a planarized third interlayer insulating film layer, and forming second contact portions of a first electrode of the magnetic tunnel junction element to a second node and a third node; a bonding process for bonding an upper surface of the first semiconductor substrate and an upper surface of the second semiconductor substrate so as to join the first contact portion and the second contact portion to form a memory cell.

16. A method for reading stored data of a semiconductor memory device, the semiconductor memory device comprising: a memory cell array, the memory cell array including memory cells arranged in a matrix, each having a magnetic tunnel junction element; read transistors connected to one electrodes of the magnetic tunnel junction elements and switchable by a read word line arranged in a row direction; shared read source lines arranged in a column direction and connected to terminals of the read transistors of memory cells adjacent in the row direction; and bit lines arranged in the column direction and connected to the other electrodes of the magnetic tunnel junction elements, the method comprising: a step of activating the read word line to activate either the bit line or the shared read source line; and a step of reading stored data based on a change in current value of an inactivated one of the bit line or the shared read source line.

17. A method for writing stored data in a semiconductor memory device, the semiconductor memory device comprising: a memory cell array, the memory cell array being arranged in a matrix, each memory cell having a magnetic tunnel junction element and a first electrode for writing data to the magnetic tunnel junction element by spin orbit torque; a write transistor connected to one terminal of the first electrode and switchable by a write word line arranged in a row direction; a read transistor connected to the other terminal of the first electrode and switchable by a read word line arranged in the row direction; shared bit lines arranged in a column direction and connected to the read transistors of the memory cells adjacent in the row direction so that a current path can be formed; a source line arranged in the column direction and connected to the other terminal of each of the first electrodes of the memory cells so that a current path can be formed by the write transistors, and selectively set to an active potential; and read bit lines arranged in the column direction and connected to upper electrodes of the magnetic tunnel junction elements, respectively; setting the write word line and the read word line corresponding to the memory cell to be written to an active potential; a step of setting a voltage value of the read bit line to an intermediate value between an active potential and an inactive potential and causing a current to flow through the first electrode in a direction corresponding to write data.

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