Method for operating storage system, and controller, storage system and electronic device

Abstract

The embodiments of the present application relate to, but are not limited to, the technical field of storage, and particularly relate to a method for operating a storage system, and a controller, a storage system and an electronic device. The method comprises: in response to a received first command which comprises a first logical address of first data to be operated, determining at least one region corresponding to the first logical address, wherein the at least one region corresponds to a first storage space of a memory of a storage system; on the basis of a first mapping relationship and the determined at least one region, acquiring at least one first physical page address corresponding to the at least one region; and on the basis of the at least one first physical page address, executing an operation on the first data in the first storage space, wherein the storage capacity of one region is less than the storage capacity corresponding to a physical block of the memory, and the first storage space is a storage space which supports only sequential reading and sequential writing. Thus, zoned storage of a storage system can be realized.

Description

Storage system operation method, controller, storage system and electronic equipment Technical Field

[0001] The embodiments of the present application relate to, but are not limited to, the field of storage technology, and in particular to an operating method of a storage system, a controller, a storage system, and an electronic device. Background Art

[0002] With the advancement of storage technology, flash memory (such as NAND flash memory) is being used more and more widely, for example, in mobile phones, computers and other devices.

[0003] The zoned universal flash storage (UFS) protocol can improve storage performance. This protocol divides the storage system's memory into zones and makes this information available to higher-level applications, which then use it to manage the zones based on their own business needs. However, implementing zoned storage in storage systems has become a pressing issue.

[0004] Summary of the Invention

[0005] Embodiments of the present application provide a storage system operation method, a controller, a storage system, and an electronic device to implement partitioned storage of the storage system.

[0006] To achieve the above objectives, the present invention adopts the following technical solutions:

[0007] In a first aspect, a method for operating a storage system is provided, the method comprising: in response to a received first command including a first logical address of first data to be operated, determining at least one area corresponding to the first logical address, the at least one area corresponding to a first storage space of a memory of the storage system; obtaining at least one first physical page address corresponding to the at least one area based on a first mapping relationship and the determined at least one area; and performing an operation on the first data in the first storage space based on the at least one first physical page address; wherein the storage capacity of an area is smaller than the storage capacity corresponding to a physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

[0008] In the above technical solution, the first storage space of the memory of the storage system is divided into multiple areas, and the first storage space is a storage space that only supports sequential reading and sequential writing. When a first command for operating first data is received, at least one area can be determined based on the first logical address of the first data included in the first command. Based on the first mapping relationship between at least one area and multiple physical page addresses (the multiple physical page addresses include at least one first physical page address), at least one first physical page address corresponding to at least one area can be obtained. If the first logical address corresponds to one area, at least one first physical page address corresponding to this area is obtained; if the first logical address corresponds to multiple areas, at least one first physical page address corresponding to each area in the multiple areas is obtained. Based on the obtained at least one first physical page address, the operation indicated by the first command can be performed on the first data in the first storage space. In this way, by determining the area based on the first logical address and then obtaining the first physical page address based on the first mapping relationship, partitioned storage of the storage system can be implemented, thereby realizing the benefits brought by partitioned storage.

[0009] In a possible implementation of the first aspect, obtaining at least one first physical page address corresponding to the at least one region based on the first mapping relationship and the determined at least one region includes: determining the at least one first physical page address in a pointer mode based on the first mapping relationship and the at least one region. In the above possible implementation, multiple physical page addresses corresponding to each region in the at least one region can be obtained based on the first mapping relationship and the at least one region. At least one first physical page address can be determined from the multiple physical page addresses corresponding to each region in the pointer mode. This provides a basis for implementing partitioned storage in a storage system.

[0010] In a possible implementation of the first aspect, the first command is used to instruct the writing of the first data, and the first command also includes the first data. According to at least one first physical page address, an operation is performed on the first data in the first storage space, including: writing the first data at at least one physical address in the first storage space. In the above possible implementation, the first command is used to instruct the writing of the first data. If the first mapping relationship has been established, at least one first physical page address can be directly obtained according to the first mapping relationship, and the first data can be written at at least one physical address in the first storage space. In this way, it not only provides a basis for realizing partitioned storage of the storage system, but also makes the data writing operation simple and convenient, with a shorter writing time and a faster writing speed.

[0011] In a possible implementation of the first aspect, before obtaining at least one first physical page address corresponding to the at least one region based on the first mapping relationship and the determined at least one region, the method further includes: establishing a first mapping relationship between the at least one region and multiple physical page addresses, the multiple physical page addresses including at least one first physical page address. The method further includes: writing the first mapping relationship between the at least one region and the multiple physical page addresses into a memory. In this possible implementation, the first command is used to instruct the writing of the first data. If the first mapping relationship has not yet been established, upon receiving the first command, a first mapping relationship between the at least one region and multiple physical page addresses, including at least one first physical page address, is first established. The first data is then written to at least one physical address in the first storage space. Furthermore, the first mapping relationship between the at least one region and the multiple physical page addresses is written into the memory. This provides a foundation for implementing partitioned storage in the storage system and facilitates subsequent use of the first mapping relationship. For the first storage space, the first mapping relationship only needs to be established once for each region of data written, rather than once for each logical page of data written. Overall, the number of times the first mapping relationship needs to be established is reduced, the number of instruction interactions is reduced, and the writing speed is faster.

[0012] In a possible implementation of the first aspect, the first command is used to instruct the reading of the first data. According to at least one first physical page address, an operation is performed on the first data in the first storage space, including: reading the first data from at least one first physical page address in the first storage space. In the above possible implementation, the first command is used to instruct the reading of the first data, and the first mapping relationship has been established. When the first command is received, at least one first physical page address can be directly obtained according to the first mapping relationship, and the first data can be read from at least one first physical page address in the first storage space. In this way, it not only provides a basis for realizing partitioned storage of the storage system, but also makes the data reading operation simple and convenient, with shorter reading time and faster reading speed.

[0013] In one possible implementation of the first aspect, a controller of the storage system includes a cache, wherein a first mapping relationship is stored in the cache. In this possible implementation, the cache in the controller can store the first mapping relationship. When the controller needs to obtain the first mapping relationship, it does not need to obtain the first mapping relationship from the memory each time, but can directly obtain the first mapping relationship from the cache. This allows the controller to obtain the first mapping relationship more quickly, enabling more efficient data operations.

[0014] In a possible implementation of the first aspect, the first mapping relationship is a two-level mapping relationship. In the above possible implementation, the first mapping relationship is a two-level mapping relationship. Compared with three-level or more-level mapping relationships, the two-level mapping relationship occupies less storage space and can save storage capacity of the storage system.

[0015] In a possible implementation of the first aspect, the method further includes: in response to receiving a second command including a second logical address of second data to be operated on, obtaining a second physical page address corresponding to the second logical address according to a second mapping relationship, the second logical address corresponding to a second storage space of the memory; and performing an operation on the second data in the second storage space according to the second physical page address; wherein the second storage space is a storage space that supports random reads or random writes. In the above possible implementation, the first storage space is a storage space that only supports sequential reads and sequential writes, and the second storage space is a storage space that supports random reads or random writes. For first data that can be sequentially written or read, at least one first physical page address corresponding to the first logical address of the first data is obtained according to the first command and the first mapping relationship, and the operation is performed on the first data in the first storage space according to the at least one physical page address. For second data that requires random write or random read, a second physical page address corresponding to the second logical address of the second data is obtained according to the second command and the second mapping relationship, and the operation is performed on the second data in the second storage space according to the second physical page address. Since the partitioned storage method only supports sequential reads and sequential writes, the controllers of some storage systems were not designed with partitioned software features in mind. The storage spaces of these storage systems need to use random writes to write some data, or use random reads to read some data. The second storage space and the second mapping relationship can be used to operate the second data. The embodiment of the present application stores some data that need to be written or read randomly in the second storage space, and stores the remaining data that can be written or read sequentially in the first storage space, thereby achieving the benefits of partitioned storage with good compatibility while making minor changes to the controller firmware.

[0016] In a possible implementation of the first aspect, the second mapping relationship is a mapping relationship including the second logical address, the physical block address corresponding to the second logical address, and the second physical page address corresponding to the physical block address. In the above possible implementation, the second mapping relationship is a mapping relationship including the second logical address, the physical block address corresponding to the second logical address, and the second physical page address corresponding to the physical block address. In this way, the second physical page address corresponding to the second logical address can be obtained based on the second logical address and the second mapping relationship, providing a basis for storing partial data that requires random writing or random reading in the second storage space.

[0017] In a possible implementation of the first aspect, the second command is used to instruct the writing of the second data. According to the second mapping relationship and the second logical address, before obtaining the second physical page address corresponding to the second logical address, it also includes: establishing a second mapping relationship corresponding to the second logical address. According to the second physical page address, performing an operation on the second data in the second storage space, including: writing the second data at the second physical page address in the second storage space. The method also includes: writing the second mapping relationship corresponding to the second logical address in the memory. In the above possible implementation, the second command is used to instruct the writing of the second data. If the first mapping relationship has not been established, after receiving the first command, the second mapping relationship corresponding to the second logical address is first established, and then the second data is written at the second physical page address in the second storage space. In addition, the second mapping relationship corresponding to the second logical address is written in the memory. In this way, a basis is provided for storing part of the data that needs to be randomly written into the second storage space.

[0018] In a possible implementation of the first aspect, the second command is used to instruct the reading of the second data. Before obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship, it also includes: in response to the second command, reading the second mapping relationship corresponding to the second logical address from the memory. According to the second physical page address, performing an operation on the second data in the second storage space, including: reading the second data from the second physical address in the second storage space. In the above possible implementation, the second command is used to instruct the reading of the second data. When the second command is received, it is necessary to first read the second mapping relationship corresponding to the second logical address from the memory, and then read the second data from the second physical address in the second storage space. In this way, a basis is provided for reading part of the data that needs to be read randomly from the second storage space.

[0019] In a possible implementation of the first aspect, the second mapping relationship is a three-level mapping relationship. In the above possible implementation, the second mapping relationship is a three-level mapping relationship, which provides a basis for storing some data that needs to be randomly written or randomly read in the second storage space.

[0020] In a possible implementation of the first aspect, the method further includes: performing a first garbage collection operation on physical blocks other than blank physical blocks in the second storage space. In this possible implementation, the first garbage collection operation is performed on physical blocks other than blank physical blocks in the second storage space, and the first garbage collection operation is retained, thereby realizing the benefits of partitioned storage with minor changes to controller firmware.

[0021] In one possible implementation of the first aspect, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value. In this possible implementation, when it is detected that the number of blank physical blocks in the second storage space is less than the first preset value, the first garbage collection operation is performed on physical blocks other than the blank physical blocks. This can free up new blank physical blocks for writing data as quickly as possible, thereby improving the performance of the storage system.

[0022] In a possible implementation of the first aspect, the method further includes: performing a second garbage collection operation on other areas in the first storage space except the blank areas. In the above possible implementation, the second garbage collection operation is performed on other areas in the first storage space except the blank areas. The second garbage collection operation in the second storage space reads and writes data in units of physical pages, and the number of times read commands and write commands are sent is relatively large. The second garbage collection operation in the first storage space reads and writes data in units of areas, and the number of times read commands and write commands are sent is relatively small. Therefore, the second garbage collection operation in the first storage space occupies less space and has less overhead, thereby reducing the write amplification of the storage system.

[0023] In one possible implementation of the first aspect, the second garbage collection operation is performed when it is detected that the number of blank areas is less than a second preset value. In this possible implementation, when it is detected that the number of blank areas in the first storage space is less than the second preset value, the second garbage collection operation is performed on areas other than the blank areas. This can quickly free up new blank areas for writing data, thereby improving the performance of the storage system.

[0024] In one possible implementation of the first aspect, the storage capacity of a region is (1 / n) times the storage capacity corresponding to a physical block of a memory of the storage system, where 1<n≤256. In this possible implementation, the storage capacity of a region is (1 / n) physical blocks, which facilitates the storage system to manage operations performed on data in each region.

[0025] In a second aspect, a controller is provided, which includes a processor and an interface circuit coupled to the processor, the interface circuit is coupled to a memory, and the processor is configured to: in response to receiving a first command including a first logical address of first data to be operated, determine at least one area corresponding to the first logical address, the at least one area corresponding to a first storage space of the memory; obtain at least one first physical page address corresponding to the at least one area based on the first mapping relationship and the determined at least one area; and send a third command to the memory through the interface circuit based on the at least one first physical page address to perform an operation on the first data in the first storage space; wherein the storage capacity of an area is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

[0026] In a possible implementation manner of the second aspect, the processor is specifically configured to: determine at least one first physical page address in a pointer mode based on the first mapping relationship and at least one region.

[0027] In a possible implementation of the second aspect, the first command is used to instruct writing of the first data, and the first command also includes the first data. The processor is specifically configured to: send a third command to the memory through the interface circuit to write the first data to at least one physical address in the first storage space.

[0028] In a possible implementation of the second aspect, the processor is further configured to: before obtaining at least one first physical page address corresponding to at least one area, establish a first mapping relationship corresponding to at least one area and multiple physical page addresses, where the multiple physical page addresses include at least one first physical page address; and send a first write command to the memory through the interface circuit to write the first mapping relationship corresponding to at least one area and multiple physical page addresses in the memory.

[0029] In a possible implementation of the second aspect, the first command is used to instruct reading of first data. The processor is specifically configured to: send a third command to the memory through the interface circuit to read the first data from at least one first physical page address in the first storage space.

[0030] In a possible implementation manner of the second aspect, the controller includes a buffer, and the buffer stores a first mapping relationship.

[0031] In a possible implementation manner of the second aspect, the first mapping relationship is a secondary mapping relationship.

[0032] In a possible implementation of the second aspect, the processor is further configured to: in response to receiving a second command including a second logical address of second data to be operated, obtain a second physical page address corresponding to the second logical address according to a second mapping relationship, and the second logical address corresponds to a second storage space of the memory; according to the second physical page address, send a fourth command to the memory through the interface circuit to perform operations on the second data in the second storage space; wherein the second storage space is a storage space that can support random reading or random writing.

[0033] In a possible implementation manner of the second aspect, the second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

[0034] In a possible implementation of the second aspect, the second command is used to instruct writing of second data. The processor is further configured to: before obtaining the second physical page address corresponding to the second logical address, establish a second mapping relationship corresponding to the second logical address. Send a second write command to the memory via the interface circuit to write the second mapping relationship corresponding to the second logical address into the memory. The processor is specifically configured to: send a fourth command to the memory via the interface circuit to write the second data at the second physical page address in the second storage space.

[0035] In a possible implementation of the second aspect, the second command is used to instruct reading of second data; and the processor is further configured to, in response to the second command, send a read command to the memory via the interface circuit to read the second mapping relationship corresponding to the second logical address, before obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship. The processor is specifically configured to send a fourth command to the memory via the interface circuit to read the second data from the second physical address in the second storage space.

[0036] In a possible implementation manner of the second aspect, the second mapping relationship is a three-level mapping relationship.

[0037] In a possible implementation manner of the second aspect, the processor is further configured to: perform a first garbage collection operation on physical blocks other than blank physical blocks in the second storage space.

[0038] In a possible implementation manner of the second aspect, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value.

[0039] In a possible implementation manner of the second aspect, the processor is further configured to: perform a second garbage collection operation on other areas in the first storage space except the blank area.

[0040] In a possible implementation of the second aspect, the second garbage collection operation is performed when it is detected that the number of blank areas is less than a second preset value.

[0041] In a possible implementation manner of the second aspect, the storage capacity of an area is (1 / n) times the storage capacity corresponding to a physical block of the memory, where 1<n≤256.

[0042] According to a third aspect, a storage system is provided, which includes a controller and a memory coupled to the controller, wherein the controller is configured to: determine at least one area corresponding to the first logical address in response to a received first command including a first logical address of first data to be operated, wherein the at least one area corresponds to a first storage space of the memory; obtain at least one first physical page address corresponding to the at least one area based on the first mapping relationship and the determined at least one area; and send a third command to the memory based on the at least one first physical page address; the memory is configured to: perform an operation on the first data in the first storage space in response to the third command; wherein the storage capacity of an area is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

[0043] In a possible implementation manner of the third aspect, the controller is specifically configured to: determine at least one first physical page address in a pointer mode based on the first mapping relationship and at least one region.

[0044] In a possible implementation of the third aspect, the first command is used to instruct writing of the first data, and the first command also includes the first data. The memory is specifically configured to: write the first data to at least one physical address in the first storage space in response to the third command.

[0045] In a possible implementation of the third aspect, the controller is further configured to: before obtaining at least one first physical page address corresponding to the at least one region, establish a first mapping relationship between the at least one region and multiple physical page addresses, the multiple physical page addresses including the at least one first physical page address; and send a first write command to the memory. The memory is further configured to: in response to the first write command, write the first mapping relationship between the at least one region and the multiple physical page addresses.

[0046] In a possible implementation of the third aspect, the first command is used to instruct reading of first data. The memory is specifically configured to: in response to the third command, read the first data from at least one first physical page address in the first storage space and send the first data to the controller.

[0047] In a possible implementation manner of the third aspect, the controller of the storage system includes a cache, and the cache stores a first mapping relationship.

[0048] In a possible implementation manner of the third aspect, the first mapping relationship is a secondary mapping relationship.

[0049] In a possible implementation of the third aspect, the controller is further configured to: in response to receiving a second command including a second logical address of second data to be operated on, obtain, according to a second mapping relationship, a second physical page address corresponding to the second logical address, where the second logical address corresponds to a second storage space of the memory; and send a fourth command to the memory based on the second physical page address. The memory is configured to: in response to the fourth command, perform the operation on the second data in the second storage space; wherein the second storage space is a storage space capable of supporting random reads or random writes.

[0050] In a possible implementation manner of the third aspect, the second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

[0051] In a possible implementation of the third aspect, the second command is used to instruct the writing of second data. The controller is further configured to: before obtaining the second physical page address corresponding to the second logical address, establish a second mapping relationship corresponding to the second logical address; and send a second write command to the memory. The memory is specifically configured to: in response to the fourth command, write the second data to the second physical page address in the second storage space. The memory is further configured to: in response to the second write command, write the second mapping relationship corresponding to the second logical address into the memory.

[0052] In a possible implementation of the third aspect, the second command is used to instruct reading of second data. The controller is further configured to, in response to the second command, send a read command to the memory before obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship. The memory is further configured to, in response to the read command, read the second mapping relationship corresponding to the second logical address and send the second mapping relationship to the controller. The memory is specifically configured to, in response to a fourth command, read the second data from the second physical address in the second storage space and send the second data to the controller.

[0053] In a possible implementation manner of the third aspect, the second mapping relationship is a three-level mapping relationship.

[0054] In a possible implementation manner of the third aspect, the controller is further configured to: perform a first garbage collection operation on physical blocks other than blank physical blocks in the second storage space.

[0055] In a possible implementation manner of the third aspect, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value.

[0056] In a possible implementation manner of the third aspect, the controller is further configured to: perform a second garbage collection operation on other areas in the first storage space except the blank area.

[0057] In a possible implementation manner of the third aspect, the second garbage collection operation is performed when it is detected that the number of blank areas is less than a second preset value.

[0058] In a possible implementation of the third aspect, the storage capacity of an area is (1 / n) times the storage capacity corresponding to a physical block of a memory of the storage system, where 1<n≤256.

[0059] In a fourth aspect, an electronic device is provided, comprising a host and a storage system provided by the third aspect or any possible implementation of the third aspect.

[0060] In a fifth aspect, a computer-readable storage medium is provided, in which a program code is stored. The program code can be called by a processor to execute the operating method of the storage system provided by the first aspect or any possible implementation of the first aspect.

[0061] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is caused to execute the storage system operating method provided by the first aspect or any possible implementation of the first aspect.

[0062] It can be understood that any of the controllers, storage systems, electronic devices, computer storage media or computer program products provided above are used to execute the corresponding methods provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding methods provided above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0063] FIG1 is a schematic structural diagram of an electronic device provided in an embodiment of the present application;

[0064] FIG2 is a schematic diagram of the structure of a storage system provided in an embodiment of the present application;

[0065] FIG3 is a schematic diagram of the structure of a controller provided in an embodiment of the present application;

[0066] FIG4 is a schematic diagram of the structure of a memory provided in an embodiment of the present application;

[0067] FIG5 is a first schematic diagram of a memory provided in an embodiment of the present application;

[0068] FIG6 is a flowchart diagram 1 of a method for operating a storage system provided in an embodiment of the present application;

[0069] FIG7 is a second schematic diagram of a memory provided in an embodiment of the present application;

[0070] FIG8 is a schematic diagram of a correspondence between regions and physical page addresses provided by an embodiment of the present application;

[0071] FIG9 is a schematic diagram of a mapping table provided in an embodiment of the present application;

[0072] FIG10 is a first schematic diagram of writing data provided by an embodiment of the present application;

[0073] FIG11 is a schematic diagram of reading data provided by an embodiment of the present application;

[0074] FIG12 is a second flow chart of a method for operating a storage system according to an embodiment of the present application;

[0075] FIG13 is a third schematic diagram of a memory provided in an embodiment of the present application;

[0076] FIG14 is a second schematic diagram of writing data provided by an embodiment of the present application;

[0077] FIG15 is a schematic diagram of garbage collection provided by an embodiment of the present application;

[0078] FIG16 is a schematic diagram of a controller and a memory provided in an embodiment of the present application;

[0079] FIG17 is a schematic diagram of a storage system and memory provided in an embodiment of the present application;

[0080] FIG18 is a schematic diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0081] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0082] In the description of this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0083] When describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

[0084] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C," and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C. "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B. The use of "suitable for" or "configured to" herein is intended to be open and inclusive language that does not exclude devices that are adapted or configured to perform additional tasks or steps.

[0085] Before introducing the embodiments of the present application, the application scenarios of the embodiments of the present application are first introduced and described. The technical solutions provided in the embodiments of the present application can be applied to electronic devices, or can be applied to components of electronic devices (such as chips built into the electronic devices). The electronic devices include but are not limited to: mobile phones, tablet computers, computers, laptops, video cameras, cameras, wearable devices, vehicle-mounted devices, or terminal devices.

[0086] First, a possible structure of an electronic device 100 is described with reference to FIG1 . The electronic device 100 may include a host 110 and a storage system 120 . The host 110 may include a processor 111 , an input / output interface 112 , a sensor component 113 , and a multimedia component 114 . The storage system 120 , the processor 111 , the input / output interface 112 , the sensor component 113 , and the multimedia component 114 may be coupled to each other via a bus 115 .

[0087] The storage system 120 can be used to store data, software programs, modules, etc.; it mainly includes a program storage area and a data storage area, wherein the program storage area can store software programs, including instructions formed in code, including but not limited to an operating system and applications required for at least one function; the data storage area can store data created according to the use of the electronic device 100.

[0088] The processor 111 is the control center of the electronic device 100. It connects various parts of the entire device using various interfaces and lines. By running or executing software programs and / or software modules stored in the storage system and calling data stored in the storage system, it performs various functions of the electronic device 100 and processes data, thereby monitoring the entire electronic device 100. Exemplarily, the processor 111 may include at least one of a central processing unit, a general-purpose processor, a digital signal processor, a neural network processor, a graphics processing unit (GPU), an image signal processor, or a microprocessor.

[0089] The input / output interface 112 provides an interface between the processor 111 and peripheral interface modules, such as a keyboard, a mouse, or a USB (Universal Serial Bus) device. The sensor component 113 includes one or more sensors for detecting the surrounding image, acceleration / deceleration, orientation, open / closed state, relative positioning of components, or temperature changes of the electronic device 100. The multimedia component 114 provides a screen as an output interface between the electronic device 100 and the user.

[0090] Next, a possible structure of a storage system 200 is described with reference to Figure 2. Storage system 200 may include a coupled memory 220 and a controller 210. Controller 210 may be coupled to a host. Controller 210 may receive an operation command from the host and, based on the operation command, send a command (CMD), an address (ADD), and data to memory 220. Memory 220 may receive the address sent by controller 210 and execute the operation corresponding to the command on the area selected by the address.

[0091] The memory 220 may include a floppy disk, a hard disk (such as a built-in hard disk and a mobile hard disk), a magnetic disk, an optical disk, a magneto-optical disk such as a compact disc read-only memory (CD-ROM), a non-volatile storage device such as a random access memory (RAM), a read-only memory (ROM), a programmable read only memory (PROM), an electrical programmable read only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory (such as NAND flash memory), or any other form of storage medium known in the technical field.

[0092] There may be one or more memories 220. In one example, the controller 210 and a single memory 220 may be integrated into a memory card. Memory cards may include a personal computer memory card international association (PCMCIA) card, a compact flash card (CF card), a smart media card (SM card), a memory stick, a multimedia card (MMC), a secure digital card (SD card), a universal flash storage (UFS), etc. Among them, multimedia cards can be divided into MMC, reduced-size MMC (RS-MMC), mini MMC (MMCmicro), etc.; secure digital cards include SD, mini SD card (miniSD), micro SD card (microSD), high-capacity SD card (secure digital high capacity, SDHC), etc. The memory card may also include a memory card connector for coupling the memory card to a host. In another example, the controller 210 and the plurality of memories 220 may be integrated into a solid state disk (SSD). The SSD may further include an SSD connector for coupling the SSD to a host.

[0093] Next, a possible structure of controller 300 is described with reference to FIG3 . Controller 300 may include an interface circuit 310, a processor 320, an interface circuit 330, other modules 340, and a bus 350. For example, bus 350 may be an Advanced Extensible Interface (AXI) bus. Other modules 340 may include, for example, write buffers and read buffers implemented using a DRAM and a DRAM controller. Interface circuit 310 in controller 300 may serve as a front-end interface to couple with a host, while interface circuit 330 may serve as a back-end interface to couple with a memory.

[0094] Next, a possible structure of a memory 400 is described with reference to FIG4 . The memory 400 includes a memory cell array 410 and peripheral circuits coupled to the memory cell array 410. The peripheral circuits include an input / output circuit 421, a control circuit 422, a register 423, a voltage generator 424, a row decoder 425, a column decoder 426, and a page buffer 427.

[0095] The memory cell array 410 may include a plurality of memory cells, a plurality of bit lines (BL), and a plurality of word lines (WL). Each memory cell is coupled to a word line and a bit line. The input / output circuit 421 may be configured to receive read and write commands from a controller and to transmit read data to the controller. The control circuit 422 may be configured to control the row decoder 425 to apply the electrical signal generated by the voltage generator 424 to the corresponding word line and the column decoder 426 to apply the electrical signal generated by the voltage generator 424 to the corresponding bit line, based on the received command, thereby performing operations on the corresponding memory cells, such as write operations, read operations, and erase operations. The register 423 may be configured to store, but is not limited to, word line addresses and string addresses, and may be configured to store the current state of the memory 400, such as ready and busy states. The page buffer 427 may be configured to cache data read from the memory cell array 410 or data to be written (programmed) to the memory cell array 410, based on control signals from the control circuit 422. Unless otherwise specified, the embodiments of the present application are described below using an example in which the memory in the storage system is a NAND flash memory.

[0096] In one example, the memory can be divided into multiple blocks, each of which can be divided into multiple pages. The memory erases data in blocks and reads and writes data in pages. For example, as shown in FIG5 , the memory 500 includes a second storage space 510, which includes multiple blocks in the memory 500, each of which includes multiple pages.

[0097] In another example, memory can be divided into multiple zones. For example, in a zoned universal flash storage (UFS) system, memory is divided into zones, and data is stored in the same zone for the same purpose and lifecycle. Partitioning a storage system allows for more efficient memory utilization, but implementing zoned storage has become a pressing issue.

[0098] Based on this, in order to realize partitioned storage of a storage system, an embodiment of the present application provides an operating method of a storage system, as shown in FIG6 .

[0099] S110 : In response to receiving a first command including a first logical address of first data to be operated, determining at least one area corresponding to the first logical address, where the at least one area corresponds to a first storage space of a memory of a storage system.

[0100] S120: Acquire at least one first physical page address corresponding to the at least one region according to the first mapping relationship and the determined at least one region.

[0101] S130: Perform an operation on the first data in the first storage space according to the at least one first physical page address. The storage capacity of the region is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space supports sequential reads and sequential writes. In some embodiments, the first storage space supports only sequential reads and sequential writes.

[0102] In some embodiments, the correspondence between the first storage space and the region may be: the first storage space may include multiple regions. For example, as shown in FIG7 , the memory 600 includes a first storage space 610 , and the first storage space 610 includes multiple regions in the memory 600 , such as region 0, region 1, ..., region Z.

[0103] Furthermore, the correspondence between regions and physical page addresses can be: one region corresponds to multiple physical page addresses, and the number of physical page addresses corresponding to each region can be the same or different. For example, as shown in Figure 8, region 0 corresponds to physical page addresses 0, 1, ..., k, and region Z corresponds to physical page addresses n, ..., m.

[0104] In addition, the first physical page address may refer to the physical page address indicated by the first logical address. The correspondence between the first logical address, the region, and the first physical page address may be: the first logical address corresponds to at least one region, and the at least one region corresponding to the first logical address corresponds to at least one first physical page address. If the first logical address corresponds to one region, then the region corresponding to the first logical address corresponds to at least one first physical page address; if the first logical address corresponds to multiple regions, then each of the multiple regions corresponding to the first logical address corresponds to at least one first physical page address.

[0105] In the operating method of the storage system provided in the embodiment of the present application, the first storage space of the memory of the storage system is divided into multiple areas, and the first storage space is a storage space that only supports sequential reading and sequential writing. When a first command to operate the first data is received, at least one area can be determined according to the first logical address of the first data included in the first command. According to the first mapping relationship between at least one area and multiple physical page addresses (multiple physical page addresses include at least one first physical page address), at least one first physical page address corresponding to at least one area can be obtained. Among them, if the first logical address corresponds to an area, at least one first physical page address corresponding to this area is obtained; if the first logical address corresponds to multiple areas, at least one first physical page address corresponding to each area in the multiple areas is obtained. According to the at least one first physical page address obtained, the operation indicated by the first command can be performed on the first data in the first storage space. In this way, by determining the area according to the first logical address and then obtaining the first physical page address according to the first mapping relationship, partitioned storage of the storage system can be realized, and then the benefits brought by partitioned storage can be realized, which include but are not limited to:

[0106] 1. Host performance booster (HPB) and file-based optimization (FBO) technologies can prevent the degradation of storage read speeds after long-term use. The functional benefits of partitioned storage can replace those of HPB and FBO technologies, and can even be greater than those achieved by HPB and FBO.

[0107] 2. Multiple cold and hot data diversions can be achieved.

[0108] 3. The host can place data with similar access frequencies in the same area and data with different access frequencies in different areas to reduce overall write amplification, thereby extending the life of the memory. It is suitable for quad level cell (QLC) devices, penta level cell (PLC) devices and devices with more levels of storage cells.

[0109] In a possible implementation, the storage capacity of a region is (1 / n) times the storage capacity corresponding to a physical block of a memory of the storage system, where 1<n≤256.

[0110] In the storage system operation method provided in the embodiment of the present application, the storage capacity of one area is (1 / n) physical blocks, which facilitates the storage system management to perform operations on data in each area.

[0111] In one possible implementation, the first mapping relationship may be a two-level mapping relationship. The first mapping relationship may include only a mapping relationship between a region and a physical page address. The mapping relationship may be stored in the form of a mapping table. The first mapping relationship may include a first-level A mapping table and a second-level A mapping table. The first-level A mapping table and the second-level A mapping table may be stored in a system block of a memory. The mapping relationship may also be stored in other forms, which is not limited in this embodiment of the present application.

[0112] In one example, the first-level A mapping table stores a physical address of the second-level A mapping table corresponding to a region in the system block, and the second-level A mapping table corresponding to the region stores multiple physical page addresses corresponding to the region. The multiple physical page addresses stored in the second-level A mapping table may include at least one first physical page address indicated by the first logical address. For example, referring to (a) in Figure 9, the first-level A mapping table stores the physical address of the second-level A mapping table corresponding to region 0 (region numbered 0) in the system block. The second-level A mapping table corresponding to region 0 stores 4 physical page addresses corresponding to region 0, namely: physical page addresses 0, 1, 2, and 3. The at least one first physical page address indicated by the first logical address may be physical page addresses 0 and 1.

[0113] In another example, the first-level A mapping table stores physical addresses in the system block corresponding to multiple second-level A mapping tables corresponding to multiple regions, and the second-level A mapping table corresponding to each region in the multiple regions stores multiple physical page addresses corresponding to the region. The multiple physical page addresses stored in the multiple second-level A mapping tables include at least one first physical page address indicated by the first logical address. For example, referring to (b) in Figure 9, the first-level A mapping table stores the physical address in the system block corresponding to the second-level A mapping table corresponding to region 0, and stores the physical address in the system block corresponding to the second-level A mapping table corresponding to region 1 (region numbered 1). The second-level A mapping table corresponding to region 0 stores four physical page addresses corresponding to region 0, namely physical page addresses 0, 1, 2, and 3. The second-level A mapping table corresponding to region 1 stores four physical page addresses corresponding to region 1, namely physical page addresses 4, 5, 6, and 7. The at least one first physical page address indicated by the first logical address can be physical page addresses 0 to 7.

[0114] In another example, compared to a three-level mapping relationship or a multi-level mapping relationship, a two-level mapping relationship occupies less storage space. For example, referring to (c) in FIG. 9 , the three-level mapping relationship is a logical to physical (L2P) mapping table. The three-level mapping table may include: a mapping relationship between a logical page address, a physical block address corresponding to the logical page address, and a physical page address corresponding to the physical block address. The three-level mapping relationship is stored in the form of a three-level mapping table, which includes a first-level B mapping table, a second-level B mapping table, and a third-level B mapping table. The first-level B mapping table stores the physical address of the second-level B mapping table corresponding to logical page address 0 in the system block. According to the second-level B mapping table corresponding to logical page address 0, it can be seen that logical page address 0 corresponds to physical block address 0. The second-level B mapping table corresponding to logical page address 0 stores the physical address of the third-level B mapping table corresponding to physical block address 0 in the system block. The third-level B mapping table corresponding to physical block address 0 stores the physical page address 1 corresponding to physical block address 0. In this way, the three-level mapping table can store the mapping relationship between logical page addresses 0, 2, 3, 6 and physical page addresses 0, 1, 2, 3 corresponding to physical block address 0, and can store the mapping relationship between logical page addresses 1, 4, 5, 7 and second physical page addresses 0, 1, 2, 3 corresponding to physical block address 1.

[0115] From the above example, we can see that for the mapping relationship of 8 physical page addresses, the secondary mapping relationship shown in Figure 9 (b) occupies less storage space than the tertiary mapping relationship shown in Figure 9 (c). For example, for a 256GB UFS storage system, the storage capacity of a region can be 16MB, and the maximum storage space occupied by the secondary mapping relationship is 64KB.

[0116] In the storage system operation method provided in the embodiment of the present application, the first mapping relationship is a two-level mapping relationship. Compared with three-level mapping relationships or more-level mapping relationships, the two-level mapping relationship occupies less storage space and can save the storage capacity of the storage system.

[0117] In another possible implementation, the first mapping relationship may also be a three-level mapping relationship or a multi-level mapping relationship, which is not limited in this embodiment of the present application.

[0118] In another possible implementation, the controller of the storage system includes a cache, and the first mapping relationship may be stored in the cache.

[0119] In one example, the cache may be a static random-access memory (SRAM). For a storage system in which the controller does not have dynamic random-access memory (DRAM) but only has SRAM, the controller can cache a relatively small amount of data. Because the first mapping relationship occupies a relatively small amount of storage space, the first mapping relationship may be stored in the cache of the controller.

[0120] In another example, the cache may be a DRAM. Since the DRAM can cache a large amount of data, the first mapping relationship may be stored in the DRAM even if the first mapping relationship occupies a large storage space.

[0121] In the storage system operating method provided in the embodiment of the present application, the cache in the controller can store the first mapping relationship. When the controller needs to obtain the first mapping relationship, it does not need to obtain the first mapping relationship from the memory 220 each time, but can directly obtain the first mapping relationship from the cache. The controller can obtain the first mapping relationship faster and operate data more efficiently.

[0122] After introducing the form and storage location of the first mapping relationship, an example is given to illustrate a method of obtaining the first physical page address according to the first logical address.

[0123] In one possible implementation, S110 (determining at least one region corresponding to the first logical address) may include calculating the first logical address according to a preset algorithm to thereby determine the at least one region corresponding to the first logical address. The preset algorithm may be an algorithm preconfigured by the storage system for determining a relationship between the first logical address and the region.

[0124] Exemplarily, the first logical address carries a calculation data, and a division calculation is performed on the calculation data carried by the first logical address, and the obtained quotient is used to indicate an area (such as area 0 in FIG. 9 ).

[0125] Exemplarily, the first logical address carries multiple calculation data, and division calculations are performed on the multiple calculation data carried by the first logical address respectively, and the multiple quotients obtained are used to indicate multiple areas respectively (such as area 0 and area 1 in Figure 9), wherein each quotient of the multiple quotients is used to indicate an area.

[0126] In another possible implementation, S120 (obtaining at least one first physical page address corresponding to the at least one region based on the first mapping relationship and the determined at least one region) may include: determining the at least one first physical page address in a pointer mode based on the first mapping relationship and the at least one region. Specifically, S120 may include S121 to S123.

[0127] S121: Calculate the first logical address according to a preset algorithm to determine a pointer corresponding to the first logical address.

[0128] S122: Based on the first mapping relationship and the at least one region corresponding to the first logical address, obtain multiple physical page addresses corresponding to the at least one region. If the first logical address corresponds to one region, obtain multiple physical page addresses corresponding to the region; if the first logical address corresponds to multiple regions, obtain multiple physical page addresses corresponding to each of the multiple regions.

[0129] S123: Determine at least one first physical page address from the plurality of physical page addresses based on the pointer corresponding to the first logical address. If the first logical address corresponds to a region, determine at least one first physical page address from the plurality of physical page addresses corresponding to the region; if the first logical address corresponds to multiple regions, determine at least one first physical page address from the plurality of physical page addresses corresponding to each of the multiple regions.

[0130] Exemplarily, the first logical address carries a calculation data, and a division calculation is performed on the calculation data carried by the first logical address. The obtained quotient is used to indicate an area (such as area 0 in Figure 9), and the obtained remainder is used to indicate the pointer corresponding to the first logical address. The pointer can be used to indicate the first physical page address is the number of multiple physical page addresses corresponding to the area (such as the second physical page address among the physical page addresses 0-3 in Figure 9, that is, physical page address 1).

[0131] Exemplarily, the first logical address carries multiple calculation data, and the above-mentioned division calculation is performed on each of the multiple calculation data. The multiple remainders obtained are used to indicate multiple pointers corresponding to the first logical address, thereby determining at least one first physical page address corresponding to at least one area.

[0132] In the storage system operating method provided in an embodiment of the present application, multiple physical page addresses corresponding to each region in the at least one region can be obtained based on a first mapping relationship and at least one region. At least one first physical page address can be determined from the multiple physical page addresses corresponding to each region in a pointer mode. This provides a basis for implementing partitioned storage in the storage system.

[0133] Next, the operation on the first data indicated by the first command is introduced through several possible implementation methods.

[0134] In some embodiments, the first command is used to instruct writing of first data, and the first command also includes the first data. S130 (performing an operation on the first data in the first storage space according to at least one first physical page address) may include: writing the first data to at least one physical address in the first storage space.

[0135] For example, referring to FIG10 , the first data includes eight data, which may include A1, B1, C1, D1, E1, F1, G1, and H1 in order, and their corresponding first logical addresses are logical block addresses (LBA) 0 to LBA7, respectively. In response to the first command, the storage system determines that the area corresponding to the first logical addresses of the four data A1, B1, C1, and D1 is area 0, and the area corresponding to the first logical addresses of the four data E1, F1, G1, and H1 is area 1. The first mapping relationship corresponding to area 0 and area 1 has been stored in the system block of the storage system's memory and is written to the controller's cache when the storage system starts. Based on the first mapping relationship in the cache, the storage system obtains the first physical page addresses 0-3 corresponding to area 0 and obtains the first physical page addresses 4-7 corresponding to area 1.

[0136] The storage system writes A1 to the first physical page 0 indicated by the first physical page address 0, B1 to the first physical page 1 indicated by the first physical page address 1, C1 to the first physical page 2 indicated by the first physical page address 2, and D1 to the first physical page 3 indicated by the first physical page address 3, in the order of A1, B1, C1, and D1. Furthermore, the storage system writes E1 to the first physical page 4 indicated by the first physical page address 4, F1 to the first physical page 5 indicated by the first physical page address 5, G1 to the first physical page 6 indicated by the first physical page address 6, and H1 to the first physical page 7 indicated by the first physical page address 7, in the order of E1 as the first, F1 as the second, G1 as the third, and H1 as the fourth.

[0137] In the operating method of the storage system provided in an embodiment of the present application, the first command is used to instruct the writing of the first data. If the first mapping relationship has been established, at least one first physical page address can be directly obtained according to the first mapping relationship, and the first data can be written at at least one physical address in the first storage space. In this way, it not only provides a basis for realizing the partitioned storage of the storage system, but also makes the data writing operation simple and convenient, with a shorter writing time and a faster writing speed.

[0138] In some embodiments, the first command is used to instruct the writing of the first data, and the first command also includes the first data. Before S120 (according to the first mapping relationship and the determined at least one area, obtaining at least one first physical page address corresponding to the at least one area), it also includes: establishing a first mapping relationship corresponding to at least one area and multiple physical page addresses, and the multiple physical page addresses include at least one first physical page address. S130 (according to the at least one first physical page address, performing an operation on the first data in the first storage space) may include: writing the first data at at least one physical address in the first storage space. The method also includes: writing the first mapping relationship corresponding to at least one area and multiple physical page addresses in the memory.

[0139] The step of establishing a first mapping relationship between at least one region and multiple physical page addresses includes: if the first logical address corresponds to one region, establishing a first mapping relationship between the region and multiple physical page addresses; and if the first logical address corresponds to multiple regions, establishing a first mapping relationship between multiple physical page addresses for each of the multiple regions.

[0140] When the storage system determines at least one region corresponding to the first logical address, a first mapping relationship for the at least one region has not yet been established. Therefore, the first mapping relationship must be established before the first physical page address can be obtained based on the first mapping relationship. After the first mapping relationship is established, the first mapping relationship is written into the memory and stored in a buffer of the controller.

[0141] In the operating method of the storage system provided in an embodiment of the present application, the first command is used to instruct the writing of the first data. If the first mapping relationship has not been established, after receiving the first command, a first mapping relationship is first established corresponding to at least one area and multiple physical page addresses, and the multiple physical page addresses include at least one first physical page address, and then the first data is written at at least one physical address in the first storage space. In addition, the first mapping relationship corresponding to at least one area and multiple physical page addresses is written in the memory. In this way, it not only provides a basis for realizing the partitioned storage of the storage system, but also facilitates the subsequent continued use of the first mapping relationship. For the first storage space, the first mapping relationship needs to be established once each time data in an area is written, rather than once each time data in a logical page is written. At the overall level of data writing, the number of times the first mapping relationship is established is less, the number of instruction interactions is less, and the writing speed is faster.

[0142] In some embodiments, the first command is used to instruct to read the first data. S130 (performing an operation on the first data in the first storage space according to at least one first physical page address) may include: reading the first data from the at least one first physical page address in the first storage space.

[0143] For example, please refer to Figure 11. The storage space that does not use partitioned storage can use an L2P mapping table (such as the three-level mapping table mentioned above) to record the mapping relationship between the logical page address and the physical page address. The L2P mapping table occupies a large storage space. In some embodiments, the capacity of the cache in the controller of the storage system is small (such as using SRAM as a cache), and the L2P mapping table is stored in the memory of the storage system, rather than being cached entirely in the controller of the storage system. In other embodiments, the capacity of the cache in the controller of the storage system is large (such as using DRAM as a cache), and the L2P mapping table is stored in the memory, and the L2P mapping table in the memory can be loaded into the cache of the controller when the storage system is powered on. In the process of reading data, the storage system needs to first read the L2P mapping table corresponding to the data from the memory or cache, and then obtain the physical page address of the data according to the second mapping relationship, and read the data from the memory according to the physical page address of the data.

[0144] In the operating method of the storage system provided in the embodiment of the present application, since the first mapping relationship occupies a small storage space, regardless of whether the cache capacity in the controller of the storage system is large or small, the first mapping relationship can be cached in the controller. Before the storage system reads the first data, there is no need to execute the step of reading the first mapping relationship from the memory, and the first data can be directly read from the memory according to the first mapping relationship cached by the controller.

[0145] In the operating method of the storage system provided in an embodiment of the present application, the first command is used to instruct the reading of the first data, and the first mapping relationship has been established. When the first command is received, at least one first physical page address can be directly obtained according to the first mapping relationship, and the first data can be read from at least one first physical page address in the first storage space. In this way, it not only provides a basis for realizing the partitioned storage of the storage system, but also makes the data reading operation simple and convenient, with shorter reading time and faster reading speed.

[0146] The storage system provided in the embodiment of the present application may include, in addition to the first storage space, a second storage space. Referring to FIG. 12 , the method may further include:

[0147] S210: In response to a received second command including a second logical address of second data to be operated, obtaining a second physical page address corresponding to the second logical address according to a second mapping relationship, where the second logical address corresponds to a second storage space of the memory.

[0148] S220: performing an operation on the second data in the second storage space according to the second physical page address; wherein the second storage space is a storage space that can support random reading or random writing.

[0149] Among them, the correspondence between the second storage space and the blocks and pages can be: the second storage space includes multiple blocks, and each block includes multiple pages. The second storage space is logically divided into pages, so the second storage space can read or write data in a random manner. From the above embodiment, it can be seen that the first storage space includes multiple areas. The first storage space is no longer logically divided into pages, so the first storage space reads or writes data in a sequential manner. For example, as shown in Figure 13, the memory 700 includes a first storage space 710 and a second storage space 720. The first storage space 710 includes multiple areas, and the second storage space 720 includes multiple blocks, and each block includes multiple pages. The flash translation layer (FTL) corresponding to the first storage space uses the first mapping relationship to perform address translation, and the flash translation layer corresponding to the second storage space uses the second mapping relationship to perform address translation.

[0150] Illustratively, a first command received by the storage system carries a first logical unit number (LUN), which is used to determine whether to perform an operation on first data in a first storage space. A second command received by the storage system carries a second logical unit number (LUN), which is used to determine whether to perform an operation on second data in a second storage space.

[0151] In the operating method of the storage system provided in the embodiment of the present application, the first storage space is a storage space that only supports sequential reading and sequential writing, and the second storage space is a storage space that can support random reading or random writing. For the first data that can be written or read sequentially, according to the first command and the first mapping relationship, at least one first physical page address corresponding to the first logical address of the first data is obtained, and operations are performed on the first data in the first storage space according to the at least one physical page address. For the second data that needs to be written or read randomly, according to the second command and the second mapping relationship, the second physical page address corresponding to the second logical address of the second data is obtained, and operations are performed on the second data in the second storage space according to the second physical page address. Since the partitioned storage method only supports sequential reading and sequential writing, the controllers of some storage systems did not anticipate the partitioning software characteristics when they were designed. The storage spaces of these storage systems need to write part of the data in a random writing manner, or read part of the data in a random reading manner. The second storage space and the second mapping relationship can be used to operate the second data. The embodiments of the present application store some data that requires random write or random read in the second storage space, and the remaining data that can be written or read sequentially in the first storage space. This allows the benefits of partitioned storage to be realized with good compatibility while making minor changes to the controller firmware. For storage system products that do not support the Zone UFS protocol or have poor hardware performance, the storage system operating method of the embodiments of the present disclosure can also be applied with minor updates to the controller firmware.

[0152] In a possible implementation, the second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

[0153] The correspondence between the logical page address, the physical block address and the physical page address may be: multiple logical page addresses correspond to one physical block address, the physical block address corresponds to multiple physical page addresses, and one logical page address corresponds to one physical page address in the physical block address.

[0154] Furthermore, the content of the second mapping relationship can refer to (c) in Figure 9. The second mapping relationship includes a mapping relationship of multiple logical page addresses, at least one physical block address, and multiple physical page addresses. The second logical address can be at least one logical page address among the multiple logical page addresses, such as logical page address 0. The physical block address corresponding to the second logical address can be physical block address 0 corresponding to logical page address 0, and the second physical page address corresponding to physical block address 0 can be physical page address 1.

[0155] In the operating method of the storage system provided in an embodiment of the present application, the second mapping relationship is a mapping relationship including a second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address. In this way, the second physical page address corresponding to the second logical address can be obtained according to the second logical address and the second mapping relationship, providing a basis for storing part of the data that needs to be randomly written or randomly read in the second storage space.

[0156] In one possible implementation, the second mapping relationship is a three-level mapping relationship. The second mapping relationship can be stored in the form of a three-level mapping table, which can include a first-level B mapping table, a second-level B mapping table, and a third-level B mapping table. The first-level B mapping table stores the physical address of the second-level B mapping table corresponding to the second logical address. The second-level B mapping table stores the physical address of the corresponding third-level B mapping table. The third-level B mapping table stores the second physical page address corresponding to the physical block address corresponding to the second logical address.

[0157] In the operating method of the storage system provided in the embodiment of the present application, the second mapping relationship is a three-level mapping relationship, which provides a basis for storing part of the data that needs to be randomly written or randomly read in the second storage space.

[0158] Next, the operation on the second data indicated by the second command is introduced through several possible implementation methods.

[0159] In the first embodiment, the second command is used to instruct the writing of the second data. Before S210 (obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship), the method may further include: reading the second mapping relationship corresponding to the second logical address from the memory in response to the second command. S220 (performing an operation on the second data in the second storage space according to the second physical page address) may include: writing the second data at the second physical page address in the second storage space.

[0160] For example, referring to FIG14 , the second data includes eight data items, which are A2, B2, C2, D2, E2, F2, G2, and H2, in order from 1 to 7. Their corresponding second logical addresses are LBA3, LBA0, LBA2, LBA6, LBA5, LBA1, LBA7, and LBA4, respectively. The second mapping relationships for the second logical addresses of these eight data items are stored in a system block of the storage system's memory. In response to the second command, the storage system reads the second mapping relationships corresponding to the second logical addresses from the memory. The storage system determines, based on the second mapping relationship read, that the physical block address corresponding to the second logical addresses of the four data B2, C2, A2, and D2 is 0, the physical block address corresponding to the second logical addresses of the four data F2, H2, E2, and G2 is 1, the second physical page address corresponding to the physical block address 0 of B2 is 1, the second physical page address corresponding to the physical block address 1 of F2 is 1, the second physical page address corresponding to the physical block address 0 of C2 is 2, the second physical page address corresponding to the physical block address 0 of A2 is 0, the second physical page address corresponding to the physical block address 1 of H2 is 3, the second physical page address corresponding to the physical block address 1 of E2 is 0, the second physical page address corresponding to the physical block address 0 of D2 is 3, and the second physical page address corresponding to the physical block address 1 of G2 is 2.

[0161] The storage system writes B2 to the second physical page 1 of the physical block 0 indicated by the physical block address 0 and the second physical page address 1, F2 to the second physical page 1 of the physical block 1 indicated by the physical block address 1 and the second physical page address 1, C2 to the second physical page 2 of the physical block 0 indicated by the physical block address 0 and the second physical page address 2, A2 to the second physical page 0 of the physical block 0 indicated by the physical block address 0 and the second physical page address 0, H2 to the second physical page 3 of the physical block 1 indicated by the physical block address 1 and the second physical page address 3, E2 to the second physical page 0 of the physical block 1 indicated by the physical block address 1 and the second physical page address 0, D2 to the second physical page 3 of the physical block 0 indicated by the physical block address 0 and the second physical page address 3, and G2 to the second physical page 2 of the physical block 1 indicated by the physical block address 1 and the second physical page address 2, in the order of B2 as the 1st, F2 as the 2nd, C2 as the 3rd, A2 to the second physical page 0 of the physical block 0 indicated by the physical block address 0 and the second physical page address 0, It can be seen that the writing order of the second data is inconsistent with the actual order of the second data, and the second data is written randomly.

[0162] In a second embodiment, the second command is used to instruct the writing of second data. Before S210 (obtaining a second physical page address corresponding to the second logical address based on the second mapping relationship and the second logical address), the method may further include: establishing a second mapping relationship corresponding to the second logical address. S220 (performing an operation on the second data in the second storage space based on the second physical page address) may include: writing the second data at the second physical page address in the second storage space. The method also includes: writing the second mapping relationship corresponding to the second logical address into the memory.

[0163] When the storage system receives the second command, the second mapping relationship corresponding to the second logical address has not yet been established. The second mapping relationship needs to be established first before the physical block address corresponding to the second logical address can be obtained based on the second mapping relationship, and then the second physical page address corresponding to the physical block address can be obtained. After the second mapping relationship is established, the second mapping relationship is written to the memory. Optionally, because the second mapping relationship is at least a three-level mapping relationship and occupies a large amount of storage space, the second mapping relationship is not stored in the controller's cache. For the second storage space, the second mapping relationship needs to be established once each time a logical page of data is written.

[0164] In the operating method of the storage system provided in an embodiment of the present application, the second command is used to instruct the writing of the second data. If the first mapping relationship has not yet been established, after receiving the first command, the second mapping relationship corresponding to the second logical address is first established, and then the second data is written to the second physical page address in the second storage space. In addition, the second mapping relationship corresponding to the second logical address is written to the memory. This provides a basis for storing partial data that requires random write in the second storage space.

[0165] In a third embodiment, the second command is used to instruct to read the second data. Before S210 (obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship), the method may further include: reading the second mapping relationship corresponding to the second logical address from the memory in response to the second command. S220 (performing an operation on the second data in the second storage space according to the second physical page address) may include: reading the second data from the second physical address in the second storage space.

[0166] For example, referring to FIG11 , because the second mapping relationship occupies a large amount of storage space, the second mapping relationship is stored in the storage system's memory rather than being cached entirely in the storage system's controller. Upon receiving the second command, the storage system must first read the second mapping relationship and then read the second data based on the second physical page address indicated by the second mapping relationship.

[0167] In the storage system operating method provided in the embodiment of the present application, the second command is used to instruct the reading of the second data. Upon receiving the second command, the second mapping relationship corresponding to the second logical address is first read from the memory, and then the second data is read from the second physical address in the second storage space. This provides a basis for reading partial data from the second storage space that requires random read.

[0168] Next, the garbage collection method of the storage system provided by the embodiment of the present application is introduced.

[0169] In a possible implementation, the method further includes: performing a first garbage collection operation on other physical blocks in the second storage space except for the blank physical blocks.

[0170] The blank physical block may be an available physical block that does not store data. The first garbage collection operation includes: the other physical blocks are multiple physical blocks, reading data of each physical page in the multiple physical blocks, writing the read data to a physical page of any physical block in the blank physical blocks, and erasing the data of each physical block.

[0171] Furthermore, when writing data, if the number of blank physical blocks is insufficient to write the data, the storage system performs a first garbage collection operation on other physical blocks in the second storage space except the blank physical blocks.

[0172] In the operating method of the storage system provided in an embodiment of the present application, a first garbage collection operation is performed on physical blocks other than blank physical blocks in the second storage space, and the first garbage collection operation is retained, thereby realizing the benefits of partitioned storage with minor changes to the controller firmware.

[0173] In another possible implementation, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value. When the storage system is in an idle state, the storage system may actively detect the number of blank physical blocks, and when it is detected that the number of blank physical blocks is less than the first preset value, the first garbage collection operation is performed on physical blocks other than the blank physical blocks in the second storage space.

[0174] In the operating method of the storage system provided in an embodiment of the present application, when it is detected that the number of blank physical blocks in the second storage space is less than a first preset value, a first garbage collection operation is performed on physical blocks other than the blank physical blocks, so that new blank physical blocks can be freed up as soon as possible to write data, thereby improving the performance of the storage system.

[0175] In another possible implementation, referring to FIG. 15 , based on the first garbage collection operation, the method further includes: performing a second garbage collection operation on other areas in the first storage space except the blank areas.

[0176] The blank area may be an available area where no data is stored. The second garbage collection operation includes: the other area is a plurality of areas, reading data from each of the plurality of areas, writing the read data to any area in the blank area, and erasing the data in each area.

[0177] Furthermore, when writing data, if the number of blank physical blocks is insufficient to write the data, the storage system performs a second garbage collection operation on the other physical blocks in the second storage space except the blank physical blocks.

[0178] In the storage system operating method provided in an embodiment of the present application, a second garbage collection operation is performed on areas other than blank areas in the first storage space. The second garbage collection operation in the second storage space reads and writes data in units of physical pages, and the number of read and write commands sent is relatively large. The second garbage collection operation in the first storage space reads and writes data in units of regions, and the number of read and write commands sent is relatively small. Therefore, the second garbage collection operation in the first storage space occupies less space and has lower overhead, thereby reducing write amplification of the storage system.

[0179] In another possible implementation, the second garbage collection operation is performed when it is detected that the number of blank areas is less than a second preset value. When the storage system is in an idle state, the storage system may actively detect the number of blank areas, and when it is detected that the number of blank areas is less than the second preset value, the second garbage collection operation is performed on areas other than the blank areas in the first storage space.

[0180] In the operating method of the storage system provided in an embodiment of the present application, when it is detected that the number of blank areas in the first storage space is less than a second preset value, a second garbage collection operation is performed on other areas except the blank areas, so that new blank areas can be freed up as soon as possible to write data, thereby improving the performance of the storage system.

[0181] An embodiment of the present application also provides a controller, please refer to Figure 16, the controller 810 includes a processor 811 and an interface circuit 812 coupled to the processor 811, the interface circuit 812 is coupled to the memory 820, and the processor 811 is configured to: in response to receiving a first command including a first logical address of first data to be operated, determine at least one area corresponding to the first logical address, the at least one area corresponds to the first storage space of the memory 820; obtain at least one first physical page address corresponding to the at least one area according to the first mapping relationship and the determined at least one area; and send a third command to the memory 820 through the interface circuit 812 according to the at least one first physical page address, so as to perform an operation on the first data in the first storage space; wherein the storage capacity of an area is smaller than the storage capacity corresponding to the physical block of the memory 820, and the first storage space is a storage space that only supports sequential reading and sequential writing.

[0182] In a possible implementation, the processor 811 is specifically configured to: determine at least one first physical page address in a pointer mode based on the first mapping relationship and at least one region.

[0183] In one possible implementation, the first command is used to instruct writing of the first data, and the first command also includes the first data. The processor 811 is specifically configured to: send a third command to the memory 820 via the interface circuit 812 to write the first data to at least one physical address in the first storage space.

[0184] In one possible embodiment, the processor 811 is also configured to: before obtaining at least one first physical page address corresponding to at least one area, establish a first mapping relationship corresponding to at least one area and multiple physical page addresses, and the multiple physical page addresses include at least one first physical page address; send a first write command to the memory 820 through the interface circuit 812 to write the first mapping relationship corresponding to at least one area and multiple physical page addresses in the memory 820.

[0185] In a possible implementation, the first command is used to instruct to read the first data. The processor 811 is specifically configured to: send a third command to the memory 820 through the interface circuit 812 to read the first data from at least one first physical page address in the first storage space.

[0186] In a possible implementation, the controller 810 includes a buffer storing a first mapping relationship.

[0187] In a possible implementation, the first mapping relationship is a secondary mapping relationship.

[0188] In one possible embodiment, the processor 811 is further configured to: in response to receiving a second command including a second logical address of second data to be operated, obtain a second physical page address corresponding to the second logical address according to a second mapping relationship, and the second logical address corresponds to the second storage space of the memory 820; according to the second physical page address, send a fourth command to the memory 820 through the interface circuit 812 to perform operations on the second data in the second storage space; wherein the second storage space is a storage space that can support random reading or random writing.

[0189] In a possible implementation, the second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

[0190] In one possible implementation, the second command is used to instruct writing of the second data. The processor 811 is further configured to: before obtaining the second physical page address corresponding to the second logical address, establish a second mapping relationship corresponding to the second logical address. Send a second write command to the memory 820 via the interface circuit 812 to write the second mapping relationship corresponding to the second logical address into the memory 820. The processor 811 is specifically configured to: send a fourth command to the memory 820 via the interface circuit 812 to write the second data at the second physical page address in the second storage space.

[0191] In one possible implementation, the second command is used to instruct to read the second data. The processor 811 is further configured to, before obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship, send a read command to the memory 820 via the interface circuit 812 in response to the second command to read the second mapping relationship corresponding to the second logical address. The processor 811 is specifically configured to send a fourth command to the memory 820 via the interface circuit 812 to read the second data from the second physical address in the second storage space.

[0192] In a possible implementation, the second mapping relationship is a three-level mapping relationship.

[0193] In a possible implementation, the processor 811 is further configured to: perform a first garbage collection operation on physical blocks other than blank physical blocks in the second storage space.

[0194] In a possible implementation, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value.

[0195] In a possible implementation, the processor 811 is further configured to perform a second garbage collection operation on other areas in the first storage space except the blank areas.

[0196] In a possible implementation, the second garbage collection operation is performed when it is detected that the amount of blank areas is less than a second preset value.

[0197] In a possible implementation, the storage capacity of a region is (1 / n) times the storage capacity corresponding to the physical block of the memory 820 , where 1<n≤256.

[0198] The controller 810 provided in the embodiment of the present application is used to implement the functions of the corresponding steps of the aforementioned storage system operation method. Since each step has been described in detail in the aforementioned storage system operation method embodiment, it will not be repeated here.

[0199] An embodiment of the present application also provides a storage system, please refer to Figure 17, the storage system 900 includes a controller 910 and a memory 920 coupled to the controller 910, the controller 910 is configured to: in response to receiving a first command including a first logical address of first data to be operated, determine at least one area corresponding to the first logical address, the at least one area corresponds to a first storage space of the memory 920; obtain at least one first physical page address corresponding to the at least one area according to the first mapping relationship and the determined at least one area; and send a third command to the memory 920 according to the at least one first physical page address; the memory 920 is configured to: in response to the third command, perform an operation on the first data in the first storage space; wherein the storage capacity of an area is smaller than the storage capacity corresponding to the physical block of the memory 920, and the first storage space is a storage space that only supports sequential reading and sequential writing.

[0200] In a possible implementation, the controller 910 is specifically configured to determine at least one first physical page address in a pointer mode based on the first mapping relationship and at least one region.

[0201] In a possible implementation, the first command is used to instruct writing of the first data, and the first command also includes the first data. The memory 920 is specifically configured to: write the first data to at least one physical address in the first storage space in response to the third command.

[0202] In one possible implementation, the controller 910 is further configured to: before acquiring at least one first physical page address corresponding to the at least one region, establish a first mapping relationship between the at least one region and multiple physical page addresses, where the multiple physical page addresses include the at least one first physical page address; and send a first write command to the memory 920. The memory 920 is further configured to: in response to the first write command, write the first mapping relationship between the at least one region and the multiple physical page addresses.

[0203] In a possible implementation, the first command is used to instruct to read the first data. The memory 920 is specifically configured to: in response to the third command, read the first data from at least one first physical page address in the first storage space, and send the first data to the controller.

[0204] In a possible implementation, the controller 910 includes a buffer storing a first mapping relationship.

[0205] In a possible implementation, the first mapping relationship is a secondary mapping relationship.

[0206] In one possible implementation, the controller 910 is further configured to: in response to receiving a second command including a second logical address of second data to be operated on, obtain, according to a second mapping relationship, a second physical page address corresponding to the second logical address, where the second logical address corresponds to a second storage space of the memory 920; and send, according to the second physical page address, a fourth command to the memory 920. In response to the fourth command, the memory 920 is configured to perform an operation on the second data in the second storage space; wherein the second storage space is a storage space capable of supporting random reads or random writes.

[0207] In a possible implementation, the second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

[0208] In one possible implementation, the second command is used to instruct the writing of second data. The controller 910 is further configured to: before obtaining the second physical page address corresponding to the second logical address, establish a second mapping relationship corresponding to the second logical address; and send a second write command to the memory 920. The memory 920 is specifically configured to: in response to the fourth command, write the second data to the second physical page address in the second storage space. The memory 920 is further configured to: in response to the second write command, write the second mapping relationship corresponding to the second logical address.

[0209] In one possible implementation, the second command is used to instruct the reading of second data. The controller 910 is further configured to, in response to the second command, send a read command to the memory 920 before obtaining the second physical page address corresponding to the second logical address according to the second mapping relationship. The memory 920 is further configured to, in response to the read command, read the second mapping relationship corresponding to the second logical address and send the second mapping relationship to the controller. The memory 920 is specifically configured to, in response to the fourth command, read the second data from the second physical address in the second storage space and send the second data to the controller 910.

[0210] In a possible implementation, the second mapping relationship is a three-level mapping relationship.

[0211] In one possible implementation, the controller 910 is further configured to perform a first garbage collection operation on physical blocks other than the blank physical blocks in the second storage space. In one possible implementation, the first garbage collection operation is performed when it is detected that the number of blank physical blocks is less than a first preset value.

[0212] In one possible implementation, the controller 910 is further configured to perform a second garbage collection operation on areas other than the blank areas in the first storage space. In one possible implementation, the second garbage collection operation is performed when it is detected that the number of blank areas is less than a second preset value.

[0213] In a possible implementation, the storage capacity of a region is (1 / n) times the storage capacity corresponding to the physical block of the memory 920 , where 1<n≤256.

[0214] The storage system 900 provided in the embodiment of the present application is used to implement the functions of the corresponding steps of the aforementioned storage system operation method. Since each step has been described in detail in the aforementioned storage system operation method embodiment, it will not be repeated here.

[0215] The present application also provides an electronic device. Referring to FIG. 18 , the electronic device 1000 includes a host 1100 and a storage system 1200. The host 1100 is coupled to the storage system 1200, which may be the storage system in the aforementioned storage system embodiment. The electronic device 1000 provided in the present application is configured to implement the functions of each step of the corresponding storage system operating method. Since each step has been described in detail in the aforementioned storage system operating method embodiment, a detailed description thereof will not be repeated here.

[0216] An embodiment of the present application also provides a computer-readable storage medium, which stores program code. When the computer-readable storage medium is run on a device (for example, the device can be a single-chip microcomputer, chip, computer or processor, etc.), the program code therein can be called by the processor to execute one or more steps in the above method embodiment.

[0217] Based on this understanding, the embodiments of the present application also provide a computer program product containing instructions. The technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the method described in each embodiment of the present application.

[0218] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for operating a storage system, characterized in that: The method comprises: In response to receiving a first command including a first logical address of first data to be operated, determining at least one area corresponding to the first logical address, the at least one area corresponding to a first storage space of a memory of the storage system; According to the first mapping relationship and the determined at least one region, acquiring at least one first physical page address corresponding to the at least one region; and performing the operation on the first data in the first storage space according to the at least one first physical page address; The storage capacity of one of the areas is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

2. The method according to claim 1, characterized in that The acquiring, according to the first mapping relationship and the determined at least one region, at least one first physical page address corresponding to the at least one region comprises: Based on the first mapping relationship and the at least one region, the at least one first physical page address is determined in a pointer mode.

3. The method according to claim 1 or 2, characterized in that: The first command is used to instruct writing of the first data, and the first command also includes the first data; The performing the operation on the first data in the first storage space according to the at least one first physical page address includes: The first data is written at the at least one physical address in the first storage space.

4. The method according to claim 3, characterized in that Before acquiring at least one first physical page address corresponding to the at least one region according to the first mapping relationship and the determined at least one region, the method further includes: Establishing the first mapping relationship between the at least one region and a plurality of physical page addresses, wherein the plurality of physical page addresses include the at least one first physical page address; The method further comprises: The first mapping relationship between the at least one area and the plurality of physical page addresses is written into the memory.

5. The method according to claim 1 or 2, characterized in that: The first command is used to instruct to read the first data; The performing the operation on the first data in the first storage space according to the at least one first physical page address includes: The first data is read from the at least one first physical page address in the first storage space.

6. The method according to any one of claims 1 to 5, characterized in that: The controller of the storage system includes a buffer, and the first mapping relationship is stored in the buffer.

7. The method according to any one of claims 1 to 6, characterized in that: The first mapping relationship is a secondary mapping relationship.

8. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: In response to receiving a second command including a second logical address of second data to be operated, according to the second mapping Relationship to obtain a second physical page address corresponding to the second logical address, where the second logical address corresponds to a second storage space of the memory; performing the operation on the second data in the second storage space according to the second physical page address; The second storage space is a storage space that can support random reading or random writing.

9. The method according to claim 8, characterized in that The second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

10. The method according to claim 8 or 9, characterized in that: The second command is used to instruct writing of the second data; Before acquiring the second physical page address corresponding to the second logical address according to the second mapping relationship and the second logical address, the method further includes: Establishing the second mapping relationship corresponding to the second logical address; The performing the operation on the second data in the second storage space according to the second physical page address includes: Writing the second data at the second physical page address in the second storage space; The method further comprises: The second mapping relationship corresponding to the second logical address is written into the memory.

11. The method according to claim 8 or 9, characterized in that: The second command is used to instruct to read the second data; Before acquiring the second physical page address corresponding to the second logical address according to the second mapping relationship, the method further includes: In response to the second command, reading the second mapping relationship corresponding to the second logical address from the memory; The performing the operation on the second data in the second storage space according to the second physical page address includes: The second data is read from the second physical address in the second storage space.

12. The method according to any one of claims 8 to 11, characterized in that The second mapping relationship is a three-level mapping relationship.

13. The method according to any one of claims 8 to 12, characterized in that: The method further comprises: A first garbage collection operation is performed on other physical blocks in the second storage space except the blank physical blocks.

14. The method according to claim 13, characterized in that The first garbage collection operation is performed when it is detected that the number of the blank physical blocks is less than a first preset value.

15. The method according to any one of claims 1 to 14, characterized in that The method further comprises: A second garbage collection operation is performed on other areas in the first storage space except the blank area.

16. The method according to claim 15, characterized in that The second garbage collection operation is performed when it is detected that the number of the blank areas is less than a second preset value.

17. The method according to any one of claims 1 to 16, characterized in that: The storage capacity of one of the areas is (1 / n) times the storage capacity corresponding to the physical block of the memory of the storage system, where 1<n≤256.

18. A controller, characterized in that: The controller includes a processor and an interface circuit coupled to the processor, wherein the interface circuit is coupled to a memory, and the processor is configured to: In response to receiving a first command including a first logical address of first data to be operated, determining at least one area corresponding to the first logical address, the at least one area corresponding to a first storage space of the memory; According to the first mapping relationship and the determined at least one region, acquiring at least one first physical page address corresponding to the at least one region; as well as sending the third command to the memory through the interface circuit according to the at least one first physical page address to perform the operation on the first data; The storage capacity of one of the areas is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

19. A storage system, characterized in that: The storage system includes a controller and a memory coupled to the controller, wherein the controller is configured to: in response to receiving a first command including a first logical address of first data to be operated, determine at least one area corresponding to the first logical address, wherein the at least one area corresponds to a first storage space of the memory; According to the first mapping relationship and the determined at least one region, acquiring at least one first physical page address corresponding to the at least one region; as well as sending a third command to the memory according to the at least one first physical page address; The memory is configured to: in response to the third command, perform the operation on the first data in the first storage space; The storage capacity of one of the areas is smaller than the storage capacity corresponding to the physical block of the memory, and the first storage space is a storage space that only supports sequential reading and sequential writing.

20. The storage system according to claim 19, characterized in that: The controller is specifically configured as follows: Based on the first mapping relationship and the at least one region, the at least one first physical page address is determined in a pointer mode.

21. The storage system according to claim 19 or 20, characterized in that: The first command is used to instruct writing of the first data, and the first command also includes the first data; The memory is specifically configured to: write the first data at the at least one physical address in the first storage space in response to the third command.

22. The storage system according to claim 21, characterized in that: The controller is further configured to: before acquiring at least one first physical page address corresponding to the at least one region, establish the first mapping relationship between the at least one region and a plurality of physical page addresses, the plurality of physical page addresses including the at least one first physical page address; Sending a first write command to the memory; The memory is further configured to: write the first mapping relationship between the at least one area and the plurality of physical page addresses in response to the first write command.

23. The storage system according to claim 19 or 20, characterized in that: The first command is used to instruct to read the first data; The memory is specifically configured to: in response to the third command, read the first data from the at least one first physical page address in the first storage space, and send the first data to the controller.

24. The storage system according to any one of claims 19 to 23, characterized in that: The controller includes a buffer, and the first mapping relationship is stored in the buffer.

25. The storage system according to any one of claims 19 to 24, characterized in that: The first mapping relationship is a secondary mapping relationship.

26. The storage system according to any one of claims 19 to 25, characterized in that: The controller is further configured to: in response to a received second command including a second logical address of second data to be operated, acquire a second physical page address corresponding to the second logical address according to a second mapping relationship, wherein the second logical address corresponds to a second storage space of the memory; sending a fourth command to the memory according to the second physical page address; The memory is configured to: in response to the fourth command, perform the operation on the second data in the second storage space; The second storage space is a storage space that can support random reading or random writing.

27. The storage system according to claim 26, characterized in that: The second mapping relationship is a mapping relationship including the second logical address, a physical block address corresponding to the second logical address, and a second physical page address corresponding to the physical block address.

28. The storage system according to claim 26 or 27, characterized in that: The second command is used to instruct writing of the second data; The controller is further configured to: before acquiring the second physical page address corresponding to the second logical address, establish the second mapping relationship corresponding to the second logical address; Sending a second write command to the memory; The memory is specifically configured to: write the second data at the second physical page address in the second storage space in response to the fourth command; The memory is further configured to: write the second mapping relationship corresponding to the second logical address in response to the second write command.

29. The storage system according to claim 26 or 27, characterized in that: The second command is used to instruct to read the second data; The controller is further configured to: before acquiring the second physical page address corresponding to the second logical address according to the second mapping relationship, in response to the second command, send a read command to the memory; The memory is further configured to: in response to the read command, read the second mapping relationship corresponding to the second logical address, and send the second mapping relationship to the controller; The memory is specifically configured to: in response to the fourth command, read the second data from the second physical address in the second storage space, and send the second data to the controller.

30. The storage system according to any one of claims 26 to 29, characterized in that: The second mapping relationship is a three-level mapping relationship.

31. The storage system according to any one of claims 26 to 30, characterized in that: The controller is also configured to: A first garbage collection operation is performed on other physical blocks in the second storage space except the blank physical blocks.

32. The storage system according to claim 31, characterized in that: The first garbage collection operation is performed when it is detected that the number of the blank physical blocks is less than a first preset value.

33. The storage system according to any one of claims 19 to 32, characterized in that: The controller is also configured to: A second garbage collection operation is performed on other areas in the first storage space except the blank area.

34. The storage system according to claim 33, characterized in that: The second garbage collection operation is performed when it is detected that the number of the blank areas is less than a second preset value.

35. The storage system according to any one of claims 19 to 34, characterized in that: The storage capacity of one of the regions is (1 / n) times the storage capacity corresponding to the physical block of the memory, 1<n≤256.

36. An electronic device, characterized in that: The electronic device comprises a host and a storage system as claimed in any one of claims 19 to 35.

37. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores program code, which can be called by a processor to execute the method described in any one of claims 1 to 17.

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