Fault detection method and apparatus and intelligent driving device

Abstract

A fault detection method and apparatus and an intelligent driving device. The method comprises: acquiring information of a first test mode, the first test mode being a test mode to be run, and the first test mode being used for detecting a fault in an integrated circuit; and on the basis of the first test mode, adjusting, to a target frequency, the running frequency of a processor used for running the first test mode, such that when the processor runs the first test mode at the target frequency, the speed of running the first test mode can be increased, or the power consumption required for running the first test mode can be reduced. The technical solution of the present application can be used in an intelligent driving device, such that the running frequency of a processor can be adjusted on the basis of an STL test mode, thereby achieving a balance between fault detection speed and required power consumption.

Description

Fault detection method, device and intelligent driving equipment Technical Field

[0001] The present application relates to the field of computer technology, and more specifically, to a fault detection method, apparatus, and intelligent driving device. Background Art

[0002] In the computer field, fault detection devices may detect random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts. In certain applications with high safety requirements, such as intelligent driving, to ensure functional safety, processors can be equipped with fault detection mechanisms to detect hardware failures and ensure safe operation in the event of a hardware failure.

[0003] However, the operation of real-time services may affect the speed and power consumption of fault detection. Therefore, how to achieve a balance between detection speed and power consumption during fault detection has become an urgent problem to be solved.

[0004] Summary of the Invention

[0005] The present application provides a fault detection method, apparatus, and intelligent driving device, which can adjust the operating frequency of the processor according to the STL test mode, and can achieve a balance between the fault detection speed and the required power consumption.

[0006] In a first aspect, a fault detection method is provided. The method can be executed by an intelligent driving device, such as a computing platform in the intelligent driving device, or a chip or processor in the intelligent driving device. The intelligent driving device can be a vehicle.

[0007] The method includes: obtaining information of a first test mode, where the first test mode is a test mode to be run and is used to detect faults of a first integrated circuit; and adjusting the operating frequency of a first processor to a first target frequency according to the first test mode, where the first processor is used to run the first test mode.

[0008] In the above technical solution, when the fault detection process is running, the operating frequency of the processor can be adjusted according to the test mode to be run. In this way, when the operating frequency of the processor used by the process running before the first test mode is run is too high, the operating frequency of the processor can be reduced to save power consumption; when the operating frequency of the processor used by the process running before the first test mode is run is too low, the operating frequency of the processor can be increased to speed up the running speed of the first test mode. When multiple test modes need to be run for the target task, and the operating frequencies of the processors required for the multiple test modes are different, for example, the multiple test modes include at least one computationally intensive test mode and at least one memory-intensive test mode, based on the above technical solution, the running speed of the computationally intensive test mode can be increased, and the power consumption required for the memory-intensive test mode to run can be reduced without reducing the running speed of the memory-intensive test mode, thereby achieving a balance between the fault detection speed and the required power consumption.

[0009] In combination with the first aspect, in certain implementations of the first aspect, the first target frequency is determined according to a type of the first test mode, and the type of the first test mode includes computation-intensive or memory-intensive.

[0010] In the above technical solution, the first target frequency can be determined according to the type of the first test mode, which can save the power consumption required to monitor the operation of the first test mode and the computing power required to modify or update the first target frequency according to the operation of the first test mode.

[0011] In combination with the first aspect, in some implementations of the first aspect, the first target frequency is determined according to the operating frequency of the first processor when the first test mode was last run and the running duration of the first test mode.

[0012] In the above technical solution, the first target frequency can be modified or updated according to the operation status of the first test mode, so that when the first processor runs the first test mode at the first target frequency, a better speed-up effect or power saving effect can be achieved.

[0013] In combination with the first aspect, in certain implementations of the first aspect, the first test mode is associated with the first virtual machine, and the method further includes: after adjusting the operating frequency of the first processor to the first target frequency, updating the frequency information of the virtual machine manager, the frequency information indicating the current operating frequency of the first processor, and the virtual machine manager is used to manage one or more virtual machines including the first virtual machine.

[0014] In the above technical solution, after adjusting the operating frequency of the first processor, the frequency information of the virtual machine manager is updated, which can avoid the virtual machine's modification of the processor frequency from being unable to be synchronized to the virtual machine manager, and helps to improve the robustness of the fault detection system.

[0015] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: obtaining frequency tuning information, the frequency tuning information indicating a target frequency of a processor corresponding to each test mode in running one or more test modes, the one or more test modes including a first test mode; determining a first target frequency based on the first test mode and the frequency tuning information.

[0016] In combination with the first aspect, in some implementations of the first aspect, the method further includes: running a first test mode when adjusting the operating frequency of the first processor.

[0017] In the above technical solution, adjusting the processor operating frequency while running the test mode helps to reduce the impact of the time required for frequency conversion on the fault detection speed, helps to further improve the fault detection speed, and thus reduces the impact of the fault detection process on the real-time performance of business layer tasks.

[0018] In combination with the first aspect, in some implementations of the first aspect, the method further includes: before adjusting the operating frequency of the first processor to the first target frequency, performing a first context switch, the first context switch being used for running the first test mode.

[0019] In the above technical solution, frequency conversion and context switching are performed simultaneously, which helps to reduce the time required for the frequency adjustment process and helps to further improve the fault detection speed.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the method further includes: after the first test mode is completed and before adjusting the operating frequency of the first processor to the second target frequency, executing a second context switch, the second context switch is used for the operation of the first process, and the second target frequency is the target frequency of the first processor corresponding to the operation of the first process.

[0021] In combination with the first aspect, in certain implementations of the first aspect, when the first test mode is associated with the trusted execution environment TEE, before executing the first context switch, the method further includes: executing a switch from the open execution environment REE to the TEE.

[0022] In the above technical solution, in a scenario where world switching is required, world switching (and context switching) is performed simultaneously with frequency conversion, which helps to reduce the time required for the frequency adjustment process and helps to further improve the fault detection speed.

[0023] In a second aspect, a fault detection device is provided, which includes: an acquisition unit for acquiring information of a first test mode, the first test mode is a test mode to be run, and the first test mode is used to detect a fault of a first integrated circuit; a first processing unit for adjusting the operating frequency of the first processor to a first target frequency according to the first test mode, and the first processor is used to run the first test mode.

[0024] In combination with the second aspect, in certain implementations of the second aspect, the first target frequency is determined according to a type of the first test mode, and the type of the first test mode includes computationally intensive or memory intensive.

[0025] In combination with the second aspect, in some implementations of the second aspect, the first target frequency is determined according to the operating frequency of the first processor when the first test mode was last run and the running duration of the first test mode.

[0026] In combination with the second aspect, in certain implementations of the second aspect, the first test mode is associated with the first virtual machine, and the device also includes a second processing unit, which is used to: after adjusting the operating frequency of the first processor to the first target frequency, update the frequency information of the virtual machine manager, the frequency information indicates the current operating frequency of the first processor, and the virtual machine manager is used to manage one or more virtual machines including the first virtual machine.

[0027] In combination with the second aspect, in certain implementations of the second aspect, the acquisition unit is further used to: obtain frequency tuning information, the frequency tuning information indicates the target frequency of the processor corresponding to each test mode in running one or more test modes, the one or more test modes including a first test mode; the first processing unit is used to: determine the first target frequency based on the first test mode and the frequency tuning information.

[0028] In combination with the second aspect, in some implementations of the second aspect, the first processing unit is further configured to: run the first test mode when adjusting the operating frequency of the first processor.

[0029] In combination with the second aspect, in some implementations of the second aspect, the first processing unit is further used to: before adjusting the operating frequency of the first processor to the first target frequency, perform a first context switch, and the first context switch is used for running the first test mode.

[0030] In combination with the second aspect, in certain implementations of the second aspect, the first processing unit is further used to: after the first test mode is completed and before adjusting the operating frequency of the first processor to the second target frequency, execute a second context switch, the second context switch is used for the operation of the first process, and the second target frequency is the target frequency of the first processor corresponding to the operation of the first process.

[0031] In combination with the second aspect, in certain implementations of the second aspect, when the first test mode is associated with the trusted execution environment TEE, before executing the first context switch, the device also includes a third processing unit for: executing the switch from the open execution environment REE to TEE.

[0032] In a third aspect, a fault detection device is provided, which includes: a memory for storing a computer program; and a processor for executing the computer program stored in the memory, so that the device performs the method in any possible implementation of the first aspect.

[0033] In a fourth aspect, a computing platform is provided, which includes a device as in any possible implementation of the second aspect or the third aspect.

[0034] In a fifth aspect, an intelligent driving device is provided, which includes an apparatus as in any possible implementation of the second aspect or the third aspect; or, the intelligent driving device includes an apparatus as in any possible implementation of the fourth aspect.

[0035] In combination with the fifth aspect, in some implementations of the fifth aspect, the intelligent driving device is a vehicle.

[0036] In a sixth aspect, a computer program product is provided, comprising: a computer program code, which, when executed on a computer, enables the computer to execute the method in any one of the possible implementations of the first aspect.

[0037] It should be noted that the above-mentioned computer program code may be stored in whole or in part on a first storage medium, wherein the first storage medium may be packaged together with the processor or separately from the processor.

[0038] In a seventh aspect, a computer-readable medium is provided, wherein the computer-readable medium stores instructions. When the instructions are executed by a processor, the processor implements the method in any possible implementation of the first aspect.

[0039] In an eighth aspect, a chip is provided, which includes a circuit for executing the method in any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of the relationship between the operation of the fault detection process and the operation of the business layer task;

[0041] FIG2 is a schematic block diagram of a fault detection system provided in an embodiment of the present application;

[0042] FIG3 is a schematic flow chart of a fault detection method provided in an embodiment of the present application;

[0043] FIG4 is another schematic block diagram of a fault detection method provided in an embodiment of the present application;

[0044] FIG5 is another schematic flow chart of the fault detection method provided in an embodiment of the present application;

[0045] FIG6 is a schematic diagram of an application scenario of a fault detection method provided in an embodiment of the present application;

[0046] FIG7 is a schematic diagram of another application scenario of the fault detection method provided in an embodiment of the present application;

[0047] FIG8 is a schematic block diagram of a fault detection device provided in an embodiment of the present application;

[0048] FIG9 is another schematic block diagram of a fault detection device provided in an embodiment of the present application;

[0049] FIG10 is a functional schematic diagram of an intelligent driving device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0050] To facilitate understanding of the solutions of the embodiments of the present application, the following concepts are first introduced:

[0051] 1. Autonomous driving operating system (hereinafter referred to as autonomous driving system): For example, an operating system based on the portable operating system interface (POSIX) standard, suitable for the high-performance computing and high-bandwidth communication required for autonomous driving, and providing environmental perception, sensor fusion, and path planning functions for intelligent driving equipment.

[0052] 2. Autonomous driving services (hereinafter referred to as services): In an autonomous driving system, a service is typically a collection of processes and / or threads with specific autonomous driving functions, encapsulated using communication middleware. This communication middleware can include the Robot Operating System (ROS) or the Automotive Open System Architecture Communication Management (AUTOSAR CM). Autonomous driving functions can include environmental perception, sensor fusion, and path planning capabilities of intelligent driving devices.

[0053] 3. Process: A process is a computer program's execution of a data set. It is the basic unit for resource allocation and scheduling in the system and forms the foundation of the operating system architecture. In early process-oriented computer architectures, processes were the basic execution entity of programs; in modern thread-oriented computer architectures, processes are containers for threads. A program is a description of instructions, data, and their organization; a process is the entity that contains the program. Processes are identified by process identifiers.

[0054] 4. Thread: A thread is the smallest unit of computation that an operating system can schedule. A thread is contained within a process and is the actual unit of operation within that process. A thread is a single, sequential flow of control within a process. A process can have multiple threads running concurrently, each executing different tasks in parallel. Threads can be identified by their thread numbers.

[0055] 5. Task: A task is an abstract concept of a thread's time slice. Tasks correspond one-to-one with thread's time slices, that is, one time slice of a thread is a task.

[0056] In summary, one or more threads can constitute a process; and one or more time segments of a process (ie, one or more tasks) can constitute a service.

[0057] 6. Central processing unit (CPU)-intensive tasks: Also known as compute-intensive tasks, this strategy allows the system to execute tasks on a computer in a very short time, with virtually no blocking time (i.e., waiting for memory reads and writes). However, because these tasks require extensive CPU computation and consume CPU resources, the CPU load can be chronically high.

[0058] 7. Memory-intensive tasks: Also known as input / output (I / O)-intensive tasks, this is another strategy for executing tasks on a computer. The system consumes very little CPU when running tasks, and most of the time during the task execution is spent waiting for memory read and write operations to complete.

[0059] 8. Functional safety: refers to the absence of unacceptable risks caused by electronic system failures. Its ultimate goal is to prevent casualties or huge property losses caused by electronic system (hereinafter referred to as system) failures.

[0060] 9. Software-based built-in self-test (SBIST): A software-based online error detection technology that uses a test pattern in a specific software test library (STL) to detect functional logic failures other than memory. When running the test pattern in the STL, the register corresponding to the test pattern can be tested. The test pattern can be a string of binary codes including logic 1 and logic 0, and logic 1 and logic 0 represent the high level and low level of drive applied to the circuit, respectively. The essence of using the test pattern for testing is to input the binary code into the circuit to be tested, and then detect whether the output signal at the output end of the circuit is consistent with the expected graphic data. If it is consistent, it is determined that the circuit function is normal. If it is not consistent, it is determined that an error has occurred in the circuit.

[0061] 10. Dynamic voltage and frequency scaling (DVFS): A technology that balances performance and power consumption by dynamically adjusting processor voltage and frequency. The principle is to dynamically adjust the processor voltage and frequency based on the processor load to meet the processor's performance and power requirements. When the processor load is low, the processor frequency and voltage are reduced to save power; when the processor load is high, the processor frequency and voltage are increased to provide better performance.

[0062] 11. Context Switch: The kernel switches processes or threads on the CPU. This involves saving the current state of the running task—that is, the contents of the CPU registers and program counter—and then loading the new task into the CPU registers and program counter, starting execution. The context refers to the state of the task in the CPU.

[0063] As mentioned above, in the computer field, fault detection devices may encounter random hardware failures, such as permanent failures caused by short circuits or open circuits in integrated circuits, or temporary failures such as bit flips caused by exposure to natural radiation or particle impacts. Therefore, to ensure the safety of computer systems, it is necessary to detect and handle these failures in a timely manner.

[0064] Under the current technical background, the STL-based SBIST technology is usually adopted. When a business layer task is running, the STL test mode corresponding to the business layer task can be run to detect whether the integrated circuit used to execute the business layer task has a fault. Generally speaking, the running priority of the fault detection process is higher than the running priority of the business layer task process. Therefore, the fault detection process such as the STL test mode will block the business layer task process, as shown in Figure 1, resulting in an increase in the time required to complete the business layer task process. In other words, the operation of the STL test mode will cause the running time of the business layer task to increase. In some application fields with higher safety requirements, such as the field of autonomous driving, the operation of the STL test mode may affect the real-time performance of autonomous driving related tasks, and thus affect driving safety.

[0065] In addition, the business layer task process may also affect the running time of the fault detection process. In existing computer systems, dynamic adjustment of the processor frequency can be achieved through DVFS technology. However, DVFS technology can only sense the processor operating frequency corresponding to the business layer task, and it cannot sense or adjust the processor operating frequency corresponding to the STL test mode. In other words, DVFS technology can only adjust the processor frequency for business layer tasks. After adjusting the processor operating frequency according to the business layer task, when running the STL test mode associated with the business layer task, the processor will run the STL test mode based on the operating frequency adjusted according to the business layer task. Among them, the STL test mode associated with the business layer task means: the STL test mode is used to perform fault detection on the integrated circuit that executes the business layer task.

[0066] In the above scenario, if the business-layer task is memory-intensive, the processor will select a lower operating frequency to reduce power consumption when running the business-layer task. If the STL test mode associated with the business-layer task is compute-intensive, since DVFS technology cannot adjust the processor operating frequency for the STL test mode, the processor will still run the STL test mode at a lower operating frequency, causing the STL test mode to take a longer time to run, thereby affecting the real-time performance of the business-layer task. If the business-layer task is compute-intensive, the processor will select a higher operating frequency to speed up processing when running the business-layer task. If the STL test mode associated with the business-layer task is memory-intensive, since DVFS technology cannot adjust the processor operating frequency for the STL test mode, the processor will still run the STL test mode at a higher operating frequency. However, based on the characteristics of memory-intensiveness, this higher operating frequency will not speed up the running speed of the STL test mode associated with the business-layer task, but will instead consume unnecessary power.

[0067] In view of this, the present application provides a fault detection method, apparatus, and intelligent driving device that can adjust the processor's operating frequency according to the STL test mode, achieving a balance between fault detection speed and required power consumption. During frequency adjustment, clock frequency switching and context switching are performed simultaneously, which helps to reduce the time required to run the STL test mode, thereby improving the real-time performance of business layer tasks.

[0068] The technical solution in this application will be described below with reference to the accompanying drawings.

[0069] FIG2 shows a schematic block diagram of a fault detection system provided in an embodiment of the present application.

[0070] As shown in FIG. 2 ( a ), the fault detection system includes a service layer 210 , a kernel 220 , a monitor 240 , and a hardware layer 250 .

[0071] The business layer 210 may include one or more tasks, such as one or more of task 211, task 212, and task 21n. These one or more tasks may constitute one or more services. If the fault detection system is installed in an autonomous vehicle, the one or more services may be autonomous driving-related services, such as obstacle perception, target recognition, intelligent driving device positioning, path planning, driver monitoring / reminders, and other services. In some implementations, a service may be an application.

[0072] The kernel 220 comprises the operating system's portion responsible for managing memory, files, peripherals, and system resources. Kernel 220 interacts with hardware in the hardware layer and runs processes based on tasks in the service layer 210, providing inter-process communication, CPU time slice management, interrupt, memory management, and I / O management. Kernel 220 includes a simplified DVFS module 221 and an STL scheduling module 222. The simplified DVFS module 221 performs preparatory work for frequency conversion, including enabling DVFS and all preceding tasks. For example, the simplified DVFS module 221 configures a target frequency for the target processor based on the STL test mode to be run and enables DVFS. After the simplified DVFS module 221 enables DVFS, a frequency manager (e.g., a cpufreq governor) adjusts the frequency of the target processor in the hardware layer 250 to the target frequency. The STL scheduling module 222, which can be located within the kernel scheduler, can call the simplified DVFS module 221 to adjust the frequency of the target processor and control the execution of the STL test mode to be run. The target processor is used to run the STL test mode to be run.

[0073] In the specific implementation process, the STL scheduling module 222 can determine the target frequency based on the STL test mode to be run and the STL frequency tuning information. The STL scheduling module 222 calls the DVFS simplified module 221 to enable the DVFS simplified module 221 to perform preparatory work for adjusting the target processor frequency to the target frequency, for example, configuring the target frequency, configuring the frequency adjustment step, and enabling DVFS. Exemplarily, the STL frequency tuning information records the recommended operating frequency corresponding to one or more STL test modes. The recommended operating frequency refers to the processor operating frequency that can improve the operating efficiency of the STL test mode and / or can reduce the power consumption required for the STL test mode to run. The STL scheduling module 222 can determine that the recommended operating frequency of the test mode to be run is the target frequency. Exemplarily, the STL frequency tuning information can be in the form of a file, or in the form of a table, or in other forms.

[0074] In one example, when or after the DVFS simplified configuration module 221 enables DVFS, the STL scheduling module 222 performs a context switch to control the execution of the pending STL test mode. In another example, when the STL scheduling module 222 calls the DVFS simplified configuration module 221 to perform frequency adjustment, when or after the DVFS simplified configuration module 221 enables DVFS, the context switch automatically executes to control the execution of the pending STL test mode. In yet another example, when the STL scheduling module 222 performs a context switch to control the execution of the pending STL test mode, it calls the DVFS simplified configuration module 221 to adjust the frequency of the target processor to the target frequency.

[0075] The monitor 240 is used to manage threads and monitor and record running processes. The monitor 240 includes a DVFS monitoring module 241 and an STL test mode module 242. The STL test mode module 242 includes one or more STL test modes, and the one or more STL test modes include a running STL test mode. Exemplarily, one or more STL test modes can be used to detect whether an integrated circuit has failed, or one or more STL test modes can also be used to detect whether multiple integrated circuits have failed. The DVFS monitoring module 241 monitors the current operating status, obtains the current operating frequency of the processor and the running time of the running STL test mode, and updates the STL frequency tuning information offline based on the current operating frequency and running time.

[0076] In some implementations, the STL test mode module 242 may include one or more schedules, each of which is associated with a business-layer task and includes one or more test patterns. The fact that each schedule is associated with a business-layer task can be understood as meaning that the test patterns in the schedule are used to detect whether the integrated circuit executing the business-layer task has failed. The schedules may be generated based on the business-layer task or pre-set in the system.

[0077] The hardware layer 250 provides the foundational hardware platform for the core 220. The hardware layer 250 may include a processor, memory, network interface card (NIC), and storage. The processor, including the aforementioned target processor, provides computing power for the core 220; the memory provides memory resources for the core 220; the NIC provides network communication resources for the core 220; and the storage provides general storage resources for the core 220. If the fault detection system is deployed in an autonomous vehicle, the hardware layer 250 may also include sensors, which provide sensory data resources for the core 220.

[0078] In some scenarios where virtualization is required, for example, when different types of operating systems need to run on the same computing platform, the fault detection system may further include a virtual machine manager 230, as specifically shown in (b) of FIG2 .

[0079] The virtual machine manager 230 is used to create or run virtual machines, providing heterogeneous operating systems with access to hardware resources on the same hardware platform. A virtual machine is a virtualized instance of a computer that can perform almost identical functions, including running applications and operating systems. A virtual machine runs on a physical machine and accesses computing resources through the virtual machine manager 230. The virtual machine manager 230 abstracts the physical machine's resources into an on-demand, provisionable, and distributable resource pool, enabling multiple virtual machines to run on a single physical machine.

[0080] Exemplarily, each virtual machine may include a virtual kernel, each of which includes a DVFS simplified module and an STL scheduling module. For example, the virtual kernels may include kernel 220-1 and kernel 220-n (where n is an integer greater than or equal to 2) shown in FIG2(b). The functions of the DVFS simplified module and the STL scheduling module in the virtual kernel can be found in the descriptions of the DVFS simplified module 221 and the STL scheduling module 222, respectively, and are not further described here.

[0081] The virtual machine manager 230 includes a DVFS management module 231. The DVFS management module 231 is used to update the processor frequency of a virtual machine to the current operating frequency of the processor in the DVFS configuration file after the virtual machine adjusts the processor frequency, so as to prevent the virtual machine's processor frequency modification from not being synchronized to the virtual machine manager 230.

[0082] In some implementations, the DVFS management module 231 may also perform arbitration processing. Exemplarily, in a virtualization scenario, the DVFS simplified module in the virtual machine (for example, before enabling DVFS) may generate a frequency adjustment request based on the target frequency, and the frequency adjustment request is used to request that the frequency of the target processor be adjusted to the target frequency. Two or more virtual machines may request that the same processor be adjusted to different frequencies. When the frequency adjustment requests of two or more virtual machines conflict, the DVFS management module 231 may perform arbitration processing, for example, responding to a frequency adjustment request with a higher priority based on the priority of the frequency adjustment request. Exemplarily, when the frequency adjustment request is generated based on the STL test mode to be run, the priority of the frequency adjustment request may be determined based on the priority of the STL test mode, or the priority of the frequency adjustment request may be determined based on the priority of the business layer task corresponding to the STL test mode.

[0083] In some implementations, the DVFS management module 231 may also determine whether to perform frequency adjustment based on a frequency adjustment request. For example, upon receiving a frequency adjustment request from a virtual machine, the DVFS management module 231 may determine whether to perform frequency adjustment based on the target frequency of the target processor requested in the frequency adjustment request and the target processor frequency recorded in the DVFS configuration file. For example, if the target processor frequency recorded in the DVFS configuration file is the same as the target frequency, no frequency adjustment is required; otherwise, the frequency of the target processor is adjusted to the target frequency.

[0084] Exemplarily, the DVFS management module 231 controls the frequency of the target processor to be adjusted to the target frequency, which may include: the DVFS management module 231 sending an instruction to the frequency manager, the instruction instructing the frequency of the target processor to be adjusted to the target frequency; or the DVFS management module 231 sending a response to the DVFS simplified configuration module, the response instructing the frequency of the target processor to be adjusted to the target frequency, and further, the DVFS simplified configuration module enabling DVFS. It is understood that after the DVFS simplified configuration module enables DVFS, the frequency manager adjusts the frequency of the target processor to the target frequency.

[0085] In some implementation scenarios, hardware-based security features introduce two protection domains with different permissions at the processor level: the secure world and the normal world. The secure world can provide a trusted execution environment (TEE), while the normal world can provide a rich execution environment (REE). The processor can only operate in one of these environments at any given time. These two worlds are completely hardware-isolated and have different permissions. Applications or operating systems running in the normal world cannot access resources in the secure world, while programs running in the secure world can access resources in both the secure and normal worlds. Generally speaking, the STL test mode usually runs in the TEE, while DVFS-related modules such as the DVFS simplified module and the DVFS management module usually run in the REE. Therefore, the architectures shown in Figure 2 (a) and (b) can evolve into the architectures shown in Figure 2 (c) and (d), respectively. In a specific implementation, the secure monitor call (SMC) handler in monitor 240 can execute a world switch from the REE to the TEE based on the DVFS enable instruction from the DVFS profile module 221, and then perform a context switch to run the test mode to be executed. In this scenario, DVFS monitor module 241 can also be used to query whether the world switch was successful after executing the context switch.

[0086] It should be understood that the architecture shown in (a) to (d) in FIG2 is merely an exemplary illustration, and in a specific implementation process, the system shown in FIG2 may include more or fewer modules.

[0087] Based on the fault detection system shown in FIG2 , the present application proposes a fault detection method.

[0088] FIG3 shows a schematic flow chart of a fault detection method provided in an embodiment of the present application. This method 300 can be executed by the fault detection system shown in FIG2 , for example, by the STL scheduling module 222 shown in FIG2 , or by the STL scheduling module 222 and the DVFS simplified configuration module 221 shown in FIG2 , or by the STL scheduling module 222, the DVFS simplified configuration module 221, and the DVFS management module 231 shown in FIG2 . This method 300 includes S301 and S302 .

[0089] S301 , obtaining information of a first test mode, where the first test mode is a test mode to be run and is used to detect a fault of a first integrated circuit.

[0090] Exemplarily, the first integrated circuit is configured to execute a target task, which may be a task currently running or about to be run in the system. If the target task is a currently running task, the target task may be, for example, a process or thread currently running in the system. Exemplarily, if the system is configured for application in a vehicle and the target task is a process, the target task may be, for example, a vehicle video inspection process, a vehicle speed calculation process, a radar detection process, a vehicle anti-lock braking process, or a tire pressure monitoring process.

[0091] Exemplarily, the information of the first test mode may be used to determine that the first test mode is the test mode to be executed, and the information of the first test mode may include a scheduling table associated with the target task.

[0092] The schedule associated with the target task may include one or more test modes, and the first test mode may be one of the one or more test modes. When the target task is a task to be executed, the first test mode may be the first test mode to be executed.

[0093] S302 , adjusting the operating frequency of the first processor to a first target frequency according to the first test mode, where the first processor is configured to run the first test mode.

[0094] Exemplarily, the first processor may include the target processor in the above embodiment.

[0095] In some implementations, before executing S302, frequency tuning information is obtained, where the frequency tuning information indicates a target frequency of the processor corresponding to each of one or more test modes, where the one or more test modes include a first test mode. S302 can be further refined to include determining a first target frequency based on the first test mode and the frequency tuning information.

[0096] Exemplarily, the frequency tuning information may include the STL frequency tuning information in the above-mentioned embodiment, or the frequency tuning information may also be determined according to the type of the first test mode. The first target frequency may be the target frequency in the above-mentioned embodiment. The target frequency of the processor corresponding to a test mode may be understood as: the frequency of the processor used to run the test mode when running the test mode, which frequency may reduce the power consumption required to run the test mode and / or make the test mode run faster, and the frequency may include the recommended operating frequency in the above-mentioned embodiment.

[0097] In some implementations, the first target frequency is determined based on the operating frequency of the first processor and the duration of the first test mode's execution the last time the first test mode was executed. For example, the DVFS monitoring module 241 records the operating frequency of the first processor and the duration of the first test mode's execution the last time the first test mode was executed, and adjusts the frequency of the first processor's execution of the first test mode based on the duration of the first test mode and the type of the first test mode.

[0098] For example, the frequency tuning information may include n test modes and their corresponding recommended operating frequencies, as shown in Table 1, where n is an integer greater than or equal to 3. In some implementations, the frequency tuning information may also include information such as the type of test mode, the runtime of the test mode when it was last run, and the processor operating frequency when the test mode was last run. Furthermore, when the DVFS monitoring module 241 updates the frequency tuning information, it may only update the information in column 2, i.e., the recommended operating frequency corresponding to the test mode. Alternatively, if the frequency tuning information includes information related to the last run of the test mode, when the DVFS monitoring module 241 updates the STL frequency tuning information, it may update the information in columns 4 and 5 of Table 1. Specifically, if the compute-intensive test mode 1 last ran at a frequency of 1.2 gigahertz (GHz) and a runtime of 1 millisecond (ms), and if the runtime of test mode 1 can be reduced to 0.5 ms after reducing the processor operating frequency limit, the recommended operating frequency of test mode 1 may be updated to 2.5 GHz. The memory-intensive test mode 2 last ran at a frequency of 2.5 GHz and lasted for 1 ms. If the runtime of test mode 2 does not increase further after reducing the processor operating frequency, DVFS monitoring module 241 may update the recommended operating frequency of test mode 2 to 1.2 GHz. The compute-intensive test mode n last ran at a frequency of 2.5 GHz and lasted for 0.5 ms. If the runtime of test mode n does not decrease further after further increasing the processor operating frequency, DVFS monitoring module 241 may not modify the recommended operating frequency, i.e., determine that the recommended operating frequency of test mode n is 2.5 GHz.

[0099] Table 1

[0100] It should be understood that the format and related data in Table 1 are only exemplary. In a specific implementation, the frequency tuning information may be in other formats, and the recommended operating frequency of the test mode may be other values.

[0101] Exemplarily, the first test mode may be any one of test modes 1 to n in Table 1, and the first target frequency may be a frequency determined according to the recommended operating frequencies in Table 1.

[0102] In some implementations, the first target frequency is determined based on a type of the first test mode, where the type of the first test mode includes computationally intensive or memory intensive. For example, when the first test mode is computationally intensive, the first target frequency is determined to be a higher frequency; and when the first test mode is memory intensive, the first target frequency is determined to be a lower frequency.

[0103] In some implementations, the first test mode is associated with the first virtual machine. After executing S302, the method further includes: updating frequency information of the virtual machine manager, where the frequency information indicates the current operating frequency of the first processor, and the virtual machine manager is used to manage one or more virtual machines including the first virtual machine.

[0104] Exemplarily, associating the first test mode with the first virtual machine can be understood as: the first virtual machine adjusting the operating frequency of the first processor according to the first test mode request. The frequency information can include the DVFS configuration file in the above embodiment.

[0105] In some implementations, when S302 is executed, a first test mode is run.

[0106] In some implementations, before adjusting the operating frequency of the first processor to the first target frequency, a first context switch is performed, where the first context switch is used for running the first test mode.

[0107] Exemplarily, before adjusting the operating frequency of the first processor to the first target frequency, executing the first context switch may include: after the DVFS simplified configuration module 221 enables DVFS, before the frequency manager adjusts the operating frequency of the first processor to the first target frequency, executing the first context switch; or, when the STL scheduling module 222 calls the DVFS simplified configuration module 221, executing the first context switch.

[0108] In some implementations, the method further includes: after the first test mode is completed and before adjusting the operating frequency of the first processor to the second target frequency, performing a second context switch, the second context switch being used for running the first process, and the second target frequency being the target frequency of the first processor corresponding to running the first process.

[0109] Exemplarily, the first process may be a process that is being run before the first test mode is run, and the second target frequency may be a frequency saved when the first context switch is performed.

[0110] In some implementations, the method further includes: obtaining a second target frequency, where the second target frequency is the frequency of the first processor corresponding to when the target task is running, or the second target frequency is the current operating frequency of the first processor; when the first target frequency is different from the second target frequency, adjusting the operating frequency of the processor to the first target frequency.

[0111] In one example, if the target task is a task currently running in the system, the second target frequency may also be the operating frequency of the first processor saved by the DVFS management module.

[0112] In another example, if the target task is about to be executed, the second target frequency can be determined based on the business-layer tuning requirement information. The business-layer tuning requirement information includes the processor frequency required for each business-layer task to execute. For example, the business-layer tuning requirement information can be in the form of a file, a table, or other formats.

[0113] The fault detection method provided in the embodiment of the present application can adjust the operating frequency of the processor according to the STL test mode, thereby increasing the operating speed of the computationally intensive STL test mode and reducing the power consumption required for the operation of the memory-intensive STL test mode. Furthermore, the fault detection method provided in the embodiment of the present application, when adjusting the operating frequency of the processor according to the STL test mode, can simultaneously perform frequency adjustment and context switching corresponding to the STL test mode to be executed, which helps to reduce the operating time of the STL test mode and reduce the impact of the STL test mode on the real-time performance of business layer tasks.

[0114] To facilitate understanding of the fault detection method provided in this application, the method 300 is further described below with reference to FIG. 4 to FIG. 7 .

[0115] FIG4 is a schematic diagram showing an application scenario of the fault detection method provided by an embodiment of the present application. As shown in FIG4 , in order to run the STL test mode, it may be necessary to execute 1-8 shown in FIG4 . Among them:

[0116] 1. The operating system (OS) scheduler of the kernel 220 obtains tuning requirement information from the service layer. The tuning requirement information may be the service layer tuning requirement information in the above embodiment.

[0117] 2. When switching business layer tasks, the OS scheduler controls the frequency manager to adjust the operating frequency of the processor.

[0118] 3. When the STL test mode needs to be run, the OS scheduler calls the STL scheduler, which can be an example of the STL scheduling module 222 .

[0119] 4. The STL scheduler obtains the STL frequency tuning information and a schedule table of a target task, which includes one or more test modes. The target task may be the target task in the above embodiment.

[0120] In some implementations, the STL scheduler determines the test mode n to be run based on the scheduling table; further, the STL scheduler determines the target frequency of the target processor based on the STL frequency tuning information, and the target processor is used to run the test mode n. The target frequency is the recommended operating frequency when the target processor runs the test mode n.

[0121] Among them, the STL frequency tuning information can be regarded as an example of the above-mentioned frequency tuning information, the test mode n can be regarded as an example of the above-mentioned first test mode, the target processor can be regarded as an example of the above-mentioned first processor, and the target frequency can be regarded as an example of the above-mentioned first target frequency.

[0122] In some implementations, the system does not store STL frequency tuning information, but the system pre-stores the relationship between the test mode type and the processor operating frequency. The STL scheduler then determines the target frequency corresponding to the test mode n according to the test mode type.

[0123] 5. The STL scheduler controls the frequency manager to adjust the operating frequency of the target processor to the target frequency according to the test mode n to be run.

[0124] 6. The STL scheduler runs test mode n.

[0125] In some implementations, before running the test pattern to be run, another test pattern, such as test pattern 1, is being run, and a context switch is performed to run test pattern n.

[0126] In some implementations, before running the test pattern to be run, no other test patterns are run, and the test pattern n is directly run.

[0127] For example, step 6 can be executed after step 5, or steps 5 and 6 can be executed simultaneously. When steps 5 and 6 are executed simultaneously, the target processor frequency may not have been adjusted to the target frequency when test mode n begins. Therefore, during the execution of test mode n, the target processor may have two operating frequencies. For example, the processor frequency corresponding to the first period of the execution of test mode n is the frequency before the frequency adjustment, such as the second target frequency in method 300, and the processor frequency corresponding to the second period of the execution of test mode n is the target frequency.

[0128] 7. The DVFS monitoring module (eg, DVFS monitoring module 241 ) in the monitor 240 monitors the running process of the test mode n, and obtains the running frequency of the target processor when running the test mode n, and the running duration of the test mode n.

[0129] 8. The DVFS monitoring module updates the STL frequency tuning information based on the operating frequency of the target processor when running test mode n and the running duration of test mode n.

[0130] Exemplarily, the specific implementation manner in which the DVFS monitoring module updates the STL frequency tuning information according to the operating frequency and the operating duration may refer to the description in method 300 and will not be repeated here.

[0131] The specific implementation of adjusting the processor frequency and running the STL test mode is described below with reference to FIG. 5 .

[0132] Fig. 5 shows another schematic diagram of an application scenario of the fault detection method provided by an embodiment of the present application. As shown in Fig. 5 , in order to make the target processor run the STL test mode at the target frequency, S501 to S503 may be executed.

[0133] S501 : The STL scheduler calls a DVFS simplified configuration module (such as the DVFS simplified configuration module 221 ).

[0134] The DVFS simplified configuration module can perform the following steps: close the phase-locked loop (PLL) frequency detection, initialize the processor voltage, initialize the processor frequency, configure the regulator step size and number, enable DVFS, and then start adjusting the processor frequency after DVFS is enabled.

[0135] Upon or after the enabling DVFS step is completed, a context switch is performed.

[0136] S502: Wait for DVFS to complete.

[0137] Waiting for DVFS to complete may be understood as waiting for the processor frequency to be adjusted to a target frequency, such as the first target frequency.

[0138] S503, running the STL test mode.

[0139] In one example, the STL scheduler switches to the layer where the monitor 240 is located while waiting for the DVFS to be completed or thereafter, and runs the STL test mode, such as the first test mode.

[0140] In another example, while or after the STL scheduler waits for the DVFS to complete, it switches to the layer where the monitor 240 is located to run the STL test mode.

[0141] In another example, after the context switch is completed, the STL test mode is directly executed. If the time required for the context switch is longer than the time required for the frequency conversion, the STL test mode is executed while waiting for the DVFS to complete.

[0142] It is understandable that in the process of adjusting the processor frequency, the steps of waiting for DVFS to complete after enabling DVFS and the process of performing context switching are both time-consuming. In this application, performing context switching while waiting for DVFS to complete can shorten the time required for the STL process to run.

[0143] In some possible implementations, S504 and S505 may be further executed when the STL test mode ends.

[0144] S504: The STL scheduler calls the DVFS simplified configuration module.

[0145] For example, if the processor operating frequency saved before the context switch needs to be restored after the STL test mode has completed, S504 is executed. Specifically, the steps for executing DVFS are as described in S501 and are not repeated here. Upon or after the DVFS enabling step is completed, a context switch is executed. Specifically, while waiting for DVFS to complete, a context switch is executed to run the next process.

[0146] Figure 6 (a) and (b) show the timing diagrams of process execution when the method of the present application is not used and when the method of the present application is used, respectively. It can be seen that since the context switch must be performed after the frequency conversion is completed when the method of the present application is not used, the time required to switch between the kernel process and the STL process is significantly longer than when the method of the present application is used. Frequency conversion can be understood as waiting for the end of DVFS, that is, the time between the time when DVFS is enabled and the time when DVFS is completed.

[0147] In some possible implementations, when the STL test mode is a test mode running in the TEE, before executing the context switch, it is also necessary to execute the switch from REE to TEE to adjust the operating frequency of the processor based on the STL test mode running in the TEE.

[0148] Figure 7 (a) and (b) show the timing diagrams of the process execution without and with the method of the present application, respectively. It can be seen that when the method of the present application is not used, the context switch must be performed after the frequency conversion and world switch are completed in sequence. Therefore, the time required to switch between the kernel process and the STL process is significantly longer than when the method of the present application is used. Among them, the world switch can be understood as the switch between REE and TEE.

[0149] It has been verified that when using the full-scale STL to perform fault detection on ten business-layer tasks (including compute-intensive and memory-intensive tasks) in the intelligent driving system, the STL execution time required is 4.205ms. When using the fault detection algorithm provided by this application to perform fault detection on the same ten business-layer tasks, the STL execution time required is 3.525ms. In other words, the running time of the STL test mode is shortened by about 17% compared with existing fault detection technologies.

[0150] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the various embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0151] The fault detection method provided in the embodiment of the present application is described in detail above with reference to Figures 2 to 7 . The fault detection device provided in the embodiment of the present application will be described in detail below with reference to Figures 8 and 9 . It should be understood that the description of the control device embodiment corresponds to the description of the method embodiment. Therefore, for matters not described in detail, reference can be made to the method embodiment above, and for the sake of brevity, they will not be repeated here.

[0152] Fig. 8 shows a schematic block diagram of a fault detection device 800 according to an embodiment of the present application. The device 800 may include units for executing the method in Fig. 3. Furthermore, each unit in the device 800 is for implementing the corresponding process of the method embodiment in Fig. 3.

[0153] Specifically, the device 800 includes an acquisition unit 810 and a first processing unit 820, wherein the acquisition unit 810 is used to obtain information of a first test mode, the first test mode is a test mode to be run, and the first test mode is used to detect faults of a first integrated circuit; the first processing unit 820 is used to adjust the operating frequency of the first processor to a first target frequency according to the first test mode, and the first processor is used to run the first test mode.

[0154] In some implementations, the first target frequency is determined according to a type of the first test mode, where the type of the first test mode includes computation-intensive or memory-intensive.

[0155] In some implementations, the first target frequency is determined based on the operating frequency of the first processor when the first test mode was last executed and the running duration of the first test mode.

[0156] In some implementations, the first test mode is associated with the first virtual machine, and the device 800 also includes a second processing unit, which is used to: after adjusting the operating frequency of the first processor to the first target frequency, update the frequency information of the virtual machine manager, the frequency information indicates the current operating frequency of the first processor, and the virtual machine manager is used to manage one or more virtual machines including the first virtual machine.

[0157] In some implementations, the acquisition unit 810 is further used to: obtain frequency tuning information, the frequency tuning information indicates the target frequency of the processor corresponding to each test mode in running one or more test modes, the one or more test modes including the first test mode; the first processing unit 820 is used to: determine the first target frequency based on the first test mode and the frequency tuning information.

[0158] In some implementations, the first processing unit 820 is further configured to: run the first test mode when adjusting the operating frequency of the first processor.

[0159] In some implementations, the first processing unit 820 is further configured to: before adjusting the operating frequency of the first processor to the first target frequency, perform a first context switch, where the first context switch is used for running the first test mode.

[0160] In some implementations, the first processing unit 820 is further used to: after the first test mode is completed and before adjusting the operating frequency of the first processor to the second target frequency, perform a second context switch, the second context switch is used for the operation of the first process, and the second target frequency is the target frequency of the first processor corresponding to the operation of the first process.

[0161] In some implementations, when the first test mode is associated with a trusted execution environment (TEE), before executing the first context switch, the apparatus 800 further includes a third processing unit configured to execute a switch from the open execution environment (REE) to the TEE.

[0162] Exemplarily, the apparatus 800 may be provided in the system shown in any one of (a) to (d) in FIG2 . More specifically, the acquisition unit 810 may include the STL scheduling module 222 (or STL scheduling module) shown in FIG2 , and the first processing unit 820 may include the STL scheduling module 222 (or STL scheduling module) shown in FIG2 . In some implementations, the first processing unit 820 may also include the DVFS simplified configuration module 221 (or DVFS simplified configuration module) shown in FIG2 . Exemplarily, the second processing unit may include the DVFS management module 231 shown in FIG2 ; and the third processing unit may include the SMC handler shown in FIG2 .

[0163] For example, the operations performed by the acquisition unit 810 and the first processing unit 820 may be performed by a single processor, or by different processors. In a specific implementation, the one or more processors may be processors provided in an intelligent driving device. Alternatively, the apparatus 800 may be a chip provided in the intelligent driving device.

[0164] In an embodiment of the present application, a processor is a circuit with a signal processing capability. In one implementation, the processor can implement a certain function through the logical relationship of a hardware circuit. The logical relationship of the hardware circuit is fixed or reconfigurable. For example, the processor is a hardware circuit implemented by an application-specific integrated circuit (ASIC) or a programmable logic device (PLD), such as a field programmable gate array (FPGA). In a reconfigurable hardware circuit, the processor loads a configuration document to implement the process of hardware circuit configuration, which can be understood as a process in which the processor loads instructions to implement the functions of some or all of the above units. In addition, it can also be a hardware circuit designed for artificial intelligence, which can be understood as an ASIC, such as a neural network processing unit (NPU), a tensor processing unit (TPU), a deep learning processing unit (DPU), etc.

[0165] In a specific implementation process, the various units in the above apparatus may be fully or partially integrated together, or may also be implemented independently. In one implementation, these units are integrated together and implemented in the form of a system-on-a-chip (SoC).

[0166] FIG9 is another schematic block diagram of a fault detection device provided in an embodiment of the present application. The fault detection device 900 shown in FIG9 may include: a processor 910, a transceiver 920, and a memory 930. The processor 910, the transceiver 920, and the memory 930 are connected via an internal connection path. The memory 930 is used to store instructions, and the processor 910 is used to execute the instructions stored in the memory 930 to implement the methods in the above embodiments. Optionally, the memory 930 can be coupled to the processor 910 via an interface or integrated with the processor 910.

[0167] It should be noted that the transceiver 920 may include but is not limited to a transceiver device such as an input / output interface to implement communication between the device 900 and other devices or a communication network.

[0168] The memory 930 may be a volatile memory and / or a non-volatile memory. The non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM). For example, RAM may be used as an external cache. By way of example and not limitation, RAM includes the following forms: static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct rambus RAM (DR RAM).

[0169] The transceiver 920 uses a transceiver device such as but not limited to a transceiver to implement communication between the device 910 and other devices or communication networks to receive / send data / information used to implement the methods in the above embodiments.

[0170] An embodiment of the present application further provides a computing platform, which includes the fault detection device 800 or the fault detection device 900 in the above embodiment.

[0171] An embodiment of the present application further provides an intelligent driving device, which includes the fault detection device 800 or the fault detection device 900 in the above embodiment.

[0172] The intelligent driving devices involved in the embodiments of the present application may include road vehicles, water vehicles, air vehicles, industrial equipment, agricultural equipment, or entertainment equipment, etc. For example, the intelligent driving device may be a vehicle, which is a vehicle in a broad sense and may be a transportation vehicle (such as a commercial vehicle, a passenger car, a motorcycle, a flying car, a train, etc.), an industrial vehicle (such as a forklift, a trailer, a tractor, etc.), an engineering vehicle (such as an excavator, a bulldozer, a crane, etc.), agricultural equipment (such as a lawn mower, a harvester, etc.), amusement equipment, a toy vehicle, etc. The embodiments of the present application do not specifically limit the type of vehicle.

[0173] Figure 10 shows a schematic block diagram of an intelligent driving device provided in an embodiment of the present application. As shown in Figure 10, intelligent driving device 1000 includes a computing platform 1050, which may include processors 1051 to 105n. For example, processors 1051 to 105n may be, for example, a CPU, a microprocessor, a GPU, or a digital signal processor (DSP). Computing platform 1050 can be considered an example of a computing platform in the above-described embodiments, and the above-described apparatus 800 or apparatus 900 may be provided in one or more processors of computing platform 1050. Optionally, intelligent driving device 1000 may also include a perception system 1020, which may include several sensors for acquiring image information surrounding the intelligent driving device. For example, perception system 1020 may include sensors such as a laser radar and a camera that can acquire image information. The image information acquired by perception system 1020 may be input into computing platform 1050 for processing, and computing platform 1050 may accelerate image processing based on the data processing method provided in this application.

[0174] For example, taking a vehicle as an intelligent driving device, the computing platform may include any one of the following: a vehicle domain controller (VDC), an advanced driving domain controller (ADC), and a cockpit domain controller (CDC). For another example, the computing platform may also include, but is not limited to, an in-car application-server (ICAS) controller, a body domain controller (BDC), a special equipment system (SAS), a media graphics unit (MGU), a body super core (BSC), and an advanced driving assistant system super core (ADAS super core). The ICAS may include at least one of the following: a vehicle control server (ICAS1), an intelligent driving server (ICAS2), an intelligent cockpit server (ICAS3), and an infotainment server (ICAS4).

[0175] An embodiment of the present application further provides a computer program product, which includes computer program code. When the computer program code runs on a computer, the computer implements the methods in the above embodiments of the present application.

[0176] An embodiment of the present application further provides a computer-readable storage medium, which stores computer instructions. When the computer instructions are executed on a computer, the computer implements the methods in the above embodiments of the present application.

[0177] An embodiment of the present application also provides a chip, including a circuit, for executing the methods in the above embodiments of the present application.

[0178] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0179] In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in this article is a kind of association relationship that describes associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In this application, "at least one" refers to one or more, and "more than one" refers to two or more. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple.

[0180] In the embodiments of this application, prefixes such as "first" and "second" are used only to distinguish different description objects and have no limiting effect on the position, order, priority, quantity, or content of the described objects. The use of prefixes such as ordinal numbers in the embodiments of this application to distinguish description objects does not constitute a limitation on the described objects. For a statement of the described objects, please refer to the description in the context of the claims or embodiments, and the use of such prefixes should not constitute an unnecessary limitation.

[0181] In the several embodiments provided in this application, it should be understood that the disclosed systems, devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0182] In the various embodiments of the present application, unless otherwise specified or there is a logical conflict, the terms and / or descriptions between the various embodiments are consistent and can be referenced by each other. The technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0183] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0184] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0185] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A fault detection method, characterized in that: include: Acquire information of a first test mode, where the first test mode is a test mode to be run, and the first test mode is used to detect a fault of a first integrated circuit; The operating frequency of the first processor is adjusted to a first target frequency according to the first test mode, and the first processor is used to run the first test mode.

2. The method according to claim 1, characterized in that The first target frequency is determined by a type of the first test pattern, which includes computationally intensive or memory intensive.

3. The method according to claim 1 or 2, characterized in that The first target frequency is determined by the operating frequency of the first processor when the first test mode was last run and the running length of the first test mode.

4. The method according to any one of claims 1 to 3, characterized in that The first test mode is associated with a first virtual machine, and the method further includes: After adjusting the operating frequency of the first processor to the first target frequency, updating frequency information of the virtual machine manager, the frequency information indicating the current operating frequency of the first processor, the virtual machine manager being used to manage one or more virtual machines including the first virtual machine.

5. The method according to any one of claims 1 to 4, characterized in that The method further comprises: Acquire frequency tuning information, where the frequency tuning information indicates a target frequency of a processor corresponding to each test mode in running one or more test modes, where the one or more test modes include the first test mode; The first target frequency is determined according to the first test pattern and the frequency tuning information.

6. The method according to any one of claims 1 to 5, characterized in that The method further comprises: The first test mode is executed when the operating frequency of the first processor is adjusted.

7. The method according to any one of claims 1 to 6, characterized in that The method further comprises: Before adjusting the operating frequency of the first processor to the first target frequency, a first context switch is performed, where the first context switch is used for running the first test mode.

8. The method according to claim 7, characterized in that The method further comprises: After the first test mode is completed and before the operating frequency of the first processor is adjusted to a second target frequency, a second context switch is performed, wherein the second context switch is used for running the first process, and the second target frequency is the target frequency of the first processor corresponding to running the first process.

9. The method according to claim 7 or 8, characterized in that When the first test mode is associated with a trusted execution environment TEE, before performing the first context switch, the method further includes: The execution opens the execution environment REE and switches to the TEE.

10. A fault detection device, characterized in that: include: An acquisition unit, configured to acquire information of a first test mode, where the first test mode is a test mode to be run, and the first test mode is used to detect a fault of a first integrated circuit; The first processing unit is used to adjust the operating frequency of the first processor to a first target frequency according to the first test mode, and the first processor is used to run the first test mode.

11. The device according to claim 10, characterized in that The first target frequency is determined by a type of the first test pattern, which includes computationally intensive or memory intensive.

12. The device according to claim 10 or 11, characterized in that The first target frequency is determined by the operating frequency of the first processor when the first test mode was last run and the running length of the first test mode.

13. The device according to any one of claims 10 to 12, characterized in that The first test mode is associated with the first virtual machine, and the apparatus further includes a second processing unit, configured to: After adjusting the operating frequency of the first processor to the first target frequency, updating frequency information of the virtual machine manager, the frequency information indicating the current operating frequency of the first processor, the virtual machine manager being used to manage one or more virtual machines including the first virtual machine.

14. The device according to any one of claims 10 to 13, characterized in that The acquisition unit is also used for: Acquire frequency tuning information, where the frequency tuning information indicates a target frequency of a processor corresponding to each test mode in running one or more test modes, where the one or more test modes include the first test mode; The first processing unit is used for: The first target frequency is determined according to the first test pattern and the frequency tuning information.

15. The device according to any one of claims 10 to 14, characterized in that The first processing unit is further configured to: The first test mode is executed when the operating frequency of the first processor is adjusted.

16. The device according to any one of claims 10 to 15, characterized in that The first processing unit is further configured to: Before adjusting the operating frequency of the first processor to the first target frequency, a first context switch is performed, where the first context switch is used for running the first test mode.

17. The device according to claim 16, characterized in that The first processing unit is further configured to: After the first test mode is completed and before the operating frequency of the first processor is adjusted to a second target frequency, a second context switch is performed, wherein the second context switch is used for running the first process, and the second target frequency is the target frequency of the first processor corresponding to running the first process.

18. The device according to claim 16 or 17, characterized in that When the first test mode is associated with a trusted execution environment TEE, before performing the first context switch, the apparatus further includes a third processing unit, configured to: The execution opens the execution environment REE and switches to the TEE.

19. A fault detection device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program stored in the memory, so that the apparatus performs the method according to any one of claims 1 to 9.

20. An intelligent driving device, characterized in that: The intelligent driving device comprises the apparatus as claimed in any one of claims 10 to 19.

21. A computer-readable storage medium, characterized in that: Instructions are stored thereon, and when the instructions are executed by a processor, the processor implements the method according to any one of claims 1 to 9.

22. A chip, characterized in that: The chip comprises a circuit for executing the method according to any one of claims 1 to 9.

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