SPI apparatus capable of connecting to multiple devices, and method therefor

Abstract

Disclosed in the present invention are an SPI apparatus capable of connecting to multiple devices, and a method therefor. The apparatus involved comprises a bus controller, an SPI transceiver, a parameter selector and a RAM cache, wherein the bus controller is used for converting a read-write operation of a CPU bus into a read-write operation of the RAM cache, a read-write operation and selection signal of the parameter selector, or a work command of the SPI transceiver; the parameter selector is used for acquiring the read-write operation and selection signal of the parameter selector, which are obtained after the bus controller performs conversion, selecting a parameter group corresponding to the SPI transceiver, and transmitting the selected parameter group to the SPI transceiver; the RAM cache is used for caching the read-write operation of the RAM cache, which is obtained after the bus controller performs conversion; and the SPI transceiver is used for acquiring the work command of the SPI transceiver, which is obtained after the bus controller performs conversion, reading the cached read-write operation from the RAM cache, and completing an operation on an external SPI peripheral according to parameters transmitted by the parameter selector.

Description

SPI interface device and method capable of connecting multiple devices Technical Field

[0001] The present invention relates to the technical field of peripheral communication interfaces, and in particular to an SPI interface device and method capable of connecting multiple devices. Background Art

[0002] The Serial Peripheral Interface (SPI) bus was first proposed by Motorola as a full-duplex, three-wire synchronous serial peripheral interface. It uses a master-slave architecture and supports one or more slave devices. It first appeared in its M68 series microcontrollers. Due to its simplicity, practicality, and excellent performance, it is supported by devices from many manufacturers and is widely used to connect MCUs and peripheral modules such as E2PROMs, ADCs, and display drivers. It is important to note that the SPI interface is a de facto standard. Most manufacturers design their designs based on Motorola's SPI interface definition, and various variants have been derived from this foundation. With the continuous development of technology, its data bus has become 1-bit, 2-bit, 4-bit, and even 8-bit and higher, greatly improving the bandwidth capability of the SPI bus and expanding its application space. This is especially true for SPI Flash. The use of a 4-bit data bus allows for faster data transmission, making SPI XIP (XIP) a popular standard.

[0003] With the development of XIP technology, the combination of a logic-based MCU and an SPI Flash has become a mainstream MCU implementation. However, the existing method connects multiple different types of devices to the same SPI bus interface. In particular, when the system is connected to both an SPI XIP Flash memory and an SPI device, there is a technical problem of having to load the code for communicating with other SPI peripherals from the SPI memory to run on other memories within the chip.

[0004] Summary of the Invention

[0005] The purpose of the present invention is to address the defects of the prior art and provide an SPI interface device and method capable of connecting multiple devices.

[0006] In order to achieve the above objectives, the present invention adopts the following technical solutions:

[0007] An SPI interface device capable of connecting multiple devices includes a bus controller, an SPI transceiver, a parameter selector, and a RAM buffer;

[0008] The bus controller is connected to the SPI transceiver, the parameter selector, and the RAM buffer respectively, and is used to convert the read and write operations of the CPU bus into the read and write operations of the RAM buffer, the read and write operations of the parameter selector, and the selection signal or the working command of the SPI transceiver;

[0009] A parameter selector is connected to the SPI transceiver, and is used to obtain the read and write operation and selection signal of the parameter selector after conversion by the bus controller, select the parameter group corresponding to the SPI transceiver, and transmit the selected parameter group to the SPI transceiver;

[0010] A RAM buffer is connected to the SPI transceiver and is used to cache the read and write operations of the RAM buffer converted by the bus controller;

[0011] The SPI transceiver is used to obtain the working command of the SPI transceiver converted by the bus controller, read the cached read and write operations from the RAM buffer, and complete the operation of the external SPI peripheral according to the parameters transmitted by the parameter selector.

[0012] Furthermore, the bus controller includes a register address interval and several peripheral address intervals;

[0013] Register address interval, used to convert CPU bus reading and writing of register address interval into reading and writing operations of RAM buffer or reading and writing operations of parameter selector;

[0014] Several peripheral address intervals are used to convert the reading and writing of the several peripheral address intervals by the CPU bus into selection signals of the parameter selector or working commands of the SPI transceiver.

[0015] Furthermore, the parameter selector includes several parameter groups, each parameter group includes memory mapping read operation parameters, memory mapping write operation parameters, memory mapping configurable command operation parameters, and SPI frame format parameters.

[0016] Furthermore, the RAM buffer is also used to buffer data sent by the SPI transceiver.

[0017] Furthermore, the operations of the SPI transceiver on the external SPI peripheral include memory mapping read operations, memory mapping write operations, and memory mapping configurable command operations.

[0018] Accordingly, a method for connecting an SPI interface of multiple devices is also provided, comprising:

[0019] A1. The bus controller obtains the bus read operation initiated by the CPU bus;

[0020] A2. The bus controller compares the target address of the bus read operation with the internal register address range and several peripheral address ranges to determine the external SPI peripheral device to be read. The controller selects the corresponding parameter group in the parameter selector and sends a read command to the SPI transceiver. The read command includes the obtained external SPI peripheral device, read address, and read length information.

[0021] A3. The SPI transceiver receives the read command sent by the parameter selector, performs a read operation on the external SPI peripheral device according to the parameters selected by the parameter selector, and responds to the bus controller with the read data.

[0022] A4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

[0023] Accordingly, a method for connecting an SPI interface of multiple devices is also provided, comprising:

[0024] B1. The bus controller obtains the bus write operation initiated by the CPU bus;

[0025] B2. The bus controller obtains the external SPI peripheral for the write operation by comparing the target address contained in the bus write operation with the internal register address interval and several peripheral address intervals, and selects the corresponding parameter group in the parameter selector to send a write command to the SPI transceiver; the write command includes the obtained external SPI peripheral, write address, and write length information;

[0026] B3. The SPI transceiver receives the write command sent by the parameter selector, receives the parameters selected by the parameter selector, performs a write operation on the external SPI peripheral, and responds to the written data to the bus controller;

[0027] B4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

[0028] Accordingly, a method for connecting an SPI interface of multiple devices is also provided, comprising:

[0029] C1. The bus controller obtains the bus write operation initiated by the CPU bus;

[0030] C2. The bus controller compares the target address of the bus write operation with the internal register address range and several peripheral address ranges to determine the external SPI peripheral device to be written to. It then selects the corresponding parameter group in the parameter selector and sends the configurable command to the SPI transceiver.

[0031] C3. The SPI transceiver receives the write command sent by the parameter selector. The SPI transceiver determines whether to read data from the RAM buffer based on the parameters selected by the parameter selector. If so, the SPI transceiver reads the data from the RAM buffer and performs a read operation on the external SPI peripheral. If not, the SPI transceiver writes the data read from the external SPI peripheral to the RAM buffer.

[0032] C4. The read data or written data is responded to the bus controller. The bus controller responds the obtained data to the CPU bus and releases the CPU bus.

[0033] Compared with the prior art, the present invention converts the read and write operations of the CPU bus into accesses to external SPI devices. Through time-sharing multiplexing, the CPU can switch between accesses to different types of SPI peripherals without the need for additional processing. A parameter group is automatically selected based on the access address and applied to the SPI transceiver to access the corresponding SPI peripheral, thereby achieving automatic switching between different types of SPI devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] FIG1 is a structural diagram of an SPI interface device capable of connecting multiple devices provided in Example 1;

[0035] FIG2 is a diagram showing an example structure of an SPI interface device capable of connecting multiple devices provided in the second embodiment. DETAILED DESCRIPTION

[0036] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. The details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other unless they conflict.

[0037] The purpose of the present invention is to address the defects of the prior art and provide an SPI interface device and method capable of connecting multiple devices.

[0038] Example 1

[0039] This embodiment provides an SPI interface device that can connect multiple devices, as shown in FIG1 , including a bus controller 100 , an SPI transceiver 200 , a parameter selector 300 , a RAM buffer 400 , and an external SPI peripheral 500 .

[0040] One end of the bus controller 100 is a CPU bus interface, which is connected to the CPU or CPU bus matrix. This connection is a channel for the device to receive and respond to CPU bus commands.

[0041] The bus controller 100 is connected to the SPI transceiver 200 , and this connection is a channel for the SPI transceiver 200 to receive operation commands and respond to operation results.

[0042] The bus controller 100 is connected to the RAM buffer 400 , and this connection is a channel for the bus controller 100 to read and write storage units of the RAM buffer 400 .

[0043] The bus controller 100 is connected to the parameter selector 300 . This connection is a channel for the bus controller 100 to read and write parameter group registers in the parameter selector 300 , as well as a control channel for selecting a parameter group.

[0044] The SPI transceiver 200 is connected to the RAM buffer 400 . This connection is a channel for the SPI transceiver 200 to access data in the RAM buffer 400 .

[0045] The SPI transceiver 200 is connected to the parameter selector 300 . This connection is a channel through which the parameter selector 300 outputs the parameters of the selected parameter group to the SPI transceiver 200 .

[0046] The SPI transceiver 200 is connected to the external SPI peripheral 500 , and the connection is an SPI bus that operates multiple external SPI peripherals.

[0047] The bus controller 100 is used to convert the read and write operations of the CPU bus into read and write operations of the RAM buffer, read and write operations of the parameter selector, and selection signals or working commands of the SPI transceiver.

[0048] The bus controller 100 identifies CPU bus read and write operations and converts them into reads and writes to the RAM buffer 400, reads and writes to and selects parameter groups within the parameter selector 300, or generates commands to control the operation of the SPI transceiver 200. The bus controller 100 uses address mapping to select corresponding operations. The bus controller 100 internally contains multiple address ranges, such as the register address range, peripheral address range 1, peripheral address range 2, ..., and peripheral address range N. CPU bus reads and writes to register address ranges convert into reads and writes to the RAM buffer 400 and to the parameter group registers of the parameter selector 300. Reads and writes to peripheral address ranges 1, peripheral address range 2, ..., and peripheral address range N select the corresponding parameter group and convert them into commands to control the corresponding SPI peripherals of the SPI transceiver 200. There is a one-to-one correspondence between peripheral address ranges, parameter groups, and SPI peripherals.

[0049] The parameter selector is used to obtain the read and write operations and selection signals of the parameter selector converted by the bus controller, select the parameter group corresponding to the SPI transceiver, and transmit the selected parameter group to the SPI transceiver.

[0050] The parameter selector 300 selects a corresponding parameter group according to the selection signal provided by the bus controller 100 and outputs it to the SPI transceiver 200. Each parameter group of the parameter selector 300 includes memory mapping read operation parameters, memory mapping write operation parameters, memory mapping configurable command operation parameters and SPI frame format parameters.

[0051] The RAM buffer 400 is used to buffer the read and write operations of the RAM buffer converted by the bus controller.

[0052] The RAM buffer 400 is used to buffer the data sent and received by the SPI transceiver.

[0053] The SPI transceiver 200 is used to obtain the SPI transceiver working command converted by the bus controller, read the cached read and write operations from the RAM buffer, and complete the operation of the external SPI peripheral according to the parameters transmitted by the parameter selector.

[0054] The SPI transceiver 200 performs read and write operations on the external SPI peripheral 500 based on commands sent by the bus controller 100 and the parameters output by the parameter selector 300. Commands sent by the bus controller 100 include memory-mapped reads, memory-mapped writes, and memory-mapped configurable commands. Read and write commands for the SPI transceiver 200 begin when the chip select signal CS is pulled low and end when the chip select signal CS is pulled high, and include the transmission and reception of bytes of a specified length. The SPI transceiver 200 can read data from the RAM buffer 400 or receive data from the bus controller 100 and send it to the external SPI peripheral 500. It can also read data from the external SPI peripheral 500 and write it to the RAM buffer 400 or send it to the bus controller 100.

[0055] This embodiment converts the read and write operations of the CPU bus into access to external SPI devices, and through time-sharing multiplexing, the CPU can switch between different types of SPI peripheral accesses without the need for additional processing.

[0056] This embodiment is initiated by a CPU bus command and terminated by a bus response. During this process, the bus is maintained to prevent other bus commands from entering. Therefore, based on this device, a method for connecting an SPI interface of multiple devices is also provided, which is for the operation of an external SPI peripheral 500. The operation specifically includes a memory mapping read operation, a memory mapping write operation and a memory mapping configurable command operation.

[0057] The memory mapped read operation is as follows:

[0058] A1. The bus controller obtains the bus read operation initiated by the CPU bus;

[0059] A2. The bus controller maintains the bus and compares the target address of the bus read operation with the internal register address range and multiple peripheral address ranges to determine which external SPI peripheral device is being read. The bus controller then determines the external SPI peripheral device being read. The controller then selects the corresponding parameter group in the parameter selector and sends a read command to the SPI transceiver. The read command includes the external SPI peripheral device, read address, and read length information.

[0060] A3. The SPI transceiver receives the read command sent by the parameter selector, performs a read operation on the external SPI peripheral device according to the parameters selected by the parameter selector, and responds to the bus controller with the read data.

[0061] A4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

[0062] The memory mapped write operations are as follows:

[0063] B1. The bus controller obtains the bus write operation initiated by the CPU bus;

[0064] B2. The bus controller maintains the bus and determines which external SPI peripheral is being written to by comparing the target address included in the bus write operation with the internal register address range and multiple peripheral address ranges. The bus controller then obtains the external SPI peripheral being written to, selects the corresponding parameter group in the parameter selector, and sends a write command to the SPI transceiver; wherein the write command includes the obtained external SPI peripheral, write address, and write length information.

[0065] B3. The SPI transceiver receives the write command sent by the parameter selector, receives the parameters selected by the parameter selector, performs a write operation on the external SPI peripheral, and responds to the written data to the bus controller;

[0066] B4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

[0067] The memory map configurable command operations are as follows:

[0068] C1. The bus controller obtains the bus write operation initiated by the CPU bus;

[0069] C2. The bus controller maintains the bus and determines which external SPI peripheral device is being commanded by comparing the target address included in the bus write operation with the internal register address range and several peripheral address ranges. The bus controller then determines the external SPI peripheral device being written to, selects the corresponding parameter group in the parameter selector, and sends a configurable command to the SPI transceiver.

[0070] C3. The SPI transceiver receives the write command sent by the parameter selector. The SPI transceiver determines whether to read data from the RAM buffer based on the parameters selected by the parameter selector. If so, the data is read from the RAM buffer and a read operation is performed on the obtained external SPI peripheral. If not, the data needs to be stored in the RAM buffer. Specifically, the data read from the external SPI peripheral is written to the RAM buffer.

[0071] C4. The read data or written data is responded to the bus controller. The bus controller responds the obtained data to the CPU bus and releases the CPU bus.

[0072] This embodiment automatically selects a parameter group according to an access address and is applied to an SPI transceiver to access a corresponding SPI peripheral device, thereby achieving automatic switching between different types of SPI devices.

[0073] Example 2

[0074] The SPI interface device capable of connecting multiple devices provided in this embodiment is different from the first embodiment in that:

[0075] As shown in Figure 2, this embodiment is described by taking the implementation of a fingerprint sensor that is simultaneously connected to an SPI Flash as an XIP memory and an SPI interface as an example; according to actual functional requirements, the device of this embodiment implements memory mapping read operations and memory mapping configurable command operations on the SPI Flash, and implements memory mapping configurable command operations on the SPI fingerprint sensor.

[0076] The bus controller is connected to the CPU via the AHB bus.

[0077] The bus controller implements three address ranges: register address range 0x50000000-0x50003FFF, SPI Flash address range 0x10000000-0x10FFFFFF and 0x50004000-0x50004003, and SPI fingerprint sensor address range 0x50004004-0x50004007. When the AHB bus reads and writes the 4KB space of address 0x50000000-0x50000FFF, the bus controller converts it to reading and writing the RAM buffer; when the AHB bus reads and writes the address 0x50001000-0x50003FFF, the bus controller converts it to reading and writing the parameter register in the parameter selector; when the AHB bus reads the address 0x10000000-0x10FFFFFF, according to the memory map read operation parameters and SPI frame format parameters of the Flash parameter group in the parameter selector, the Flash read command byte and address are sent, and then the data is read back to realize Flash XIP function; when the AHB bus reads the address 0x50004000-0x50004003 space, according to the memory mapping programmable command operation parameters and SPI frame format parameters of the Flash parameter group in the parameter selector, the data of the specified length is sent, and then the data of the specified length is read back, thereby realizing basic operations such as reading ID, programming, and erasing of Flash; when the AHB bus reads the address 0x50004004-0x50004007 space, according to the memory mapping programmable command operation parameters and SPI frame format parameters of the Flash parameter group in the parameter selector (3), the data of the specified length is sent, and then the data of the specified length is read back, thereby realizing operations such as controlling the sensor, reading sensor image data, and reading status.

[0078] The parameter selector implements two parameter groups: the SPI Flash parameter group and the SPI fingerprint sensor parameter group. The SPI Flash parameter group includes SPI frame format parameters, memory-mapped read operation parameters, and memory-mapped configurable command operation parameters; the SPI fingerprint sensor parameter group includes SPI frame format parameters and memory-mapped configurable command operation parameters. SPI frame format parameters include the clock division factor, SPI clock polarity, SPI clock phase, bit order, time from CS valid to data start, interval between two consecutive bytes, time from data end to CS invalid, and time from CS invalid to next CS valid. Memory-mapped read operation parameters include instruction length, instruction width, instruction code, address length, address width, parameter length, parameter width, parameter data, wait length, and data width. Memory-mapped configurable command operation parameters include instruction length, instruction width, instruction code source, parameter length, parameter width, parameter source, wait length, data direction, data length, data width, and data access location.

[0079] The RAM buffer has a capacity of 4KB of SRAM.

[0080] The SPI transceiver implements memory-mapped read and memory-mapped configurable commands.

[0081] The operation method implemented based on the above device includes Flash memory mapping read operation, Flash programming operation, and SPI fingerprint sensor image reading.

[0082] Flash memory map read operation:

[0083] A1.CPU initiates an AHB WRAP8 read operation on the address area 0x10000000-0x10FFFFFF;

[0084] A2. The bus controller maintains the bus and compares the target address contained in the AHB bus WRAP8 read operation with its internal address range. It determines that the operation is to read the SPI Flash. It then selects the SPI Flash parameter group and sends a read command to the SPI Flash, including the Flash storage address and a read length of 32 bytes.

[0085] A3. After receiving the command, the SPI transceiver reads the SPI Flash according to the SPI frame format parameters and memory map read operation parameters given by the parameter selector, and then responds to the bus controller with the 32-byte data read back.

[0086] A4. The bus controller responds to the received data to the AHB bus and releases the bus.

[0087] Flash programming operations:

[0088] B1. The CPU initiates a write operation to address 0x50000000-0x50000FFF, writing the data to be programmed into the RAM buffer.

[0089] B2. The CPU initiates a write operation to address 0x50004000;

[0090] B3. The bus controller maintains the bus, compares the target address 0x50004000 contained in the AHB write operation with its internal address range, determines that it is a configurable command operation for the SPI Flash, then selects the SPI Flash parameter group and sends a configurable command operation command to the SPI transceiver;

[0091] B4. After receiving the command, the SPI transceiver sends the programming instruction and programming address to the SPI Flash according to the SPI frame format parameters and memory mapping configurable command operation parameters given by the parameter selector (3). It then reads the data to be programmed from the RAM buffer and sends it to the SPI Flash. After the data is sent, it responds to the bus controller.

[0092] B5. After receiving the response, the bus controller responds to the AHB bus and releases the bus.

[0093] SPI fingerprint sensor read image:

[0094] C1.CPU initiates a write operation to address 0x50004004;

[0095] C2. The bus controller holds the bus, compares the target address 0x50004004 contained in the AHB write operation with its internal address range, determines that it is a configurable command operation for the SPI fingerprint sensor, then selects the SPI fingerprint sensor parameter group and sends the configurable command operation command to the SPI transceiver;

[0096] C3. After receiving the command, the SPI transceiver sends a read image command to the SPI fingerprint sensor according to the SPI frame format parameters and memory mapping configurable command operation parameters given by the parameter selector. It then reads data from the SPI fingerprint sensor and writes it into the RAM buffer. After the data reading is completed, it responds to the bus controller.

[0097] C4. After receiving the response, the bus controller responds to the AHB bus and releases the bus.

[0098] This embodiment automatically selects a parameter group according to an access address and is applied to an SPI transceiver to access a corresponding SPI peripheral, thereby achieving automatic switching between different types of SPI devices.

[0099] Note that the above are only preferred embodiments of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments, and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments and may include many other equivalent embodiments without departing from the concept of the present invention. The scope of the present invention is determined by the scope of the appended claims.

Claims

1. An SPI interface device capable of connecting multiple devices, characterized in that: Includes bus controller, SPI transceiver, parameter selector, RAM buffer; A bus controller is connected to the SPI transceiver, the parameter selector, and the RAM buffer, respectively, and is used to convert the read and write operations of the CPU bus into the read and write operations of the RAM buffer, the read and write operations of the parameter selector, and the selection signal or the working command of the SPI transceiver; A parameter selector is connected to the SPI transceiver, and is used to obtain the read and write operations and selection signals of the parameter selector converted by the bus controller, and select a parameter group corresponding to the SPI transceiver, and transmit the selected parameter group to the SPI transceiver; A RAM buffer, connected to the SPI transceiver, for caching the read and write operations of the RAM buffer converted by the bus controller; The SPI transceiver is used to obtain the working command of the SPI transceiver converted by the bus controller, read the cached read and write operations from the RAM buffer, and complete the operation of the external SPI peripheral according to the parameters transmitted by the parameter selector.

2. The SPI interface device capable of connecting multiple devices according to claim 1, characterized in that: The bus controller includes a register address interval and a plurality of peripheral address intervals; Register address interval, used to convert the CPU bus reading and writing the register address interval into the reading and writing operation of the RAM buffer or the reading and writing operation of the parameter selector; Several peripheral address intervals are used to convert the reading and writing of several peripheral address intervals by the CPU bus into selection signals of parameter selectors or working commands of SPI transceivers.

3. The SPI interface device capable of connecting multiple devices according to claim 1, characterized in that: The parameter selector includes several parameter groups, each of which includes memory mapping read operation parameters, memory mapping write operation parameters, memory mapping configurable command operation parameters, and SPI frame format parameters.

4. The SPI interface device capable of connecting multiple devices according to claim 1, characterized in that: The RAM buffer is also used to buffer data sent by the SPI transceiver.

5. The SPI interface device capable of connecting multiple devices according to claim 3, characterized in that: The operation of the SPI transceiver on the external SPI peripheral includes a memory mapping read operation, a memory mapping write operation, and a memory mapping configurable command operation.

6. A method for an SPI interface device capable of connecting multiple devices based on any one of claims 1 to 5, characterized in that: include: A1. The bus controller obtains the bus read operation initiated by the CPU bus; A2. The bus controller obtains the external SPI peripheral for the read operation by comparing the target address contained in the bus read operation with the internal register address interval and several peripheral address intervals, and selects the corresponding parameter group in the parameter selector to send a read command to the SPI transceiver; the read command includes the obtained external SPI peripheral, read address, and read length information; A3. The SPI transceiver receives the read command sent by the parameter selector, receives the parameters selected by the parameter selector, performs a read operation on the external SPI peripheral, and responds the read data to the bus controller; A4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

7. A method for an SPI interface device capable of connecting multiple devices based on any one of claims 1 to 5, characterized in that: include: B1. The bus controller obtains the bus write operation initiated by the CPU bus; B2. The bus controller obtains the external SPI peripheral for the write operation by comparing the target address contained in the bus write operation with the internal register address interval and several peripheral address intervals, and selects the corresponding parameter group in the parameter selector to send a write command to the SPI transceiver; the write command includes the obtained external SPI peripheral, write address, and write length information; B3. The SPI transceiver receives the write command sent by the parameter selector, receives the parameters selected by the parameter selector, performs a write operation on the external SPI peripheral, and responds to the written data to the bus controller; B4. The bus controller responds to the received data to the CPU bus and releases the CPU bus.

8. A method for an SPI interface device capable of connecting multiple devices based on any one of claims 1 to 5, characterized in that: include: C1. The bus controller obtains the bus write operation initiated by the CPU bus; C2. The bus controller obtains the external SPI peripheral for the write operation by comparing the target address contained in the bus write operation with the internal register address interval and several peripheral address intervals, and selects the corresponding parameter group in the parameter selector to send the operation command of the configurable command to the SPI transceiver; C3. The SPI transceiver receives the write command sent by the parameter selector. The SPI transceiver receives the parameter selected by the parameter selector and determines whether to read data from the RAM buffer. If so, it reads data from the RAM buffer. Read data and perform read operations on the external SPI peripherals obtained; If not, the data read from the external SPI peripheral is written into the RAM buffer; C4. The read data or written data is responded to the bus controller, and the bus controller responds the obtained data to the CPU bus and releases the CPU bus.

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