Circuit optimization method and system for digital domain calibration of temperature sensor

Abstract

The present invention provides a circuit optimization method and system for digital domain calibration of a temperature sensor. The method comprises: controlling negative temperature coefficient voltages Vbep and Vben by means of switch timing, generating a corresponding negative temperature coefficient Vbep voltage and a positive temperature coefficient Dvbe voltage, and outputting same to an input of a core circuit OTA of a Sigma-Delta ADC; and by means of a switch sampling circuit, generating Vintx by using integration, then inputting same into a comparator CMP to obtain a final ADC output, and then via a digital domain, feeding back the final ADC output to an analog domain to control a switch logic. By means of digital domain calibration, optimal temperature factors in different processes can be intelligently found, and desired ratio values can be obtained accurately. In addition, trim circuits to be implemented in the analog domain are reduced, significantly reducing the area of an analog layout and improving the temperature conversion precision of the chip.

Description

Circuit optimization method and system for digital domain correction temperature sensor Technical Field

[0001] The present invention relates to the technical field of electronic circuits, and in particular to a circuit optimization method and system for a digital domain correction temperature sensor. Background Art

[0002] Temperature sensor chips are widely used in life, including various electronic products, mobile phones, servers, temperature guns, air conditioners, medical equipment, etc.; because there are many different scenarios, different application scenarios have different requirements for temperature accuracy. For high-precision application scenarios, high-precision optimization technology is needed to achieve high-precision temperature sensing. Therefore, the demand for high precision is constantly increasing, and more high-precision technologies need to be proposed and implemented.

[0003] As shown in Figure 1, traditional temperature sensors generate VREF by amplifying Dvbe by a factor of A while controlling the output cycle in the digital domain. This ultimately creates a positive correlation between the ratio of the two and the temperature, ultimately converting the result into the output temperature. This A-fold amplification is typically achieved using analog switched capacitors or resistor ratios. Because trim capacitors use relatively small unit capacitance, small capacitors per unit area can lead to significant mismatch. Furthermore, there are numerous issues, such as nonlinear errors caused by the limited gain of the op amp itself, setup-and-hold accuracy issues, and leakage from the charge-sharing switch.

[0004] Patent document CN115514366A (application number: CN202211420962.3) discloses a timing control optimization method for a single-to-dual drive circuit in a temperature sensor. This method belongs to the field of temperature sensor power design technology. The temperature sensor chip includes: a temperature-to-single-ended voltage conversion circuit, which converts the temperature detected by the temperature sensor into a single-ended voltage; a single-to-dual drive circuit, connected to the temperature-to-single-ended voltage conversion circuit, which converts the single-ended voltage into a dual-ended voltage; an ADC circuit, connected to the single-to-dual drive circuit, which converts the voltage signal into a digital signal; and an LDO circuit, connected to the ADC circuit, which supplies power to the ADC circuit. However, this patent fails to solve existing technical problems.

[0005] Summary of the Invention

[0006] In view of the defects in the prior art, the object of the present invention is to provide a circuit optimization method and system for digital domain correction temperature sensor.

[0007] The circuit optimization method of the digital domain correction temperature sensor provided by the present invention includes:

[0008] Step 1: The negative temperature coefficient voltages Vbep and Vben are controlled by switching timing to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage, which are output to the input of the core circuit OTA of the Sigam-DeltADC;

[0009] Step 2: Through the switch sampling circuit, the integration generates Vintx, which is then input into the comparator CMP to obtain the final ADC output, and then fed back to the analog domain through the digital domain to control the switch logic.

[0010] Preferably, Dvbe and its derivative with respect to temperature are small, requiring multiple periodic conversions, or using a high multiple of the capacitance ratio to achieve a single conversion, so the T0 period is the conversion period of Vbe, T0=1, T1 is the conversion period of Dvbe, T1≥1, where T0+T1=U;

[0011] The ratio relationship between Vbe and Dvbe is determined according to the actual process. Temperature conversion requires the superposition of U complete cycles to generate VREF. The ratio of Dvbe and Vbep generated by digital control is equivalent to the OTA input, and the output proportional to Vbep is sent to the OTA. Finally, after digital domain processing, the output digital temperature Dout is obtained.

[0012] Preferably, a PTAT current I0 is generated by a Bandgap circuit, and the PTAT current is mirrored to Mp1 and Mp2 through Mp0, with the number ratio being Mp0:Mp1:Mp2=1:1:N; thus, the current ratio of the three paths is 1:1:N, and the current ratio flowing through transistors Q0 and Q1 is 1:N;

[0013] Since the ratio of the number of Q0 and Q1 is 1, the voltages Vbep and Vben with negative temperature coefficients are obtained respectively. After Vbep is amplified by the switching logic, it is superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); VREF=A*Vbep+Vben (1)

[0014] At the same time, the PTAT voltage DVbe is generated, as shown in formula (2);

[0015] Wherein, the expressions of Vbep and Vben are as shown in formula (3) and formula (4);

[0016] The ratio of A*DVbe and VREF voltage is converted by Sigma-Delta ADC to obtain a digital temperature Dout, as shown in formula (5);

[0017] Where A is the proportional coefficient implemented in the analog domain; K is the Boltzmann constant; T is the temperature; q is the charge of an electron; Is is the saturation current of the transistor; k1 and k2 are the slope and offset values ​​of the temperature converter, respectively.

[0018] Preferably, a fully differential Sigma-Delta ADC is used, and the initial state is set to 0 input signals at both ends of the OTA, and the common mode is Vcm. At this time, the result of the comparator is not counted in the digital domain. When the first large cycle U comes, the OTA input is forced to pass through the switching logic to obtain the OTA positive end as Vcm-Vbep and the negative end as Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation. The digital domain uses a 24-bit register ctrl_vbep[23:0] to count a value p, and another 24-bit register ctrl_tpq[23:0] to count a value w. At the same time, after the OTA integration, the result obtained by the comparator is 0, which is fed back to the digital control switch logic to generate a +Dvbe operation. The digital domain uses a 24-bit register ctrl_Dvbe[23:0] to count a value r;

[0019] Thus, through the switching logic, the positive end of the OTA is Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation will continue until the xth cycle, which just satisfies formula (6) or (7); Vcm≥Vcm+Vbep-x*Dvbe≥Vcm-0.5*Dvbe (6) Vcm+0.5*Dvbe≥Vcm+Vbep-x*Dvbe≥Vcm (7)

[0020] When formula (6) is just satisfied, T1 = 2x + 1; when formula (7) is just satisfied, T1 = 2x - 1; x means the cycle closest to the comparator flip, and the signal amplitude at this time is between (-0.5Dvbe, 0.5Dvbe); in order to prevent an erroneous judgment from occurring at a moment when the signal amplitude is small, resulting in loss of accuracy in the Sigma-Delta ADC, it is necessary to double x to 2x, thereby obtaining a ratio close to vbep / Dvbe. This ratio is related to temperature and is ultimately fed back to the digital register output, as well as the number of x times.

[0021] Preferably, the number of complete Dvbe and Vbe conversion cycles is U. If the entire temperature conversion has a total of v periodic conversions, the total number of temperature conversion cycles is U*v, wherein the number of vbep conversions is v*T0, then the value counted in the digital domain register ctrl_vbep[23:0] is p*v, the value counted in the digital domain register ctrl_tpq[23:0] is w*v, the number of Dvbe conversions is T1*v, and the value counted in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, where T1=m*T0;

[0022] The digital domain additionally configures registers k1 and k2, which serve as the slope and deviation values ​​of the temperature converter, respectively. The analog value Temp corresponding to the digital temperature Dout is finally obtained, as shown in formula (8);

[0023] Further simplification yields formula (9);

[0024] Let k0*w / r=k3*p / r, and substitute into formula (9) to obtain formula (10);

[0025] The digital domain temperature model is constructed in this way. Compared with formula (5), formula (5) is divided by Dvbe at both the top and bottom, and formula (11) is obtained by adjustment.

[0026] We can get Vbep / Dvbe≈m, where m is a value infinitely close to Vbep / Dvbe, and its accuracy is determined by the total number of temperature conversion cycles U*v. Therefore, only register configuration is required to achieve p / r=A. At the same time, the optimal slope k1 or k3 of different processes is adjusted according to the optimal temperature curve, and the deviation value k2 is finally determined by the register trim.

[0027] The denominator m in formula (10) is a value infinitely close to Vbep / Dvbe, which shows that it is a temperature-related quantity. The final linear curve is obtained by fitting according to the actual model, and u = (A) / (A + m) is positively correlated with temperature. According to the m value of different processes, digital domain correction is directly used to find the optimal A value, realizing a curvature to linear temperature conversion. At the same time, the optimal A value is found by function modeling, and the temperature conversion curve with the highest linearity is obtained.

[0028] The circuit optimization system for a digital domain correction temperature sensor provided by the present invention includes:

[0029] Module M1: controls the negative temperature coefficient voltages Vbep and Vben through switch timing to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage, which are output to the input of the core circuit OTA of Sigam-DeltADC;

[0030] Module M2: Through the switch sampling circuit, the integration generates Vintx, which is then input into the comparator CMP to obtain the final ADC output, and then fed back to the analog domain through the digital domain to control the switch logic.

[0031] Preferably, Dvbe and its derivative with respect to temperature are small, requiring multiple periodic conversions, or using a high multiple of the capacitance ratio to achieve a single conversion, so the T0 period is the conversion period of Vbe, T0=1, T1 is the conversion period of Dvbe, T1≥1, where T0+T1=U;

[0032] The ratio relationship between Vbe and Dvbe is determined according to the actual process. Temperature conversion requires the superposition of U complete cycles to generate VREF. The ratio of Dvbe and Vbep generated by digital control is equivalent to the OTA input, and the output proportional to Vbep is sent to the OTA. Finally, after digital domain processing, the output digital temperature Dout is obtained.

[0033] Preferably, a PTAT current I0 is generated by a Bandgap circuit, and the PTAT current is mirrored to Mp1 and Mp2 through Mp0, with the number ratio being Mp0:Mp1:Mp2=1:1:N; thus, the current ratio of the three paths is 1:1:N, and the current ratio flowing through transistors Q0 and Q1 is 1:N;

[0034] Since the ratio of the number of Q0 and Q1 is 1, the voltages Vbep and Vben with negative temperature coefficients are obtained respectively. After Vbep is amplified by the switching logic, it is superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); VREF=A*Vbep+Vben (1)

[0035] At the same time, the PTAT voltage DVbe is generated, as shown in formula (2);

[0036] Wherein, the expressions of Vbep and Vben are as shown in formula (3) and formula (4);

[0037] The ratio of A*DVbe and VREF voltage is converted by Sigma-Delta ADC to obtain a digital temperature Dout, as shown in formula (5);

[0038] Where A is the proportional coefficient implemented in the analog domain; K is the Boltzmann constant; T is the temperature; q is the charge of an electron; Is is the saturation current of the transistor; k1 and k2 are the slope and offset values ​​of the temperature converter, respectively.

[0039] Preferably, a fully differential Sigma-Delta ADC is used, and the initial state is set to 0 input signals at both ends of the OTA, and the common mode is Vcm. At this time, the result of the comparator is not counted in the digital domain. When the first large cycle U comes, the OTA input is forced to pass through the switch logic to obtain the OTA positive end Vcm-Vbep and the negative end Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation, and the digital domain uses a 24-bit register ctrl_vbep[23:0] to count a value p, and another 24-bit register ctrl_tpq[23:0] to count a value w. At the same time, after the OTA integration, the result obtained by the comparator is 0, which is fed back to the digital control switch logic to generate a +Dvbe operation, and the digital domain uses a 24-bit register ctrl_Dvbe[23:0] to count a value r;

[0040] Thus, through the switching logic, the positive end of the OTA is Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation will continue until the xth cycle, which just satisfies formula (6) or (7); Vcm≥Vcm+Vbep-x*Dvbe≥Vcm-0.5*Dvbe (6) Vcm+0.5*Dvbe≥Vcm+Vbep-x*Dvbe≥Vcm (7)

[0041] When formula (6) is just satisfied, T1 = 2x + 1; when formula (7) is just satisfied, T1 = 2x - 1; x means the cycle closest to the comparator flip, and the signal amplitude at this time is between (-0.5Dvbe, 0.5Dvbe); in order to prevent an erroneous judgment from occurring at a moment when the signal amplitude is small, resulting in loss of accuracy in the Sigma-Delta ADC, it is necessary to double x to 2x, thereby obtaining a ratio close to vbep / Dvbe. This ratio is related to temperature and is ultimately fed back to the digital register output, as well as the number of x times.

[0042] Preferably, the number of complete Dvbe and Vbe conversion cycles is U. If the entire temperature conversion has a total of v periodic conversions, the total number of temperature conversion cycles is U*v, wherein the number of vbep conversions is v*T0, then the value counted in the digital domain register ctrl_vbep[23:0] is p*v, the value counted in the digital domain register ctrl_tpq[23:0] is w*v, the number of Dvbe conversions is T1*v, and the value counted in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, where T1=m*T0;

[0043] The digital domain additionally configures registers k1 and k2, which serve as the slope and deviation values ​​of the temperature converter, respectively. The analog value Temp corresponding to the digital temperature Dout is finally obtained, as shown in formula (8);

[0044] Further simplification yields formula (9);

[0045] Let k0*w / r=k3*p / r, and substitute into formula (9) to obtain formula (10);

[0046] The digital domain temperature model is constructed in this way. Compared with formula (5), formula (5) is divided by Dvbe at both the top and bottom, and formula (11) is obtained by adjustment.

[0047] We can get Vbep / Dvbe≈m, where m is a value infinitely close to Vbep / Dvbe, and its accuracy is determined by the total number of temperature conversion cycles U*v. Therefore, only register configuration is required to achieve p / r=A. At the same time, the optimal slope k1 or k3 of different processes is adjusted according to the optimal temperature curve, and the deviation value k2 is finally determined by the register trim.

[0048] The denominator m in formula (10) is a value infinitely close to Vbep / Dvbe, which shows that it is a temperature-related quantity. The final linear curve is obtained by fitting according to the actual model, and u = (A) / (A + m) is positively correlated with temperature. According to the m value of different processes, digital domain correction is directly used to find the optimal A value, realizing a curvature to linear temperature conversion. At the same time, the optimal A value is found by function modeling, and the temperature conversion curve with the highest linearity is obtained.

[0049] Compared with the prior art, the present invention has the following beneficial effects:

[0050] (1) By adopting the digital domain correction method, we can achieve the integration of the optimal proportional adjustment ratio of the temperature curve completed in the analog domain and the final trim optimization for the product. Through digital domain correction, we can intelligently find the optimal temperature factor under different processes and obtain the desired proportional value more accurately. At the same time, it reduces the trim circuit to be implemented in the analog domain, greatly saves the area of ​​the analog layout, and improves the temperature conversion accuracy of the chip;

[0051] (2) The implementation principle of the method of the present invention is to realize temperature conversion in the traditional analog domain and then output it to digital output. The correction principle realized by the analog part is directly obtained by all processing in the digital domain, which can be more accurate, convenient and intelligent. At the same time, the principle of temperature conversion is simplified, and there is no need to artificially construct a reference voltage that is independent of temperature. By first obtaining the temperature characteristics of the process transistor, the desired parameter curvature change factor A can be quickly scanned with the help of software, and finally the optimal temperature conversion curve is obtained.

[0052] (3) Good process compatibility. Only a few register values ​​need to be manually changed to quickly adapt to different manufacturing processes and adapt to more high-precision applications. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Other features, objects and advantages of the present invention will become more apparent upon reading the detailed description of non-limiting embodiments with reference to the following drawings:

[0054] Figure 1 is a schematic diagram of a traditional temperature sensor circuit;

[0055] FIG2 is a schematic diagram of a temperature sensor circuit according to the present invention;

[0056] FIG3 is a schematic diagram of a temperature sensor circuit according to the present invention;

[0057] FIG4 is a timing diagram of the temperature sensor coefficient optimization operation of the present invention;

[0058] FIG5 is a schematic diagram showing the optimization principle of the temperature sensor of the present invention. DETAILED DESCRIPTION

[0059] The present invention will be described in detail below with reference to specific embodiments. The following examples will help those skilled in the art to further understand the present invention, but are not intended to limit the present invention in any form. It should be noted that, for those skilled in the art, several changes and improvements can be made without departing from the scope of the present invention. These all fall within the scope of protection of the present invention.

[0060] Example 1

[0061] The present invention provides a circuit optimization method for a digital domain correction temperature sensor, comprising:

[0062] As shown in Figure 1, this is a common temperature sensor circuit schematic. The PTAT current I0 is generated by the bandgap circuit, and then the PTAT current is mirrored to Mp1 and Mp2 through Mp0. The number ratio is Mp0:Mp1:Mp2=1:1:N. Therefore, the current ratio of the three paths is 1:1:N, so the current ratio flowing through transistors Q0 and Q1 is 1:N. Since the ratio of the number of Q0 and Q1 is 1, voltages Vbep and Vben with negative temperature coefficients are obtained respectively, and after Vbep is amplified by A, it can be superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); at the same time, a PTAT voltage DVbe is generated, as shown in formula (2), where A is the proportional coefficient implemented in the analog domain; Vbep and Vben can be obtained respectively, as shown in formula (3) and formula (4); where K is the Boltzmann constant, T is the temperature, q is the charge of an electron, and Is is the saturation current of the transistor; then, the ratio of A*DVbe and VREF voltage is converted by Sigma-Delta ADC to obtain a digital temperature Dout, as shown in formula (5); where k1 and k2 are Boltzmann constants, k1≈600, k2≈273. VREF=A*Vbep+Vben (1)

[0063] Figures 2 and 3 show the circuit optimization principle of the digital domain correction temperature sensor proposed in the present invention. First, the generated Vbep and Vben are controlled through a specific switching timing sequence to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage, which are output to the OTA input. The OTA is the core circuit of the Sigma-Delt ADC. Through the switch sampling circuit, after the timing operation shown in Figure 4, the integration generates Vintx, which is then input to the comparator CMP to obtain the final ADC output. This is then fed back to the analog domain through the digital domain to control the switching logic. To achieve high precision through multiple cycles, the analog domain requires large area trimming. If 8-bit precision capacitor ratio is required, 8-bit capacitors are required to achieve precision adjustment, which greatly increases the layout area. By only using 1x capacitor ratio technology, Axes are used for digital domain implementation. The digital domain can generate multi-digit decimal values ​​with less cost to achieve high-precision ratio. The digital part does not suffer from the offset problem of the analog part, and the register value can be adjusted to achieve precise ratio. Ultimately, a more optimal temperature characteristic curve is adjusted. In actual operation, digital domain optimization is more convenient and intelligent than analog domain optimization.

[0064] The specific digital domain operation method is as follows: As shown in Figure 4, the U duty shown in the figure represents a complete conversion cycle of the Vbe voltage and Dvbe voltage. Because Dvbe and its temperature derivative are generally small, multiple conversion cycles are required, or a high-multiplier capacitor ratio is used to achieve a single conversion. Therefore, the T0 cycle is the Vbe conversion cycle, T0 = 1, and T1 is the Dvbe conversion cycle, T1 ≥ 1. Where T0 + T1 = U, and the specific ratio relationship between Vbe and Dvbe is determined by the actual process. Generally, temperature conversion requires the superposition of U complete cycles to generate VREF. The ratio of Dvbe and Vbep is generated through digital control and is equivalent to the OTA input. At the same time, it is output to the OTA in proportion to Vbep. Finally, after digital domain processing, the output digital temperature Dout is obtained.

[0065] Because a fully differential Sigma-Delta ADC is used, the initial state is set to zero input signals at both ends of the OTA, with a common mode of Vcm. At this time, the comparator result is not included in the digital domain. When the first large cycle U arrives, the OTA input is forced through the switching logic to obtain a positive terminal of Vcm-Vbep and a negative terminal of Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation. The digital domain uses a 24-bit register ctrl_vbep[23:0] to enter a value of p, and another 24-bit register ctrl_tpq[23:0] to enter a value of w. At the same time, after OTA integration, the comparator result is 0, which is fed back to the digital control switching logic to generate a +Dvbe operation. The digital domain uses a 24-bit register ctrl_Dvbe[23:0] to enter a value of r. Thus, through the switching logic, the positive end of the OTA is obtained as Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation is continued until the xth cycle, which just satisfies formula (6) or (7); when formula (6) is just satisfied, T1=2x+1; when formula (7) is just satisfied, T1=2x-1; x means the cycle closest to the comparator flip, and the signal amplitude at this time is between (-0.5Dvbe, 0.5Dvbe). In order to ensure that an incorrect judgment occurs at the moment when the signal amplitude is small, which will cause the Sigma-Delta ADC to lose accuracy, it is necessary to double x to get 2x, thereby obtaining a ratio close to vbep / Dvbe. This ratio can be related to temperature and is finally fed back to the digital register output and the number of times x.

[0066] The number of complete Dvbe and Vbe conversion cycles is U. Assuming that the entire temperature conversion has a total of v cycle conversions, the total number of temperature conversion cycles is U*v. Therefore, the number of vbep conversions is v*T0=v, so the value recorded in the digital domain register ctrl_vbep[23:0] is p*v, and the value recorded in the digital domain register ctrl_tpq[23:0] is w*v. The number of Dvbe conversions is T1*v, so the value recorded in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, where T1=m*T0. Since U changes with each cycle, m may be a decimal. The digital domain additionally configures registers k1 and k2 as the slope and offset values ​​of the temperature converter, respectively. The analog value Temp corresponding to the final digital temperature Dout is shown in formula (8).

[0067] Further simplification yields formula (9), setting k0*w / r = k3*p / r. Substituting this into formula (9) yields formula (10), which constructs the digital domain temperature modulus. Comparing formula (5), dividing formula (5) by Dvbe both above and below, and adjusting to obtain formula (11), yields Vbep / Dvbe≈m, where m is a number that continuously approaches Vbep / Dvbe. Its accuracy is determined by the total number of temperature conversion cycles, U*v. However, this only requires register configuration to achieve p / r = A. At the same time, the optimal slope k1 or k3 for different processes can be adjusted based on the optimal temperature curve, and the deviation k2 can also be ultimately determined by the register trim.

[0068] Furthermore, as shown in formula (10), the denominator m is itself a value infinitely close to Vbep / Dvbe, which indicates that it is a temperature-dependent quantity. The actual model can be fitted to obtain the final linear curve, realizing that u = (A) / (A + m) is positively correlated with temperature, as shown in Figure 5.

[0069] Instead of constructing a temperature-independent VREF voltage in the analog domain, the optimal A value can be directly found using digital domain correction based on the m value of different processes, achieving a curvature-to-linear temperature conversion. This not only reduces the construction of a portion of the reference voltage in principle, but also enables software-assisted function modeling to quickly find the optimal A value in practice, resulting in the most linear temperature conversion curve. Vcm ≥ Vcm + Vbep-x*Dvbe ≥ Vcm-0.5*Dvbe (6) Vcm + 0.5*Dvbe ≥ Vcm + Vbep-x*Dvbe ≥ Vcm (7)

[0070] Explanation of names: NMOS: N-type field-effect transistor (abbreviated as Mn); PMOS: P-type field-effect transistor (abbreviated as Mp); PTAT: proportional to absolute temperature; ADC: analog-to-digital converter; OTA: transconductance amplifier.

[0071] Example 2

[0072] The present invention also provides a circuit optimization system for a digital domain correction temperature sensor. The circuit optimization system for the digital domain correction temperature sensor can be implemented by executing the process steps of the circuit optimization method for the digital domain correction temperature sensor. That is, those skilled in the art can understand the circuit optimization method for the digital domain correction temperature sensor as a preferred implementation of the circuit optimization system for the digital domain correction temperature sensor.

[0073] The circuit optimization system for a digital domain correction temperature sensor provided by the present invention includes:

[0074] Module M1: controls the negative temperature coefficient voltages Vbep and Vben through switch timing to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage, which are output to the input of the core circuit OTA of Sigam-DeltADC;

[0075] Module M2: Through the switch sampling circuit, the integration generates Vintx, which is then input into the comparator CMP to obtain the final ADC output, and then fed back to the analog domain through the digital domain to control the switch logic.

[0076] Preferably, Dvbe and its derivative with respect to temperature are small, requiring multiple periodic conversions, or using a high multiple of the capacitance ratio to achieve a single conversion, so the T0 period is the conversion period of Vbe, T0=1, T1 is the conversion period of Dvbe, T1≥1, where T0+T1=U;

[0077] The ratio relationship between Vbe and Dvbe is determined according to the actual process. Temperature conversion requires the superposition of U complete cycles to generate VREF. The ratio of Dvbe and Vbep generated by digital control is equivalent to the OTA input, and the output proportional to Vbep is sent to the OTA. Finally, after digital domain processing, the output digital temperature Dout is obtained.

[0078] Preferably, a PTAT current I0 is generated by a Bandgap circuit, and the PTAT current is mirrored to Mp1 and Mp2 through Mp0, with the number ratio being Mp0:Mp1:Mp2=1:1:N; thus, the current ratio of the three paths is 1:1:N, and the current ratio flowing through transistors Q0 and Q1 is 1:N;

[0079] Since the ratio of the number of Q0 and Q1 is 1, the voltages Vbep and Vben with negative temperature coefficients are obtained respectively. After Vbep is amplified by the switching logic, it is superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); VREF=A*Vbep+Vben (1)

[0080] At the same time, the PTAT voltage DVbe is generated, as shown in formula (2);

[0081] Wherein, the expressions of Vbep and Vben are as shown in formula (3) and formula (4);

[0082] The ratio of A*DVbe and VREF voltage is converted by Sigma-Delta ADC to obtain a digital temperature Dout, as shown in formula (5);

[0083] Where A is the proportional coefficient implemented in the analog domain; K is the Boltzmann constant; T is the temperature; q is the charge of an electron; Is is the saturation current of the transistor; k1 and k2 are the slope and offset values ​​of the temperature converter, respectively.

[0084] Preferably, a fully differential Sigma-Delta ADC is used, and the initial state is set to 0 input signals at both ends of the OTA, and the common mode is Vcm. At this time, the result of the comparator is not counted in the digital domain. When the first large cycle U comes, the OTA input is forced to pass through the switch logic to obtain the OTA positive end Vcm-Vbep and the negative end Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation, and the digital domain uses a 24-bit register ctrl_vbep[23:0] to count a value p, and another 24-bit register ctrl_tpq[23:0] to count a value w. At the same time, after the OTA integration, the result obtained by the comparator is 0, which is fed back to the digital control switch logic to generate a +Dvbe operation, and the digital domain uses a 24-bit register ctrl_Dvbe[23:0] to count a value r;

[0085] Thus, through the switching logic, the positive end of the OTA is Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation will continue until the xth cycle, which just satisfies formula (6) or (7); Vcm≥Vcm+Vbep-x*Dvbe≥Vcm-0.5*Dvbe (6) Vcm+0.5*Dvbe≥Vcm+Vbep-x*Dvbe≥Vcm (7)

[0086] When formula (6) is just satisfied, T1 = 2x + 1; when formula (7) is just satisfied, T1 = 2x - 1; x means the cycle closest to the comparator flip, and the signal amplitude at this time is between (-0.5Dvbe, 0.5Dvbe); in order to prevent an erroneous judgment from occurring at a moment when the signal amplitude is small, resulting in loss of accuracy in the Sigma-Delta ADC, it is necessary to double x to 2x, thereby obtaining a ratio close to vbep / Dvbe. This ratio is related to temperature and is ultimately fed back to the digital register output, as well as the number of x times.

[0087] Preferably, the number of complete Dvbe and Vbe conversion cycles is U. If the entire temperature conversion has a total of v periodic conversions, the total number of temperature conversion cycles is U*v, wherein the number of vbep conversions is v*T0, then the value counted in the digital domain register ctrl_vbep[23:0] is p*v, the value counted in the digital domain register ctrl_tpq[23:0] is w*v, the number of Dvbe conversions is T1*v, and the value counted in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, where T1=m*T0;

[0088] The digital domain additionally configures registers k1 and k2, which serve as the slope and deviation values ​​of the temperature converter, respectively. The analog value Temp corresponding to the digital temperature Dout is finally obtained, as shown in formula (8);

[0089] Further simplification yields formula (9);

[0090] Let k0*w / r=k3*p / r, and substitute into formula (9) to obtain formula (10);

[0091] The digital domain temperature model is constructed in this way. Compared with formula (5), formula (5) is divided by Dvbe at both the top and bottom, and formula (11) is obtained by adjustment.

[0092] We can get Vbep / Dvbe≈m, where m is a value infinitely close to Vbep / Dvbe, and its accuracy is determined by the total number of temperature conversion cycles U*v. Therefore, only register configuration is required to achieve p / r=A. At the same time, the optimal slope k1 or k3 of different processes is adjusted according to the optimal temperature curve, and the deviation value k2 is finally determined by the register trim.

[0093] The denominator m in formula (10) is a value infinitely close to Vbep / Dvbe, which shows that it is a temperature-related quantity. The final linear curve is obtained by fitting according to the actual model, and u = (A) / (A + m) is positively correlated with temperature. According to the m value of different processes, digital domain correction is directly used to find the optimal A value, realizing a curvature to linear temperature conversion. At the same time, the optimal A value is found by function modeling, and the temperature conversion curve with the highest linearity is obtained.

[0094] In the description of this application, it should be understood that the terms "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0095] Those skilled in the art will appreciate that, in addition to implementing the system, device, and various modules provided by the present invention in purely computer-readable program code, it is entirely possible to implement the same program in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, embedded microcontrollers, and the like by logically programming the method steps. Therefore, the system, device, and various modules provided by the present invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; the modules for implementing various functions can also be considered both software programs for implementing the method and structures within the hardware component.

[0096] The above describes specific embodiments of the present invention. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art may make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. The embodiments of this application and the features in the embodiments may be combined with each other in any manner unless there is a conflict.

Claims

1. A circuit optimization method for a digital domain correction temperature sensor, characterized in that: include: Step 1: The negative temperature coefficient voltages Vbep and Vben are controlled by switch timing to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage and output them to the input of the core circuit OTA of the Sigam-Delt ADC; Step 2: Through the switch sampling circuit, the integration generates Vintx and then inputs it into the comparator CMP to obtain the final ADC output, which is then fed back to the analog domain through the digital domain to control the switch logic.

2. The circuit optimization method of the digital domain correction temperature sensor according to claim 1, characterized in that: Dvbe and its derivative to temperature are small, requiring multiple periodic conversions, or using a high multiple of the capacitance ratio to achieve a conversion, so the T0 period is the conversion period of Vbe, T0 = 1, T1 is the conversion period of Dvbe, T1 ≥ 1, where T0 + T1 = U; The ratio relationship between Vbe and Dvbe is determined according to the actual process. The temperature conversion needs to be superimposed on U complete cycles to generate VREF. The ratio of Dvbe and Vbep is generated through digital control and is equivalent to the OTA input. At the same time, it is output to the OTA in proportion to Vbep. Finally, it is processed in the digital domain to obtain the output digital temperature Dout.

3. The circuit optimization method of the digital domain correction temperature sensor according to claim 2, characterized in that: The PTAT current I0 is generated through the Bandgap circuit, and the PTAT current is mirrored to Mp1 and Mp2 through Mp0, and the number ratio is Mp0:Mp1:Mp2=1:1:N; thus, the current ratio of the three paths is 1:1:N, and the current ratio flowing through the transistors Q0 and Q1 is 1:N; Since the ratio of the number of Q0 and Q1 is 1, voltages Vbep and Vben with negative temperature coefficients are obtained respectively, and after Vbep is amplified by the switch logic, it is superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); VREF=A*Vbep+Vben (1) At the same time, the PTAT voltage DVbe is generated, as shown in formula (2); Wherein, the expressions of Vbep and Vben are as shown in formula (3) and formula (4); The Sigma-Delta ADC converts the ratio of A*DVbe and VREF voltage to obtain a digital temperature Dout, as shown in formula (5); Among them, A is the proportional coefficient realized in the analog domain; K is the Boltzmann constant; T is the temperature; q is the charge of an electron; Is is the saturation current of the transistor; k1 and k2 are the slope and deviation values ​​of the temperature converter respectively.

4. The circuit optimization method of the digital domain correction temperature sensor according to claim 3, characterized in that: A fully differential Sigma-Delta ADC is used. The initial state is set to 0 input signals at both ends of the OTA, and the common mode is Vcm. At this time, the result of the comparator is not counted in the digital domain. When the first large cycle U comes, the OTA input is forced to pass through the switch logic to obtain the OTA positive end Vcm-Vbep and the negative end Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation. The digital domain uses a 24-bit register ctrl_vbep[23:0] to count a value p, and another 24-bit register ctrl_tpq[23:0] to count a value w. At the same time, after OTA integration, the result obtained by the comparator is 0, which is fed back to the digital control switch logic to generate a +Dvbe operation. The digital domain uses a 24-bit register ctrl_Dvbe[23:0] to count a value r; Therefore, through the switch logic, the positive end of OTA is Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation will continue until the xth cycle, which just satisfies formula (6) or (7); Vcm≥Vcm+Vbep-x*Dvbe≥Vcm-0.5*Dvbe (6) Vcm+0.5*Dvbe≥Vcm+Vbep-x*Dvbe≥Vcm (7) When formula (6) is just satisfied, T1=2x+1; when formula (7) is just satisfied, T1=2x-1; x means a cycle closest to the comparator flip, and the signal amplitude at this time is between (-0.5Dvbe, 0.5Dvbe); in order to prevent an erroneous judgment from occurring when the signal amplitude is small, resulting in a loss of accuracy in the Sigma-Delta ADC, x needs to be doubled to 2x, thereby obtaining a ratio close to vbep / Dvbe, which is related to temperature and is ultimately fed back to the digital register output, as well as the number of x.

5. The circuit optimization method of the digital domain correction temperature sensor according to claim 4, characterized in that: The number of complete Dvbe and Vbe conversion cycles is U. If the entire temperature conversion has a total of v periodic conversions, the total number of temperature conversion cycles is U*v, of which the number of vbep conversions is v*T0. The value counted in the digital domain register ctrl_vbep[23:0] is p*v, the value counted in the digital domain register ctrl_tpq[23:0] is w*v, the number of Dvbe conversions is T1*v, and the value counted in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, T1=m*T0; The digital domain additionally configures registers k1 and k2, which are used as the slope and deviation value of the temperature converter respectively. The analog value Temp corresponding to the digital temperature Dout is finally obtained, as shown in formula (8); Further simplifying to get formula (9); Let k0*w / r=k3*p / r, substitute into formula (9), and we get formula (10); Thus, the temperature model in the digital domain is constructed and compared with formula (5), formula (5) is divided by Dvbe both above and below, and formula (11) is obtained by adjustment; Vbep / Dvbe≈m, where m is a value infinitely close to Vbep / Dvbe, and its accuracy is determined by the total number of temperature conversion cycles U*v; therefore, only register configuration is required to achieve p / r=A, and at the same time, the optimal slope k1 or k3 of different processes is adjusted according to the optimal temperature curve, and the deviation value k2 is finally determined by the register trim; The denominator m in formula (10) is a value infinitely close to Vbep / Dvbe, so it is a temperature-related quantity. The final linear curve is fitted according to the actual model, realizing that u=(A) / (A+m) is positively correlated with temperature. According to the m value of different processes, digital domain correction is directly used to find the optimal A value, realizing a curvature-to-linear temperature conversion. At the same time, function modeling is used to find the optimal A value, and the temperature conversion curve with the highest linearity is obtained.

6. A circuit optimization system for a digital domain correction temperature sensor, characterized in that: include: Module M1: Controls the negative temperature coefficient voltages Vbep and Vben through switch timing to generate the corresponding negative temperature coefficient Vbep voltage and positive temperature coefficient Dvbe voltage and outputs them to the input of the core circuit OTA of the Sigam-Delt ADC; Module M2: Through the switch sampling circuit, the integration generates Vintx and then inputs it into the comparator CMP to obtain the final ADC output, which is then fed back to the analog domain through the digital domain to control the switch logic.

7. The circuit optimization system of the digital domain correction temperature sensor according to claim 6, characterized in that: Dvbe and its derivative to temperature are small, requiring multiple periodic conversions, or using a high multiple of the capacitance ratio to achieve a conversion, so the T0 period is the conversion period of Vbe, T0 = 1, T1 is the conversion period of Dvbe, T1 ≥ 1, where T0 + T1 = U; The ratio relationship between Vbe and Dvbe is determined according to the actual process. The temperature conversion needs to be superimposed on U complete cycles to generate VREF. The ratio of Dvbe and Vbep is generated through digital control and is equivalent to the OTA input. At the same time, it is output to the OTA in proportion to Vbep. Finally, it is processed in the digital domain to obtain the output digital temperature Dout.

8. The circuit optimization system for a digital domain correction temperature sensor according to claim 7, characterized in that: The PTAT current I0 is generated through the Bandgap circuit, and the PTAT current is mirrored to Mp1 and Mp2 through Mp0, and the number ratio is Mp0:Mp1:Mp2=1:1:N; thus, the current ratio of the three paths is 1:1:N, and the current ratio flowing through the transistors Q0 and Q1 is 1:N; Since the number ratio of Q0 and Q1 is 1, the voltages Vbep and Vben with negative temperature coefficients are obtained respectively, and After Vbep is amplified by the switch logic, it is superimposed with Vben to generate a reference voltage VREF that is independent of temperature, as shown in formula (1); VREF=A*Vbep+Vben (1) At the same time, the PTAT voltage DVbe is generated, as shown in formula (2); Wherein, the expressions of Vbep and Vben are as shown in formula (3) and formula (4); The Sigma-Delta ADC converts the ratio of A*DVbe and VREF voltage to obtain a digital temperature Dout, as shown in formula (5); Among them, A is the proportional coefficient realized in the analog domain; K is the Boltzmann constant; T is the temperature; q is the charge of an electron; Is is the saturation current of the transistor; k1 and k2 are the slope and deviation values ​​of the temperature converter respectively.

9. The circuit optimization system for a digital domain correction temperature sensor according to claim 8, characterized in that: A fully differential Sigma-Delta ADC is used. The initial state is set to 0 input signals at both ends of the OTA, and the common mode is Vcm. At this time, the result of the comparator is not counted in the digital domain. When the first large cycle U comes, the OTA input is forced to pass through the switch logic to obtain the OTA positive end Vcm-Vbep and the negative end Vcm+Vbep. At this time, the T0 cycle is a -Vbep operation. The digital domain uses a 24-bit register ctrl_vbep[23:0] to count a value p, and another 24-bit register ctrl_tpq[23:0] to count a value w. At the same time, after OTA integration, the result obtained by the comparator is 0, which is fed back to the digital control switch logic to generate a +Dvbe operation. The digital domain uses a 24-bit register ctrl_Dvbe[23:0] to count a value r; Therefore, through the switch logic, the positive end of OTA is Vcm-Vbep+Dvbe and the negative end is Vcm+Vbep-Dvbe. If the comparator result is still 0 at this time, the +Dvbe operation will continue until the xth cycle, which just satisfies formula (6) or (7); Vcm≥Vcm+Vbep-x*Dvbe≥Vcm-0.5*Dvbe (6) Vcm+0.5*Dvbe≥Vcm+Vbep-x*Dvbe≥Vcm (7) When formula (6) is just satisfied, T1=2x+1; when formula (7) is just satisfied, T1=2x-1; x means the cycle closest to the comparator flip, and the signal amplitude is between (-0.5Dvbe, 0.5Dvbe) at this time; in order to prevent an erroneous judgment from occurring at a time when the signal amplitude is small, resulting in a loss of accuracy of the Sigma-Delta ADC, x needs to be doubled to 2x, thereby obtaining a ratio close to vbep / Dvbe, which is related to temperature. The final feedback is in the register output of the number, and the number of times x.

10. The circuit optimization system of the digital domain correction temperature sensor according to claim 9, characterized in that: The number of complete Dvbe and Vbe conversion cycles is U. If the entire temperature conversion has a total of v periodic conversions, the total number of temperature conversion cycles is U*v, of which the number of vbep conversions is v*T0. The value counted in the digital domain register ctrl_vbep[23:0] is p*v, the value counted in the digital domain register ctrl_tpq[23:0] is w*v, the number of Dvbe conversions is T1*v, and the value counted in the digital domain register ctrl_Dvbe[23:0] is r*T1*v, T1=m*T0; The digital domain additionally configures registers k1 and k2, which are used as the slope and deviation value of the temperature converter respectively. The analog value Temp corresponding to the digital temperature Dout is finally obtained, as shown in formula (8); Further simplifying to get formula (9); Let k0*w / r=k3*p / r, substitute into formula (9), and we get formula (10); Thus, the temperature model in the digital domain is constructed and compared with formula (5), formula (5) is divided by Dvbe both above and below, and formula (11) is obtained by adjustment; Vbep / Dvbe≈m, where m is a value infinitely close to Vbep / Dvbe, and its accuracy is determined by the total number of temperature conversion cycles U*v; therefore, only register configuration is required to achieve p / r=A, and at the same time, the optimal slope k1 or k3 of different processes is adjusted according to the optimal temperature curve, and the deviation value k2 is finally determined by the register trim; The denominator m in formula (10) is a value infinitely close to Vbep / Dvbe, so it is a temperature-related quantity. The final linear curve is fitted according to the actual model, realizing that u=(A) / (A+m) is positively correlated with temperature. According to the m value of different processes, digital domain correction is directly used to find the optimal A value, realizing a curvature-to-linear temperature conversion. At the same time, function modeling is used to find the optimal A value, and the temperature conversion curve with the highest linearity is obtained.

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