Data processing method and apparatus

Abstract

Provided in the present application are a data processing method and apparatus. The method comprises: after a first management unit sends a first request message corresponding to a first write request message, until the first management unit receives a first response message, if other write requests having the same Cacheline address as the first write request message are received, writing a plurality of pieces of data having the same Cacheline address into a cache space corresponding to the first management unit, and then writing the data into a storage space corresponding to a second management unit. Thus, the interaction with a second management unit during the process of writing a plurality of pieces of data is reduced, thereby effectively reducing a data processing delay, and increasing the overall efficiency of data processing.

Description

Data processing method and device

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of China on September 25, 2023, with application number 202311246217.6 and application name “Data Processing Method and Device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The embodiments of the present application relate to the field of data storage, and more particularly to a data processing method and apparatus. Background Art

[0003] In modern computing systems, multi-core chips utilize shared memory to improve inter-process communication efficiency. A series of memory consistency models (Memory Consistency Models) have been defined around the order of read and write operations in software and the visible order of their results on the hardware. Common models include the Sequential Consistency Model (SC), Total Store Order (TSO), and the Relaxed Sequential Model (RM). When these two models interact, when a sequence of SO (Strict Order) requests with order constraints on the strong side enters the weak side, the weak side must ensure that the visible order of the final processing results meets the expectations of the strong side. Using a fully serialized approach on the weak side significantly impacts bandwidth. A typical scenario is the interaction between multi-core chips and peripherals, where the communication bandwidth between them is crucial to system performance. Therefore, efficiently processing SO requests becomes a key factor limiting bandwidth.

[0004] Summary of the Invention

[0005] The present application provides a data processing method and device, which can improve the processing efficiency of SO requests to a certain extent.

[0006] To achieve the above objectives, this application adopts the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a data processing method. The method includes: a first management unit receives a first write request message, the first write request message is used to request that first data be written into a target cache line; the first management unit responds to the first write request message and sends a first request message to a second management unit, the first request message is used to request the permission of the target cache line; if the first management unit receives at least one second write request before receiving a first response message fed back by the second management unit, wherein the at least one second write request is used to request that at least one second data be written into the target cache line, then after receiving the first response message, the first management unit caches the first data and the at least one second data into a first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permission of the target cache line; the first management unit writes the target data in the first storage space to the second management unit, the target data including the first data and the at least one second data.

[0008] In this way, the present application can achieve parallel processing of consecutive small packets of data with the same cacheline address within a certain range, thereby improving data processing efficiency. In addition, the present application adopts a method of parallel processing on the memory side for small packets of data with the same cacheline address before writing them to the storage side, thereby reducing bus data interaction between the memory side and the storage side, thereby reducing processing latency and improving data write bandwidth.

[0009] In one possible implementation, the first management unit includes a first management subnode and a second management subnode. After receiving a first response message, the first management unit caches the first data and at least one data in a first storage space corresponding to the first management unit, including: the first management subnode sends a second request message to the second management subnode in response to the first response message, the second request message is used to indicate that the permission of the target cacheline has been obtained, and is used to request that the first data be written to the target cacheline; the first management subnode receives a second response message fed back by the second management subnode, the second response message is used to indicate that writing of the first data is allowed; the first management subnode requests the second management subnode to write at least one second data in response to the second response message, and in the process of the first management subnode requesting the second management subnode to write at least one second data, the second management subnode obtains the first data and writes the first data to the first storage space; the second management subnode obtains the second data and writes the second data to the second storage space.

[0010] In this way, the present application completes the handshake process for small packets with the same cacheline address inside the memory side (which can also be understood as the upstream node) to reduce interaction with the bus, reduce latency, and improve bandwidth.

[0011] In one possible implementation, requesting the second management subnode to write at least one second data includes: the first management subnode sends a third request message to the second management subnode, the third request message is used to request permission for the target cacheline; the first management subnode receives a third response message sent by the second management subnode, the third response message is used to indicate permission for the target cacheline; the first management subnode sends a fourth request message to the second management subnode in response to the third response message, the fourth request message is used to indicate writing a single second data to the target cacheline; the second management subnode obtains the single second data in response to the fourth request message, and writes the single second data to the first storage space after the first data is written to the first storage space.

[0012] In this way, the present application can realize parallel processing of small packets with the same cacheline address within the module on the memory side, which can effectively improve data processing efficiency.

[0013] In one possible implementation, the method further includes: if the first management unit does not receive any other request to write data to the target cacheline before receiving the first response message fed back by the second management unit, the first management unit requests the second management unit to write the third data to the target cacheline. In this way, if the application does not receive a small packet with the same cacheline address within the merge window, it can process it according to the original IO Cache mode to avoid introducing negative returns.

[0014] For example, small packets with the same cacheline address received outside the Merge window are also processed according to the original IO Cache mode.

[0015] In one possible implementation, the first management unit requests the second management unit to write the third data to the target cacheline, including: the first management unit sends a fifth request message to the second management unit, the fifth request message being used to request that the first data be written to the target cacheline; the first management unit, in response to the fifth response message sent by the second management unit, sends a data sending indication message to the data sending module, the data sending indication message being used to instruct the data sending module to send the first data to the second management unit; the fifth response message being used to indicate permission to write the first data. In this way, the present application interacts with the management unit on the storage side to write data to the storage space.

[0016] In a second aspect, the present application provides a data processing device, comprising a first management unit and a second management unit; the first management unit is used to receive a first write request message, the first write request message being used to request that first data be written into a target cache line; the first management unit is also used to send a first request message to the second management unit in response to the first write request message, the first request message being used to request permission for the target cache line; the first management unit is also used to cache the first data and the at least one second data into a first storage space corresponding to the first management unit after receiving the first response message if the first management unit receives at least one second write request before receiving a first response message fed back by the second management unit, wherein the at least one second write request is used to request that at least one second data be written into the target cache line; wherein the first response message is used to indicate permission for the target cache line; the first management unit is also used to write target data in the first storage space to the second management unit, the target data including the first data and at least one second data.

[0017] In one possible implementation, the first management unit includes a first management subnode and a second management subnode. The first management subnode is used to send a second request message to the second management subnode in response to a first response message, where the second request message is used to indicate that permission to the target cacheline has been obtained and to request that the first data be written to the target cacheline; the first management subnode is also used to receive a second response message fed back by the second management subnode, where the second response message is used to indicate that writing of the first data is allowed; the first management subnode is also used to request the second management subnode to write at least one second data in response to the second response message, and in the process of the first management subnode requesting the second management subnode to write at least one second data, the second management subnode obtains the first data and writes the first data into the first storage space; the second management subnode is used to obtain the second data and write the second data into the second storage space.

[0018] In one possible implementation, the first management subnode is further configured to send a third request message to the second management subnode, where the third request message is used to request permission for the target cacheline; the first management subnode is further configured to receive a third response message sent by the second management subnode, where the third response message is used to indicate permission for the target cacheline; the first management subnode is further configured to send a fourth request message to the second management subnode in response to the third response message, where the fourth request message is used to indicate writing a single second data into the target cacheline; the second management subnode is further configured to obtain the single second data in response to the fourth request message, and write the single second data into the first storage space after the first data is written into the first storage space.

[0019] In a possible implementation, the first management unit is further configured to, before receiving the first response message fed back by the second management unit, request the second management unit to write the third data into the target cacheline if no other request for writing data into the target cacheline is received.

[0020] In one possible implementation, the first management unit is used to send a fifth request message to the second management unit, where the fifth request message is used to request that the first data be written into the target cacheline; the first management unit is also used to send a data sending indication message to the data sending module in response to the fifth response message sent by the second management unit, where the data sending indication message is used to instruct the data sending module to send the first data to the second management unit; and the fifth response message is used to indicate that writing of the first data is allowed.

[0021] In a third aspect, embodiments of the present application provide an electronic device. The electronic device includes: one or more processors; a memory; and one or more computer programs, wherein the one or more computer programs are stored in the memory and, when executed by the one or more processors, cause the electronic device to perform instructions of the method of the first aspect or any possible implementation of the first aspect.

[0022] In a fourth aspect, an embodiment of the present application provides a computer-readable medium for storing a computer program, wherein the computer program includes instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0023] In a fifth aspect, an embodiment of the present application provides a computer program comprising instructions for executing the method in the first aspect or any possible implementation of the first aspect.

[0024] In the sixth aspect, an embodiment of the present application provides a chip comprising one or more interface circuits and one or more processors; the interface circuit is used to receive signals from a memory of an electronic device and send signals to the processor, the signals including computer instructions stored in the memory; when the processor executes the computer instructions, the electronic device executes the instructions of the method in the first aspect or any possible implementation of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments of the present application. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0026] FIG1 is a flow chart showing an exemplary data processing method;

[0027] FIG2 is a flow chart showing an exemplary data processing method;

[0028] FIG3 is a flow chart showing an exemplary data processing method;

[0029] FIG4 is a flow chart of a data processing method in an embodiment of the present application;

[0030] FIG5 is a flow chart of a data processing method in an embodiment of the present application;

[0031] FIG6 is a flow chart of a data processing method in an embodiment of the present application;

[0032] FIG7 is a flow chart of a data processing method in an embodiment of the present application;

[0033] FIG8 is a schematic structural diagram of an exemplary device. DETAILED DESCRIPTION

[0034] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0035] The term "and / or" in this article is merely a description of the association relationship between associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

[0036] In the description and claims of the embodiments of this application, the terms "first" and "second" are used to distinguish different objects, rather than to describe a specific order of objects. For example, the terms "first target object" and "second target object" are used to distinguish different objects, rather than to describe a specific order of objects.

[0037] In the embodiments of this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described as "exemplary" or "for example" in the embodiments of this application should not be interpreted as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0038] In the description of the embodiments of this application, unless otherwise specified, "multiple" means two or more. For example, "multiple processing units" means two or more processing units; "multiple systems" means two or more systems.

[0039] FIG1 is a flow chart showing an exemplary data processing method in the prior art. Referring to FIG1 , the method specifically includes:

[0040] Node A is the node on the Model-0 side, node C is the upstream boundary node, and node B is the downstream node.

[0041] 1) Node A sends a write request sequence (including SO0Req and SO1Req) with order requirements to node C.

[0042] 2) Node C sends a write request serially to node B.

[0043] Specifically, in response to SO0Req (Request), Node C sends Req0 to Node B. After receiving DBID Rep0 (Response) from Node B, Node C sends Req1 corresponding to SO1Req to Node B and receives DBID Rep1 from Node B. DBID Rep contains the location of the received data (which can also be understood as the location where the data is written, which is in the storage space of Node B).

[0044] 3) Node C and node B perform data write operations in parallel.

[0045] For example, node C sends Write Data0 and Write Data1 to node B to request writing corresponding data. After writing the data into the storage space, node B sends Comp0 (Completion) and Comp1 to node C to indicate that the corresponding data has been written.

[0046] 4) Node C sends ACK to node B.

[0047] For example, after receiving the completion response, the upstream node C needs to send an Ack (Acknowledge) signal to node B in the order of write requests (i.e., SO0Req and SO1Req) to inform the downstream (i.e., node B) that the corresponding request results are globally visible, and the visible order of the request results is guaranteed through sequential Ack handshakes.

[0048] In the approach shown in Figure 1, the DBID handshake ensures that data on Node B is written correctly. That is, Node B writes the received data to the cache in the order in which the Reqs were received. This allows for partial parallel processing of SO request sequences. However, this approach still presents the following issues:

[0049] 1) The operations related to the next data packet need to wait for the DBID response corresponding to the previous data packet before continuing processing. Therefore, there is still a serial processing part, and the latency of waiting for the response is high, resulting in low request bandwidth.

[0050] 2) Downstream node B needs to handshake with upstream node C multiple times to ensure the order of data writing. This process has a large delay and many interactions, which causes communication burden and affects the efficiency of data writing.

[0051] FIG2 is a flow chart of another data processing method of the prior art, which is exemplified by FIG2 . Specifically, the method includes: based on the hardware consistency protocol, extending the consistency range, incorporating the intersection of the two storage models into the cache consistency domain on the side of the weak order model, completing sequential processing at the nodes at the intersection, and ensuring the globally visible order of the results.

[0052] 1) Node C at the storage model interface receives a sequence of SO requests (including SO Req0, SO Req1, etc.) from node A on the strong-order model side, and determines that the result visibility order on the weak-order model side must meet the strong-order requirements.

[0053] 2) After receiving the SO request sequence, node C concurrently obtains the E state (also known as CompUC, an exclusive state, indicating that the corresponding cacheline is allocated to node C and unavailable to other modules) from downstream node B, completing the migration of sequential processing nodes. During this process, the CC domain (Cache Coherency) is expanded (i.e., node B's CC domain is extended to node C), giving the boundary node C the ability to process coherently, thereby ensuring the visible order of request results.

[0054] After node C completes sequential processing, it no longer needs to ensure the order through serial handshakes with downstream nodes. Therefore, requests can be processed in parallel on the weak order model side, thereby improving the request bandwidth between models.

[0055] In conjunction with Figure 2, the following uses the data processing flow diagram shown in Figure 3 as an example for a brief explanation. In this scenario, when node A (IO device, such as a PCIe controller) interacts with the chip SOC, the IO side SO write request enters the SOC side. Node C, as the boundary node between IO and SOC, is used to complete sequential processing and cooperate with the internal node of the SOC (i.e., node B) to complete the request, thereby improving processing bandwidth. The submodule within node C that implements this function is called the IO Cache module. Please refer to Figure 3, which specifically includes:

[0056] 1) Node C receives multiple write requests (So0Req, SO1Req, etc.) sent by node A.

[0057] 2) Based on multiple write requests, node C obtains E State from downstream node B in parallel (including sending CleanUqnique (for requesting E STATE), receiving ComRsp (for receiving E state) and feeding back Comp ACK (for responding to having received E state)), and expands CC Domain to complete the migration of sequential processing nodes.

[0058] After node C obtains permission (i.e., E state), it sends a write-back request (i.e., Write BACK) to node B according to the request order on the PCIe side to ensure the global visibility order of the request results and complete the request processing in parallel.

[0059] This method applies a hardware consistency solution to complete global visibility management of operation results at the upstream node, avoiding processing order through upstream and downstream handshakes, thereby achieving parallel processing of requests and improving bandwidth. However, this method cannot achieve parallel processing when faced with a sequence of consecutive SO requests with the same cacheline address.

[0060] This application provides a data processing method that can realize parallel processing of a sequence of consecutive SO requests with the same cacheline address. FIG4 is a flow chart of a data processing method provided by an embodiment of this application. Please refer to FIG4 , which specifically includes but is not limited to the following steps:

[0061] S401: A first management unit receives a first write request message, where the first write request message is used to request writing first data into a target cacheline.

[0062] Exemplarily, PCIe (i.e., node A in the embodiment of the present application) sends a write request message to the first management unit to write data into the target Cacheline. The first management unit (i.e., node C in the embodiment of the present application) receives the write request message and obtains the Cacheline address indicated in the message. Among them, the Cacheline address indicated in the write request message is all or part of the address of the Cacheline. In the embodiment of the present application, multiple consecutive small data packets are used as an example for explanation. Therefore, the small data corresponding to the small data packets involved in the embodiment of the present application are all data with a granularity smaller than one Cacheline. For example, taking the length of a Cacheline as 128Bytes (only for illustrative purposes, which can be set according to actual needs and is not limited in this application), the corresponding data packet corresponding to the write data with a length of less than 128Bytes is called a small data packet. For example, a data packet with a write data length of 64Bytes is a small data packet (referred to as a small packet in the embodiment of the present application, and will not be repeated below).

[0063] S402: The first management unit sends a first request message to the second management unit in response to the first write request message, where the first request message is used to request permission for a target cacheline.

[0064] Exemplarily, after the first management unit receives the write request message and obtains the target cacheline address to be written, it sends a first request message (also called an E State acquisition request message, or a cacheline state acquisition request, etc., which is not limited in this application) to the second management unit (i.e., node B in the embodiment of the present application). The first request message is used to request the state of the target cacheline (which can also be understood as permission).

[0065] In an embodiment of the present application, the second management unit is used to manage the status (i.e., permissions) of all cachelines. It should be noted that a cacheline can only be used by one node (e.g., node C) at the same time. That is, the usage permission of a cacheline is enabled to a node. When the node has the usage permission of the target cacheline, other nodes cannot access (including writing and reading) the data in the target cacheline. In an embodiment of the present application, when a node requests the permission of a single cacheline (also called usage permission) from the second management unit, the second management unit detects whether the target cacheline is available, which can also be understood as whether the status of the cacheline is unlocked, or whether the permissions of the cacheline are not assigned to any node. In one example, if the second management unit detects that the target cacheline is currently available, that is, the target cacheline is not occupied by other nodes or modules, the second management unit can send the E state of the target cacheline to the first management unit to indicate that the first management unit is allowed to use the target cacheline. At the same time, the second management unit records the permission status of the target cacheline as unavailable and the permissions are assigned to the first management unit. In another example, if the second management unit detects that the target cacheline is in an unavailable state, it waits for the target cacheline to become available (i.e., other nodes return the cacheline's usage rights) before sending the target cacheline's E state to the first management unit, indicating that the first management unit is allowed to use the target cacheline. Simultaneously, the second management unit records the target cacheline's permission state as unavailable and assigns the permission to the first management unit.

[0066] Therefore, in an embodiment of the present application, there is a certain waiting period between the first management unit sending the first write request message and receiving the first response message (i.e., E state). This waiting period is called a merge (parallel) window in the embodiment of the present application, that is, the starting point of the merge window is the moment corresponding to the first management unit sending the first write request message, and the end point is the moment corresponding to the receipt of the first response message.

[0067] S403, if the first management unit receives at least one second write request before receiving the first response message fed back by the second management unit, wherein the at least one second write request is used to request to write at least one second data into the target cacheline, then after receiving the first response message, the first management unit caches the first data and the at least one data into the first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permission of the target cacheline.

[0068] For example, in an embodiment of the present application, if the first management unit receives at least one second write request with the same cacheline address as the first write request within the merge window, that is, before receiving the first response message, the first management unit can execute an internal interaction process to cache the data requested to be written to the same cacheline into the storage space corresponding to the first management unit.

[0069] For example, if at least one second write request with the same address is not received within the merge window, or if other write requests with different cacheline addresses are received, the IO Cache process in the prior art is followed.

[0070] It should be noted that the "packets with the same cacheline address" described in the embodiments of the present application means that the cacheline addresses to be written indicated by multiple packets are within the same cacheline. For example, assume that the address of the first cacheline is 0 to 127 bytes. The cacheline address indicated by packet 1 is 0 to 63 bytes, and the cacheline address indicated by packet 2 is 64 to 127 bytes, then the cacheline addresses indicated by packet 1 and packet 2 are in the same cacheline (i.e., the first cacheline). Accordingly, packet 1 and packet 2 are packets with the same cacheline address.

[0071] S404: The first management unit writes target data in the first storage space to the second management unit, where the target data includes first data and at least one second data.

[0072] For example, the first management unit writes multiple packets with the same cacheline address received within the merge window into the cache, and then writes the data in the cache to the second management unit. This enables parallel processing of multiple packets with the same cacheline address, reduces bus interactions, lowers latency, and improves bandwidth (i.e., throughput).

[0073] The data processing method in the embodiment of the present application is described in detail below using a specific embodiment. FIG5 is a flow chart illustrating an exemplary data processing method. In this example, a small packet with the same cacheline address is not received in the merge window. Referring to FIG5 , the method specifically includes but is not limited to the following steps:

[0074] S501: Node A sends a first write request message to node C.

[0075] Exemplarily, when node A (e.g., PCIe) needs to write data, it sends a first write request message to node C. The first write request message is used to request the writing of first data. The first write request message includes, but is not limited to, the first cacheline address corresponding to the first data and other control information. Optionally, the control information includes, but is not limited to, a write instruction and a command identifier.

[0076] Exemplarily, the first cacheline address is the cacheline address to which node A desires the first data to be written. Optionally, the first cacheline address includes, but is not limited to, a first starting address and a first length. The first starting address indicates the starting position of the cacheline to be written, and the length indicates the length of the data. For example, if the first cacheline address includes a starting address of 0 and a length of 64, the indicated first cacheline address is 0 to 63 bytes. In other words, the cacheline address requested to be written by the first write request message is 0 to 63 bytes.

[0077] For example, a write indication is used to request data writing. The command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command indication to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0078] S502: Node C sends a cacheline status request message to node B.

[0079] Exemplarily, node C obtains the first cacheline address and other control information in response to the first write request message.

[0080] Node C sends a Cacheline State Request message (e.g., a Clean Unique message) to node B, requesting the E state of the target cacheline to which the first cacheline belongs (see above for details). The Cacheline State Request message includes, but is not limited to, node C's identification information, the first cacheline address, and an E state request indication.

[0081] Exemplarily, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the E state used to request the target cacheline, which can also be understood as requesting permission to use the target cacheline. The target cacheline is the cacheline where the first cacheline is located, and this description will not be repeated below.

[0082] S503: Node B sends a cacheline status response message to node C.

[0083] For example, as described above, node B can detect the state of the target cacheline. When determining that the state of the target cacheline is available, node B sends a cacheline state response message to node C based on the identification information of node C. The message includes but is not limited to: the E State of the target cacheline, which is used to indicate that the permission of the target cacheline is allocated to node C.

[0084] Exemplarily, node B records the state of the target cacheline, for example, records the correspondence between the target cacheline and the identification information of node C, to indicate that the current usage permission of the target cacheline is allocated to node C.

[0085] In the embodiment of the present application, the time period between S502 and S503 is the merge window. In this example, no other small packets with the same cacheline address are received within the merge window as an example for explanation.

[0086] S504: Node C sends a Write Back message to node B.

[0087] Exemplarily, node C determines that it has obtained the right to use the target cacheline (which can also be understood as access rights) based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of the first data and to indicate the release of the cacheline's E state. That is, in this embodiment of the present application, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the right to use the cacheline.

[0088] The Write Back message includes, but is not limited to: Write Back indication information, identification information of node C, and the first cacheline address. The Write Back indication information is used to request writing data.

[0089] S505 , node B sends a CompDBID (Data buffer Identification) message to node C.

[0090] Exemplarily, in response to the Write Back message, node B reclaims the permission of the target cacheline corresponding to node C based on the identification information of node C and the first cacheline address.

[0091] Node B then determines the corresponding data cache address in the storage space (also referred to as cache space) corresponding to node B based on the first cacheline address. Node B sends a CompDBID message to node C, indicating permission to write the first data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0092] S506: Node C sends an ACK message to node A.

[0093] For example, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message may also be referred to as a first write response message, which indicates permission to write the first data. The ACK message includes, but is not limited to, a command identifier, node B's identifier, and a data cache address.

[0094] S507: Node A sends a write message to node B.

[0095] Exemplarily, in response to the ACK message, node A sends a write message (also referred to as a W dat message, not limited in this application) to node B based on the identification information of node B. The write message is used to instruct node B to write data to a specified address. The write message includes, but is not limited to, the first data, the DBID, a command identifier, etc.

[0096] S508: Node B writes the first data into the cache space.

[0097] Exemplarily, in response to the write message, node B writes the first data into the cache space indicated by DBID. Afterwards, node B may write the data in the cache space into the memory. The specific implementation method may refer to the existing technology and will not be described in detail in this application.

[0098] FIG6 is a flowchart illustrating an exemplary data processing method. In this example, a small packet with the same cacheline address is received in the merge window as an example. Referring to FIG6 , the method specifically includes but is not limited to the following steps:

[0099] S601-1, node A sends a first write request message to node C.

[0100] For example, when node A (e.g., PCIe) needs to write data, it sends a first write request message to node C. The first write request message is used to request the writing of first data. The first write request message includes, but is not limited to, the first cacheline address corresponding to the first data and other control information. Optionally, the control information includes, but is not limited to, a write instruction and command identifier 1.

[0101] Exemplarily, the first cacheline address is the cacheline address to which node A desires the first data to be written. Optionally, the first cacheline address includes, but is not limited to, a first starting address and a first length. The first starting address indicates the starting position of the cacheline to be written, and the length indicates the length of the data. For example, if the first cacheline address includes a starting address of 0 and a length of 64, the indicated first cacheline address is 0 to 63 bytes. In other words, the cacheline address requested to be written by the first write request message is 0 to 63 bytes.

[0102] For example, a write indication is used to request data writing. The command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command indication to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0103] S602-1, the requesting node sends a cacheline status request message 1 to node B.

[0104] Exemplarily, the requesting node in node C (which may also be referred to as a first management subunit, which is not limited in this application) obtains the first cacheline address and other control information in response to the first write request message.

[0105] The requesting node sends a Cacheline State Request Message 1 (e.g., a Clean Unique message) to Node B, requesting the E state of the target cacheline to which the first cacheline belongs (see above for details). Cacheline State Request Message 1 includes, but is not limited to, node C's identification information, the first cacheline address, and an E state request indication.

[0106] Exemplarily, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the E state used to request the target cacheline, which can also be understood as requesting permission to use the target cacheline. The target cacheline is the cacheline where the first cacheline is located, and this description will not be repeated below.

[0107] S601-2, node A sends a first write request message to node C.

[0108] In this example, node A continues to send a second write request message to node C. The second write request message is used to request the writing of the second data. The second write request message includes, but is not limited to, the second cacheline address corresponding to the second data and other control information. Optionally, the control information includes, but is not limited to, a write instruction and command identifier 2.

[0109] Exemplarily, the second cacheline address is the cacheline address to which node A desires the second data to be written. Optionally, the second cacheline address includes, but is not limited to, a second start address and a second length. The second start address indicates the start position of the cacheline to be written, and the length indicates the length of the data. For example, if the second cacheline address includes a start address of 64 and a length of 64, the indicated second cacheline address is 64 to 127 bytes. In other words, the cacheline address requested to be written by the second write request message is 64 to 127 bytes.

[0110] For example, a write indication is used to request data writing. The command identifier is used to identify the request message, which can also be understood as identifying the session. Accordingly, all subsequent interactions performed in response to the write request message must carry the command indication to indicate that the interaction information carrying the command identifier is performed in response to the write request.

[0111] S603-1, node B sends a cacheline status response message 1 to node C.

[0112] Exemplarily, as described above, node B can detect the state of the target cacheline. When determining that the state of the target cacheline is available, node B sends a cacheline state response message 1 to node C based on the identification information of node C. The message includes but is not limited to: the E State of the target cacheline, which is used to indicate that the permission of the target cacheline is allocated to node C.

[0113] Exemplarily, node B records the state of the target cacheline, for example, records the correspondence between the target cacheline and the identification information of node C, to indicate that the current usage permission of the target cacheline is allocated to node C.

[0114] In the embodiment of the present application, the time period between S602 and S603 is the merge window. In this example, the case where other packets with the same cacheline address are received within the merge window is used as an example for explanation. It should be noted that this example only uses the case where another packet with the same cacheline address is received within the merge window as an example for explanation. In other embodiments, more packets with the same cacheline address may be received, and the processing method is similar. This application will not further illustrate each one of them.

[0115] It should be noted that in this example, in order to distinguish the steps executed for different write request messages, the "X-1" step in this example represents the step executed for the first write request message, and "X-2" represents the step executed for the second write request message.

[0116] S604-1, the requesting node sends a write-back message 1 to the cache node.

[0117] Exemplarily, after receiving the second write request message, the requesting node determines, based on the cacheline address indicated in the second write request message, that the second cacheline address indicated in the second write request message and the first cacheline address indicated in the first write request message belong to the same target cacheline. In other words, the first data (also referred to as the first data packet) and the second data (also referred to as the second data packet) are data written to the same cacheline. This can be understood as the first data packet and the second data packet being consecutively received within the merge window and having the same cacheline address.

[0118] It should be noted that the embodiments of the present application are described only by taking the cacheline addresses of the first data and the second data as consecutive addresses. In other embodiments, the first data and the second data may be discontinuous addresses in the same cacheline, and the present application does not limit this.

[0119] Exemplarily, the requesting node determines that a packet with the same cacheline address is received in the merge window, and then executes the internal node data processing flow to achieve parallel processing of the packets with the same cacheline address.

[0120] Continuing to refer to FIG6 , in the internal node data processing process, the requesting node determines whether it has obtained the usage rights (also understood as access rights) of the target cacheline based on the cacheline status response message. Unlike the process in FIG5 , in this example, the requesting node sends a Write Back message 1 to the cache node (also referred to as an IO data cache node, which is not limited in this application). In other words, node C still holds the usage rights of the target cacheline and does not return it to node B for the time being. In this way, while node C is performing internal process processing on multiple data to be written to the target cacheline, other modules or units cannot access the target cacheline, thereby preventing data read and write errors.

[0121] The Write Back message 1 includes, but is not limited to, Write Back indication information and the first cacheline address. The Write Back message is used to request the writing of the first data and to indicate that permission to use the target cacheline described by the first cacheline has been obtained. Optionally, the Write Back message may also carry an E State to indicate that permission to use the target cacheline described by the first cacheline has been obtained, which is not limited in this application.

[0122] S605-1, the cache node sends a CompDBID message 1 to the requesting node.

[0123] Exemplarily, in response to Write Back Message 1, the cache node determines a corresponding data cache address in the cache node's corresponding storage space based on the first cacheline address. The cache node then sends CompDBID Message 1 to the requesting node, indicating permission to write the first data. CompDBID Message 1 includes, but is not limited to, a command identifier and the data cache address.

[0124] S606-1, the requesting node sends an ACK message 1 to node A.

[0125] Exemplarily, in response to the CompDBID message, the requesting node sends ACK message 1 to node A. ACK message 1 may also be referred to as a first write response message, indicating permission to write the first data. The ACK message includes, but is not limited to, a command identifier, identification information of node C, and a data cache address.

[0126] S607-1, node A sends a write message 1 to node C.

[0127] For example, in response to ACK message 1, node A sends a write message (also referred to as a W dat message, not limited in this application) to node C based on the identification information of node C. The write message is used to instruct the writing of data to a specified address. The write message includes, but is not limited to, the first data, the DBID, a command identifier, etc.

[0128] S608-1, the cache node writes the first data into the cache space.

[0129] Exemplarily, the cache node writes the first data into the cache space indicated by the DBID in response to the write message.

[0130] In this embodiment of the present application, to achieve order preservation for cacheline addresses, the cache node will schedule the next CleanUnique request only after receiving the Write Back message corresponding to the previous write request and replying with a CompDBID message. That is, as shown in Figure 6, after executing S605-1, the cache node can begin executing S602-2, the data processing flow corresponding to the second write request, which specifically includes:

[0131] S602-2: The requesting node sends a cacheline status request message 2 to node B.

[0132] Exemplarily, the requesting node in node C (which may also be referred to as a first subunit, not limited in this application) obtains the second cacheline address and other control information in response to the second write request message.

[0133] The requesting node sends a Cacheline State Request Message 2 (e.g., a Clean Unique message) to the cache node, requesting the E state of the target cacheline to which the first cacheline belongs (see above for details). Cacheline State Request Message 2 includes, but is not limited to, the first cacheline address and the E state request indication.

[0134] S603-2: The cache node sends a cacheline status response message 2 to the requesting node.

[0135] Exemplarily, as described above, in S604-1, the cache node obtains the E state of the target cacheline. Accordingly, in this step, the cache node sends a cacheline state response message 2 to the requesting node. The message includes but is not limited to: the E state of the target cacheline, which is used to indicate that the permission of the target cacheline is allocated to the requesting node.

[0136] S604-2: The requesting node sends a write-back message to the cache node.

[0137] Exemplarily, the requesting node determines that it has obtained permission to use the target cacheline (which can also be understood as access permission) based on Cacheline Status Response Message 2. The requesting node sends a Write Back Message 2 to the cache node (which may also be referred to as an IO data cache node, not limited in this application). Write Back Message 2 includes, but is not limited to, Write Back indication information and the second cacheline address. Write Back Message 2 is used to request the writing of the second data.

[0138] S605-2: The cache node sends a CompDBID message 2 to the requesting node.

[0139] Exemplarily, in response to Write Back Message 2, the cache node determines a corresponding data cache address in the cache node's corresponding storage space based on the second cacheline address. The cache node then sends CompDBID Message 2 to the requesting node, indicating that writing the second data is permitted. CompDBID Message 2 includes, but is not limited to, a command identifier and a data cache address.

[0140] In an embodiment of the present application, in order to ensure visibility order between data, the cache node controls the reply CompDBID to achieve visibility order. In another embodiment of the present application, for the case of the same cacheline address, the cache node can only reply to the CompDBID corresponding to the next write request after receiving the previous write data (i.e., receiving the write message). In other words, after the cache node receives the write back message, it records the order of the received write back messages. The cache node receives the corresponding write message in the order of the received write back messages, which can also be understood as continuing to execute the following process only after receiving the corresponding write data.

[0141] For example, as shown in Figure 6, S606-1 to S607-1 corresponding to the first write request and S602-2 to S604-2 corresponding to the second write request are executed in parallel. The cache node will receive the Write Back message 1 corresponding to the first write request before receiving the Write Back message 2 corresponding to the second write request. Accordingly, the order of the command identifiers recorded by the cache node (which can also be recorded in other information orders, which is not limited by this application) is the command identifier corresponding to the Write Back message 1 (for example, the first command identifier) ​​and the command identifier corresponding to the Write Back message 2 (for example, the second command identifier). Therefore, the cache node will execute S605-2 only after receiving the data requested to be written by the Write Back message 1 (i.e., the first data). For example, assuming that S604-2 is executed before S607-1, the cache node receives the Write Back message 2. Based on the order of the currently recorded command identifiers (i.e., the first command identifier), the cache node determines that the write data corresponding to the command identifier 1 (which can also be understood as the first write message or the Write Back message 1) has not yet been received. The cache node then stores the corresponding information (i.e., the second command identifier) ​​in the order in which the write-back messages were received. Subsequently, the cache node receives write message 1 and, based on the command identifier, determines the data requested by the write message. Corresponding to write-back message 1, the cache node writes the first data in write message 1 to the storage address allocated for the first data in S605-1 (i.e., the address indicated by the DBID). The cache node then executes S605-2.

[0142] S606-2, the requesting node sends an ACK message 2 to node A.

[0143] Exemplarily, in response to CompDBID message 2, the requesting node sends ACK message 2 to node A. ACK message 2 may also be referred to as a second write response message, indicating permission to write the second data. ACK message 2 includes, but is not limited to, a command identifier, identification information of node C, and a data cache address.

[0144] S607-2, node A sends a write message 2 to node C.

[0145] Exemplarily, in response to ACK message 1, node A sends a write message 2 (also referred to as a W dat message, not limited in this application) to node C based on the identification information of node C. Write message 2 is used to instruct that data be written to a specified address. Write message 2 includes, but is not limited to, the second data, the DBID, a command identifier, and the like.

[0146] S608-1, the cache node writes the second data into the cache space.

[0147] Exemplarily, in response to write message 2 , the cache node writes the second data into the cache space indicated by the DBID.

[0148] S609: The cache node sends a write-back message 3 to node B.

[0149] Exemplarily, after writing the first data and the second data, the cache node sends a Write Back message 3 to node B, requesting that the target data (including the first data and the second data) be written. The Write Back message 3 includes, but is not limited to, a third command identifier, Write Back indication information, identification information of node C, and a third cacheline address (including the first cacheline address and the second cacheline address). The Write Back indication information is used to request that the data be written.

[0150] S610 , node B sends CompDBID message 3 to node C.

[0151] Exemplarily, in response to Write Back message 3, node B determines the corresponding data cache address in the storage space corresponding to node B based on the third cacheline address. Node B then sends CompDBID message 3 to node C, indicating that writing of the target data is permitted. CompDBID message 3 includes, but is not limited to, the third command identifier, node B's identification information, and the data cache address.

[0152] S611: The cache node sends a write message 3 to node B.

[0153] Exemplarily, in response to CompDBID message 3, the cache node in node C sends a write message 3 (also referred to as a W dat message, not limited herein) to node B based on the identification information of node B. Write message 3 is used to instruct the writing of data to a specified address. Write message 3 includes, but is not limited to, target data, DBID, and a third command identifier.

[0154] S612: Node B writes the first data into the cache space.

[0155] Exemplarily, in response to the write message 3, the node B writes the target data into the cache space indicated by the DBID.

[0156] FIG7 is a flowchart illustrating an exemplary data processing method. In this example, a packet with the same cacheline address is received outside the merge window. Referring to FIG7 , the method specifically includes but is not limited to the following steps:

[0157] S701-1, node A sends a first write request message to node C.

[0158] S702-1, the node sends a cacheline status request message 1 to node B.

[0159] S703-1, node B sends a cacheline status response message to node C.

[0160] In this example, if node C (specifically, the requesting node in node C) does not receive a packet with the same cacheline address in merge window 1 corresponding to the first write request, processing continues according to the flow in FIG5 .

[0161] For details not described, please refer to Figures 5 and 6 and will not be repeated here.

[0162] S704-1, node C sends a Write Back message to node B.

[0163] Exemplarily, node C determines that it has obtained the right to use the target cacheline (which can also be understood as access rights) based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of the first data and to indicate the release of the cacheline's E state. That is, in this embodiment of the present application, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the right to use the cacheline.

[0164] The Write Back message includes, but is not limited to: Write Back indication information, identification information of node C, and the first cacheline address. The Write Back indication information is used to request writing data.

[0165] S705 - 1 , node B sends a CompDBID message to node C.

[0166] Exemplarily, in response to the Write Back message, node B reclaims the permission of the target cacheline corresponding to node C based on the identification information of node C and the first cacheline address.

[0167] Node B then determines the corresponding data cache address in the storage space (also referred to as cache space) corresponding to node B based on the first cacheline address. Node B sends a CompDBID message to node C, indicating permission to write the first data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0168] S706-1, node C sends an ACK message to node A.

[0169] For example, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message may also be referred to as a first write response message, which indicates permission to write the first data. The ACK message includes, but is not limited to, a command identifier, node B's identifier, and a data cache address.

[0170] S707-1, node A sends a write message to node B.

[0171] Exemplarily, in response to the ACK message, node A sends a write message (also referred to as a W dat message, not limited in this application) to node B based on the identification information of node B. The write message is used to instruct node B to write data to a specified address. The write message includes, but is not limited to, the first data, the DBID, a command identifier, etc.

[0172] S708-1, Node B writes the first data into the cache space.

[0173] Exemplarily, in response to the write message, node B writes the first data into the cache space indicated by DBID. Afterwards, node B may write the data in the cache space into the memory. The specific implementation method may refer to the existing technology and will not be described in detail in this application.

[0174] In this embodiment of the present application, to achieve order preservation for cacheline addresses, the cache node will schedule the next CleanUnique request only after receiving the Write Back message corresponding to the previous write request and replying with a CompDBID message. That is, as shown in Figure 7, after executing S705-1, the cache node can begin executing S702-2, the data processing flow corresponding to the second write request, which specifically includes:

[0175] S702-2: Node C sends a cacheline status request message to node B.

[0176] Exemplarily, node C obtains the second cacheline address and other control information in response to the second write request message.

[0177] Node C sends a cacheline state request message (e.g., a Clean Unique message) to node B, requesting the E state of the target cacheline to which the second cacheline address belongs (see above for details). The cacheline state request message includes, but is not limited to, node C's identification information, the second cacheline address, and an E state request indication.

[0178] Exemplarily, the identification information of node C can be the ID of node C, etc., which is not limited in this application. The E State request indicates the E state used to request the target cacheline, which can also be understood as requesting permission to use the target cacheline. The target cacheline is the cacheline where the first cacheline is located, and this description will not be repeated below.

[0179] S703-2, Node B sends a cacheline status response message to node C.

[0180] For example, as described above, node B can detect the state of the target cacheline. When determining that the state of the target cacheline is available, node B sends a cacheline state response message to node C based on the identification information of node C. The message includes but is not limited to: the E State of the target cacheline, which is used to indicate that the permission of the target cacheline is allocated to node C.

[0181] In the embodiment of the present application, in S704-1, node C has returned the right to use the target cacheline. Accordingly, in this step, node B detects that the target cacheline is currently in an available state.

[0182] Exemplarily, node B records the state of the target cacheline, for example, records the correspondence between the target cacheline and the identification information of node C, to indicate that the current usage permission of the target cacheline is allocated to node C.

[0183] S704-2, node C sends a Write Back message to node B.

[0184] Exemplarily, node C determines that it has obtained the right to use the target cacheline (which can also be understood as access rights) based on the cacheline status response message. Node C sends a Write Back message to node B to request the writing of the second data and to indicate the release of the cacheline's E state. That is, in this embodiment of the present application, if no consecutive write requests to the same cacheline address are received within the merge window, node C releases the cacheline's right to use.

[0185] The Write Back message includes, but is not limited to: Write Back indication information, identification information of node C, and the second cacheline address. The Write Back indication information is used to request writing data.

[0186] It should be noted that in merge window 2 (i.e., between node C executing S702-2 and S703-2), if node C receives a write request with the same cacheline address as the second write request message, it will process the second write request and other write requests with the same cacheline address according to the node internal data processing flow in Figure 6. The description will not be repeated here, and the specific steps can be referred to in Figure 6.

[0187] S705 - 2 , node B sends a CompDBID message to node C.

[0188] Exemplarily, in response to the Write Back message, node B reclaims the permission of the target cacheline corresponding to node C based on the identification information of node C and the second cacheline address, that is, marks the target cacheline as available.

[0189] Node B then determines the corresponding data cache address in the storage space (also referred to as cache space) corresponding to node B based on the second cacheline address. Node B sends a CompDBID message to node C, indicating permission to write the second data. The CompDBID message includes, but is not limited to, a command identifier, node B's identification information, and the data cache address.

[0190] S706-2, node C sends an ACK message to node A.

[0191] Exemplarily, in response to the CompDBID message, node C sends an ACK message to node A. The ACK message may also be referred to as a first write response message, which indicates permission to write the second data. The ACK message includes, but is not limited to, a command identifier, node B's identification information, and a data cache address.

[0192] S707-2, node A sends a write message to node B.

[0193] Exemplarily, in response to the ACK message, node A sends a write message (also referred to as a W dat message, not limited in this application) to node B based on the identification information of node B. The write message is used to instruct node B to write data to a specified address. The write message includes, but is not limited to, the second data, the DBID, a command identifier, etc.

[0194] S708-2, Node B writes the second data into the cache space.

[0195] Exemplarily, in response to the write message, node B writes the second data into the cache space indicated by DBID. Afterwards, node B may write the data in the cache space into the memory. The specific implementation method may refer to the existing technology and will not be described in detail in this application.

[0196] In summary, the small packets received beyond the merge window are processed according to the process of the original IO Cache mode (i.e., in Figure 5), thereby avoiding the introduction of negative returns. It can be understood that in the original IO Cache mode, node C is used to manage requests. As an upstream node, it is used to interact with the downstream node B based on the upstream data sending end (such as PCIe, or other modules or chips, etc., which are not limited in this application) to write the data of the data sending end into node B. In an embodiment of the present application, if multiple small packets with the same cacheline address are received in the merge window, node C will execute the node internal data processing process, that is, through internal interaction, write multiple data into the cache space corresponding to node C, and then interact with node B to write the corresponding data, thereby effectively reducing the number of interactions in the scenario of multiple data packets to reduce the transmission delay on the bus. In addition, the delay of the internal interaction of the node is greatly shortened compared to the bus data interaction, further improving the overall throughput of data processing.

[0197] Figure 8 shows a schematic block diagram of an apparatus 800 according to an embodiment of the present application. Apparatus 800 may include a processor 801 and a transceiver / transceiver pin 802, and optionally, a memory 803. Processor 801 may be configured to execute the steps performed by the database in the methods of the aforementioned embodiments, control the receive pin to receive signals, and control the transmit pin to send signals.

[0198] The various components of the device 800 are coupled together via a bus 804. The bus system 804 includes not only a data bus but also a power bus, a control bus, and a status signal bus. However, for clarity, the various buses are labeled as the bus system 804 in the figure.

[0199] Optionally, the memory 803 may be used to store instructions in the aforementioned method embodiment.

[0200] Among them, all relevant contents of each step involved in the above method embodiment can be referred to the functional description of the corresponding functional module and will not be repeated here.

[0201] Based on the same technical concept, an embodiment of the present application also provides a computer-readable storage medium, which stores a computer program. The computer program includes at least one section of code, and the at least one section of code can be executed by a computer to control the computer to implement the above method embodiment.

[0202] Based on the same technical concept, an embodiment of the present application also provides a computer program, which, when executed by a computer, is used to implement the above method embodiment.

[0203] The program may be stored in whole or in part on a storage medium packaged with the processor, or may be stored in whole or in part on a memory not packaged with the processor.

[0204] Based on the same technical concept, the embodiment of the present application further provides a processor, which is used to implement the above method embodiment. The above processor can be a chip.

[0205] The steps of the method or algorithm described in conjunction with the disclosure of the embodiments of the present application can be implemented in a hardware manner, or can be implemented by a processor executing a software instruction. The software instruction can be composed of corresponding software modules, and the software module can be stored in a random access memory (Random Access Memory, RAM), a flash memory, a read-only memory (Read Only Memory, ROM), an erasable programmable read-only memory (Erasable Programmable ROM, EPROM), an electrically erasable programmable read-only memory (Electrically EPROM, EEPROM), a register, a hard disk, a mobile hard disk, a read-only compact disc (CD-ROM) or any other form of storage medium well known in the art. An exemplary storage medium is coupled to the processor so that the processor can read information from the storage medium and can write information to the storage medium. Of course, the storage medium can also be a component of the processor. The processor and the storage medium can be located in an ASIC.

[0206] Those skilled in the art will appreciate that in one or more of the above examples, the functions described in the embodiments of the present application can be implemented using hardware, software, firmware, or any combination thereof. When implemented using software, these functions can be stored in a computer-readable medium or transmitted as one or more instructions or codes on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any media that facilitates the transmission of computer programs from one place to another. The storage medium can be any available medium that can be accessed by a general-purpose or special-purpose computer.

Claims

1. A data processing method, characterized in that: include: The first management unit receives a first write request message, where the first write request message is used to request to write the first data into a target cache line; The first management unit sends a first request message to the second management unit in response to the first write request message, where the first request message is used to request permission for the target cacheline; If the first management unit receives at least one second write request before receiving the first response message fed back by the second management unit, wherein the at least one second write request is used to request to write at least one second data into the target cacheline, then after receiving the first response message, the first management unit caches the first data and the at least one second data into the first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permission of the target cacheline; The first management unit writes target data into a second storage space corresponding to the second management unit, where the target data includes the first data and the at least one second data.

2. The method according to claim 1, characterized in that: The first management unit includes a first management subnode and a second management subnode, and after receiving the first response message, the first management unit caches the first data and the at least one data into a first storage space corresponding to the first management unit, including: The first management subnode sends a second request message to the second management subnode in response to the first response message, where the second request message is used to indicate that the permission of the target cacheline has been obtained and to request to write the first data into the target cacheline; The first management subnode receives a second response message fed back by the second management subnode, where the second response message is used to indicate that writing of the first data is allowed; The first management subnode requests the second management subnode to write the at least one second data in response to the second response message, and in the process of the first management subnode requesting the second management subnode to write the at least one second data, the second management subnode obtains the first data and writes the first data into the first storage space; The second management subnode obtains the second data, and writes the second data into the second storage space.

3. The method according to claim 2, characterized in that The requesting the second management subnode to write the at least one second data includes: The first management subnode sends a third request message to the second management subnode, where the third request message is used to request permission for the target cacheline; The first management subnode receives a third response message sent by the second management subnode, where the third response message is used to indicate the permission of the target cacheline; In response to the third response message, the first management subnode sends a fourth request message to the second management subnode, where the fourth request message is used to instruct to write a single second data into the target cacheline; The second management subnode obtains the single second data in response to the fourth request message, and writes the single second data into the first storage space after the first data is written into the first storage space.

4. The method according to claim 1, characterized in that The method further comprises: If the first management unit does not receive other requests for writing data to the target cacheline before receiving the first response message fed back by the second management unit, the first management unit requests the second management unit to write the third data to the target cacheline.

5. The method according to claim 4, characterized in that The first management unit requests the second management unit to write the third data into the target cacheline, including: The first management unit sends a fifth request message to the second management unit, where the fifth request message is used to request to write the first data into the target cacheline; In response to the fifth response message sent by the second management unit, the first management unit sends a data sending indication message to the data sending module, wherein the data sending indication message is used to instruct the data sending module to send the first data to the second management unit; the fifth response message is used to indicate that writing of the first data is allowed.

6. A data processing device, characterized in that: comprising a first management unit and a second management unit; The first management unit is used to receive a first write request message, where the first write request message is used to request to write the first data into a target cache line; The first management unit is further configured to send a first request message to the second management unit in response to the first write request message, wherein the first request message is used to request permission for the target cacheline; The first management unit is further configured to, if before receiving the first response message fed back by the second management unit, the first management unit receives at least one second write request, wherein the at least one second write request is used to request to write at least one second data into the target cacheline, then after receiving the first response message, the first management unit caches the first data and the at least one second data into a first storage space corresponding to the first management unit; wherein the first response message is used to indicate the permission of the target cacheline; The first management unit is further configured to write target data in the first storage space into the second management unit, where the target data includes the first data and the at least one second data.

7. The device according to claim 6, characterized in that The first management unit includes a first management sub-node and a second management sub-node, The first management subnode is used to send a second request message to the second management subnode in response to the first response message, where the second request message is used to indicate that the permission of the target cacheline has been obtained and to request to write the first data into the target cacheline; The first management subnode is further used to receive a second response message fed back by the second management subnode, where the second response message is used to indicate that writing of the first data is allowed; The first management subnode is further configured to, in response to the second response message, request the second management subnode to write the at least one second data, and in the process of the first management subnode requesting the second management subnode to write the at least one second data, the second management subnode obtains the first data and writes the first data into the first storage space; The second management subnode is used to obtain the second data and write the second data into the second storage space.

8. The device according to claim 7, characterized in that The first management subnode is further used to send a third request message to the second management subnode, where the third request message is used to request permission for the target cacheline; The first management subnode is further configured to receive a third response message sent by the second management subnode, where the third response message is used to indicate the permission of the target cacheline; The first management subnode is further configured to send a fourth request message to the second management subnode in response to the third response message, wherein the fourth request message is used to instruct to write a single second data into the target cacheline; The second management subnode is further configured to obtain the single second data in response to the fourth request message, and write the single second data into the first storage space after the first data is written into the first storage space.

9. The device according to claim 6, characterized in that The first management unit is further configured to request the second management unit to write the third data into the target cacheline if no other request for writing data into the target cacheline is received before the first response message fed back by the second management unit is received.

10. The device according to claim 9, characterized in that The first management unit is used to send a fifth request message to the second management unit, where the fifth request message is used to request to write the first data into the target cacheline; The first management unit is further configured to send data to the data sending module in response to a fifth response message sent by the second management unit. A sending indication message is used to instruct the data sending module to send the first data to the second management unit; and the fifth response message is used to indicate permission to write the first data.

11. A chip, characterized in that: It comprises one or more interface circuits and one or more processors; the interface circuit is used to receive a signal from a memory of an electronic device and send the signal to the processor, wherein the signal includes a computer instruction stored in the memory; when the processor executes the computer instruction, the electronic device executes the method described in any one of claims 1 to 5.

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