Chip packaging structure and radio frequency front-end module

Abstract

The present application is applicable to the field of front-end radio frequency. Disclosed are a chip packaging structure and a radio frequency front-end module. The chip packaging structure comprises: a first chip and a second chip, which are arranged on a first surface, wherein a cavity is formed between the first chip, a solder mask and a substrate; the solder mask, which is arranged on the first surface, wherein at least part of the solder mask is arranged between the first chip and the substrate; a first adhesive material portion, which is arranged on the solder mask and at least partially surrounds the first chip, wherein the distance between the bottom surface of the first chip and the solder mask is less than the height of the first adhesive material portion adjacent to the first chip, and the distance between the bottom surface of the first chip and the substrate is less than the distance between the second chip and the substrate; and a plastic packaging material, which covers the solder mask, an adhesive material portion, the first chip and the second chip, and fills a gap between the second chip and a base. Therefore, the reliability of the chip packaging structure is improved, and the size of the chip packaging structure is reduced.

Description

Chip packaging structure and RF front-end module

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on September 28, 2023, with application number CN202322658136.9 and application name “Chip Packaging Structure and RF Front-end Module”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of radio frequency filtering, and in particular to a chip packaging structure and a radio frequency front-end module. Background Art

[0003] In chip packaging, some chips require a cavity structure between themselves and the substrate to meet their functions, performance or other special requirements.

[0004] Based on this, related technologies use a lamination process on flip-chip chips mounted on a substrate to create a cavity between the chip and the substrate. However, the lamination process requires the mold to fill the gap between two adjacent chips. Therefore, the distance between the two adjacent chips needs to be large to allow the film to adhere to the substrate between the two adjacent chips. This results in a large chip package structure, which is not convenient for subsequent integration. On the other hand, some chips do not require a cavity structure between them and the substrate. Lamination increases the cost of chip packaging and may cause some chips that do not require a cavity structure to fail, thereby reducing the reliability of the chip package structure.

[0005] Application Contents

[0006] The first purpose of the present application is to provide a chip packaging structure, which aims to solve the technical problems of large packaging structure volume and low reliability in multi-chip scenarios.

[0007] To achieve the above objectives, the present application provides a solution: a chip packaging structure, comprising:

[0008] a substrate, having a first chip bonding pad and a second chip bonding pad provided on a first surface thereof;

[0009] A first chip is disposed on the first surface, wherein a first conductive bump is disposed on a bottom surface of the first chip, and the first conductive bump is interconnected with the first chip pad;

[0010] a second chip disposed on the first surface, wherein a second conductive bump is disposed on a bottom surface of the second chip, and the second conductive bump is interconnected with the second chip pad;

[0011] a solder resist layer disposed on the first surface, wherein the solder resist layer is at least partially disposed between the first chip and the substrate, and a cavity is formed between the first chip, the solder resist layer, and the substrate;

[0012] an adhesive portion, the adhesive portion including a first adhesive portion, the first adhesive portion at least partially surrounding the first chip and disposed on the solder resist layer; wherein a distance between a bottom surface of the first chip and the solder resist layer is smaller than a height of the first adhesive portion adjacent to the first chip, and a distance between a bottom surface of the first chip and the substrate is smaller than a distance between the second chip and the substrate;

[0013] A plastic encapsulation material covers the solder resist layer, the adhesive portion, the first chip and the second chip, and fills a gap between the second chip and the substrate.

[0014] To achieve the above-mentioned purpose, another solution provided by the present application is: a chip packaging structure, comprising:

[0015] a substrate, having a first chip bonding pad and a second chip bonding pad provided on a first surface thereof;

[0016] A first chip is disposed on the first surface, wherein a first conductive bump is disposed on a bottom surface of the first chip, and the first conductive bump is interconnected with the first chip pad;

[0017] a second chip disposed on the first surface, wherein a second conductive bump is disposed on a bottom surface of the second chip, and the second conductive bump is interconnected with the second chip pad;

[0018] The distance between the first chip and the second chip is less than 150 microns;

[0019] an adhesive portion, the adhesive portion including a first adhesive portion, the first adhesive portion at least partially covering a side surface of the first chip;

[0020] The molding compound covers the adhesive portion, the first chip, and the second chip, and fills a gap between the second chip and the substrate.

[0021] The second object of the present application is to provide a radio frequency front-end module, including the chip packaging structure as described above.

[0022] The chip packaging structure provided by the present application sets a first adhesive portion around the first chip to prevent the plastic encapsulation material from entering the cavity between the first chip and the substrate, thereby ensuring the reliability of the cavity. At the same time, the distance between the second chip and the substrate is set to be higher than the distance between the first chip and the substrate, so that the plastic encapsulation material can fully enter between the second chip and the substrate to fill the gap between the second chip and the base, thereby improving the reliability of the second chip and thus improving the reliability of the chip packaging structure; and since there is no need for a lamination to form a cavity between the first chip and the substrate, the distance between two adjacent chips does not need to be set larger, which can reduce the volume of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the structures shown in these drawings without paying any creative work.

[0024] FIG1 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0025] FIG2 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0026] FIG3 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0027] FIG4 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0028] FIG5 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application;

[0029] FIG6 is a schematic structural diagram of another chip packaging structure provided in an embodiment of the present application.

[0030] Description of Figure Numbers:

[0031] 10. substrate, 11. first surface, 12. solder resist layer, 13. molding compound;

[0032] 20. First chip, 21. First chip pad, 22. First conductive bump, 23. Cavity;

[0033] 30. Second chip, 31. Second chip pad, 32. Second conductive bump;

[0034] 40. third chip, 41. third chip pad, 42. bonding wire;

[0035] 51. First adhesive material portion, 52. Second adhesive material portion, 53. Third adhesive material portion, 54. Fourth adhesive material portion. DETAILED DESCRIPTION

[0036] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0037] It should be noted that all directional indications in the embodiments of the present application (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship and movement status between the components in a certain specific posture. If the specific posture changes, the directional indication will also change accordingly.

[0038] It should also be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or there may be an intervening element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element through an intervening element.

[0039] In addition, the descriptions of "first", "second", etc. in this application are for descriptive purposes only and should not be understood as indicating or implying their relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined as "first" or "second" may explicitly or implicitly include at least one of such features. In addition, the technical solutions between the various embodiments can be combined with each other, but this must be based on the fact that they can be implemented by ordinary technicians in this field. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such combination of technical solutions does not exist and is not within the scope of protection required by this application.

[0040] In one embodiment, a chip package structure is provided, including a substrate 10 , on a first surface 11 of which a first chip bonding pad 21 and a second chip bonding pad 31 are provided;

[0041] The substrate 10 is provided with a first chip bonding pad 21 and a second chip bonding pad 31 on the first surface 11;

[0042] A first chip 20 is disposed on the first surface 11. A first conductive bump 22 is disposed on the bottom surface of the first chip 20. The first conductive bump 22 is interconnected with the first chip pad 21. A cavity 23 is formed between the first chip, the solder resist layer 12, and the substrate 10.

[0043] A second chip 30 is disposed on the first surface 11 , and a second conductive bump 32 is disposed on the bottom surface of the second chip 30 , and the second conductive bump 32 is interconnected with the second chip pad 31 ;

[0044] A solder resist layer 12 is disposed on the first surface 11 , and the solder resist layer 12 is at least partially disposed between the first chip 20 and the substrate 10 ;

[0045] The adhesive portion includes a first adhesive portion 51, which at least partially surrounds the first chip 20 and is disposed on the solder resist layer 12; wherein the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is less than the height of the first adhesive portion 51 adjacent to the first chip, and the distance between the bottom surface of the first chip 20 and the substrate 10 is less than the distance between the second chip 30 and the substrate 10;

[0046] The molding compound 13 covers the solder resist layer 12 , the adhesive portion, the first chip 20 and the second chip 30 , and fills the gap between the second chip 30 and the substrate.

[0047] In this embodiment, the substrate 10 may be a resin substrate, a ceramic substrate, a glass substrate, a quartz substrate or other types of substrates. Optionally, the substrate 10 is a resin substrate.

[0048] In this embodiment, the first chip can be a filter chip or a non-filter chip, and the number of first chips 20 can be one or more. When the number of first chips 20 is multiple, the first chips 20 can all be filter chips or all be non-filter chips, or some can be filter chips and the other part can be non-filter chips.

[0049] The second chip 30 is a non-filter chip, and the number of the second chips can be one or more.

[0050] Specifically, filter chips include filtering function chips such as surface acoustic wave filters and bulk acoustic wave filters; non-filtering function chip devices, such as power amplifiers, low-noise amplifiers, radio frequency switches and other non-filtering function chips; passive components include passive components such as capacitors, inductors or resistors.

[0051] In this embodiment, the first chip pad 21 and the second chip pad 31 are exposed on the first surface 11. Specifically, the first chip pad 21 or the second chip pad 31 is arranged on the first surface 11, and the portion exposed to the first surface 11 has a certain height in the thickness direction of the chip packaging structure; of course, the first chip pad 21 or the second chip pad 31 can also be arranged inside the substrate 10 and exposed on the first surface 11, wherein the portion exposed to the first surface 11 has a certain height in the thickness direction of the chip packaging structure, or the portion exposed to the first surface 11 is flush with the first surface 11.

[0052] The first chip pad 21 and the second chip pad 31 can be metal or alloy. The metal can be nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, etc. The pads are connected to external or internal circuits through wiring on the substrate 10.

[0053] The first chip 20 and the second chip 30 are flip-chip mounted on the first surface 11, wherein the first conductive bump 22 and the second conductive bump 32 can be copper, tin, gold or alloy, or can be commonly used bump types such as metal bumps (for conductive connection), and the chip device is connected to the external circuit through the raised structure and the pad.

[0054] In this embodiment, the solder resist layer 12 is arranged on the first surface 11. As shown in Figures 1 and 2, the solder resist layer 12 can only surround the four sides of the first chip 20, and the solder resist layer 12 is at least partially arranged between the first chip 20 and the substrate 10. The solder resist layer 12 is at least partially arranged between the first chip 20 and the substrate 10, which can be regarded as the projection of the first chip 20 on the substrate 10, overlapping with the projection of the solder resist layer 12 on the chip, and the overlapping area includes at least the edge area of ​​the projection area of ​​the first chip 20 on the substrate 10. The edge area is a closed figure, that is, the edge area is obtained by extending a certain distance from each periphery of the projection area of ​​the first chip 20 on the substrate 10 to the center of the projection area of ​​the first chip 20 on the substrate 10, that is, the periphery of the figure formed by the projection of the first chip 20 on the substrate 10 overlaps with the projection of the solder resist layer 12 on the chip.

[0055] In this embodiment, the solder resist layer 12 can protect metal areas that do not require soldering (such as traces on the substrate) on the one hand, and can also serve as a buffer layer to relieve the stress caused by the difference in thermal expansion coefficient between the plastic encapsulation material 13 and the substrate 10 when filling, so as to protect the substrate.

[0056] At the same time, in this embodiment, when the solder resist layer 12 is not provided, the distance between the bottom surface of the first chip 20 and the substrate is too large, which may cause the glue portion to flow into the cavity when the substrate is formed, or cause the first conductive bump to break due to excessive force when the plastic molding compound is filled. By providing the solder resist layer 12, the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is reduced, and the first glue portion is provided on the solder resist layer, thereby reducing the occurrence of the first glue portion flowing into the cavity under the first chip 20 when it is formed. At the same time, due to the presence of the solder resist layer, the stress-bearing solder resist layer of the first chip can provide support when the plastic molding compound is filled, reducing the risk of the first conductive bump breaking due to excessive force, thereby improving the reliability of the first chip.

[0057] In some embodiments, the solder resist layer 12 is also provided on the first surface 11 in other areas except for the four sides surrounding the first chip 20. As shown in FIG2 , it can be provided around the second chip 30, or can also be provided in the area between the first conductive bumps 22 of the first chip 20. The solder resist layer 12 provided in the area between the first conductive bumps 22 of the first chip 20 can be different in height and material from the solder resist layer 12 at other positions, and no specific restrictions are made here. It should be noted that the projection of the second chip 30 on the substrate 10 does not overlap with the projection of the solder resist layer 12 on the substrate 10. In this way, the subsequent plastic encapsulation material 13 can fill the gap between the second chip 30 and the substrate, thereby improving the reliability of the chip packaging structure.

[0058] In this embodiment, referring to Figures 1 to 4, the adhesive portion at least includes a first adhesive portion 51, wherein the first adhesive portion 51 is arranged on the solder resist layer 12, and the adhesive portion arranged on the solder resist layer 12 can be regarded as the first adhesive portion 51. As shown in Figures 1 and 2, the first adhesive portion 51 can be arranged on the solder resist layer 12 only around the first chip 20 to prevent the plastic encapsulation material 13 from entering the cavity 23 from the gap between the first chip 20 and the solder resist layer 12 when the plastic encapsulation material 13 is filled. At the same time, due to different needs for lamination, there is no need to set a large distance between the first chip 20 and the second chip 30 to ensure normal attachment of the lamination. In this way, the volume of the chip packaging structure can be reduced while ensuring the reliability of the chip packaging structure.

[0059] Of course, the first adhesive portion 51 may also be provided in other places of the solder resist layer 12. As shown in FIG3 , the exposed first solder resist layer 12 is provided with the first adhesive portion 51. No specific restriction is imposed on the setting position of the first adhesive portion 51. It is sufficient to keep the first adhesive portion 51 at least partially surrounding the first chip 20 and provided on the solder resist layer 12.

[0060] In this embodiment, the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is set to be smaller than the height of the first adhesive portion 51 adjacent to the first chip 20. In this way, the plastic encapsulation material 13 can be reduced from entering the cavity 23 through the gap between the first chip 20 and the solder resist layer 12. The bottom surface of the first chip 20 is the side of the first chip 20 opposite to the substrate 10. The distance between the bottom surface of the first chip 20 and the solder resist layer 12 is the distance between the bottom surface of the first chip 20 and the solder resist layer 12 in the thickness direction. The height of the first adhesive portion 51 adjacent to the first chip 20 can be regarded as the height of the position of the first adhesive portion 51 closest to the first chip 20 in the thickness direction among the first adhesive portions 51 arranged around the first chip 20.

[0061] Specifically, as shown in Figures 1 to 3, the first adhesive portion 51 disposed on the solder resist layer 12 can contact the side surface of the first chip 20, or can be at a certain distance from both sides of the first chip 20. When the first adhesive portion 51 can contact the side surface of the first chip 20, if the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is less than the height of the first adhesive portion 51 adjacent to the first chip 20, it can be considered that the portion of the first adhesive portion 51 covering the side surface of the first chip 20 has a greater height in the thickness direction than the distance between the bottom surface of the first chip 20 and the solder resist layer 12. When the first adhesive portion 51 is at a certain distance from both sides of the first chip 20, if the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is less than the height of the first adhesive portion 51 adjacent to the first chip 20, it can be considered that the portion of the first adhesive portion 51 closest to the side surface of the first chip 20 has a greater height in the thickness direction than the distance between the bottom surface of the first chip 20 and the solder resist layer 12 in the extension direction, wherein the extension direction is the direction extending outward from the side surface of the first chip 20.

[0062] Preferably, when there is a certain distance between the first adhesive portion 51 and the side of the first chip 20 , the distance should be smaller than the diameter of particles in the molding compound 13 .

[0063] In this embodiment, the distance between the bottom surface of the first chip 20 and the substrate 10 is set to be smaller than the distance between the second chip 30 and the substrate 10. At this time, it can also be regarded as the distance between the bottom surface of the first chip 20 and the solder resist layer 12 is smaller than the distance between the second chip 30 and the solder resist layer 12. In this way, after the adhesive portion is set, not only can a closed cavity 23 be formed between the first chip 20 and the substrate 10, but the plastic encapsulation material 13 can also completely fill the gap between the second chip 30 and the base, thereby ensuring the reliability of the second chip 30, thereby improving the reliability of the chip packaging structure.

[0064] In this embodiment, the molding compound 13 fills the gap between the second chip 30 and the substrate, so that the second chip 30 that does not need the cavity 23 is surrounded by the molding compound 13, ensuring the dryness of the working environment of the second chip 30. At the same time, it can avoid the problem of the second conductive bump 32 being melted by heat and causing interconnection failure during subsequent operation due to the gap between the second chip 30 and the substrate being not completely filled in the second chip 30.

[0065] At the same time, the setting of the plastic packaging material 13 can provide physical support and protection, and can also block substances such as water vapor, salt, and fog in the external environment, thereby protecting the packaged chip.

[0066] The molding compound 13 can be made of an insulating resin material or other conventional molding materials. Optionally, the molding compound 13 is a resin material containing particulate matter. The particulate matter can be silicon dioxide (SiO2) particles or aluminum oxide (Al2O3) particles, which is not limited in this embodiment. It is understood that the molding compound 13 can be made of other insulating materials that have good fluidity or are liquid at high temperatures, or other materials that can achieve a sealing function.

[0067] In one embodiment, the first adhesive portion 51 at least partially covers the side surface of the first chip 20 .

[0068] In this embodiment, the first adhesive portion 51 is disposed on the solder resist layer 12 around the first chip 20 . The first adhesive portion 51 can cover the side surface of the first chip 20 to prevent the molding compound 13 from entering the cavity 23 from the gap between the first chip 20 and the solder resist layer 12 .

[0069] Of course, the first adhesive portion 51 at least partially covers the side surface of the first chip 20. The portion of the side surface of the first chip 20 covered by the first adhesive portion 51 may be a closed figure surrounding the side surface of the first adhesive portion 51, that is, at any cross section of the first chip 20 (the cross section is perpendicular to the surface where the substrate 10 is located), both sides of the side surface corresponding to the cross section are partially covered by the first adhesive portion 51.

[0070] In some embodiments, the first adhesive portion 51 at least partially covers the side surface of the first chip 20. The portion of the side surface of the first chip 20 covered by the first adhesive portion 51 is a broken pattern surrounding the side surface of the first adhesive portion 51, that is, on some cross-sections of the first chip 20 (the cross-section is perpendicular to the surface where the substrate 10 is located), both sides of the side surface corresponding to the cross-section are partially covered by the first adhesive portion 51; on some cross-sections of the first chip 20, at least one side of the two sides of the side surface corresponding to the cross-section is not partially covered by the first adhesive portion 51.

[0071] In one embodiment, the first adhesive portion 51 has at least one peak.

[0072] In this embodiment, the first adhesive portion 51 can be obtained by dispensing. Specifically, the dispensing process can be performed precisely at the location where dispensing is required, such as dispensing on the solder mask layer 12 around the first chip 20. At this time, in the top view direction, the first adhesive portion 51 has at least one peak, which can be regarded as a point or a surface composed of multiple points. The height of other parts of the first adhesive portion 51 outside the first peak is less than the height of the first peak.

[0073] In this embodiment, the number of the slope peaks of the first adhesive material portion can be one or more, and is not specifically limited here.

[0074] Specifically, reference may be made to FIG1 , which is a partial structure of a certain cross-section of the chip packaging structure. The figure shows two parts of the first adhesive portion 51 located on both sides of the first chip 20. There is a certain distance between the left part and the side surface of the first chip 20, and the right part is attached to the side surface of the first chip 20. At this time, it can be found that there is a highest point on the left part, which can be regarded as a slope peak on the cross-section of FIG1 .

[0075] The slope peak in this embodiment can be considered as a highest point in a certain area of ​​the first adhesive portion 51 , and the height of the parts of the first adhesive portion 51 around the highest point is smaller than the height of the highest point.

[0076] In this embodiment, the peak can buffer the stress on the first chip 20 or the solder resist layer 12 when the molding compound 13 is filled, and can also release the stress caused by the thermal expansion of the first adhesive portion 51 .

[0077] Of course, in addition to dispensing, the first adhesive portion 51 can also be formed by full spraying. In this case, adhesive will be present on the solder mask 12, the first chip 20, the second chip 30, and the first surface 11, and the height of the adhesive at each position is basically the same. Similarly, when the adhesive portion is formed by full spraying, the adhesive portion can also buffer the stress of filling the plastic encapsulation material 13.

[0078] In some embodiments, the entire surface may be sprayed first, and then glue may be dispensed at some locations to form a glue portion, such as the first glue portion 51 in the glue portion. At this time, the dispensed portion may also have a slope peak, which is not specifically limited here.

[0079] In some embodiments, glue may be dispensed at some locations first and then fully sprayed to form a glue portion, such as the first glue portion 51 in the glue portion. At this time, the dispensed portion may also have a slope peak, which is not specifically limited here.

[0080] In one embodiment, the adhesive portion further includes a second adhesive portion 52 . The second adhesive portion 52 is disposed on the upper surface of the first chip 20 and / or the second chip 30 .

[0081] In this embodiment, the adhesive material provided on the upper surface of the first chip 20 or the second chip 30 may be referred to as a second adhesive material portion 52. The second adhesive material portion 52 may be provided only on the upper surface of the first chip 20, or only on the upper surface of the second chip 30, or may be provided on both the upper surfaces of the first chip 20 and the second chip 30. No specific limitation is imposed herein.

[0082] The second glue portion 52 is arranged on the upper surface of the first chip 20 and / or the second chip 30 to relieve the stress on the first chip 20 and / or the second chip 30 when the plastic encapsulation material 13 is filled. At the same time, the second glue portion 52 can be arranged above the first conductive bump 22 and / or the second conductive bump 32, and can also relieve the stress on the first conductive bump 22 and / or the second conductive bump 32 when the plastic encapsulation material 13 is filled. The second glue portion 52 can also be arranged above the cavity 23, and can also relieve the stress on the cavity 23 when the plastic encapsulation material 13 is filled.

[0083] Of course, the first adhesive material portion 51 can be formed by full spraying or by dispensing, and details can be found in FIG. 3 and FIG. 4 .

[0084] In some embodiments, the second adhesive portion 52 can be as shown in Figure 3. Figure 3 shows that after the chip is flipped on the first surface 11, the adhesive can be sprayed directly onto the first surface 11 in a full spraying manner to form an adhesive portion on the solder mask 12, the first chip 20, the second chip 30 and the exposed portion of the first surface 11. At this time, the second adhesive portion 52 completely covers the upper surfaces of the first chip 20 and the second chip 30.

[0085] In other embodiments, the second glue portion 52 can be formed as a discontinuous second glue portion 52 on the upper surface of the first chip 20 and the second chip 30 by dispensing as shown in Figure 4. The second glue portion 52 can be set at the position corresponding to the conductive bump, or at the position of the cavity 23, or can be set by dispensing to completely cover the upper surface of the first chip 20 and the second chip 30.

[0086] It is understandable that during full spraying, the adhesive portion has no slope peak, but during dispensing, the adhesive portion has a slope peak. Therefore, the second adhesive portion 52 has at least one slope peak when formed during the dispensing process.

[0087] In one embodiment, the adhesive portion further includes a third adhesive portion 53 . The third adhesive portion 53 is disposed on the first surface 11 .

[0088] In this embodiment, when the adhesive portion is formed by dispensing or full spraying, some adhesive will flow onto the first surface 11 of the substrate 10 . At this time, the portion of the adhesive portion located on the first surface 11 is referred to as the third adhesive portion 53 .

[0089] Specifically, as shown in FIG5 , when the glue portion is formed during glue dispensing, part of the glue portion is located on the first surface 11 , forming a third glue portion 53 ; or as shown in FIG3 and FIG6 , when the glue portion is formed during full spraying, part of the glue portion is located on the first surface 11 , forming a third glue portion 53 ; of course, the glue portion can also be formed by combining full spraying and glue dispensing processes, in which case the part of the glue portion located on the first surface 11 is still referred to as the third glue portion 53 .

[0090] In one embodiment, a height difference between any two positions in the adhesive portion in the thickness direction is smaller than a preset error value.

[0091] In this embodiment, when the adhesive portion is formed by full spraying, the height difference between each position of the adhesive portion is small. At this time, it can be considered that the height difference between any two positions in the adhesive portion in the thickness direction is less than the preset error value.

[0092] For example, the preset error value is less than or equal to 8um, and may be 5um, 4um (micrometers), 0.9um, etc. The specific value of the preset error is not limited.

[0093] Of course, in other embodiments, due to the different full-spraying processes, the shape of the obtained glue portion is also different. Specifically, in some embodiments, the height difference between any two positions in the glue portion in the thickness direction is less than the preset error value, which can be regarded as the height difference between any two positions in the glue portion on the same structure in the thickness direction is less than the preset error value. The same structure can be a specific structure, such as the height difference between any two positions in the thickness direction of the glue portion in the portion on the upper surface of the first chip 20 is less than the preset error value, the height difference between any two positions in the thickness direction of the glue portion in the portion on the upper surface of the second chip 30 is less than the preset error value, the height difference between any two positions in the thickness direction of the glue portion in the portion on the upper surface of the solder mask layer 12 is less than the preset error value, the height difference between any two positions in the thickness direction of the glue portion in the portion on the upper surface of the substrate 10 is less than the preset error value, etc.

[0094] At the same time, the height difference between two positions of the glue portion in the thickness direction on different structures is less than a preset threshold value, such as the numerical difference between the height of the glue portion in the thickness direction at a certain position in the portion on the upper surface of the second chip 30 and the height of the glue portion in the thickness direction at a certain position in the portion on the upper surface of the first chip 20 is less than a preset threshold value. In this embodiment, the preset threshold value is different from the preset error value, and the preset threshold value is greater than the preset error value. For example, the preset error value is less than or equal to 8um, such as 5um, 4um (micrometers), 0.9um, etc., and the preset threshold value is less than or equal to 20um, such as 20um, 18um, 15um, etc. The specific values ​​of the preset error and the preset threshold value are not limited.

[0095] In fact, when the adhesive portion is formed only by the full spraying process, it can be considered that when no plastic filling is performed, in the top view direction (i.e., the direction from the solder mask layer to the substrate), all surfaces of the structure exposed to the air will have adhesive to form the adhesive portion.

[0096] In this embodiment, when the adhesive portion is formed by full spraying, the process is simpler, and the obtained adhesive portion can prevent the molding compound 13 from entering the cavity 23 through the gap between the first chip 20 and the solder resist layer 12, thereby improving the safety of the chip packaging structure.

[0097] In one embodiment, in the thickness direction, the height of the first adhesive portion 51 is greater than the distance between the first chip 20 and the solder resist layer 12 , and less than the distance between the second chip 30 and the solder resist layer 12 .

[0098] In this embodiment, regardless of whether the first adhesive portion 51 is formed by full spraying or by dispensing, or by a combination of full spraying and dispensing (e.g., full spraying first, followed by dispensing in some parts that require stress buffering; or dispensing in parts with greater stress, followed by full spraying), the height of the first adhesive portion 51 should be greater than the distance between the first chip 20 and the solder resist layer 12, and less than the distance between the second chip 30 and the solder resist layer 12.

[0099] Specifically, the height of the first adhesive portion 51 being greater than the height between the first chip 20 and the solder resist layer 12 can be regarded as the highest height of the first adhesive portion 51 in the thickness direction being greater than the distance between the first chip 20 and the solder resist layer 12; or it can be regarded as the height of the portion of the first adhesive portion 51 arranged around the first chip 20 that is closest to the side surface of the first chip 20 being greater than the height between the first chip 20 and the solder resist layer 12. As can be seen from Figures 1 to 5, the height of the portion of the first adhesive portion 51 adjacent to the side surface of the first chip 20 is greater than the height of the gap between the first chip 20 and the solder resist layer 12. That is, it can be regarded as that, in any extension direction, the height of the portion of the first adhesive portion 51 that is closest to the side surface of the first chip 20 is greater than the distance between the first chip 20 and the solder resist layer 12.

[0100] The distance between the first chip 20 and the solder resist layer 12 is the distance between the bottom surface of the first chip 20 and the solder resist layer 12 in the thickness direction. When the height of some parts of the solder resist layer 12 is different from the height of other parts, the distance between the bottom surface of the first chip 20 and the solder resist layer 12 can be regarded as the distance between the bottom surface of the first chip 20 and the solder resist layer 12 at any height, or directly regarded as the distance between the bottom surface of the first chip 20 and the solder resist layer 12 adjacent to the first chip 20.

[0101] In this embodiment, the height of the first adhesive portion 51 is set to be greater than the distance between the first chip 20 and the solder resist layer 12. This can avoid the first adhesive portion 51 being insufficient in height, resulting in the gap between the first chip 20 and the solder resist layer 12 not being blocked by the first adhesive portion 51, thereby allowing the molding compound 13 to enter the cavity 23 through the gap between the first chip 20 and the solder resist layer 12, thereby reducing the performance of the first chip 20.

[0102] The height of the first adhesive portion 51 is smaller than the distance between the second chip 30 and the solder resist layer 12 . Specifically, the highest height of the first adhesive portion 51 in the thickness direction is smaller than the distance between the second chip 30 and the solder resist layer 12 . Alternatively, the height of the first adhesive portion 51 adjacent to the second chip 30 in the thickness direction is smaller than the distance between the second chip 30 and the solder resist layer 12 . Specifically, referring to FIG. 1 to FIG. 5 , in any extending direction, the height of the portion of the first adhesive portion 51 closest to the second chip 30 is smaller than the distance between the second chip 30 and the solder resist layer 12 .

[0103] The distance between the second chip 30 and the solder resist layer 12 can be regarded as the distance between the bottom surface of the second chip 30 and the solder resist layer 12 in the thickness direction. When the height of some parts of the solder resist layer 12 is different from that of other parts, the distance between the bottom surface of the second chip 30 and the solder resist layer 12 can be regarded as the distance between the bottom surface of the second chip 30 and the solder resist layer 12 of any height, or directly regarded as the distance between the bottom surface of the second chip 30 and the solder resist layer 12 adjacent to the second chip 30.

[0104] In this embodiment, the height of the first adhesive portion 51 is set to be smaller than the distance between the second chip 30 and the solder resist layer 12. As a result, a gap exists between the first adhesive portion 51 and the bottom surface of the second chip 30. The molding compound 13 can fill the gap between the second chip 30 and the substrate through the gap, thereby improving the reliability of the second chip 30.

[0105] In one embodiment, the distance between the second chip 30 and the first adhesive portion 51 is greater than 30 micrometers, such as 40 micrometers, 45 micrometers, etc.

[0106] In this embodiment, the distance between the second chip 30 and the first adhesive portion 51 can be considered as the shortest distance between the outer surface of the first adhesive portion 51 exposed to the molding compound and the bottom surface of the second chip 30 in any extending direction, as shown by L in Figures 1 to 5. The distance between the second chip 30 and the first adhesive portion 51 can be considered as the distance between the bottom surface of the second chip 30 and the first adhesive portion 51 in any cross-section.

[0107] Of course, in some embodiments, the distance between the second chip 30 and the first adhesive portion 51 can also be regarded as the distance between a point on the bottom surface of the second chip 30 and a point at which the first adhesive portion contacts the solder resist layer in any extension direction or in any cross section. The distance between a point on the bottom surface of the second chip 30 in the cross section and a point at which the first adhesive portion contacts the solder resist layer in the extension direction or in any cross section can be calculated as follows: let the distance between the projection of the second chip 30 on the substrate and the projection of the first adhesive portion on the substrate in the extension direction or in the cross section (the minimum distance between the two projection boundaries in the extension direction or in the cross section) be x, let the height of the bottom surface of the second chip and the solder resist layer in the thickness direction of the substrate be y, then the square of the distance between the second chip 30 and the first adhesive portion 51 should be equal to x 2 +y 2 .

[0108] In this embodiment, the distance between the second chip 30 and the first adhesive portion 51 is set to be greater than 30 microns, thereby ensuring that the molding compound 13 can enter the gap between the second chip 30 and the substrate from the opening between the first adhesive portion 51 and the second chip 30, thereby improving the reliability of the second chip 30.

[0109] In other embodiments, the distance between the second chip 30 and the first adhesive portion 51 is set to be greater than 30 microns, such as 70 microns, 90 microns, etc., to ensure that the molding compound 13 can fully enter the gap between the second chip 30 and the substrate through the opening between the first adhesive portion 51 and the second chip 30, thereby improving the reliability of the second chip 30.

[0110] In one embodiment, the distance between the first chip 20 and the second chip 30 is less than 150 micrometers.

[0111] In this embodiment, since no lamination is required to form the cavity 23, there is no need to set a large distance between two adjacent chips, which is generally greater than 160 microns. In this embodiment, the distance between the first chip 20 and the second chip 30 can be set to less than 150 microns, such as 80 microns, 90 microns, etc., so that the volume of the chip packaging structure can be reduced while ensuring the formation of the cavity 23 through the adhesive part.

[0112] It can be understood that in this embodiment, the distance between the first chip 20 and the second chip 30 is less than 150 microns, which means the first chip 20 and the second chip 30 are adjacent. When the number of first chips 20 or second chips 30 is multiple, the distance between adjacent first chips 20 and second chips 30 is set to be less than 150 microns, rather than setting the distance between any first chip 20 and any second chip 30 to be less than 150 microns.

[0113] In one embodiment, the distance between the first chip 20 and the second chip 30 is greater than 50 microns and less than 100 microns, such as 60 microns, 70 microns, etc., so that the volume of the chip packaging structure can be reduced while ensuring the formation of the cavity 23 by the adhesive portion.

[0114] In this embodiment, the distance between the first chip 20 and the second chip 30 is not set to be too small. If the distance between the first chip 20 and the second chip 30 is too small, the opening between the second chip 30 and the first adhesive portion 51 may be too small, or the opening between the solder resist layer 12 and the second chip 30 may be too small, resulting in the molding compound 13 being unable to completely fill the gap between the second chip 30 and the substrate 10.

[0115] In one embodiment, on the plane where the substrate 10 is located, the distance between the second chip 30 and the solder resist layer 12 is greater than 100 micrometers.

[0116] In this embodiment, there is no solder resist layer 12 in the projection area of ​​the second chip 30 on the substrate 10 , and the distance between the second chip 30 and the solder resist layer 12 is greater than 100 micrometers.

[0117] Furthermore, the distance between the second chip 30 and the solder resist layer 12 is greater than 100 microns, which can be regarded as the distance (minimum distance) between the boundary of the projection area of ​​the second chip 30 on the substrate 10 and the boundary of the projection area of ​​the solder resist layer 12 on the substrate 10 being greater than 100 microns. Thus, it can be ensured that the molding compound 13 enters from the opening between the second chip 30 and the first adhesive portion 51, or the opening between the solder resist layer 12 and the second chip 30, to completely fill the gap between the second chip 30 and the substrate 10, thereby ensuring the reliability of the second chip 30.

[0118] In one embodiment, the chip packaging structure further includes a third chip 40 . Bonding wires 42 are disposed on the top surface of the third chip 40 . The bonding wires 42 of the third chip 40 are interconnected with third chip pads 41 disposed on the first surface 11 .

[0119] As shown in Figures 5 and 6, in this embodiment, the first chip 20 and the second chip 30 are both flip-chip structures, and a third chip 40 can also be provided. The third chip 40 is a wire-bonded structure, and a bonding lead 42 is provided on its top surface. The bonding lead 42 of the third chip 40 is interconnected with the third chip pad 41 provided on the first surface 11.

[0120] The third chip pad 41 can be a metal or alloy. The metal can be nickel, palladium, molybdenum, tungsten, ruthenium, gold, magnesium, aluminum, copper, chromium, titanium, osmium, iridium, etc. The pad is connected to the external or internal circuit through the wiring on the substrate 10.

[0121] In this embodiment, by setting a first glue material portion on the solder mask layer, the first chip forms a closed cavity, and at the same time, the plastic encapsulation material is ensured to fill the gap between the second chip and the substrate. At the same time, since there is no need for lamination to ensure that the first chip forms a cavity, the influence of the lamination on the wire-bonding structure chip is avoided. Compared with the solution of forming a cavity by the lamination process, the present embodiment can set the chip with the wire-bonding structure (that is, the third chip) and the chip requiring a cavity (that is, the first chip) on the same surface of the substrate (in the lamination process, if the chip with the wire-bonding structure and the chip requiring a cavity are set on the same surface of the substrate, during lamination, the bonding wires of the wire-bonding structure will be broken, causing the chip with the wire-bonding structure to fail), thereby reducing the process difficulty of the chip packaging structure and reducing the size of the chip packaging structure to a certain extent.

[0122] The third chip pad 41 is exposed on the first surface 11. Specifically, the third chip pad 41 is arranged on the first surface 11, and the portion exposed on the first surface 11 has a certain height in the thickness direction of the chip packaging structure; of course, the third chip pad 41 can also be arranged inside the substrate 10 and exposed on the first surface 11, wherein the portion exposed on the first surface 11 has a certain height in the thickness direction of the chip packaging structure, or the portion exposed on the first surface 11 is flush with the first surface 11.

[0123] It should be noted that the height of the portion of the third die pad 41 exposed from the first surface 11 should be smaller than the height of the solder resist layer 12 on both sides of the third die pad 41 , thereby protecting the third die pad 41 .

[0124] In this embodiment, the bottom surface of the third chip can be set on the solder resist layer 12 and bonded to the solder resist layer 12 through a bonding material, or it can be directly set on the first surface 11 and bonded to the first surface 11 through a bonding material.

[0125] In one embodiment, the adhesive portion includes a fourth adhesive portion 54, and the chip packaging structure also includes a first solder joint and a second solder joint, and the fourth adhesive portion 54 at least partially covers the first solder joint and / or the second solder joint; wherein the first solder joint is a solder joint connecting the bonding wire to the top surface of the third chip, and the second solder joint is a solder joint connecting the bonding wire to the third chip pad 41.

[0126] In this embodiment, for the third chip 40 of the wire bonding structure, a fourth glue material portion 54 is further provided to cover at least the first solder joint and / or the second solder joint, as shown in Figures 5 and 6. The fourth glue material portion 54 can be formed by a dispensing process, or by a full spraying process, or by the combined action of a dispensing process and a full spraying process. No specific restrictions are made here, and the first solder joint and the second solder joint are not shown in the drawings of this application.

[0127] For example, in one embodiment, the fourth adhesive portion 54 only covers the second welding point; in another embodiment, the fourth adhesive portion 54 only covers the first welding point; in yet another embodiment, the fourth adhesive portion 54 covers the first welding point and the second welding point.

[0128] In some embodiments, the fourth adhesive portion 54 may only cover the second solder joint, or may cover the third chip pad 41 while covering the second solder joint, which is not limited in this application.

[0129] In this embodiment, the fourth adhesive portion 54 can be formed at the first solder joint and / or the second solder joint by a dispensing process. It covers at least one of the first solder joint and the second solder joint, thereby protecting the solder joint of the third chip and preventing the solder joint from falling off and causing a circuit breaker in the third chip.

[0130] In this embodiment, the fourth adhesive portion 54 at least partially covers the first solder joint and / or the second solder joint, thereby protecting the solder joint of the third chip, such as reducing the impact of the plastic encapsulation material 13 on the third chip pad 41 during filling, thereby reducing damage to the first solder joint and / or the second solder joint, causing failure of the third chip 40.

[0131] As shown in Figures 5 and 6, in this embodiment, the glue part includes a first glue part 51, a second glue part 52, and a third glue part 53, wherein the first glue part 51 is arranged on the substrate, the second glue part 52 is arranged on the top surface of the first chip 20 and / or the second chip 30, wherein the second chip 30 is a non-filter chip with a flip-chip structure, and the third glue part is arranged on the first surface 11 of the substrate.

[0132] In particular, when there is a third chip, the third chip is a non-filter chip with a wire bonding structure. Since the third chip is interconnected with the third chip pad 41 through a bonding wire 42, and generally includes a third chip pad 41, a solder resist layer 12 will be set around the third chip pad 41, and the third chip pad 41 is exposed to the first surface. At this time, the adhesive part also includes a fourth adhesive part, and the fourth adhesive part can be regarded as being set on the top surface of the third chip and / or the outer surface of the third chip pad 41 and the part of the first surface adjacent to the third chip pad 41.

[0133] In this embodiment, the portion of the first surface adjacent to the third die pad 41 is the portion of the first surface surrounded by the solder resist layer disposed around the third die pad 41 .

[0134] Specifically, as shown in Figure 5, the fourth glue portion 54 covers the first solder joint by dispensing, and covers the portion of the top surface of the third chip 40 adjacent to the first solder joint. At the same time, the fourth glue portion 54 also covers the second solder joint by dispensing, and covers the outer surface of the third chip pad 41, and covers the portion of the first surface adjacent to the third chip pad 41.

[0135] 6 , in the manner of forming the adhesive portion by a full spraying process, the fourth adhesive portion 54 covers the top surface of the third chip 40 and covers the portion of the first surface enclosed by the solder resist layer disposed around the third chip pad 41 .

[0136] In one embodiment, the first chip 20 includes a filter chip and / or a non-filter chip, and the second chip 30 includes a non-filter chip.

[0137] It can be understood that although Figures 1 to 6 all show that the first chip 20, the second chip 30 and the third chip are arranged on the first surface 11, in some embodiments, in order to further reduce the volume of the chip packaging structure, the first chip 20, the second chip 30 and the third chip 40 can also be arranged on the other surface of the substrate 10 opposite to the first surface 11.

[0138] An embodiment of the present application provides a radio frequency front-end module, including the chip packaging structure proposed in the above embodiment.

[0139] The present application also provides an electronic device, including a circuit board and a chip packaging structure. The chip packaging structure is arranged on the circuit board and electrically connected to the circuit board. The chip packaging structure includes the structure described in the above embodiment. For related descriptions, please refer to the contents of the above embodiment. The embodiments of the present application will not be repeated here.

[0140] In an exemplary embodiment, the electronic device includes but is not limited to any electronic device or component having a PCBA board assembly, such as an LED panel, a tablet computer, a laptop computer, a navigator, a mobile phone, and an electronic watch, and this application does not impose specific restrictions on this.

[0141] It is understandable that the electronic device may also include electronic devices such as personal digital assistants (PDAs) and / or music player functions, such as mobile phones, tablet computers, wearable electronic devices with wireless communication functions (such as smart watches), etc. The above-mentioned electronic devices may also be other electronic devices, such as laptop computers (Laptops) with touch-sensitive surfaces (such as touch panels), etc. In some embodiments, the electronic device may have a communication function, that is, it may establish communication with the network through 2G (second-generation mobile phone communication technology specifications), 3G (third-generation mobile phone communication technology specifications), 4G (fourth-generation mobile phone communication technology specifications), 5G (fifth-generation mobile phone communication technology specifications), 6G (sixth-generation mobile phone communication technology specifications) or W-LAN (wireless local area network) or communication methods that may appear in the future. For the sake of simplicity, this embodiment of the present application is not further limited.

[0142] It is understandable that in order to avoid redundancy, some details of the same or similar technical features in the above specification are not described in detail in some embodiments or implementations, but in fact these details are also applicable to different embodiments or implementations.

[0143] The above are only preferred embodiments of the present application and do not limit the patent scope of the present application. All equivalent structural transformations made based on the contents of the present application specification and drawings, or direct / indirect applications in other related technical fields, are included in the patent protection scope of the present application.

Claims

1. A chip packaging structure, wherein: A substrate having a first chip bonding pad and a second chip bonding pad disposed on a first surface; A first chip is disposed on the first surface, a first conductive bump is disposed on the bottom surface of the first chip, and the first conductive bump is interconnected with the first chip pad; A second chip is arranged on the first surface, a second conductive bump is arranged on the bottom surface of the second chip, and the second conductive bump is interconnected with the second chip pad; A solder resist layer is disposed on the first surface, and the solder resist layer is at least partially disposed between the first chip and the substrate, and a cavity is formed between the first chip, the solder resist layer and the substrate; A glue part, the glue part includes a first glue part, the first glue part at least partially surrounds the first chip and is arranged on the solder resist layer; wherein the distance between the bottom surface of the first chip and the solder resist layer is smaller than the height of the first glue part adjacent to the first chip, and the distance between the bottom surface of the first chip and the substrate is smaller than the distance between the second chip and the substrate; The plastic packaging material covers the solder resist layer, the adhesive material portion, the first chip and the second chip, and fills a gap between the second chip and the substrate.

2. The chip packaging structure according to claim 1, wherein: The first adhesive portion at least partially covers a side surface of the first chip.

3. The chip packaging structure according to claim 1, wherein: The first adhesive material portion has at least one slope peak.

4. The chip packaging structure according to claim 1, wherein: The adhesive part further includes a second adhesive part, and the second adhesive part is arranged on the upper surface of the first chip and / or the second chip.

5. The chip packaging structure according to claim 1, wherein: The adhesive material portion further includes a third adhesive material portion, and the third adhesive material portion is disposed on the first surface.

6. The chip packaging structure according to claim 1, wherein: The height difference between any two positions in the adhesive material portion in the thickness direction is less than a preset error value.

7. The chip packaging structure according to claim 1, wherein: In the thickness direction of the substrate, the height of the first adhesive portion is smaller than the distance between the second chip and the solder resist layer.

8. The chip packaging structure according to claim 1, wherein: The distance between the second chip and the first adhesive material portion is greater than 30 micrometers.

9. The chip packaging structure according to claim 1, wherein: The distance between the second chip and the first adhesive material portion is greater than 50 micrometers.

10. The chip packaging structure according to claim 1, wherein: The distance between the first chip and the second chip is less than 150 micrometers.

11. The chip packaging structure according to claim 1, wherein: A distance between the first chip and the second chip is greater than 50 micrometers and less than 100 micrometers.

12. The chip packaging structure according to claim 1, wherein: On the plane where the substrate is located, the distance between the second chip and the solder resist layer is greater than 100 micrometers.

13. The chip packaging structure according to claim 1, wherein: The chip packaging structure further includes a third chip. A bonding wire is disposed on the top surface of the third chip. The bonding wire of the third chip is interconnected with a third chip pad disposed on the first surface.

14. The chip packaging structure according to claim 13, wherein: The adhesive material portion includes a fourth adhesive material portion, the chip packaging structure further includes a first solder joint and a second solder joint, and the fourth adhesive material portion at least partially covers the first solder joint and / or the second solder joint; wherein, The first solder joint is a solder joint where the bonding wire is connected to the top surface of the third chip, and the second solder joint is a solder joint where the bonding wire is connected to the pad of the third chip.

15. The chip packaging structure according to claim 1, wherein: The first chip includes a filter chip and / or a non-filter chip, and the second chip includes a non-filter chip.

16. A chip packaging structure, wherein: A substrate having a first chip bonding pad and a second chip bonding pad disposed on a first surface; A first chip is disposed on the first surface, a first conductive bump is disposed on the bottom surface of the first chip, and the first conductive bump is interconnected with the first chip pad; A second chip is arranged on the first surface, a second conductive bump is arranged on the bottom surface of the second chip, and the second conductive bump is interconnected with the second chip pad; The distance between the first chip and the second chip is less than 150 microns; A glue part, the glue part comprising a first glue part, the first glue part at least partially covers a side surface of the first chip; The plastic packaging material covers the plastic material portion, the first chip and the second chip, and fills the gap between the second chip and the substrate.

17. A radio frequency front-end module, wherein: Comprising the chip packaging structure as claimed in any one of claims 1 to 16.

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