Lightning strike counting method and apparatus for communication power supply

Abstract

A lightning strike counting method and apparatus for a communication power supply. The method comprises: generating a plurality of sequential pulses for a plurality of ADCs in a time-interleaved analog-to-digital converter (TIADC) (S202); on the basis of the plurality of sequential pulses, sequentially starting the plurality of ADCs to sample a lightning strike voltage and a lightning strike current (S204); and the plurality of ADCs sequentially outputting sampling signals, to complete lightning strike counting of a communication power supply (S206).

Description

Communication power supply lightning strike counting method and device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on Chinese patent application CN202311258023.8, filed on September 26, 2023, entitled “Method and Device for Counting Lightning Strike for Communication Power Supply”, and claims the priority of the patent application. All the disclosed contents are incorporated into this application by reference. Technical Field

[0003] The embodiments of the present disclosure relate to the field of communications, and in particular, to a method and device for counting lightning strikes on a communications power supply. Background Art

[0004] For communications equipment rooms, lightning protection systems generally consist of external and internal systems. The external lightning protection system includes lightning arresters (or lightning rods), conductors that direct current to the ground (or down conductors), and buried grounding bodies, among other grounding devices. The internal lightning protection system is designed to prevent damage to energized equipment caused by lightning and surges. It includes specialized equipment such as equipotential bonding, surge protectors, AC / DC power supply lightning arresters, signal lightning arresters, and antenna lightning arresters. For example, based on the IEC (International Electrotechnical Commission) standard for zoned lightning protection and multi-level protection, a first-level lightning arrester (Class B) is deployed on the main distribution cabinet within the equipment room building to dissipate high-energy lightning currents from the power supply lines. A second-level lightning arrester (Class C) is deployed on branch distribution cabinets to further dissipate current and reduce residual voltage. A third-level lightning arrester (Class D) is deployed at the front of critical equipment to further dissipate current and reduce voltage, protecting the equipment ports and the high-precision integrated circuits within. Clearly, the working condition and timely maintenance of each level of lightning arresters are key to ensuring safe system operation. The industry also typically uses lightning strike counters with lightning arresters to record and count the number of lightning strikes on the arrester. This serves as an important basis for targeted inspections by maintenance personnel.

[0005] Currently, various communication power supply lightning strike counters on the market simply record the number and duration of lightning strikes, serving as a basic reference for lightning arrester performance testing and lifespan assessment. Because they fail to accurately record key operating parameters such as the number, duration, and discharge energy of repeated strikes during a lightning strike, they offer no clear and accurate understanding of local lightning strike frequency, the true operating status of lightning arresters, and provide a crucial basis for lightning arrester inspection.

[0006] Summary of the Invention

[0007] Embodiments of the present disclosure provide a method and device for counting lightning strikes on a communication power supply.

[0008] According to one embodiment of the present disclosure, a method for counting lightning strikes on a communication power supply is provided, comprising: generating a plurality of sequential pulses for a plurality of analog-to-digital converters (ADCs) in a time-interleaved analog-to-digital converter (TIADC); sequentially starting the plurality of ADCs to sample lightning voltage and lightning current based on the plurality of sequential pulses; and sequentially outputting the sampled signals by the plurality of ADCs to complete the counting of lightning strikes on the communication power supply.

[0009] According to another embodiment of the present disclosure, a communication power supply lightning strike counting device is provided, comprising: a microprocessor, a beat generator, a voltage sensor, a current sensor, and a time-interleaved analog-to-digital converter (TIADC), wherein the microprocessor is configured to generate a high-frequency clock; the beat generator is configured to generate a plurality of sequential pulses for a plurality of analog-to-digital converters (ADC) in the TIADC according to the high-frequency clock; the voltage sensor is configured to collect a lightning strike voltage and condition the lightning strike voltage; the current sensor is configured to collect a lightning strike current and condition the lightning strike current; and the TIADC is configured to sequentially start a plurality of the ADCs to sample the lightning strike voltage and the lightning strike current according to a plurality of the sequential pulses. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG1 is a hardware structure block diagram of a computer terminal for a communication power supply lightning strike counting method according to an embodiment of the present disclosure;

[0011] FIG2 is a flow chart of a method for counting lightning strikes of a communication power supply according to an embodiment of the present disclosure;

[0012] FIG3 is a structural block diagram of a communication power supply lightning strike counting device according to an embodiment of the present disclosure;

[0013] FIG4 is a diagram showing the overall structure of a lightning strike counting device according to an embodiment of the present disclosure;

[0014] FIG5 is a schematic diagram of a voltage and current signal acquisition principle according to an embodiment of the present disclosure;

[0015] FIG6 is a schematic diagram of temperature and humidity signal acquisition principles according to an embodiment of the present disclosure;

[0016] FIG7 is a schematic diagram of lightning counting and timing according to an embodiment of the present disclosure;

[0017] FIG8 is a schematic diagram of a sequential pulse generation principle according to an embodiment of the present disclosure;

[0018] FIG9 is a schematic diagram showing the principle of sequentially starting sampling and latching of voltage and current signals according to an embodiment of the present disclosure;

[0019] FIG10 is a schematic diagram of a signal analog-to-digital conversion output principle according to an embodiment of the present disclosure;

[0020] FIG11 is a schematic diagram of the central processing module architecture according to an embodiment of the present disclosure;

[0021] FIG12 is a schematic diagram of a high-speed sampling interrupt response service process according to an embodiment of the present disclosure;

[0022] FIG13 is a schematic diagram of a microprocessor background program operation process according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0023] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings and in combination with the embodiments.

[0024] It should be noted that the terms "first", "second", etc. in the description and claims of the embodiments of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0025] Lightning strikes are a common natural phenomenon, characterized by high current, high voltage, and short duration. Their immense destructive power brings devastating disasters to human society, increasingly posing a serious threat to the national economy and human safety. A single lightning strike can instantly damage communications equipment worth millions of yuan, disrupt communication networks, and even cause fires and casualties, bringing immeasurable losses and damage to the modern information society. Therefore, telecommunications operators are actively implementing lightning protection and disaster reduction measures to minimize damage and ensure communication network security and business profitability.

[0026] Currently, there are three main types of lightning strike counters on the market.

[0027] The most common lightning strike counting device is generally mounted on a 35mm electrical rail and uses a dedicated electromagnetic mechanical counter to count lightning strikes. The basic principle is that when struck by lightning, the arrester activates, and the voltage drop across the nonlinear resistor of the high-temperature valve plate is rectified by a bridge to charge the energy storage capacitor. This capacitor then discharges the energy into the coil of the electromagnetic counter. The inductive current flows through the coil, inducing an electromagnetic field, magnetizing the internal iron core, attracting the armature, and rotating the counter pointer, completing the count. Obviously, this counter is relatively slow and only records the number of lightning strikes, with a timing interval of at least 1 second. To prevent moisture, corrosion, or damage, the counter is sealed in a plastic box, which is epoxy-infused to ensure a tight seal. Opening the box lid is strictly prohibited during use.

[0028] Another type of intelligent lightning strike counter is this one. It draws power from a 220VAC power supply. The arrester's ground wire passes through the counter's transformer coil, and displays are typically LED or LCD. When lightning strikes a line, the arrester activates, discharging the lightning current to the ground. The transformer, attached to the ground wire, collects the current signal and transmits it to the counter's calculation and comparison circuits, thereby counting the lightning strikes. The counter also includes a built-in clock chip that records the year, month, day, hour, minute, and second of the lightning strike. It can record up to 1,000 lightning strikes, has a power-off memory function, and supports remote monitoring via communication interfaces such as RS485 and Ethernet. Obviously, this counter also records the number of lightning strikes, with a timing interval of at least 100ms.

[0029] A single lightning discharge typically consists of multiple repetitive impulse discharges. A typical lightning discharge will include two or three lightning strikes, separated by approximately one-twentieth of a second, and most lightning currents typically last less than 100µs. Statistics show that approximately 55% of lightning strikes contain two or more impulses, 25% contain three impulses, and 4% contain more than ten impulses. The average repetition rate is three, with a maximum of 42. Fifty percent of lightning discharges last less than 0.2µs, while only 5% last longer than 0.62µs. Lightning current waveforms are also generally consistent, with a wave head of approximately 1-10µs, a wavelength of 20-100µs, an average of approximately 50µs, and only 18-30% lasting longer than 50µs. Therefore, recording the number and duration of impulse discharges more accurately reflects the lightning strike; recording the arrester leakage current more directly reflects the energy of the lightning strike and the arrester's performance. The above two technical solutions only simply record and count the number of lightning strikes, but cannot record the complete process of lightning discharge, including the number of impulse discharges, duration, leakage current, etc.; therefore, it is impossible to clearly and intuitively understand the local lightning strike frequency, grasp the working status of the lightning protection device, and provide a reference basis for the inspection of the lightning arrester.

[0030] Of course, there are also highly specialized intelligent lightning arrester condition detection terminals on the market that can comprehensively monitor lightning current parameters, including peak value, effective value, wave crest, duration, energy, and number of lightning currents. These products also integrate solar panels, lithium batteries, and GPS. However, these terminals are typically used in medium- and high-voltage power distribution networks ranging from 10kV to 750kV. Furthermore, their size and cost make them unsuitable for widespread deployment and use in communications rooms and power supply equipment.

[0031] Therefore, the embodiments of the present disclosure provide a lightning strike counter device that can be widely used in communication rooms and power supply equipment. It can quickly, accurately and completely record and truly reproduce a lightning discharge process; at the same time, it has high measurement accuracy, low cost, small size and no sealing requirements; it is convenient for users to clearly and intuitively understand the impact frequency of lightning induction and grasp the working status of the power supply lightning arrester; it realizes real-time and accurate lightning strike recording and warning, completes the transformation from preventive maintenance to predictive maintenance, reduces maintenance costs, and better avoids lightning disasters, ensuring the security of communication networks and corporate benefits.

[0032] The method embodiments provided in the embodiments of the present application can be executed in a mobile terminal, a computer terminal or a similar computing device. Taking operation on a computer terminal as an example, FIG1 is a hardware structure block diagram of a computer terminal of a communication power supply lightning strike counting method according to an embodiment of the present disclosure. As shown in FIG1 , the computer terminal may include one or more (only one is shown in FIG1 ) processors 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above-mentioned computer terminal may also include a transmission device 106 and an input and output device 108 for communication functions. It will be understood by those skilled in the art that the structure shown in FIG1 is only for illustration, and it does not limit the structure of the above-mentioned computer terminal. For example, the computer terminal may also include more or fewer components than those shown in FIG1 , or have a configuration different from that shown in FIG1 .

[0033] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the communication power supply lightning strike counting method in the embodiment of the present disclosure. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implementing the above-mentioned method. The memory 104 may include a high-speed random access memory and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include a memory remotely located relative to the processor 102, and these remote memories may be connected to the mobile terminal via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0034] The transmission device 106 is used to receive or transmit data via a network. A specific example of the aforementioned network may include a wireless network provided by a communications provider of a computer terminal. In one embodiment, the transmission device 106 includes a network interface controller (NIC), which can be connected to other network devices via a base station to enable communication with the Internet. In another embodiment, the transmission device 106 may be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0035] In this embodiment, a method for counting lightning strikes of a communication power supply running on the above-mentioned computer terminal is provided. FIG2 is a flow chart of the method for counting lightning strikes of a communication power supply according to an embodiment of the present disclosure. As shown in FIG2 , the flow chart includes the following steps:

[0036] Step S202, generating a plurality of sequential pulses for a plurality of analog-to-digital converters (ADCs) in a time-interleaved analog-to-digital converter (TIADC);

[0037] In an exemplary embodiment, generating multiple sequential pulses for multiple analog-to-digital converters ADC in a time-interleaved analog-to-digital converter TIADC includes dividing a high-frequency clock and generating multiple sequential pulses according to the divided high-frequency clock.

[0038] In actual implementation, the high-speed clock is divided and then enters the beat generator (or ring counter) to generate multiple sequential pulses.

[0039] Step S204: sequentially start multiple ADCs to sample the lightning voltage and current according to the multiple sequential pulses;

[0040] In an exemplary embodiment, multiple ADCs are sequentially started to sample lightning voltage and lightning current according to multiple sequential pulses, including: the lightning voltage or lightning current is simultaneously connected to multiple ADCs, and the multiple ADCs are sequentially started to perform analog-to-digital conversion according to the sequential pulses to complete the sampling of the lightning voltage or lightning current.

[0041] In an exemplary embodiment, sequentially starting multiple ADCs to sample lightning voltage and lightning current includes: m ADCs alternately sampling the same lightning voltage or lightning current according to multiple sequential pulses, wherein the clock phase deviation of adjacent ADCs is 2π / m.

[0042] In actual implementation, the lightning voltage signal is simultaneously connected to the analog inputs of m ADCs (the same applies to the lightning current). Sequential pulses Q1, Q2, Q3, and Qm serve as sampling start signals for each ADC, sequentially activating analog-to-digital conversion. These alternately sampled signals are combined in chronological order to achieve high-speed sampling.

[0043] In an exemplary embodiment, when a lightning strike occurs, a common counter is used to count the number of lightning strikes, and a high-speed counter is used to time the duration of a single lightning strike and the duration of an interval between lightning strikes.

[0044] In an exemplary embodiment, before using an ordinary counter to count the number of lightning strikes and using a high-speed counter to time the duration of a single lightning strike and the duration of the interval between lightning strikes, the method also includes: conditioning the leakage current of the lightning arrester to obtain a comparison voltage; when the comparison voltage is greater than a first voltage threshold, determining that a lightning strike has occurred; when the comparison voltage is greater than a second voltage threshold, determining to start sampling the lightning voltage and lightning current, wherein the second voltage threshold is less than the first voltage threshold.

[0045] In actual implementation, when the second voltage threshold is less than the first voltage threshold, fast sampling can be started before triggering lightning counting to record the lightning current wave head.

[0046] In an exemplary embodiment, an ordinary counter is used to count the number of lightning strikes, and a high-speed counter is used to time the duration of a single lightning strike and the duration of an interval between lightning strikes, including: obtaining a first level signal based on a comparison result between a comparison voltage and the first voltage threshold; triggering the ordinary counter to add 1 to the count of the number of lightning strikes based on a rising edge of the first level signal; when the first level signal is at a high level, using a first high-speed counter to time the duration of a single lightning strike; and when the first level signal is at a low level, using a second high-speed counter to time the duration of an interval between lightning strikes.

[0047] In an exemplary embodiment, an ordinary counter is used to count the number of lightning strikes, and a high-speed counter is used to time the duration of a single lightning strike and the duration of the interval between lightning strikes. It also includes: triggering a first interrupt response signal according to the rising edge of a first level signal, and the first high-speed counter obtains the timing start time of the duration of a single lightning strike according to the first interrupt response signal; triggering a second interrupt response signal according to the falling edge of the first level signal, and the first high-speed counter obtains the timing end time of the duration of a single lightning strike according to the second interrupt response signal.

[0048] In an exemplary embodiment, a high-speed counter is used to time the duration of a single lightning strike and the duration of the interval between lightning strikes, including: connecting a high-speed counter in series with an ordinary counter to time the duration of a single lightning strike and the duration of the interval between lightning strikes.

[0049] In actual implementation, due to the wide range of counts required, a high-speed counter is connected in series with a conventional counter to expand the counting range while reducing hardware costs. For example, a 32-bit counter can be constructed by connecting one 8-bit high-speed counter in series with three 8-bit conventional counters, achieving a maximum count of 4G. If the counter clock is 1.0GHz, the maximum count duration is 4s.

[0050] In an exemplary embodiment, after sequentially starting the plurality of ADCs to sample the lightning voltage and the lightning current, the method further includes: latching the sampling results.

[0051] In the actual implementation process, the sampling results are latched, which essentially allows the microprocessor to retrieve the results of the previous round of sampling before the end of the next round of conversion, reducing the real-time requirements of the interrupt response to read the conversion results, thereby reducing the performance requirements and hardware costs of the microprocessor and improving the reliability of the system.

[0052] In step S206 , the plurality of ADCs sequentially output the sampling signals to complete the counting of lightning strikes on the communication power supply.

[0053] In an exemplary embodiment, multiple ADCs sequentially output sampling signals, including: triggering a third interrupt response signal after the multiple ADCs perform analog-to-digital conversion on the sampling signals; sequentially reading the ADC outputs according to the first third interrupt response signal until the ADC outputs are invalid; and sequentially reading the ADC outputs starting from the ADC output whose reading is completed according to the (m-1)th third interrupt response signal according to the mth third interrupt response signal, until the sequential reading of the outputs of the multiple ADCs is completed.

[0054] In actual implementation, after each ADC completes analog-to-digital conversion, it outputs a "conversion complete" signal; after using this signal to latch the conversion result, the next sequential pulse automatically initiates the next sampling cycle. Depending on the requirements of the ADC chip, the "conversion complete" signal may require a short delay before the sampled data can be read and latched. In actual implementation, the fast sampling completion interrupt signal is only generated during the duration of the lightning strike. When the interrupt signal is generated, the microprocessor's interrupt response program first reads the general-purpose input / output (GPIO) input terminal to determine which ADC completed the conversion, and then reads the conversion output value of that ADC.

[0055] Through the above steps, a method for counting lightning strikes on a communications power supply is provided. Multiple sequential pulses are generated for multiple ADCs in a time-interleaved analog-to-digital converter (TIADC). Based on these sequential pulses, multiple ADCs are sequentially activated to sample lightning voltage and current. The multiple ADCs sequentially output the sampled signals to complete the lightning strike counting for the communications power supply. This method solves the problem in related technologies of being unable to clearly and accurately understand the local lightning strike frequency and the true working condition of the lightning protection device, achieving the effect of accurately counting the lightning strike frequency and understanding the true working condition of the lightning protection device.

[0056] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the embodiment of the present disclosure is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD-ROM), including a number of instructions for enabling a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the method described in the embodiment of the present disclosure.

[0057] This embodiment also provides a communication power supply lightning strike counting device, which is used to implement the above-mentioned embodiments and preferred embodiments. Details already described will not be repeated here. As used below, the term "module" may refer to a combination of software and / or hardware that implements a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, implementation using hardware, or a combination of software and hardware, is also possible and contemplated.

[0058] Figure 3 is a structural block diagram of a communication power supply lightning strike counting device according to an embodiment of the present disclosure. As shown in Figure 3, the counting device 30 includes: a microprocessor 310, a beat generator 320, a voltage sensor 330, a current sensor 340, and a time-interleaved analog-to-digital converter TIADC 350, wherein the microprocessor 310 is configured to generate a high-frequency clock; the beat generator 320 is configured to generate multiple sequential pulses for multiple analog-to-digital converters ADC in the TIADC 350 according to the high-frequency clock; the voltage sensor 330 is configured to collect lightning strike voltage and condition the lightning strike voltage; the current sensor 340 is configured to collect lightning strike current and condition the lightning strike current; and the TIADC 350 is configured to sequentially start multiple ADCs to sample lightning strike voltage and lightning strike current according to multiple sequential pulses.

[0059] In an exemplary embodiment, the counting device further includes: a normal counter and a high-speed counter, wherein the normal counter is configured to count the number of lightning strikes; and the high-speed counter is configured to time the duration of a single lightning strike and the duration of the interval between lightning strikes.

[0060] In an exemplary embodiment, the above-mentioned counting device also includes: a first voltage comparator and a second voltage comparator, wherein the first voltage comparator is configured to compare the comparison voltage with a first voltage threshold, determine whether a lightning strike occurs, and output a first level signal; the second voltage comparator is configured to compare the comparison voltage with a second voltage threshold, determine whether to start sampling the lightning strike voltage and lightning strike current, and output a second level signal.

[0061] In an exemplary embodiment, the above-mentioned microprocessor 310 is also configured to trigger a first interrupt response signal according to the rising edge of the first level signal, and the first interrupt response signal is configured to indicate the first high-speed counter in the high-speed counter to obtain the timing start time of the duration of a single lightning strike; the microprocessor 310 is also configured to trigger a second interrupt response signal according to the falling edge of the first level signal, and the second interrupt response signal is configured to indicate the first high-speed counter to obtain the timing end time of the duration of a single lightning strike.

[0062] In an exemplary embodiment, the microprocessor 310 is further configured to trigger a third interrupt response signal after the plurality of ADCs sample the lightning voltage and the lightning current, wherein the third interrupt response signal is configured to indicate reading the outputs of the plurality of ADCs.

[0063] It should be noted that the above modules can be implemented through software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0064] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail here.

[0065] Obviously, those skilled in the art should understand that the modules or steps of the above-mentioned embodiments of the present disclosure can be implemented using a general-purpose computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented using program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be performed in a different order than herein, or they can be made into individual integrated circuit modules, or multiple modules or steps can be made into a single integrated circuit module for implementation. Thus, the embodiments of the present disclosure are not limited to any specific combination of hardware and software.

[0066] In order to enable those skilled in the art to better understand the technical solutions of the embodiments of the present disclosure, the following is an elaboration with reference to specific scenario embodiments.

[0067] Scenario Example 1

[0068] Figure 4 is a diagram of the overall architecture of a lightning strike counting device according to an embodiment of the present disclosure. As shown in Figure 4, the lightning strike counting device includes four parts: a signal acquisition and comparison module, a lightning strike counting and timing module, an analog-to-digital conversion module, and a central processing module. The signal acquisition and comparison module completes data acquisition and signal conditioning from the lightning strike current and voltage signal sensors, and compares and determines whether a lightning strike has occurred and whether rapid sampling should be performed; the lightning strike counting and timing module completes the accumulation of the number of lightning strikes and the timing of the duration of a single strike; the analog-to-digital conversion module completes the sampling of lightning strike current and voltage; and the central processing module, consisting of a microprocessor (DSP, MCU, or MPU) minimum application system, is the brain of the device and is responsible for various functions such as receiving, processing, storing, analyzing, and executing measurement data.

[0069] In the actual implementation process, the signal acquisition and comparison module completes the data acquisition, signal conditioning, and comparison and judgment of the lightning current and voltage signal sensors.

[0070] 1. Lightning voltage signal acquisition. Figure 5 is a schematic diagram of the voltage and current signal acquisition principle according to an embodiment of the present disclosure. As shown in Figure 5, the grid voltage (normal voltage or overvoltage) borne by the lightning arrester is collected through a voltage sensor or a mutual inductor. Due to the high noise and interference on the line during a lightning strike, it is necessary to first reduce the noise and filter the sensor acquisition signal to obtain relatively ideal data before conditioning. Signal conditioning is actually to convert the sensor signal into a suitable voltage signal through an operational amplifier and clamp it to a certain value (such as within the ADC analog input range), and the output is V0.

[0071] 2. Lightning current signal acquisition: The leakage current of the arrester (lightning current or total leakage current) is collected through a current sensor (such as a Rogowski coil). Similarly, the current signal collected by the sensor must first be noise-reduced and filtered before being conditioned. In order to improve the accuracy of ADC sampling, the collected signal is conditioned through three different channels: the first channel conditioning target is the larger lightning current, and the clamped output is V1; the second channel conditioning target is the weak total leakage current (generally with a range of 0 to 10mA), and the clamped output is V2 after gain amplification; the third channel conditioning output V3 is used to compare with the threshold voltage to determine whether a lightning strike has occurred and whether fast sampling is required:

[0072] (1) V3 enters the input terminal of the voltage comparator 1 and is compared with the voltage threshold Vr1 set by the system (for example, corresponding to the lower limit operating current value of the lightning arrester). The output Ca is used to judge whether there is a lightning strike: if the V3 value is lower than the threshold, the comparator output Ca is low, indicating that there is no lightning strike; otherwise, Ca is a high-level signal, indicating that there is a lightning strike.

[0073] (2) V3 enters the input of voltage comparator 2 and is compared with the system-set voltage threshold Vr2. The output Cb is used to determine whether rapid sampling is required. If the value of V3 is lower than the threshold, the comparator output Cb is low, indicating that rapid sampling is not required; otherwise, Cb is high, indicating that rapid sampling is required. In addition, the set voltage threshold Vr2 should be slightly lower than Vr1, indicating that rapid sampling should be initiated before triggering the lightning count to record the lightning current wave head.

[0074] 3. Temperature and humidity signal acquisition. FIG6 is a schematic diagram of the temperature and humidity signal acquisition principle according to an embodiment of the present disclosure. As shown in FIG6 , similar to the lightning voltage signal acquisition, the sensor acquisition signal is subjected to noise reduction and filtering, and after conditioning, the clamped output is V4 and V5.

[0075] In actual implementation, the lightning strike counting and timing module completes the accumulation of the number of lightning strikes and the timing of the duration of a single impact. Figure 7 is a schematic diagram of the lightning strike counting and timing principle according to an embodiment of the present disclosure, as shown in Figure 7:

[0076] 1. Accumulation of lightning strikes: The comparator Ca signal output by the signal acquisition and comparison module is connected to the clock input of the "strike count counter." The rising edge of the Ca signal triggers the counter to increment by one. Because a single strike typically lasts from tens of microseconds to hundreds of milliseconds, counting is slow, so a conventional counter is used.

[0077] 2. Timing of single impulse duration: To truly reproduce the lightning discharge process, it is necessary to accurately measure the duration of a single impulse to nanoseconds. Since the timers / counters built into ordinary microprocessors have low accuracy, high-speed counting technology is used, which mainly includes three parts: high-frequency clock generation, clock distribution, and high-speed counters:

[0078] (1) High-frequency clock generation: High-frequency clock generation is based on the principle of phase-locked frequency multiplication. The microprocessor communicates with the high-frequency clock generator PLL with integrated VCO and writes command words to control the output of the required high-frequency clock. If the high-frequency clock is 1.0GHz, the time-length timing accuracy can reach 1ns.

[0079] (2) Clock distribution: The high-frequency clock generated by the PLL is an analog signal with low output power. It is converted through a clock divider to obtain the clock source CLK (Clock) suitable for the high-speed counter.

[0080] (3) High-speed counter: Two high-speed counters are designed, one for timing the duration of the impact and the other for timing the interval between two impacts. Therefore, the enable terminal of the counter is connected to the comparator Ca signal. When Ca is high, the duration of the impact is timed; when Ca is low, the interval is timed. In addition, since the range to be counted is wide, a high-speed counter is connected in series with an ordinary counter to expand the counting range while reducing hardware costs. For example, a 32-bit counter can be constructed by connecting an 8-bit high-speed counter in series with three 8-bit ordinary counters to achieve a maximum count of 4G; if the counter clock is 1.0GHz, the maximum timing duration is 4s.

[0081] 3. The counter's output, the comparator Ca signal, is connected to the microprocessor's two external interrupt inputs: a rising edge triggers the interrupt routine to obtain the start time or interval time of the impact; a falling edge triggers the interrupt routine to obtain the duration of the impact. After obtaining the counter output value, the microprocessor immediately sends an active-low signal to reset the counter to zero for the next count.

[0082] In actual implementation, the analog-to-digital conversion module samples the lightning voltage and current. TIADC technology is used to achieve high-speed sampling during the lightning impulse period, while conventional sampling technology is used during the non-impact period.

[0083] 1. Conventional Sampling: A common multiplexed analog-to-digital converter (ADC) chip is used to sample four signals: AC voltage, total leakage current, temperature, and humidity. The AC voltage value can be used to assess grid quality during normal periods (when no lightning strikes occur); the total leakage current value can be used as a reference for evaluating the performance of lightning arresters; and the sampled temperature and humidity are used to mitigate the effects of total leakage current interference and improve its sampling accuracy. After the ADC conversion is complete, an interrupt signal triggers the microprocessor program to obtain the analog-to-digital conversion result. Since conventional sampling requires a relatively low speed, typically completing in about 1 second, an inexpensive, common ADC chip can be used. Furthermore, if the microprocessor has integrated ADC resources, these can be used directly, further reducing hardware costs.

[0084] 2. High-speed sampling: TIADC technology is used to achieve high-speed sampling of the lightning voltage V0 and lightning current V1 during the duration of the lightning impulse, facilitating the reproduction of the lightning waveform and the calculation of the impulse energy. The basic principle is to use m ADCs to alternately sample the same input signal, with the clock phase deviation of adjacent ADCs being 2π / m; the sampling results are then combined to achieve high-speed sampling. The details are as follows:

[0085] (1) Generate m sequential pulses: FIG8 is a schematic diagram of the sequential pulse generation principle according to an embodiment of the present disclosure. As shown in FIG8 , the high-speed clock CLK generated by the lightning strike counting and timing module is divided and then enters the beat generator (or ring counter) to generate m sequential pulses, Q1, Q2, Q3, ..., up to Qm; m is a positive integer;

[0086] (2) Sequential sampling: FIG9 is a schematic diagram showing the principle of sequentially sampling and latching voltage and current signals according to an embodiment of the present disclosure. As shown in FIG9 , the lightning voltage V0 signal is simultaneously connected to the analog input terminals of m ADCs (the same applies to the lightning current V1); sequential pulses Q1, Q2, Q3, ... Qm serve as sampling start signals for each ADC, sequentially starting each ADC to perform analog-to-digital conversion. The lightning current V1 is also sampled sequentially in the same manner;

[0087] (3) Latching the sampling results: After each ADC completes the analog-to-digital conversion, it will output a "conversion completed" signal; after the conversion result is latched using this signal, the next sequential pulse can automatically start the next sampling cycle. Depending on the requirements of different ADC chips, the "conversion completed" signal may also need a short delay to complete the reading and latching of the sampled data. Latching the sampling results essentially allows the microprocessor to retrieve the previous round of sampling results before the next round of conversion is completed, reducing the real-time requirements of the interrupt response to read the conversion results, thereby reducing the performance requirements and hardware costs of the microprocessor and improving the reliability of the system;

[0088] (4) Interrupt notification processing: FIG10 is a schematic diagram of the signal analog-to-digital conversion output principle according to an embodiment of the present disclosure. As shown in FIG10 , the "conversion completed" signal output by each ADC after completing the analog-to-digital conversion is connected to the GPIO input terminal of the microprocessor; at the same time, it is first connected to the external interrupt input terminal of the microprocessor after being wired and then ORed with the inverted signal of the fast sampling comparison output Cb. In other words, the interrupt signal indicating the completion of fast sampling will only be generated within the duration of the lightning strike. When the interrupt signal is generated, the interrupt response program of the microprocessor first reads the GPIO input terminal to determine which ADC has completed the conversion, and then reads the conversion output value of the ADC.

[0089] In the actual implementation process, the central processing module is composed of a microprocessor minimum application system. Figure 11 is a schematic diagram of the central processing module architecture according to an embodiment of the present disclosure. As shown in Figure 11, the central processing module is responsible for various functions such as receiving, processing, storing, analyzing and executing measurement data.

[0090] 1. Generate a high-frequency clock: The microprocessor communicates with the phase-locked loop (PLL) of the integrated voltage-controlled oscillator (VCO) via the serial peripheral interface (SPI). After writing a command word, it controls the output of the required high frequency. For example, controlling the ADF4360-6 chip can output a high-frequency clock of up to 1.2GHz.

[0091] 2. Generating a software clock: The microprocessor program generates a base software timer interrupt with a frequency of 1ms. The tick value in the interrupt program continuously accumulates and counts in a loop from 0 to 999.

[0092] 3. Constructing the decoding logic: By combining the logic and timing of the microprocessor's address bus and control bus (using methods such as erasable programmable logic devices (EPLDs)), the decoding logic is completed. This is supplemented by the data bus's transceiver buffer to enable read and write access to devices such as timers and ADCs.

[0093] 4. Get calendar time (millisecond precision): There are two ways to get it, the first one is preferred.

[0094] (1) The microprocessor extends a real-time clock (RTC) chip via a bus such as SPI or Inter-Integrated Circuit (I2C) (some microprocessors have a built-in RTC, which can also be used directly). Some RTCs can also achieve sub-second accuracy of 1ms, and after reading, the precise calendar time (year-month-day-hour-minute-second-millisecond) can be directly obtained;

[0095] (2) If the RTC real-time clock accuracy is only to the second level (year-month-day-hour-minute-second), use the tick value in the software clock as the millisecond part of the calendar time. Obviously, to improve the accuracy, it is necessary to synchronize the time (especially the tick value) through the network regularly;

[0096] 5. Fast timing and sampling: Through four external interrupt input signals, quickly respond and receive data.

[0097] (3) The rising edge of the lightning comparator output signal Ca triggers an interrupt: the interrupt response program reads the output value and carry output terminal of high-speed counter 2, and sends a low-active signal to clear the counter; finally, the current calendar time (millisecond accuracy) is obtained;

[0098] (4) The falling edge of the lightning comparator output signal Ca triggers an interrupt: the interrupt response program completes the accumulation of the number of impacts, reads the output value of high-speed counter 1 as the timing of the impact stop moment, and then sends a low-active signal to clear the counter; finally, obtains the current calendar time (millisecond accuracy);

[0099] (5) Conventional sampling completion triggers an interrupt: AC voltage V0, total leakage current of the lightning arrester V2, temperature V4 and humidity V5 are triggered after sampling by a common multiplexed ADC chip. The interrupt response program can read the conversion data output by the ADC chip. Among them, V0 and V2 are the AC voltage and total leakage current values ​​of the lightning arrester during normal periods (no lightning strikes). Of course, if an ADC integrated in a microprocessor is used, the processing process is the same. The only difference is that the ADC sampling completion interrupt source is generated inside the processor;

[0100] (6) High-speed sampling completion triggers interrupt: FIG12 is a schematic diagram of the high-speed sampling interrupt response service process according to an embodiment of the present disclosure. As shown in FIG12 , an interrupt is triggered after the lightning voltage V0 and lightning current V1 are sampled by TIADC. TIADC is composed of m ADCs. The interrupt response program first reads the input GPIO port to determine which of the m ADCs has completed the conversion, and then reads the conversion output value of the ADC. It is particularly important to note that the conversion output values ​​of each ADC need to be read sequentially in the program to avoid time misalignment:

[0101] ① When responding to the interrupt for the first time, the software first reads the completed output status values ​​of all ADCs on the GPIO port; and starting from the first ADC (sequence number 0), reads out the conversion output values ​​of all valid ADCs in sequence until a certain ADC state value is invalid; records the sequence number k of the ADC, obviously 0≤k <m;

[0102] ② When the subsequent response interrupt occurs, the software starts from k and loops to read the completed output status values ​​of the kth, k+1th (if the value of m is reached, it starts from 0) and so on ADCs on the GPIO port; if the status is valid, the corresponding ADC conversion output value is read; if the status is invalid, the reading stops and the new invalid ADC sequence number is reassigned to k;

[0103] ③ Repeat step ② to complete the sequential reading of each ADC conversion output value;

[0104] ④ It should be noted that since V0 and V1 are sampled synchronously, the ADC conversion output values ​​of V0 and V1 can be read simultaneously in the interrupt response program.

[0105] 6. Tasks such as data processing, storage and analysis are all performed in the program in the background.

[0106] (1) Data processing: The number of lightning strikes, impact duration, and sampled raw data values ​​read by the processor need to be processed for easy use.

[0107] ① Data conversion: According to the input clock frequency of the high-speed counter, the count values ​​of the impact duration and impact interval are converted into intuitive time length values, such as how many seconds, how many milliseconds, how many us, how many nanoseconds, etc.; according to the amplification factor of the conditioning circuit, the sampled original data value is converted into how many volts of voltage, how many amperes of current, etc.

[0108] ② Event identification: A lightning discharge usually includes multiple repeated impulse discharges. The duration of all impulse intervals is judged to identify the lightning event. For example, if the interval duration is less than the threshold value (such as 100ms, this value can be set), it is determined to be multiple impulses in a lightning process; if the interval duration exceeds the threshold value, it can be considered as another lightning event. As mentioned above, in the Ca signal rising edge interrupt response program, the output value and carry output terminal of high-speed counter 2, and calendar time (millisecond accuracy) are read. If any of the following three conditions are met, it will be identified as a new lightning discharge event:

[0109] The output value of high-speed counter 2 is 0 (indicating the first lightning strike);

[0110] The output value of high-speed counter 2 exceeds the threshold value (indicating that the interval duration is too long);

[0111] The carry output of high-speed counter 2 is valid (indicating that the interval is too long and the counter is full);

[0112] ③ Event Recording: Based on the identification of events, all data are integrated and aggregated to generate event record data. Including:

[0113] The starting time of this lightning strike event (year-month-day-hour-minute-second-millisecond) can be obtained by using the calendar time read in the interrupt response program;

[0114] The number of impacts in this lightning event;

[0115] Monitoring data of each impulse discharge process. Including:

[0116] a. Duration of the shock (milliseconds-microseconds-nanoseconds), or simply expressed in total nanoseconds;

[0117] b. The impulse voltage and impulse current values ​​during the impulse duration (the sampling interval is fixed, that is, the interval between sequential pulses);

[0118] Monitoring data after each impulse discharge. Including:

[0119] a. The duration of the interval after the impact ends (milliseconds-microseconds-nanoseconds), or directly expressed in total nanoseconds. That is, the interval between two discharges;

[0120] b. Normal AC voltage value and full leakage current value (conventional sampling interval is longer, about 1s level);

[0121] (2) Data storage: Data is saved after power failure according to the event recording format. Data is stored in a flash memory or electrically erasable programmable read-only memory (EEPROM) external to the microprocessor via a bus such as SPI / I2C. The data is saved in a cyclic manner, and the number of saved data depends on the size of the memory.

[0122] (3) Data analysis: After further analysis, the data can realize more valuable applications:

[0123] ① Value parameters: Analyze and calculate to obtain other parameters of the impulse discharge process, such as current peak, residual voltage peak, effective value, and energy;

[0124] ② Accurate counting: Analyze data, identify lightning impulses and power grid fluctuation impulses, and achieve accurate counting. The lightning current waveform is usually a unipolar pulse waveform, rising to a peak value in a short period of time, and then slowly decreasing from the peak value, presenting an arch pulse shape; the current waveform of induced lightning in communication sites and computer rooms is similar to the 8 / 20us waveform. Therefore, by analyzing whether the lightning current waveform is similar to the 8 / 20us arch pulse, it can be determined whether the impulse is a lightning impulse or a power grid fluctuation impulse, avoiding the mistaken counting of the power grid fluctuation impulse in the number of lightning strikes;

[0125] ③ In terms of the rising part of these lightning current waveforms, the lightning current of the subsequent negative lightning stroke rises very quickly, followed by the first negative lightning stroke, and the first positive lightning stroke is the slowest. In terms of the falling part of each lightning current waveform, the lightning current of the subsequent negative lightning stroke drops faster than the first negative lightning stroke, and the first negative lightning stroke drops faster than the first positive lightning stroke;

[0126] ④ Accurate monitoring: Through software compensation algorithm, the interference of temperature, humidity, etc. on leakage current is reduced or eliminated, and the arrester status monitoring is more accurate;

[0127] ⑤ Working condition prediction: Based on international or industry standard Qrs, number of impulses, leakage current and other multi-parameter criteria, the arrester working condition can be effectively predicted and its life can be judged.

[0128] Scenario Example 2

[0129] According to the overall architecture of the lightning strike counting device provided in the first scenario embodiment, the specific process of power supply lightning strike counting is introduced in the second scenario embodiment. FIG13 is a schematic diagram of the microprocessor background program operation process according to the embodiment of the present disclosure. As shown in FIG13 , the specific process is as follows:

[0130] 1. The software in the microprocessor is powered on and starts to complete the necessary initialization:

[0131] 1. Initialize the processor's internal and external device resources such as memory and ADC;

[0132] 2. Generating a software clock: The microprocessor program has a base software timer interrupt with a frequency of 1ms. The tick value in the interrupt program is continuously accumulated and counted from 0 to 999.

[0133] 3. Generate high-frequency clock: The microprocessor communicates with the PLL integrated with the VCO through the SPI interface. After writing the command word, it controls the output of the required high-frequency clock. For example, controlling the ADF4360-6 chip can output a high-frequency clock of up to 1.2G.

[0134] 4. Set threshold values: including voltage threshold Vr1 (corresponding to the current value that triggers lightning counting), voltage threshold Vr2 (corresponding to the current value that starts fast sampling), and interval time threshold (a value exceeding which is considered the next lightning strike event);

[0135] 5. Correct the RTC clock: Regularly synchronize and correct the microprocessor's built-in or external RTC calendar clock (including the ms tick value in the software clock) via the network. This step can be performed based on actual conditions.

[0136] 2. The software in the microprocessor operates normally, completing the measurement, processing, storage, and analysis of voltage, current and other signals:

[0137] 1. Periodically start the multiplexed ADC chip to alternately sample AC voltage, total leakage current, temperature, and humidity. When the ADC conversion is complete, the system generates an external interrupt / INT2-ADC;

[0138] 2. Interrupt response to receive data: After the INT2-ADC interrupt service routine runs, read the ADC conversion output value;

[0139] 3. Backend data processing: Based on the sampling channel of the current ADC chip, the received ADC sampled values ​​are assigned to specific values, such as AC voltage, total leakage current, temperature, or humidity. Then, based on different conditioning circuits, the sampled raw data values ​​are restored to analog voltage, current, temperature, or humidity values; for example, to 220V AC voltage or 25°C temperature.

[0140] 4. Background data recording: read the current calendar time, add a timestamp to the restored data and record it;

[0141] 5.Background storage record: save the recorded data with time stamp in a loop to FLASH / EEPROM and other memory;

[0142] 6. Background data analysis: Based on the currently measured temperature and humidity values, the software compensation algorithm corrects the total leakage current value to reduce the interference of temperature and humidity on the total leakage current. The total leakage current can also be used to further analyze the performance of the lightning arrester.

[0143] When a lightning strike occurs, the microprocessor's software also accumulates the number of strikes, measures the duration of strikes and the duration of rest periods, and performs high-speed sampling of the lightning voltage and current. Similarly, this data is received, processed, stored, and analyzed through interrupt response and background execution.

[0144] 1. Quickly respond and receive data through three external interrupt input signals.

[0145] (1) Impact start trigger interrupt / INT3-SC: The interrupt response program reads the output value of high-speed counter 2 and the current Japanese time (millisecond accuracy) as the timing of the impact start time or the impact interval length;

[0146] (2) Impact end trigger interrupt / INT4-EC: The interrupt response program completes the accumulation of impact times and reads the output value of high-speed counter 1 as the timing of the impact end time;

[0147] (3) High-speed sampling completion trigger interrupt / INT1-ADC: The interrupt response program first reads the input GPIO port to determine which ADC has completed the conversion, and then reads the conversion output value of that ADC. The conversion output values ​​of each ADC need to be read in chronological order to avoid misalignment.

[0148] 2. Tasks such as data processing, storage, and analysis are all performed in the program in the background.

[0149] (1) Data processing: The number of lightning strikes, impact duration, and sampled raw data values ​​read by the processor need to be processed for easy use;

[0150] ① Data conversion: Convert the count values ​​such as impact duration and impact interval into time length in ms / us / ns; restore the original sampled values ​​into analog values ​​such as voltage, current, temperature and humidity;

[0151] ② Event identification: A lightning discharge usually contains multiple repeated impulse discharges. The lightning event is identified by comparing the impulse interval duration and the threshold value;

[0152] ③ Event Recording: Based on the identification of events, all data is integrated and aggregated to generate event record data, including:

[0153] The starting time of this lightning strike event (year-month-day-hour-minute-second-millisecond);

[0154] The number of impacts in this lightning event;

[0155] Monitoring data of each impulse discharge process, including the duration of the impulse, and the quickly collected impulse voltage and impulse current values;

[0156] The monitoring data after each impulse discharge, including the impulse interval duration, and the normally collected AC voltage value and leakage current full current value;

[0157] (2) Data storage: Complete data preservation after power failure according to the event record format;

[0158] (3) Data analysis: The data is further analyzed and utilized.

[0159] Scenario Example 3

[0160] In the third scenario embodiment, examples are given with reference to actual data.

[0161] A company manufactures an indoor communications DC power supply system. Housed in a standard 2m cabinet, it incorporates AC power distribution, DC power distribution, a rectifier, batteries, and a monitoring unit. Each rectifier has a capacity of 50A or 75A, resulting in a maximum system output current of 1200A. The system supports 220 / 380V AC three-phase, four-wire input and is equipped with a lightning arrester (SPD) with a nominal discharge current of 10kA and an 8 / 20µs waveform, as well as a 32A / 3P SPD circuit breaker. During routine maintenance, the SPD's window color is typically checked first. If the window is green, the SPD is functioning properly. If it is red, it indicates damage caused by a voltage surge or lightning. Next, the SPD circuit breaker status is checked. If the circuit breaker is ON, it indicates normal operation; if it is OFF, the input is disconnected. If the SPD is intact, simply turn the circuit breaker ON. Otherwise, the circuit breaker is damaged. Damaged SPDs and circuit breakers should be replaced as soon as possible.

[0162] Obviously, to ensure the stability and safety of the power supply system, lightning arresters (APs) need to be promptly inspected and replaced as soon as possible. This is especially true before or during the thunderstorm season, when users or maintenance personnel will conduct inspections at each site. In the current 5G network era, there are numerous sites, many of which are unmanned and located in remote areas with inconvenient transportation. Furthermore, these inspections can only identify damaged APs, leaving those on the verge of failure unattended and unable to guarantee their survival during the thunderstorm season. This scattershot, inefficient, and even ineffective maintenance approach results in significant costs. To address this, the disclosed embodiments shift from passive to proactive approaches by adding a lightning strike counter to the downstream stage of the AP. This allows for accurate and intuitive understanding of lightning strike frequency, understanding the AP's operating status, calculating its degradation trend, and predicting its lifespan. These devices can then be promptly replaced if they are on the verge of failure or unable to survive the thunderstorm season. This approach significantly reduces maintenance costs while better avoiding lightning strikes, ensuring communication network security and business profitability.

[0163] Before adding a lightning strike counter, it's necessary to understand the various parameters of the lightning arrester on the power system. The arrester has a nominal discharge current In of 10kA, a maximum discharge current Imax of 20kA, and a maximum continuous operating voltage Uc of 275V. Therefore, the disclosed embodiments can design and implement a lightning strike counter based on these operating parameters and user needs:

[0164] 1. Embedded measurement and control system solutions using a mainstream ARM / RTOS Advanced RISC Machine (Advanced RISC Machine) or Real-Time Operating System (Real-Time Operating System): The industry-standard ARM Cortex-M7 microprocessor and RT-Thread RTOS are selected. The M7 processor integrates Flash and RAM, external memory interfaces, an ADC, an RTC, and multiple Universal Synchronous / Asynchronous Serial Receivers / Transmitters (USARTs), SPI, I2C, Ethernet, and other rich resources, significantly reducing hardware costs and accelerating project design.

[0165] 2. In the central processing unit module, the FLASH external memory is expanded through the SPI interface as a storage space for lightning event records. The SPI interface communicates with a PLL chip with an integrated VCO, such as the ADF4360-6 chip, to control the output of a 1.2G high-frequency clock. The decoding logic is implemented through the EPLD, combined with the 74HC245 bus transceiver and 74HC373 latch, to realize the reading and writing of various counters and ADCs.

[0166] 3. In the signal acquisition and comparison module, a Rogowski coil is used to collect the lightning arrester leakage current, and a voltage sensor is used to collect the AC voltage. The voltage threshold Vr1 of comparator 1 needs to be set according to the lower limit operating current of the lightning arrester, for example, corresponding to a current value of 50A. The voltage threshold Vr2 of comparator 2 must be lower than Vr1 and can be set to a value corresponding to 40A.

[0167] 4. The lightning strike counting and timing module uses the ADF4360-6 PLL chip with an integrated VCO to output a 1.2GHz high-frequency analog signal. This signal is then converted to a PECL-level clock CLK by the AD9515 clock distribution chip. CLK serves as the clock input for two high-speed counters. Both high-speed counters utilize an 8-bit high-speed counter, the MC100E P016, connected in series with a 24-bit conventional counter to form a 32-bit counter. This achieves a maximum count of 4GHz and a maximum timing of approximately 3 seconds.

[0168] 5. In the analog-to-digital conversion module, the 1.2GHz high-speed clock is first divided by 16 and fed into the beat generator, generating four sequential pulses that serve as the sequential start signals for the TIADC. Four AD7825s with a conversion rate of 2Mbps form the TIADC, enabling rapid sampling of lightning voltage V0 and current V1. Obviously, the maximum sampling rate is 8Mbps. In addition, the processor's integrated ADC performs routine sampling of AC voltage V0, total lightning arrester leakage current V2, temperature V4, and humidity V5.

[0169] 6. In the microprocessor program, at least 5 interrupt response procedures are designed:

[0170] (1) Base software timer interrupt: The interrupt frequency is 1ms, which enables the continuous accumulation of tick values ​​and cyclic counting;

[0171] (2) External ADC conversion completion interrupt: triggered by the falling edge, reads the sampling data of TIADC (lightning voltage V0 and lightning current V1);

[0172] (3) Internal ADC conversion completion interrupt: read the sampled data of the processor integrated ADC (AC voltage V0, total leakage current of the lightning arrester V2, temperature V4 and humidity V5);

[0173] (4) Counter start counting interrupt: triggered by rising edge, reads the output value of high-speed counter 2 (lightning start time or interval length) and current calendar time;

[0174] (5) Counter stop counting interrupt: Triggered by the rising edge, reads the output value of high-speed counter 1 (the duration of the lightning strike) and the current calendar time.

[0175] 7. Install the counter device behind the lightning arrester and power it on to start operation. This will enable the system to accumulate the number of strikes, measure the duration and rest intervals of strikes, and perform high-speed sampling of lightning voltage and current. This system also enables the reception, processing, storage, and analysis of these measured data. In actual implementation, the reception, processing, storage, and analysis of measured data will be tailored to your specific needs and will not be detailed here.

[0176] Scenario Example 4

[0177] In combination with the lightning strike counting and sampling method in the above embodiment, in this scenario embodiment, how to realize the life prediction of the lightning arrester based on the counter recorded data.

[0178] The parameters of the lightning arrester are analyzed as follows:

[0179] 1. Its nominal discharge current In is 10kA, which means the maximum value of the surge current that the lightning arrester can withstand when the standard 8 / 20 microsecond lightning surge occurs 10 times. A general power supply lightning arrester can withstand a maximum of 20 nominal discharge current surges;

[0180] 2. Its maximum discharge current Imax is 20kA, which means that the lightning arrester can withstand 20kA current impact twice without damage;

[0181] 3. Repetitive Charge Transfer Rating (Qrs). The arrester manufacturer failed to provide specific parameters. According to the technical specifications published by an association, the Qrs of low-voltage AC arresters is 0.4C. In other words, the arrester can withstand a maximum cumulative lightning energy of 0.4C.

[0182] 4. Total leakage current: The SPD manufacturer failed to provide specific parameters. According to the technical specifications published by an association, the total leakage current of a low-voltage AC SPD should not exceed 0.05mA.

[0183] Therefore, the embodiment of the present disclosure can comprehensively consider these four parameters to perform working condition evaluation and life prediction of the lightning arrester. For example:

[0184] 1. When the total leakage current obtained by conventional sampling reaches 0.10mA or exceeds 0.05mA, it indicates that the performance of the lightning arrester has begun to deteriorate and may need to be replaced;

[0185] 2. Due to the high-speed sampling, the peak value of the impact current can be recorded. If the peak current is close to the nominal discharge current 15 times, it means that the number of times it can withstand a similar lightning strike intensity may only be 5 times.

[0186] 3. By integrating the lightning current over time, the cumulative charge (in coulombs) flowing through the arrester can be calculated. If the cumulative charge reaches 0.4C, it means that the arrester has been subjected to excessive energy and needs to be replaced as soon as possible.

[0187] In summary, the embodiments of the present disclosure provide a method and device for counting lightning strikes on communication power supplies. In actual implementation, the technical solution provided by the embodiments of the present disclosure is not only limited to communication lightning protection scenarios, but is also applicable to different scenarios such as power grid scenarios for determining power grid fluctuation shocks, as well as measuring power grid fluctuation shocks. It can also be used for overvoltage damage assessment and precise analysis of equipment such as power supplies.

[0188] Currently, various communication power supply lightning strike counters on the market simply record the number and duration of lightning strikes, serving as a basic reference for lightning arrester performance testing and lifespan assessment. Because they fail to accurately record key operating parameters such as the number, duration, and discharge energy of repeated strikes during a lightning strike, they offer no clear and accurate understanding of local lightning strike frequency, the true operating status of lightning arrester devices, or the crucial basis for device testing. The actual functionality and effectiveness of these lightning strike counters is quite limited.

[0189] In order to overcome the drawbacks of various types of communication power supply lightning strike counters currently on the market, the technical solution of the disclosed embodiment achieves high-precision, high-speed, and low-cost measurement by cleverly applying innovative technologies such as high-speed counting and interleaved sampling, so that a lightning discharge process can be accurately and completely recorded and truly reproduced; at the same time, it is small in size, has no sealing requirements, and can also be integrated into equipment such as rectifiers. It allows users to clearly and intuitively understand the frequency of lightning strikes, grasp the working conditions of power supply lightning arresters, and make effective predictions and judgments (for example, through parameters such as impact moment, impact duration, leakage current, combined with lightning arrester characteristic parameters, scientifically calculate the degradation trend of the lightning arrester and predict the life of the lightning arrester); facilitate fault location and design improvements, and support the realization of real-time and accurate lightning strike warnings, fast and efficient predictive maintenance. It has significant advantages such as real-time measurement, accurate counting, superior performance, significant effects, low cost, and easy implementation.

[0190] The present disclosure provides a communication power supply lightning strike counting method, in which slow signals such as AC voltage, total leakage current, temperature and humidity are sampled using ordinary sampling, while the lightning voltage and lightning current within the duration of the lightning strike are sampled at high speed; hardware costs are reduced; ordinary counters are used to count the number of lightning strikes, thereby reducing hardware costs; high-speed counters are used to time the duration of a single impact and the duration of the impact interval to achieve accurate measurement; a high-speed counter is connected in series with an ordinary counter to expand the high-speed counting range and reduce hardware costs; the lightning voltage V0 and lightning current V1 within the duration of the lightning strike are sampled using TIADC technology, which has high speed, low power consumption and low cost. Low; each ADC in TIADC latches the output result after the conversion is completed, which reduces the performance requirements of the microprocessor; each ADC in TIADC outputs the same interrupt signal after the conversion is completed, which reduces the number of interrupt signals and interrupt response overhead, and reduces hardware costs; the interrupt response program of TIADC reads the conversion output values ​​of each ADC in sequence to avoid time misalignment; achieves accurate measurement; analyzes whether the lightning current waveform is similar to an arch pulse, determines whether it is a lightning impulse or a power grid fluctuation impulse, and achieves more accurate lightning strike counting; at the same time, the measurement of power grid fluctuation impulse can also be used for overvoltage damage assessment and accurate analysis of equipment such as power supplies.

[0191] The communication power supply lightning strike counting device provided by the embodiment of the present disclosure can be deployed after the first-level lightning arrester, second-level lightning arrester or third-level lightning arrester in the communication room and base station. The hardware needs to add a voltage sensor (to collect the grid voltage borne by the lightning arrester) and a current sensor (to collect the leakage current of the lightning arrester). In addition to recording and counting the number of times each lightning arrester is struck by lightning, multiple operating parameters such as the impact moment, impact duration, leakage current, etc. during the induced lightning discharge process can also be monitored and recorded. Through relevant mathematical calculations and processing, the lightning current waveform and lightning strike energy can be restored, which is convenient for users to clearly and intuitively understand the impact of lightning induction and effectively predict and judge the working condition of the lightning arrester. In addition, the device can also be integrated in equipment such as communication power rectifiers to facilitate fault location and design improvements, thereby improving the reliability of the equipment.

[0192] The communication power supply lightning counting method and device provided by the embodiment of the present disclosure, compared with the prior art, has the following beneficial effects of the technical solution of the embodiment of the present disclosure: 1. Complete records, convenient for comprehensive understanding of the lightning strike process: The lightning strike counter device and technology implemented by the embodiment of the present disclosure can monitor and record multiple operating parameters in a lightning discharge process: including the starting time of the lightning discharge, the number of repeated impulse discharges, the duration and interval of each impulse, the lightning voltage, the lightning current, etc. The recorded data is sufficient and complete, and it is easy to restore and reproduce the discharge process through these data, which is convenient for users to intuitively understand the lightning strike conditions; 2. The recording is detailed, which is convenient for in-depth analysis: The embodiment of the present disclosure records the operating parameters of the lightning discharge process with high real-time performance and high precision. For example, the recording accuracy of the lightning strike moment is at the ms level, and the accuracy of the impulse duration and interval duration is at the ns level; high-speed sampling of lightning current and voltage is achieved through TIADC technology, with a sampling frequency of more than tens of megahertz. High-precision data, after further calculation and processing, can obtain important information such as current peak value, residual voltage peak value, effective value, impact energy, etc. during the impact process, which facilitates users to more deeply analyze the lightning strike process and the working condition of the lightning arrester; 3. Accurate counting: Since multiple repeated impact discharges during a lightning discharge process are recorded, the number of lightning strikes and the number of impacts can be counted separately, avoiding the error of repeated counting of the number of lightning strikes. In addition, the current waveform of the lightning impact has a certain regularity, which is similar to an 8 / 20us arch pulse, while the grid fluctuation impact is random and irregular. Due to the high-speed sampling of more than tens of megabytes, the software determines whether it is a lightning impact by analyzing whether the lightning current waveform is similar to the arch pulse, avoiding the mistaken counting of the grid fluctuation impact as a lightning strike, thereby achieving more accurate lightning strike counting. 4. Working condition prediction: Through the software compensation algorithm, the interference of temperature and humidity on the leakage current is reduced, and the leakage current monitoring of the lightning arrester is more accurate. At the same time, combined with the comprehensive judgment criteria of other parameters such as international or industry standard Qrs and the number of impacts, the working conditions of the lightning arrester can be effectively predicted and the life span can be judged; 5. Cost leadership: The disclosed embodiment realizes high-speed timing through phase-locked frequency multiplication and the series connection of a high-speed counter and a low-speed counter; in addition, high-speed sampling is realized using TIADC technology. The technical combination of high-speed timing and high-speed sampling has the outstanding advantages of high precision, high speed, low power consumption, and huge cost advantages. Therefore, it can be widely used in communication rooms and power supply equipment, greatly strengthening the lightning protection measures of communication networks, reducing lightning disasters and accident losses, and ensuring the security of communication networks.

[0193] The above description is merely a preferred embodiment of the present disclosure and is not intended to limit the present disclosure. Those skilled in the art will appreciate that various modifications and variations of the present disclosure are possible. Any modifications, equivalent substitutions, or improvements made within the principles of the present disclosure should be included within the scope of protection of the present disclosure.

Claims

1. A method for counting lightning strikes of a communication power supply, comprising: generating a plurality of sequential pulses for a plurality of analog-to-digital converters ADC in a time-interleaved analog-to-digital converter TIADC; According to the plurality of sequential pulses, sequentially starting the plurality of ADCs to sample the lightning voltage and the lightning current; The plurality of ADCs sequentially output sampling signals to complete the counting of lightning strikes on the communication power supply.

2. The method according to claim 1, wherein: Also includes: In the event of a lightning strike, an ordinary counter is used to count the number of lightning strikes, and a high-speed counter is used to time the duration of a single lightning strike and the duration of the interval between lightning strikes.

3. The method according to claim 2, wherein: Before using a common counter to count the number of lightning strikes and using a high-speed counter to time the duration of a single lightning strike and the duration of an interval between lightning strikes, the method further includes: Condition the leakage current of the arrester to obtain a comparison voltage; When the comparison voltage is greater than a first voltage threshold, determining that a lightning strike occurs; When the comparison voltage is greater than a second voltage threshold, it is determined to start sampling the lightning strike voltage and the lightning strike current, wherein the second voltage threshold is less than the first voltage threshold.

4. The method according to claim 3, wherein: The method of using a common counter to count the number of lightning strikes and using a high-speed counter to time the duration of a single lightning strike and the duration of the interval between lightning strikes includes: Obtaining a first level signal according to a comparison result between the comparison voltage and the first voltage threshold; According to the rising edge of the first level signal, trigger the common counter to add 1 to the count of the number of lightning strikes; When the first level signal is at a high level, a first high-speed counter is used to time the duration of a single lightning strike; when the first level signal is at a low level, a second high-speed counter is used to time the duration of an interval between lightning strikes.

5. The method according to claim 4, wherein: The method of using a common counter to count the number of lightning strikes and using a high-speed counter to time the duration of a single lightning strike and the duration of the interval between lightning strikes also includes: A first interrupt response signal is triggered according to the rising edge of the first level signal, and the first high-speed counter obtains the timing start time of the single lightning impact duration according to the first interrupt response signal; The second interrupt response signal is triggered according to the falling edge of the first level signal, and the first high-speed counter obtains the timing end time of the single lightning impact duration according to the second interrupt response signal.

6. The method according to claim 2, wherein: The method of using a high-speed counter to time the duration of a single lightning strike and the duration of an interval between lightning strikes includes: The high-speed counter is connected in series with the common counter to time the duration of a single lightning strike and the duration of the interval between lightning strikes.

7. The method according to claim 1, wherein: The method generates a plurality of sequential pulses for a plurality of analog-to-digital converters ADC in a time-interleaved analog-to-digital converter TIADC, comprising: The high-frequency clock is frequency-divided, and a plurality of sequential pulses are generated according to the high-frequency clock after the frequency-division processing.

8. The method according to claim 1, wherein: The method of sequentially starting a plurality of ADCs to sample the lightning voltage and the lightning current according to the plurality of sequential pulses comprises: The lightning strike voltage or the lightning strike current is simultaneously connected to a plurality of the ADCs, and the plurality of ADCs are sequentially started to perform analog-to-digital conversion according to the sequential pulses to complete sampling of the lightning strike voltage or the lightning strike current.

9. The method according to claim 8, wherein: The sequentially starting the plurality of ADCs to sample the lightning voltage and the lightning current comprises: The m ADCs alternately sample the same lightning voltage or lightning current according to the plurality of sequential pulses, wherein the clock phase deviation of adjacent ADCs is 2π / m.

10. The method according to claim 1, wherein: The plurality of ADCs sequentially output the sampled signals, including: The plurality of ADCs trigger a third interrupt response signal after performing analog-to-digital conversion on the sampling signal; sequentially reading the output of the ADC according to the first of the third interrupt response signals until the output of the ADC is invalid; According to the mth third interrupt response signal, the outputs of the ADCs are read sequentially starting from the output of the ADC whose reading is completed according to the m-1th third interrupt response signal until the sequential reading of the outputs of the plurality of ADCs is completed.

11. The method according to claim 1, wherein: After sequentially starting the plurality of ADCs to sample the lightning voltage and the lightning current, the method further includes: The sampling results are latched.

12. A communication power supply lightning strike counting device, comprising: Microprocessor, beat generator, voltage sensor, current sensor, time interleaved analog-to-digital converter TIADC, among which, The microprocessor is configured to generate a high-frequency clock; The beat generator is configured to generate a plurality of sequential pulses for a plurality of analog-to-digital converters ADC in the TIADC according to the high-frequency clock; The voltage sensor is configured to collect lightning strike voltage and perform conditioning on the lightning strike voltage; The current sensor is configured to collect lightning current and perform conditioning on the lightning current; The TIADC is configured to sequentially start the multiple ADCs to sample the lightning voltage and the lightning current according to the multiple sequential pulses.

13. The device according to claim 12, wherein: Also includes: Ordinary counter and high-speed counter, among which, The ordinary counter is configured to count the number of lightning strikes; The high-speed counter is configured to time the duration of a single lightning strike and the duration of an interval between lightning strikes.

14. The device according to claim 12, wherein: It also includes: a first voltage comparator and a second voltage comparator, wherein: The first voltage comparator is configured to compare the comparison voltage with a first voltage threshold, determine whether a lightning strike occurs, and output a first level signal; The second voltage comparator is configured to compare the comparison voltage with the second voltage threshold, determine whether to start sampling the lightning strike voltage and the lightning strike current, and output a second level signal.

15. The device according to claim 12, wherein: The microprocessor is further configured to trigger a first interrupt response signal according to a rising edge of the first level signal, wherein the first interrupt response signal is configured to instruct a first high-speed counter in the high-speed counter to obtain a timing start time of a single lightning strike duration; The microprocessor is further configured to trigger a second interrupt response signal according to a falling edge of the first level signal, and the second interrupt response signal is configured to indicate the timing end time of the first high-speed counter to obtain the duration of a single lightning strike.

16. The device according to claim 12, wherein: The microprocessor is further configured to trigger a third interrupt response signal after the plurality of ADCs sample the lightning voltage and the lightning current, wherein the third interrupt response signal is configured to indicate reading of the outputs of the plurality of ADCs.

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