Phase change material, phase change storage chip, storage device, and electronic device

Abstract

Disclosed are a phase change material, a phase change storage chip, a storage device, and an electronic device, belonging to the technical field of semiconductor storage. The phase change material comprises a Ge-Sb-Te phase change substrate, and a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate. The first doping element comprises Hf, and the atomic percentage thereof is 1.5%-6.5%. The second doping element comprises at least one of N, C, In and Ga, and the atomic percentage thereof is 1.0%-5%. The phase change material has high adhesion, and enables a phase change device to have properties such as a large read window and a long life.

Description

Phase change material, phase change memory chip, storage device and electronic device

[0001] This application claims priority to Chinese patent application No. 202311290353.5 filed on September 28, 2023, with the invention name “A phase change memory”, and to Chinese patent application No. 202410316618.2 filed on March 19, 2024, with the invention name “Phase change material, phase change memory chip, storage device and electronic device”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present disclosure relates to the field of semiconductor storage technology, and in particular to phase change materials, phase change storage chips, storage devices, and electronic devices. Background Art

[0003] Phase change memory (PCM) has advantages such as low latency and high fatigue life. It uses phase change material as the storage medium. Phase change material exhibits low resistivity in the crystalline state and high resistivity in the amorphous state. Phase change memory uses the resistance difference between the crystalline and amorphous states of the phase change material to realize data storage and erasure.

[0004] In the related art, the phase change memory includes multiple phase change memory units, each of which includes a phase change material layer and a barrier layer located on both sides of the phase change material layer. The sandwich structure composed of the phase change material layer and the barrier layer is subjected to large stress during processes such as annealing and etching, which may cause interface peeling between the phase change material layer and other functional layers such as the barrier layer. This will not only cause the phase change memory unit to be unable to be used normally, but also the material particles dropped due to peeling will have an adverse effect on the equipment, etc.

[0005] It can be seen that it is necessary to improve the interface adhesion between the phase change material layer and other functional layers in the phase change memory.

[0006] Public content

[0007] On the one hand, a phase change material is provided, which includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; the first doping element includes an Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-6.5%; the second doping element includes at least one of an N element, a C element, an In element, and a Ga element, and the atomic percentage of the second doping element in the phase change material is 1.0%-5%.

[0008] The phase change material provided by the embodiments of the present disclosure can enhance the adhesion of the phase change material layer by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change base material doped with Hf element, achieve tight bonding between the phase change material layer and other adjacent functional layers, reduce the probability of interface peeling, increase the product yield of the phase change memory chip, and avoid pollution and interference to the production line and production equipment. In particular, by making the doping amount of Hf element be 1.5%-6.5%, and the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-5.0%, while achieving the improvement of the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window and high lifetime.

[0009] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0010] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change base material is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0011] By making the chemical general formula of the Ge-Sb-Te phase change base material as described above, the purpose is to ensure that the adhesion of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change base material. <s

[0012] On the other hand, a phase change material is provided, which includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; the first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-7%; the second doping element includes at least one of N element, C element, In element, and Ga element, and the atomic percentage of the second doping element in the phase change material is 1.0%-7%; the sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

[0013] For the phase change materials provided in the embodiments of the present disclosure, by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change substrate doped with Hf element, the adhesion force of the phase change material layer can be enhanced, the tight combination between the phase change material layer and other adjacent functional layers can be achieved, the probability of interface peeling can be reduced, the product yield of the phase change memory chip can be increased, and pollution and interference to the production line and production equipment can be avoided. In particular, by making the doping amount of Hf element be 1.5%-7%, and making the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-7%, and the sum of the atomic percentages of the two doping elements is greater than 4% and less than 10%, while improving the adhesion force of the phase change material layer, it is also beneficial to make the phase change device have a large read window, high life and cycle stability.

[0014] In some possible implementation manners, the phase change material further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved.

[0015] In some possible implementation manners, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; or, (GeTe 1-c ) x (Sby Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, and y, c, and d are parameters related to the ratio of the number of atoms, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0016] By making the chemical general formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0017] Furthermore, the chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , and 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , and 0.2 < x ≤ 0.4.

[0018] The embodiments of the present disclosure further limit the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, which is beneficial to making the phase change device have both low latency and high lifespan, and ensuring that the phase change material layer has high adhesion.

[0019] On the other hand, a phase change memory chip is provided. The phase change memory chip includes: a plurality of phase change memory cells, and the phase change memory cells include a phase change material layer, and the phase change material layer is prepared from the phase change material described in any one of the above.

[0020] For the phase change memory chip provided by the embodiments of the present disclosure, since its phase change material layer is prepared from the phase change material provided by the embodiments of the present disclosure, the phase change memory chip has all the advantages of the phase change material provided by the embodiments of the present disclosure.

[0021] In some possible implementation manners, the phase change memory cell further includes an adhesion layer, and the adhesion layer is stacked on at least one surface of the phase change material layer, and the adhesion layer is used to increase the adhesion force between the phase change material layer and the adjacent functional layer.

[0022] For the phase change memory chip provided by the embodiments of the present disclosure, not only the phase change material itself is improved, but also the structure of the phase change memory chip is improved by adding an adhesion layer to further enhance the adhesion force between the phase change material layer and the adjacent functional layer, significantly reducing the probability of interface peeling, thereby increasing the product yield of the phase change memory cell, and also avoiding pollution and interference to the production line.

[0023] In some possible implementations, the adhesion layer raw material used for the adhesion layer includes at least one of a nitride of the target element and a carbide of the target element;

[0024] The target element is selected from at least one of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo.

[0025] In some possible implementations, the adhesion layer material used for the adhesion layer includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesion layer material is different from the phase change material;

[0026] The fourth doping element is selected from at least one of Hf, N, C, In, and Ga. The atomic percentage of the fourth doping element in the raw material of the adhesion layer is 0.01%-20%.

[0027] In some possible implementations, the phase-change memory unit further includes a barrier layer, and the adhesion layer is located between the phase-change material layer and the barrier layer to increase adhesion between the phase-change material layer and the barrier layer.

[0028] In some possible implementations, the barrier layer material used for the barrier layer includes at least one of the elements W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, nitrides, and carbides.

[0029] In some possible implementations, the phase-change memory unit further includes an electrode layer, and the adhesion layer is located between the phase-change material layer and the electrode layer to increase adhesion between the phase-change material layer and the electrode layer.

[0030] In some possible implementations, the phase-change memory chip further includes: a plurality of gate tube units, wherein the gate tube units are arranged in series with the phase-change memory units.

[0031] In some possible implementations, the gate tube unit includes a gate layer, and the gate tube material used in the gate layer includes at least one of an S-series gate tube material, a Se-series gate tube material, and a Te-series gate tube material.

[0032] In some possible implementations, the gate tube material also includes a fifth doping element, and the fifth doping element is selected from at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, O element, Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

[0033] On the other hand, an embodiment of the present disclosure provides a storage device, which includes a controller and at least one phase-change memory chip as described above, wherein the controller is configured to store data in the phase-change memory chip.

[0034] The storage device (also referred to as a memory) may be configured to store various types of data, which may be contact data, phone book data, messages, pictures, videos, etc., or may be instructional data.

[0035] On the other hand, an embodiment of the present disclosure provides an electronic device, which includes a processor and the above-mentioned storage device, and the processor is used to store data generated by the electronic device in the storage device.

[0036] The electronic devices include but are not limited to computers, mobile phones, music playing devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, etc. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] FIG1 is a schematic diagram of the interface peeling process between the phase change material layer and the barrier layer in the related art;

[0038] FIG2 is a mean square displacement diagram of Hf element in Ge-Sb-Te phase change substrate;

[0039] FIG3 is a mean square displacement diagram of the In element in the Ge-Sb-Te phase change substrate;

[0040] FIG4 is a diagram showing the mean square displacement of Ga in a Ge-Sb-Te phase change substrate;

[0041] FIG5 is a schematic structural diagram of an exemplary phase change memory unit provided by an embodiment of the present disclosure;

[0042] FIG6 is a schematic structural diagram of another exemplary phase change memory unit provided by an embodiment of the present disclosure;

[0043] FIG7 is a schematic structural diagram of another exemplary phase change memory unit provided by an embodiment of the present disclosure;

[0044] FIG8 is a schematic structural diagram of another exemplary phase change memory unit provided by an embodiment of the present disclosure;

[0045] FIG9 is a schematic structural diagram of an exemplary phase-change memory chip provided by an embodiment of the present disclosure;

[0046] FIG10 is a schematic structural diagram of another exemplary phase-change memory chip provided by an embodiment of the present disclosure;

[0047] FIG11 is a schematic structural diagram of another exemplary phase-change memory chip provided by an embodiment of the present disclosure;

[0048] FIG12 is a schematic structural diagram of another exemplary phase-change memory chip provided by an embodiment of the present disclosure;

[0049] FIG13 is an array diagram of an exemplary phase change memory chip provided by an embodiment of the present disclosure;

[0050] FIG14 is a schematic diagram of the first preparation step of the phase change memory chip provided in Example 1;

[0051] FIG15 is a schematic diagram of a second preparation step of the phase change memory chip provided in Example 1;

[0052] FIG16 is a schematic diagram of the third preparation step of the phase change memory chip provided in Example 1;

[0053] FIG17 is a schematic diagram of the fourth preparation step of the phase change memory chip provided in Example 1;

[0054] FIG18 is a schematic diagram of the fifth preparation step of the phase-change memory chip provided in Example 1;

[0055] FIG19 is a schematic diagram of the sixth preparation step of the phase change memory chip provided in Example 1;

[0056] FIG20 is a schematic diagram of the seventh preparation step of the phase change memory chip provided in Example 1;

[0057] FIG21 is a schematic diagram of the eighth preparation step of the phase-change memory chip provided in Example 1;

[0058] FIG22 is a schematic diagram of the ninth step of preparing the phase-change memory chip provided in Example 1;

[0059] FIG23 is a schematic diagram of the tenth preparation step of the phase-change memory chip provided in Example 1;

[0060] FIG24 is a schematic diagram showing the relationship between the lifespan and SET state resistance of the phase change memory chip provided by an embodiment of the present disclosure.

[0061] The reference numerals in the figures represent respectively: 001, storage subunit; 002, word line; 003, bit line; 004, substrate; 005, mask layer; 100, phase change material layer; 200, adhesion layer; 300, barrier layer; 400, insulating layer; 401, first insulating layer; 402, second insulating layer; 403, third insulating layer; 404, fourth insulating layer; 501, top electrode; 502, bottom electrode; 503, middle electrode; 600, selection layer; 701, first trench; 702, second trench; 703, third trench. DETAILED DESCRIPTION

[0062] In the description of the embodiments of the present disclosure, the terms "vertical direction," "horizontal direction," "top," "bottom," "upper," and "lower" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings. These terms are intended solely to facilitate the description of the embodiments of the present disclosure and to simplify the description. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on the embodiments of the present disclosure. When a product is positioned in different postures, the orientation may change; for example, "top" and "bottom" may be interchangeable.

[0063] Phase change memory (PCM), also known as phase change memory chip, is a solid-state semiconductor non-volatile memory that uses phase change material as the storage medium. Phase change material can reversibly change between crystalline and amorphous states. By utilizing the difference in high resistivity and low resistivity corresponding to the amorphous and crystalline states of the phase change material, the phase change memory can store data "0" and "1".

[0064] The operating process of phase-change memory includes an erase operation (SET) and a write operation (RESET). The SET process involves applying a broad, weak electric pulse to heat the phase-change material, raising its temperature to between its crystallization and melting temperatures. The material then crystallizes into an ordered state, forming a crystalline state with low resistivity, enabling the storage of data "0." The RESET process involves applying a narrow, strong electric pulse to heat the phase-change material, raising its temperature above its melting temperature, causing it to melt into a disordered state. Subsequently, through a rapid cooling quenching process, the material transitions directly from the molten state to an amorphous state with higher resistivity, enabling the storage of data "1."

[0065] In the related art, the phase change memory includes a plurality of phase change memory cells. As shown in FIG1 , the phase change memory cell includes a phase change material layer 100 and a barrier layer 300 located on both sides of the phase change material layer 100. The sandwich structure formed by the phase change material layer 100 and the barrier layer 300 undergoes many processes such as annealing, patterning, etching, and protective layer covering during the preparation of the phase change memory, which causes it to be subjected to large stress, thereby possibly causing peeling between the interface between the phase change material layer 100 and other functional layers such as the barrier layer 300 (see FIG1 ). This will not only cause the phase change memory cell in the peeling area to be unable to be used normally (for example, the interface between the phase change material layer and the barrier layer peels off, making it impossible to combine). In addition, the particulate material that falls due to peeling will also have an adverse effect on production equipment, etc. (for example, polluting the production line, interfering with the normal operation of the equipment, etc.). It can be seen that it is necessary to improve the interface adhesion between the phase change material layer and other functional layers.

[0066] A first embodiment of the present disclosure provides a phase-change material comprising a Ge-Sb-Te phase-change substrate and a first doping element and a second doping element doped into the Ge-Sb-Te phase-change substrate. The first doping element comprises Hf, and the first doping element accounts for 1.5% to 6.5% of the phase-change material by atomic percentage. The second doping element comprises at least one of N, C, In, and Ga, and the second doping element accounts for 1.0% to 5.0% of the phase-change material by atomic percentage.

[0067] For example, some examples of the atomic percentage of the first doping element Hf in the phase change material include but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%. , 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, etc.

[0068] Illustratively, some examples of the atomic percentage of the second doping element in the phase change material include, but are not limited to, 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, etc.

[0069] The second doping element can be one of the N element, C element, In element, and Ga element. For example, the second doping element is the N element, C element, In element, or Ga element, or the second doping element can also be a combination of any two elements among the N element, C element, In element, and Ga element, a combination of any three elements, or include all four elements at the same time.

[0070] The phase change material provided in the embodiments of the present disclosure can enhance the adhesion between the phase change material layer and other functional layers by doping the Ge-Sb-Te phase change substrate with Hf and at least one of N, C, In, and Ga. The principles for enhancing adhesion are described below.

[0071] (1) When the second doping element is N or C, N or C can form a bond with Hf, thereby introducing HfN compound or HfC compound into the phase change material. The introduced HfN compound or HfC compound does not match the lattice constant of the Ge-Sb-Te phase change substrate (for example, the lattice constant of the HfN compound is 0.452 nm, and the lattice constant of the HfC compound is 0.463 nm). They do not match the lattice constant of the Ge-Sb-Te phase change substrate (for example, the lattice constant of Ge1Sb4Te6 is 0.612 nm). Therefore, additional grain boundaries are introduced, the grain size of the phase change material is reduced, the roughness of the phase change material is reduced, and the contact area and bonding force between the phase change material layer and other functional layers are increased, thereby achieving the effect of increasing the adhesion of the phase change material layer.

[0072] Further research found that when the atomic percentage of N element or C element is 1.0%-5.0%, it can further ensure that the phase change device has a large read window. The relevant principle is as follows: for the operation of the 1S1R type phase change memory chip, the threshold voltage of turning on the gate tube unit + crystalline phase change memory unit is VtS, and the threshold voltage of turning on the gate tube unit + amorphous phase change memory unit is VtR. The read window is VtR-VtS. It can be seen that the size of the read window is proportional to the difference between the high resistance and low resistance of the phase change material layer.

[0073] On the one hand, HfN compounds and HfC compounds can increase the high resistance of phase change materials, which is beneficial for increasing the read window of phase change devices. On the other hand, if Hf is doped alone into the Ge-Sb-Te phase change substrate, since Hf will come into contact with O or other substances with oxidizing properties during the process preparation, it will be easily oxidized to form HfOx. The resistivity of HfOx is greater than that of the phase change material, which will cause the low resistance of the phase change material to increase to a certain extent, thereby reducing the read window of the phase change device. However, the melting points of HfN compounds and HfC compounds are 3310℃ and 3900℃ respectively. They have high chemical stability and are not easy to react with other elements such as O, which reduces the oxidation probability of the Hf element and ensures that the phase change device has a large read window.

[0074] However, the influence of N or C elements on the read window of the phase change device is related to the doping amount in the phase change material. The embodiments of the present disclosure have confirmed through relevant experiments that when the atomic percentage of the Hf element is greater than 6.5% (not within the specified range of 1.5% to 6.5%) and the atomic percentage of the N or C element is greater than 5.0% (not within the specified range of 1% to 5%), the read window of the phase change device will deteriorate.

[0075] For example, the above-mentioned “related experiments” are as follows:

[0076] The disclosed embodiments provide a phase-change material in which a Ge-Sb-Te phase-change matrix is ​​doped with Hf and N, wherein the atomic percentage ratio of the elements in the chemical formula of the Ge-Sb-Te phase-change matrix satisfies the following formula: Ge:Sb:Te = 1:4:6 (referred to as Ge1Sb4Te6, GeSbTe146, or GST146). While maintaining constant values ​​for other parameters, the doping levels of Hf and N were varied to test the low resistance of the phase-change material layer in its crystalline state and the high resistance in its amorphous state. The relevant test parameters and test results are shown in Table 1.

[0077] Table 1

[0078] Combining phase change material 1 and phase change material 3 in Table 1, it can be seen that by further doping N element into the Ge-Sb-Te phase change substrate doped with Hf element, the high resistance of the phase change material layer can be increased, thereby facilitating an increase in the read window size.

[0079] Combining Phase Change Material 2 in Table 1, it can be seen that when the Hf doping concentration is 6.5% and the N doping concentration is 5%, its crystallization temperature is increased by 35°C compared to Phase Change Material 1 (undoped N) in Table 1, its low resistance is increased by more than 100 times compared to Phase Change Material 4 (Hf2% + N2%) in Table 1, and its low resistance is increased by more than 5 times compared to Phase Change Material 3 (Hf4% + N4%) in Table 1. This shows a certain degree of read window degradation. It can be seen that when the atomic percentage of the Hf element is greater than 6.5% and the atomic percentage of the N element or the C element is greater than 5.0%, the crystallization temperature will be further increased. Therefore, under certain back-end device process heat treatment conditions, the low resistance of the phase change material layer will increase, which will cause the read window of the phase change device to decrease. It can be seen that the embodiment of the present disclosure has an important significance for ensuring that the phase change device has a large read window by making the atomic percentage of the Hf element 1.5% to 6.5% and the atomic percentage of the N element or the C element greater than 1% to 5%.

[0080] In addition, as mentioned above, the melting points of HfN compounds and HfC compounds are 3310°C and 3900°C, respectively, and they have high chemical stability. It can be seen that the high melting points of HfN compounds and HfC compounds enable them to remain stably during the melting process of the phase change material RESET (about 600°C). Moreover, the stable clusters of HfN compounds and HfC compounds hinder the segregation and phase separation of elements in the GeSbTe phase change substrate, which is conducive to making the phase change device have a long life characteristics.

[0081] (2) When the second doping element is In or Ga, In and Ga easily form metal-metal bonds with metal elements such as Hf, thereby enhancing the bonding force between the phase change material layer and other functional layers. This is because In and Ga have low melting points (<200°C) compared to other solid metal elements at room temperature, which gives them strong diffusion capabilities. As a result, In and Ga are conducive to forming metal-metal bonds with metal elements in other functional layers, and then forming alloys, thereby improving the adhesion between the phase change material and other functional layers containing metal elements. For example, the "other functional layers" involved here can be the barrier layer or adhesion layer involved in the phase change memory chip described below.

[0082] In the embodiments of the present disclosure, the mean square displacements of Hf, In, and Ga in the Ge-Sb-Te phase change matrix are calculated based on first principles. As shown in Figures 2 to 4, the mean square displacements of In and Ga in the Ge-Sb-Te phase change matrix system are relatively large, indicating that under ambient temperature conditions, In and Ga are more likely to diffuse, making it easier for them to form alloys with metal elements in other functional layers.

[0083] For example, when other functional layers contain metal elements such as W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, In and Ga elements can easily combine with these metal elements to form alloys, forming metal-metal bonds, thereby improving the adhesion between the phase change material and other functional layers, thereby increasing the adhesion of the phase change material layer.

[0084] The embodiments of the present disclosure also conducted relevant tests on the adhesion between the phase change material layer and the W electrode corresponding to some phase change materials doped with In element and those not doped with In element. See Table 2. These phase change materials are: (a) phase change material Hf-GeSbTe, which refers to a single Hf element doped in a Ge1Sb4Te6 phase change matrix, with the atomic percentage of Hf being 5%; (b) phase change material In-GeSbTe, which refers to a single In element doped in a Ge1Sb4Te6 phase change matrix, with the atomic percentage of In being 3%; (c) phase change material InHf-GeSbTe, which refers to a Ge1Sb4Te6 phase change matrix doped with both Hf and In elements, with the atomic percentages of Hf and In being 3% and 2%, respectively.

[0085] Table 2

[0086] As can be seen from Table 2, on the basis that the atomic percentage of the In element satisfies the specified range of 1% to 5%, compared with the Hf-GeSbTe phase change material layer doped with only Hf and the In-GeSbTe phase change material layer doped with only In, the InHf-GeSbTe phase change material layer doped with both Hf and In elements has a higher adhesion to the W electrode, thereby achieving an improvement in the interfacial adhesion and thus achieving the effect of increasing the adhesion of the phase change material layer.

[0087] Further research has revealed that when In or Ga is co-doped with Hf into the GeSbTe phase-change substrate, the phase-change device can also achieve a long lifespan. To support this conclusion, the disclosed embodiments also tested the bond strengths of Hf, In, and Ga with Ge, Sb, and Te, as well as their own bond strengths. The unit of bond strength is kJ / mol. The test results are shown in Table 3.

[0088] Table 3

[0089] As shown in Table 3, Hf, In, and Ga can form covalent bonds with themselves, as well as with Ge, Sb, and Te, with similar strengths. Therefore, if In or Ga is doped into the Ge-Sb-Te phase change substrate alone, the In or Ga element easily forms a solid solution with the Ge-Sb-Te phase change substrate, and after electrical operation, it is impossible to prevent the element segregation of Ge, Sb, and Te, resulting in a shorter lifespan of the phase change device. The phase change material provided in the embodiment of the present disclosure, while introducing In and / or Ga elements into the Ge-Sb-Te phase change substrate, also introduces Hf. The HfIn alloy or HfGa alloy formed has a high melting point. The HfIn alloy or HfGa alloy can be stably retained during the melting process (about 600°C) of the phase change material RESET, and the above-mentioned stable HfIn and HfGa alloy clusters also hinder the element segregation and phase separation of the Ge-Sb-Te phase change substrate, which is conducive to making the phase change device have a long lifespan. Of course, as mentioned above, when other functional layers adjacent to the phase-change material layer contain Hf elements, HfIn alloy or HfGa alloy is also very beneficial for enhancing the adhesion of the phase-change material layer.

[0090] In summary, the phase-change material provided in the embodiments of the present disclosure, by further doping the Hf-doped Ge-Sb-Te phase-change substrate with at least one of the elements N, C, In, and Ga, can enhance the adhesion of the phase-change material layer, achieve close bonding between the phase-change material layer and other adjacent functional layers, reduce the probability of interface delamination, increase the product yield of the phase-change memory chip, and avoid contamination and interference with production lines and equipment. In particular, by setting the doping level of the Hf element to 1.5%-6.5% and the doping level of at least one of the elements N, C, In, and Ga to 1.0%-5.0%, the adhesion of the phase-change material layer is enhanced while also enabling the phase-change device to have a large read window and a long life.

[0091] In some implementations, the phase change material provided by the embodiments of the present disclosure further includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved. Among them, the atomic percentage of the third doping element in the phase change material is 0.01%-10%.

[0092] For the Ge-Sb-Te phase change substrate, the chemical general formula of its Ge-Sb-Te compound can be shown as any of the following chemical general formulas:

[0093] Chemical general formula one, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously. For example, for the compound GeTe 1-a , it means that the atomic number ratio of Ge element to Te element is 1:1 - a, and for Sb2Te 3-b , it means that the atomic number ratio of Sb element to Te element is 2:3 - b. Of course, it is not excluded that in the compound GeTe 1-a , the atomic numbers of Ge element and Te element are 1 and 1 - a respectively, and in the compound Sb2Te 3-b , the atomic numbers of Sb element and Te element are 2 and 3 - b respectively.

[0094] Chemical general formula two, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously. For example, for the compound GeTe 1-c , it means that the atomic number ratio of Ge element to Te element is 1:1 - c, and for Sb y Te 1-d, which means that the ratio of the number of atoms of Sb element to Te element is y:1-d. Of course, it is not excluded that the compound GeTe 1-c In the equation, the number of atoms of Ge and Te are 1 and 1-c respectively, and the compound Sb y Te 1-d In the figure, the atomic numbers of Sb and Te are y and 1-d, respectively.

[0095] Illustratively, the value of a includes, but is not limited to, 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0096] The value of b includes but is not limited to: 0.1, 0.2, 0.3, 0.4, 0.5, 0.6, 0.7, 0.8, 0.9, 1, 1.1, 1.2, 1.3, 1.4, 1.5, 1.6, 1.7, 1.8, 1.9, 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, etc.

[0097] The value of y includes but is not limited to: 2, 2.1, 2.2, 2.3, 2.4, 2.5, 2.6, 2.7, 2.8, 2.9, 3, 3.1, 3.2, 3.3, 3.4, 3.5, 3.6, 3.7, 3.8, 3.9, 4, 4.1, 4.2, 4.3, 4.4, 4.5, 4.6, 4.7, 4.8, 4.9, 5, 6, 7, 8, 9, 10, etc.

[0098] The value of c includes but is not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0099] The value of d includes but is not limited to: 0.1, 0.15, 0.2, 0.25, 0.3, 0.35, 0.4, 0.45, 0.5, 0.55, 0.6, 0.65, 0.7, 0.75, 0.8, 0.85, 0.9, 0.95, 1, etc.

[0100] The embodiment of the present disclosure makes the chemical formula of the Ge-Sb-Te phase change substrate as described above, which is intended to ensure that the adhesion of the phase change material layer obtained based on the Ge-Sb-Te phase change substrate of the embodiment of the present disclosure is stronger than that of the phase change material layer obtained from other Ge-Sb-Te phase change substrates. This is because GeTe, Sb2Te3, Sb yTe (y≥2) are all stable compounds with a stable chemical composition ratio. Considering that Te单质 is a typical two-dimensional material, after Te-Te bonding, a layered structure is formed, and the interlayer is bonded by van der Waals forces, with poor adhesion. At the same time, the melting point of Sb2Te3 (620 °C) is higher than that of Te单质 (450 °C). At high temperatures during the phase change process, Te is more likely to precipitate to form Te单质 two-dimensional material, resulting in poor adhesion. In the embodiments of the present disclosure, a, b, c, and d are all greater than 0, which can make the Ge-Sb-Te phase change substrate in a state of lacking Te compared with the above-mentioned stable compounds. By appropriately reducing the content of Te element, it is ensured that the adhesion of the phase change material layer is stronger than that of the phase change material layer corresponding to the Ge-Sb-Te phase change substrate.

[0101] To support the above conclusion, the embodiments of the present disclosure conducted relevant adhesion tests. The test results show that the adhesion between the Te-deficient Ge-Sb-Te phase change substrate and the W electrode is 1.14 a.u., and the adhesion between the non-Te-deficient Ge-Sb-Te phase change substrate and the W electrode is 1 a.u. It can be seen that the Te-deficient Ge-Sb-Te phase change substrate has stronger adhesion than the non-Te-deficient Ge-Sb-Te phase change substrate.

[0102] In some examples, for the first chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where 0.2 < x ≤ 0.4. For the second chemical general formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0103] Exemplarily, the values of x include but are not limited to: 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0104] By making the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, on the basis of ensuring that the adhesion of the phase change material layer is strong enough, it is also beneficial to accelerate the phase change device delay and improve the phase change device life.

[0105] The phase change material provided in the embodiments of the present disclosure exists in the form of, but is not limited to, alloy, compound, combination of a single substance and a compound, combination of a single substance and an alloy, etc. The phase change material layer is prepared based on the above various forms of phase change materials.

[0106] For example, one form of phase change material is a combination of a Ge-Sb-Te ternary compound / alloy, a single substance or compound corresponding to the Hf element, and a single substance or compound corresponding to at least one of the N element, the C element, the In element, and the Ga element. In this case, according to the atomic percentage of each element in the phase change material, corresponding amounts of the above-mentioned single substances or compounds are provided in accordance with the ratio. The three types of materials, Ge-Sb-Te ternary compound / alloy, Hf element single substance or compound, and at least one single substance or compound corresponding to the N element, the C element, the In element, and the Ga element, do not need to be mixed, so that they can be kept independent of each other for standby use. Alternatively, these three types of materials can also be mixed and formed into a phase change material in the form of a compound or alloy by smelting.

[0107] Of course, it is not excluded that the phase change material can also exist in the following forms: a combination of Ge element, Sb element, Te element, Hf element and at least one corresponding element among N element, C element, In element, and Ga element. According to the atomic percentage of each element in the phase change material, according to the ratio, the corresponding amount of each element is provided respectively. These specific amounts of elements do not need to be mixed and can be independent of each other. Alternatively, these specific amounts of elements can also be mixed and formed into a phase change material in the form of a compound or alloy by smelting.

[0108] A second embodiment of the present disclosure further provides a phase-change material comprising a Ge-Sb-Te phase-change substrate and a first doping element and a second doping element doped into the Ge-Sb-Te phase-change substrate. The first doping element comprises Hf, and the first doping element accounts for 1.5% to 7% of the phase-change material by atomic percentage. The second doping element comprises at least one of N, C, In, and Ga, and the second doping element accounts for 1.0% to 7% of the phase-change material by atomic percentage. Furthermore, the sum of the atomic percentages of the first and second doping elements is greater than 4% and less than 10%.

[0109] For example, some examples of the atomic percentage of the first doping element Hf in the phase change material include but are not limited to: 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%. , 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0110] For example, some examples of the atomic percentage of the second doping element in the phase change material include, but are not limited to: 1%, 1.1%, 1.2%, 1.3%, 1.4%, 1.5%, 1.6%, 1.7%, 1.8%, 1.9%, 2%, 2.1%, 2.2%, 2.3%, 2.4%, 2.5%, 2.6%, 2.7%, 2.8%, 2.9%, 3%, 3.1%, 3.2%, 3.3%, 3.4%, 3.5%, 3.6%, 3.7%, 3.8%, 3.9%, 4. %, 3.7%, 3.8%, 3.9%, 4%, 4.1%, 4.2%, 4.3%, 4.4%, 4.5%, 4.6%, 4.7%, 4.8%, 4.9%, 5%, 5.1%, 5.2%, 5.3%, 5.4%, 5.5%, 5.6%, 5.7%, 5.8%, 5.9%, 6%, 6.1%, 6.2%, 6.3%, 6.4%, 6.5%, 6.6%, 6.7%, 6.8%, 6.9%, etc.

[0111] The sum of the atomic percentages of the first doping element and the second doping element may be 4.5%, 5%, 5.5%, 6%, 6.5%, 7%, 7.5%, 8%, 8.5%, 9%, 9.5%, etc.

[0112] The second doping element can be one of the N element, C element, In element, and Ga element. For example, the second doping element is the N element, C element, In element, or Ga element, or the second doping element can also be a combination of any two elements among the N element, C element, In element, and Ga element, a combination of any three elements, or include all four elements at the same time.

[0113] Regarding the relevant principles of enhancing the adhesion of the phase change material layer by the second doping element being N, C, In or Ga, please refer to the relevant principle description of the phase change material involved in the first embodiment above, which will not be repeated here.

[0114] Compared with the phase change material of the first embodiment, the atomic percentage of N, C, In or Ga in the phase change material of the second embodiment is increased (atomic percentage is 1.0%-7%).

[0115] In this type of phase-change material layer, the doping concentrations of the first doping element and the second doping element need to be controlled within 7% or less. This ensures that the phase-change material layer has strong adhesion while also ensuring that the phase-change device has a high and stable high resistance, thereby improving the read window and cycle stability of the phase-change device. Furthermore, it ensures that the phase-change device has a high and stable low resistance, thereby improving the lifespan and cycle stability of the phase-change device. The reasons are as follows:

[0116] Research has found that when the atomic percentages of the first doping element and the second doping element are each greater than 7%, side effects will occur, leading to degradation of the read window, lifespan and other performance of the phase change device.

[0117] Taking nitrogen as the second doping element as an example, and combining the data in Table 5 of Example 5, it can be seen that when the atomic percentage of Hf is too high (greater than 7%), the high resistance of the phase-change device decreases, resulting in a smaller read window. Furthermore, the high resistance is unstable during cycling, prone to segregation, and thus prone to fatigue failure of the phase-change device. When the atomic percentage of nitrogen is too high (greater than 7%), the low resistance of the phase-change device increases abnormally and is unstable during cycling, continuously decreasing during fatigue. This may be related to the increased likelihood of thermoelectric accumulation during operation, leading to segregation.

[0118] As shown in Table 5, when the atomic percentage of the Hf element is 8% (exceeding the upper limit of 7%), the high resistance of the phase-change memory chip will become low and unstable during cycling. When the atomic percentage of the N element is 8% (exceeding the upper limit of 7%), the low resistance of the phase-change memory chip will become high, but it will be unstable during cycling. Therefore, the embodiments of the present disclosure ensure that the atomic percentages of the Hf element and the N element are each less than or equal to 7%, thereby ensuring that the phase-change device has a high and stable high resistance, and also ensuring that the phase-change device has a high and stable low resistance.

[0119] In addition, in this type of phase change material, the sum of the atomic percentages of the first doping element and the second doping element must be greater than 4% and less than 10%. This ensures that the phase change material layer has strong adhesion while also enabling the phase change device to have a long lifespan and cycle stability. The reasons are as follows:

[0120] Research has found that for this type of phase change material, the lifespan of the phase change device is closely related to the doping concentration of Hf and the secondary doping element. Performance analysis of phase change devices reveals that the low resistance of the device is proportional to its ultimate fatigue life. As shown in Figure 24, within a certain range, the higher the low resistance of the phase change device, the better the fatigue characteristics. The low resistance of the phase change device is primarily determined by the low resistance of the phase change material layer and the crystallization temperature. The values ​​on the horizontal and vertical axes of Figure 24 are obtained by normalizing and taking logarithms.

[0121] Taking N as the second doping element as an example and combining the data in Table 1, it can be seen that when the doping concentrations of Hf and N increase, the low resistance and crystallization temperature of the phase change material layer will increase accordingly (see phase change material 3 and phase change material 4 in Table 1). As a result, the low resistance of the phase change device will also increase, thereby obtaining a longer lifespan of the phase change device.

[0122] Therefore, to ensure a longer lifespan for the phase change device, it is necessary to make the low resistance of the phase change material layer as high as possible while maintaining a certain read window. Phase change material 4 in Table 1 has an atomic percentage of 2% Hf and an atomic percentage of 2% N, and phase change material 1 in Table 1 has an atomic percentage of 4% Hf and an atomic percentage of 0% N. The low-resistance state resistance of the phase change material layer corresponding to both is approximately 400 ohms, which is much less than 1k ohm. In addition, the sum of the atomic percentages of Hf and N in both is 4%. Therefore, the embodiment of the present disclosure limits the sum of the atomic percentages of Hf and N to greater than 4%, that is, the sum of the atomic percentages of the first doping element and the second doping element to greater than 4%, which is very necessary to give the phase change device a long lifespan.

[0123] The sum of the doping concentrations of the first and second doping elements is not necessarily better. Research has confirmed that when the sum of the doping concentrations of the first and second doping elements is greater than 10%, side effects can occur, leading to unstable cycling of the phase change device. This includes causing the low resistance of the phase change device to rise abnormally and become unstable during cycling. Specifically, it continuously decreases during cycling. This may be due to the phase change material layer being more susceptible to thermoelectric accumulation and resulting in segregation during operation. Still taking N as the second doping element as an example and combining the data in Table 5 of Example 5, it can be seen that when the atomic percentage of Hf is 6.5% and the atomic percentage of N is 5%, since the sum of the atomic percentages of the two is greater than 10%, the low resistance rises abnormally and becomes unstable during cycling. Therefore, it is desirable that the sum of the atomic percentages of Hf and N be less than 10%.

[0124] In summary, for the phase change materials provided in the embodiments of the present disclosure, by further doping at least one of N element, C element, In element, and Ga element into the Ge-Sb-Te phase change base material doped with Hf element, the adhesion of the phase change material layer can be enhanced, achieving a tight combination between the phase change material layer and other adjacent functional layers, reducing the probability of interface peeling, increasing the product yield of the phase change memory chip, and avoiding contamination and interference to the production line and production equipment. In particular, by making the doping amount of Hf element be 1.5%-7%, and making the doping amount of at least one of N element, C element, In element, and Ga element be 1.0%-7%, and the sum of the atomic percentages of the two doping elements is greater than 4% and less than 10%, while achieving the improvement of the adhesion of the phase change material layer, it is also beneficial to make the phase change device have a large read window, high lifespan, and cycling stability.

[0125] In some implementation manners, the phase change materials provided in the embodiments of the present disclosure further include: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, Ce element. By further introducing a specific content of the third doping element into the phase change material, the purpose of optimizing the comprehensive performance of the phase change memory device can also be achieved. Among them, the atomic percentage of the third doping element in the phase change material is 0.01%-10%.

[0126] For the Ge-Sb-Te phase change base material, the chemical general formula of its Ge-Sb-Te compound can be shown as any of the following chemical general formulas:

[0127] Chemical general formula one, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously.

[0128] Chemical general formula two, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

[0129] Regarding the first general chemical formula and the second general chemical formula of the Ge-Sb-Te phase change substrate involved above, for the exemplary values of each parameter and the relevant explanations, reference can be made to the relevant descriptions in the phase change material involved in the above first embodiment, and details will not be repeated here.

[0130] In the embodiments of the present disclosure, by making the general chemical formula of the Ge-Sb-Te phase change substrate as described above, the purpose is to ensure that the adhesion force of the phase change material layer obtained based on the Ge-Sb-Te phase change substrate of the embodiments of the present disclosure is stronger than that of the phase change material layers obtained from other Ge-Sb-Te phase change substrates. This is because GeTe, Sb2Te3, and Sb y Te (y≥2) are all stable compounds with stable chemical component ratios. Considering that Te单质 is a typical two-dimensional material, after Te-Te bonding, a layered structure is formed, and the interlayer is bonded by van der Waals forces, resulting in poor adhesion. At the same time, the melting point of Sb2Te3 (620°C) is higher than that of Te单质 (450°C). At the high temperature during the phase change process, Te is more likely to precipitate to form Te单质 two-dimensional material, resulting in poor adhesion. In the embodiments of the present disclosure, making a, b, c, and d all greater than 0 can make the Ge-Sb-Te phase change substrate in a state of lacking Te compared with the above-mentioned stable compounds. By appropriately reducing the content of the Te element, it is ensured that the adhesion force of the phase change material layer is strong enough.

[0131] In addition, regarding the relevant adhesion force test of the above Ge-Sb-Te phase change substrate, reference can still be made to the relevant descriptions in the phase change material involved in the above first embodiment, and details will not be repeated here.

[0132] In some examples, for the first general chemical formula of the Ge-Sb-Te phase change substrate, (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where 0.2 < x ≤ 0.4. For the second general chemical formula of the Ge-Sb-Te phase change substrate, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.4.

[0133] Exemplarily, the values of x include but are not limited to: 0.22, 0.23, 0.24, 0.25, 0.26, 0.27, 0.28, 0.29, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, 0.37, 0.38, 0.39, 0.4, etc.

[0134] When 0.2 < x ≤ 0.4, the first chemical general formula or the second chemical general formula of the Ge-Sb-Te phase change substrate corresponds to another expression of the chemical general formula, which can also be shown as follows: Ge x Sb y Te 1-x-y , where x and y both represent the atomic percentages of the corresponding elements, and 6% < x < 15%, 35% < y < 45% (alternatively, Ge x Sb y Te 100-x-y , where x and y are both the mass parts of the corresponding atoms, 6 < x < 15, 35 < y < 45).

[0135] For example, on the basis of satisfying the above chemical general formula, in the Ge-Sb-Te phase change substrate, the ratio of the atomic percentage contents of Ge element, Sb element and Te element includes but is not limited to: 1:4:5, 1:4:6, 1:4:7, etc. The corresponding GeSbTe compounds are respectively abbreviated as GeSbTe145 (or Ge1Sb4Te5, GST145), GeSbTe146 (or Ge1Sb4Te6, GST146), GeSbTe147 (or Ge1Sb4Te7, GST147).

[0136] By making the chemical general formula of the Ge-Sb-Te phase change substrate as shown above, it not only ensures that the adhesion force of the phase change material layer is strong enough, but also helps to reduce the time delay of the phase change device and improve the life of the phase change device.

[0137] The embodiments of the present disclosure have made relevant tests on the influence of the contents of Ge element and Sb element in the Ge-Sb-Te phase change substrate on the adhesion force, time delay and life. The test results show that the atomic percentage of Sb element is an important factor determining the speed of the phase change device. The crystallization temperature of Sb单质 is low and the growth speed is fast. Therefore, the atomic percentage of Sb element is positively correlated with the SET performance of the phase change device. In theory, the higher the atomic percentage of Sb element, the shorter the time delay of the phase change device.

[0138] Experiments have shown that when the atomic percentage of Sb in the Ge-Sb-Te phase change matrix is ​​greater than 35% (corresponding to x≤0.4 in the above stoichiometric ratio), the phase change device delay can reach below 100ns due to the low crystallization temperature and fast growth rate of the Sb element. However, the higher the atomic percentage of Sb, the better. When the atomic percentage of Sb in the Ge-Sb-Te phase change matrix exceeds 45% (corresponding to x>0.2 in the above stoichiometric ratio), the amount of Sb and Te forming a stable compound is relatively reduced, and the Sb element is relatively excessive and has poor stability, resulting in a certain reduction in the life of the phase change device. It can be seen that by limiting the atomic percentage of Sb to greater than 35% and less than 45%, it is beneficial for the phase change device to have both low delay and long life.

[0139] Experiments have shown that when the Ge atomic percentage is greater than 15%, its concentration is too high, which will cause the phase change device's delay to slow down to a certain extent. When the Ge atomic percentage is less than 6% (corresponding to satisfying the above stoichiometric ratio x>0.2), its concentration is too low, which will reduce the adhesion of the phase change material layer, making mass production process tuning too difficult. Therefore, by limiting the Ge atomic percentage to greater than 6% and less than 15%, it is beneficial to ensure that the phase change material layer has high adhesion and the phase change device has low delay.

[0140] In addition, for the existence form of the phase change material provided in the second embodiment, reference can still be made to the relevant description of the phase change material involved in the first embodiment, and no further details will be given here.

[0141] It can be seen that the embodiments of the present disclosure achieve balanced optimization of the performance of the phase change memory chip by identifying the corresponding coupling relationship between different elements in the phase change material and key device performance (speed, life, window, adhesion), and adjusting the stoichiometric ratio of each element, thereby ensuring that the overall performance of the phase change memory chip is more excellent.

[0142] The embodiment of the present disclosure further provides a phase change memory chip, which includes a plurality of phase change memory units. The phase change memory units include a phase change material layer 100. The phase change material layer 100 is prepared from any of the phase change materials described above.

[0143] The phase change memory chip can also be called a phase change memory. The phase change memory chip provided by the embodiment of the present disclosure is based on the fact that its phase change material layer 100 is prepared from the phase change material provided by the embodiment of the present disclosure, so that the phase change memory chip has all the advantages of the phase change material provided by the embodiment of the present disclosure.

[0144] The phase-change memory cell is disposed on a substrate 004. In some examples, as shown in FIG5 , the phase-change memory cell includes, in addition to the aforementioned phase-change material layer 100, a top electrode 501, a bottom electrode 502, and an insulating layer 400. From bottom to top, the substrate 004, the bottom electrode 502, the phase-change material layer 100, and the top electrode 501 are stacked in sequence, with the insulating layer 400 at least covering the outer side of the phase-change material layer 100.

[0145] In other examples, in addition to the phase-change material layer 100, the phase-change memory cell further includes a top electrode 501, a bottom electrode 502, an insulating layer 400, and a barrier layer 300, as shown in FIG6 . From bottom to top, the substrate 004, the bottom electrode 502, the barrier layer 300, the phase-change material layer 100, the barrier layer 300, and the top electrode 501 are stacked in sequence, and the insulating layer 400 at least covers the outside of the phase-change material layer 100 and the barrier layer 300.

[0146] Exemplarily, the barrier layer material used for the barrier layer 300 includes at least one of the following: single elements of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, nitrides of the above elements, and carbides of the above elements.

[0147] Taking the second doping element in the phase change material layer 100 as N element or C element as an example, N element or C element can form a bond with the above-mentioned metal element in the barrier layer 300 to form a non-metal-metal ion bond, thereby enhancing the bonding force between the adhesion layer 200 and the barrier layer 300 and reducing the probability of interface peeling between the two during the process.

[0148] Furthermore, as shown in Figures 7 and 8, the phase change memory unit provided in the embodiment of the present disclosure also includes an adhesion layer 200, which is stacked on at least one surface of the phase change material layer 100. The adhesion layer 200 is used to increase the adhesion between the phase change material layer 100 and the adjacent functional layer.

[0149] For example, the adhesion layer 200 may be provided on the surface of the phase change material layer 100 facing the top electrode 501, or on the surface of the phase change material layer 100 facing the bottom electrode 502, or respectively on the two opposite surfaces of the phase change material layer 100.

[0150] By adding the adhesion layer 200 on at least one surface of the phase change material layer 100 , the adhesion between the phase change material layer 100 and the adjacent functional layer is increased, wherein the adjacent functional layer may be the barrier layer 300 or the electrode layer.

[0151] It can be seen that the phase change memory chip provided by the embodiment of the present disclosure not only improves the phase change material itself, but also improves the structure of the phase change memory chip to add an adhesion layer 200 to further enhance the adhesion between the phase change material layer 100 and the adjacent functional layer, significantly reducing the probability of interface peeling, thereby increasing the product yield of the phase change memory unit, and also avoiding pollution and interference to the production line.

[0152] Adhesion layer 200 is prepared using an adhesion layer raw material. In some implementations, the adhesion layer raw material includes at least one of a nitride of a target element and a carbide of a target element. The target element is selected from at least one of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo. For example, if the target element is W, the adhesion layer raw material can be either tungsten nitride or tungsten carbide.

[0153] When the second doping element in the phase change material layer 100 is N element or C element, N element or C element can form a non-metal-metal ion bond with the target element in the adhesion layer 200, thereby improving the bonding force between the adhesion layer 200 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0154] When the second doping element in the phase change material layer 100 is In or Ga, the In or Ga element can combine with the target element in the adhesion layer 200 to form an alloy, forming a metal-metal bond, thereby improving the bonding force between the adhesion layer 200 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0155] It can be seen that by using the above-mentioned adhesion layer materials, the interface bonding ability and adhesion force between the phase change material layer and the adhesion layer can be achieved, thereby preventing the phase change material layer from falling off from the interface of the barrier layer and causing a decrease in device yield.

[0156] To demonstrate the enhanced interfacial adhesion in phase-change memory chips with adhesion layers, the present disclosure provides several types of phase-change materials for adhesion testing. These phase-change materials are as follows: (d) HfGST, a Ge1Sb4Te6 phase-change matrix doped with Hf alone, with an Hf atomic percentage of 3%; (e) NHfGST, a Ge1Sb4Te6 phase-change matrix doped with both Hf and N, with Hf and N atomic percentages of 3% and 2%, respectively. Adhesion tests were conducted between the corresponding phase-change material layers and the W electrodes. The test results are shown in Table 2.

[0157] The adhesion forces between the phase change material layers corresponding to these phase change materials and the W electrode and the adhesion layer made of W2N were tested respectively. The test results are shown in Table 4.

[0158] Table 4

[0159] As can be seen from Table 4, on the basis that the atomic percentages of the Hf element and the N element meet their respective defined atomic percentage ranges, it can be seen that compared with the phase change material layer doped with only the single Hf element, the adhesion force between the phase change material layer doped with both the Hf element and the N element in this application and the W electrode is significantly greater than the adhesion force between the phase change material layer without doping the N element and the W electrode. And the adhesion force between the phase change material layer doped with both the Hf element and the N element and the W electrode is slightly less than the adhesion force between the phase change material layer doped with both the Hf element and the N element and the adhesion layer W2N. It can be seen that by further increasing the adhesion layer, the interfacial adhesion force of the phase change material layer can be further improved.

[0160] In some other implementation manners, the raw material of the adhesion layer includes: a Ge-Sb-Te phase change material doped with a fourth doping element, and the raw material of the adhesion layer is different from the phase change material used for the phase change material layer. Among them, the fourth doping element is selected from at least one of the Hf element, the N element, the C element, the In element, and the Ga element, and the atomic percentage of the fourth doping element in the raw material of the adhesion layer is 0.01%-20%, and further can be 0.01%-10%.

[0161] The chemical general formula of the involved Ge-Sb-Te phase change material can be shown as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where 0 < x < 1, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously (here, x, a, and b involved are some parameters representing atomic percentages). Or, the chemical general formula of the Ge-Sb-Te phase change material can also be shown as follows: (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0 < x < 1, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously (here, x, y, c, and d involved are some parameters representing atomic percentages).

[0162] For example, the simplified formulas of some suitable adhesion layer materials can be as follows: NHfGeSbTe, CHfGeSbTe, InHfGeSbTe, GaHfGeSbTe, HfGeSbTe, NGeSbTe, CGeSbTe, InGeSbTe, GaGeSbTe, etc.

[0163] The doping amount of the fourth doping element in the Ge—Sb—Te phase change material is within the above range, so that the Ge—Sb—Te phase change material doped with the fourth doping element is different from the phase change material in the phase change material layer 100 , and mainly plays an interface adhesion role.

[0164] As mentioned above, the adhesion layer 200 is located between the phase change material layer 100 and the adjacent functional layer, wherein the adjacent functional layer may be the barrier layer 300 or the electrode layer (including at least one of the top electrode 501 and the bottom electrode 502 ).

[0165] In one solution, the phase change memory unit includes a barrier layer 300 , and the adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300 to increase adhesion between the phase change material layer 100 and the barrier layer 300 .

[0166] The barrier layer 300 prevents the elements in the phase change material layer 100 from diffusing into the electrode layer in the phase change memory cell. The adhesion layer 200 is located between the phase change material layer 100 and the barrier layer 300, effectively preventing peeling between the phase change material layer 100 and the barrier layer 300.

[0167] In some examples, as shown in FIG7 , there are two barrier layers 300 , which are located on opposite sides of the phase-change material layer 100 . In this case, there may also be two adhesion layers 200 , wherein one adhesion layer 200 is located between the first surface of the phase-change material layer 100 and one barrier layer 300 , and the other adhesion layer 200 is located between the second surface of the phase-change material layer 100 and the other barrier layer 300 .

[0168] Illustratively, the barrier layer material used for barrier layer 300 includes at least one of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co, and Mo, their nitrides, and their carbides. Of course, the barrier layer material is different from the adhesion layer material.

[0169] When the second doping element in the phase change material layer 100 is N element or C element, N element or C element can form a non-metal-metal ion bond with the metal element in the barrier layer 300, thereby improving the bonding force between the barrier layer 300 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0170] When the second doping element in the phase change material layer 100 is In or Ga, the In or Ga element can combine with the metal element in the barrier layer 300 to form an alloy, forming a metal-metal bond, thereby improving the bonding force between the barrier layer 300 and the phase change material layer 100, enhancing the interface adhesion, and reducing the probability of interface peeling between the two during the process.

[0171] In the above solution, the phase-change memory cell may further include, in addition to the phase-change material layer 100, adhesion layer 200, and barrier layer 300, a top electrode 501, a bottom electrode 502, and an insulating layer 400. In one example, as shown in FIG7 , from bottom to top, the substrate 004, the bottom electrode 502, the barrier layer 300, the adhesion layer 200, the phase-change material layer 100, the adhesion layer 200, the barrier layer 300, and the top electrode 501 are sequentially stacked, and the insulating layer 400 at least covers the outer sides of the phase-change material layer 100, the adhesion layer 200, and the barrier layer 300.

[0172] In some examples, the thickness of the blocking layer 300 and the adhesion layer 200 are each independently 1 nm to 8 nm, including but not limited to: 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, etc. For example, the thickness of the blocking layer 300 and the adhesion layer 200 can both be 2 nm.

[0173] Alternatively, the phase-change memory cell includes an electrode layer, and an adhesion layer 200 is positioned between the phase-change material layer 100 and the electrode layer to increase adhesion between the phase-change material layer 100 and the electrode layer. The adhesion layer 200 is positioned between the phase-change material layer 100 and the corresponding electrode layer to effectively prevent delamination between the phase-change material layer 100 and the electrode layer.

[0174] In the above solution, the phase-change memory cell may further include, in addition to the phase-change material layer 100 and the adhesion layer 200, a top electrode 501, a bottom electrode 502, and an insulating layer 400. In one example, as shown in FIG8 , from bottom to top, the substrate 004, the bottom electrode 502, the adhesion layer 200, the phase-change material layer 100, the adhesion layer 200, and the top electrode 501 are stacked in sequence, with the insulating layer 400 at least covering the outside of the phase-change material layer 100 and the adhesion layer 200.

[0175] Regarding the phase-change memory cell mentioned above, the structure of the phase-change memory cell includes but is not limited to the following: a confined structure, a T-shaped structure, a U-shaped trench structure, an L-shaped structure, and the like.

[0176] In some implementations, the phase-change memory chip provided by the embodiments of the present disclosure further includes: a plurality of gate transistor units, which are arranged in series with the phase-change memory cells. The gate transistor units are used as switching devices for the phase-change memory cells, thereby effectively suppressing leakage current generated during the operation of the phase-change memory chip.

[0177] Referring to FIG9 , the gate tube unit includes a gate layer 600 . The gate tube material used in the gate layer 600 includes at least one of an S-based gate tube material, a Se-based gate tube material, and a Te-based gate tube material. The S-based gate tube material, the Se-based gate tube material, and the Te-based gate tube material can all be currently known or commercially available gate materials, and examples are not provided here. The gate tube materials can be binary compounds, ternary compounds, or other multi-component compounds containing more elements.

[0178] Furthermore, the gate tube material further includes a fifth doping element, which is selected from at least one of B, Al, Ga, In, C, Si, Ge, Sn, N, P, As, Sb, Bi, O, Au, Hf, Pd, Cu, Co, Ag, Pt, Sc, Ti, and Ta. The atomic percentage of the fifth doping element in the gate tube material may be 0.01% to 20%, and further may be 0.01% to 10%.

[0179] In some examples, the fifth doping element includes at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, and O element, and also includes at least one of Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

[0180] By doping the fifth doping element into the gate tube material, the gate layer 600 can have the advantages of low leakage current, strong thermal stability, and long cycle life.

[0181] The thickness of the gate layer 600 can be 10 nm to 50 nm, for example, 1 nm, 2 nm, 3 nm, 4 nm, 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, 35 nm, 40 nm, 45 nm, 50 nm, etc. The thickness of the gate layer 600 can be determined based on the electrical properties of the phase change memory cell connected in series with the gate layer 600 to ensure that the gate transistor cell maintains the desired switching characteristics.

[0182] In some examples, as shown in Figures 9 to 12, the gate tube unit may only include a gate layer 600, and the gate layer 600 is integrated into the phase change memory unit, and the gate layer 600 and the phase change material layer 100 in the phase change memory unit are connected in series through the intermediate electrode 503.

[0183] In some examples, the gate transistor unit and the corresponding phase-change memory unit are independent of each other (not shown in the figure). For such examples, the gate transistor unit may include a substrate, a bottom electrode, a gate layer, and a top electrode stacked from bottom to top, and the gate layer is further coated with an insulating layer. The electrode layer of the gate transistor unit and the electrode layer of the corresponding phase-change memory unit can be connected in series via a wire (e.g., a copper interconnect).

[0184] The phase change memory chip provided in the embodiments of the present disclosure can be prepared by thin film deposition processes, photolithography processes, etching processes, etc., wherein multiple functional layers in the phase change memory chip, such as the phase change material layer 100, the adhesion layer 200, the barrier layer 300, the gating layer 600, etc., can all be prepared by thin film deposition processes.

[0185] For example, some applicable thin film deposition processes include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), etc. For further example, the above-mentioned functional layers can be prepared using plasma enhanced chemical vapor deposition (PECVD) process, magnetron sputtering process, electron beam evaporation process, etc.

[0186] Magnetron sputtering is a type of physical vapor deposition process with advantages such as ease of control, large coating area, strong adhesion, and a wide range of coating applications. For example, embodiments of the present disclosure may utilize a magnetron sputtering process to form the various functional layers. The sputtering gases used in the magnetron sputtering process include, but are not limited to, at least one of argon (Ar), krypton (Kr), xenon (Xe), neon (Ne), and nitrogen (N2).

[0187] The substrate 004 involved in the above-mentioned phase change memory unit and some gate tube units includes but is not limited to: silicon dioxide liner, silicon carbide substrate, silicon wafer substrate, sapphire substrate, diamond substrate, etc.

[0188] The electrodes (top electrode 501, bottom electrode 502 and middle electrode 503) involved in the above-mentioned phase change memory unit and some selection tube units, their electrode materials include but are not limited to: titanium tungsten TiW (such as Ti3W7), tungsten W, aluminum Al, titanium nitride TiN, titanium Ti, tantalum Ta, silver Ag, platinum Pt, carbon C, copper Cu, ruthenium Ru, gold Au, cobalt Co, chromium Cr, nickel Ni, iridium Ir, palladium Pd, rhodium Rh, etc.

[0189] The electrode materials may be deposited into corresponding electrode layers by using a physical vapor deposition (PVD) process (eg, magnetron sputtering).

[0190] The insulating layer 400 involved in the aforementioned phase-change memory cells and some gate tube cells is used to provide insulation and thermal isolation. The insulating and thermal insulating materials used include, but are not limited to, silicon nitride (Si3N4), silicon carbide (SiC), silicon dioxide (SiO2), etc. A chemical vapor deposition (CVD) process, such as a plasma-enhanced chemical vapor deposition (PECVD) process, can be used to deposit the insulating and thermal insulating materials into the insulating layer 400.

[0191] In some examples, as shown in Figures 9 to 12 , the insulating layer 400 includes a first insulating layer 401 and a second insulating layer 402. The first insulating layer 401 at least covers the outer surface of the phase-change material layer 100 and may further cover the outer surfaces of the barrier layer 300, the adhesion layer 200, and the top electrode 501. The second insulating layer 402 covers the outer surface of the first insulating layer 401.

[0192] For example, the first insulating layer 401 is made of silicon nitride Si3N4, silicon carbide SiC, or the like, and has a thickness greater than 1 nm, for example, 2 nm to 3 nm. The second insulating layer 402 is made of a compound formed by Si and at least one of N, C, and O, for example, at least one of silicon nitride Si3N4, silicon carbide SiC, and silicon dioxide SiO2, and has a thickness greater than 1 nm, for example, 2 nm to 3 nm.

[0193] By disposing the first insulating layer 401 and the second insulating layer 402 from the inside to the outside of the phase change material layer 100 , the purpose of optimizing insulation isolation and thermal isolation is achieved.

[0194] In some examples, as shown in Figures 9 to 12 , the insulating layer includes a third insulating layer 403 and a fourth insulating layer 404. The third insulating layer 403 covers at least the outer surface of the gate layer 600 and may also cover the outer surfaces of the middle electrode 503 and the bottom electrode 502. The fourth insulating layer 404 covers the outer surface of the third insulating layer 403.

[0195] For example, the third insulating layer 403 is made of silicon nitride Si3N4, silicon carbide SiC, or the like, and has a thickness greater than 1 nm, for example, 2 nm to 3 nm. The fourth insulating layer 404 is made of a compound formed by Si and at least one of N, C, and O, for example, at least one of silicon nitride Si3N4, silicon carbide SiC, and silicon dioxide SiO2, and has a thickness greater than 1 nm.

[0196] For example, the thickness of the fourth insulating layer 404 of a single-layer structure may be 2 nm to 3 nm. In some examples, the fourth insulating layer 404 may also be configured as a two-layer structure sequentially covering from the inside out, with the two layers made of different materials. For a double-layer structure, the thickness of the fourth insulating layer 404 may be 2 nm to 15 nm.

[0197] By disposing the third insulating layer 403 and the fourth insulating layer 404 from the inside to the outside of the gate layer 600, the purpose of optimizing insulation isolation and thermal isolation is achieved.

[0198] The structures of the phase-change memory chips provided in the embodiments of the present disclosure include, but are not limited to, 1S1R (One Selector One Resistor) structures and 1SnR (One Selector n Resistor) structures. For a 1S1R phase-change memory chip, one gate transistor unit controls one phase-change memory cell. For a 1SNR phase-change memory chip, one gate transistor unit controls N phase-change memory cells simultaneously.

[0199] In some examples, the structure of the phase-change memory chip involved in the embodiments of the present disclosure can be a 1S1R structure, where each group of series-connected gate transistor units and phase-change memory units is defined as a storage sub-unit 001. As shown in FIG13 , the 1S1R phase-change memory chip includes multiple storage sub-units 001, multiple word lines 002, and multiple bit lines 003. Of course, the phase-change memory chip also includes peripheral control circuits.

[0200] A plurality of storage sub-units 001 constitute a phase change memory array, wherein the plurality of storage sub-units 001 are arranged in an array, a plurality of word lines 002 are distributed in parallel and spaced apart, and each word line 002 can extend inwardly along a first direction, a plurality of bit lines 003 are distributed in parallel and spaced apart, and each bit line 003 can extend inwardly along a second direction, and an angle is formed between the first direction and the second direction, and the angle is greater than 0° and less than or equal to 90°.

[0201] For example, if the angle between the first direction and the second direction is equal to 90°, multiple word lines 002 can be arranged sequentially in rows, and multiple bit lines 003 can be arranged sequentially in columns. The multiple rows of word lines 002 and the multiple rows of bit lines 003 cooperate to form an array compatible with multiple memory sub-units 001. Each memory sub-unit 001 is located within a matrix sub-unit formed by word lines 002 and bit lines 003 (i.e., located within the overlapping region of word lines 002 and bit lines 003). Each memory sub-unit 001 is connected to the bit line 003 of the corresponding column via its top electrode 501, and each memory sub-unit 001 is connected to the word line 002 of the corresponding row via its bottom electrode 502.

[0202] During operation, multiple word lines 002 arranged in rows are connected to row select circuit A1, which can be driven by row voltage control circuit B1. Multiple bit lines 003 arranged in columns are connected to column select circuit A2, which can be driven by column voltage control circuit B2. Read / write circuit C receives processor commands and connects to row voltage control circuit B1 or column voltage control circuit B2, respectively. Thus, read / write circuit C receives processor commands and controls row select circuit A1 or column select circuit A2 via row voltage control circuit B1 or column voltage control circuit B2, thereby performing read / write operations on the phase-change memory cells in the selected memory sub-unit 001.

[0203] During the read and write operations on the phase-change memory cell, the gate transistor unit is used as a switching device. When the storage sub-cell 001 is not selected by both the row selection circuit A1 and the column selection circuit A2, its corresponding gate transistor unit is in a closed state to prevent leakage current from affecting other cells.

[0204] The phase change memory chip provided by the embodiment of the present disclosure can be stacked in three dimensions, thereby forming an N-layer structure (N≥1) in the vertical direction, so that the storage density of the three-dimensional stacked memory reaches 4F. 2 *N, where F is the semiconductor process feature size.

[0205] The following describes the structures of some phase-change memory chips provided by the embodiments of the present disclosure in an exemplary manner, in combination with a solution in which the phase-change memory chip includes a gating layer 600 and the gating layer 600 is integrated into a phase-change memory unit.

[0206] As an example 1, refer to Figure 9, which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0207] Each storage sub-unit 001 includes a bottom electrode 502, a gating layer 600, an intermediate electrode 503, a blocking layer 300, a phase-change material layer 100, a blocking layer 300 and a top electrode 501 stacked in sequence from bottom to top. Adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of its blocking layer 300, phase-change material layer 100, blocking layer 300 and top electrode 501 are sequentially covered with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, the gating layer 600 and the intermediate electrode 503 are sequentially covered with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0208] In the phase-change memory chip provided in Example 1, the phase-change material layer 100 adopts the improved phase-change material provided in the above embodiment of the present disclosure, which can effectively improve the adhesion between the phase-change material layer 100 and the barrier layer 300.

[0209] As a second example, refer to Figure 10, which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0210] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, a blocking layer 300, an adhesion layer 200, a phase-change material layer 100, an adhesion layer 200, a blocking layer 300 and a top electrode 501 stacked in sequence from bottom to top. Adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of its blocking layer 300, adhesion layer 200, phase-change material layer 100, adhesion layer 200, blocking layer 300 and top electrode 501 are sequentially covered with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially covered with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0211] The phase change memory chip provided in Example 2, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the barrier layer 300, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0212] As a third example, refer to Figure 11, which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0213] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, a blocking layer 300, a phase-change material layer 100, an adhesion layer 200, a blocking layer 300 and a top electrode 501 stacked in sequence from bottom to top. Adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of its blocking layer 300, phase-change material layer 100, adhesion layer 200, blocking layer 300 and top electrode 501 are sequentially covered with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially covered with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0214] The phase change memory chip provided in Example 3, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure; on the other hand, an adhesion layer 200 is added to the side of the phase change material layer 100 close to the top electrode 501, which can further enhance the adhesion between the phase change material layer 100 and the barrier layer 300.

[0215] Of course, the phase change memory chip provided in Example 3 may also add an adhesion layer 200 on the side of the phase change material layer 100 close to the gate layer 600 to increase the bonding force between the phase change material layer 100 and the barrier layer 300 close to the gate layer 600 .

[0216] As a fourth example, refer to Figure 12, which illustrates a 1S1R type phase change memory chip, which is arranged on a substrate 004. The 1S1R type phase change memory chip includes multiple storage sub-units 001, multiple word lines 002 and multiple bit lines 003. The multiple storage sub-units 001 are arranged in an array, the multiple word lines 002 are arranged in rows, and the multiple bit lines 003 are arranged in columns. Each storage sub-unit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0217] Each storage sub-unit 001 includes a bottom electrode 502, a selection layer 600, an intermediate electrode 503, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200 and a top electrode 501 stacked in sequence from bottom to top. Adjacent storage sub-units 001 are isolated by an insulating layer. Specifically, for each storage sub-unit 001, the outer surfaces of its adhesion layer 200, phase change material layer 100, adhesion layer 200 and top electrode 501 are sequentially covered with a first insulating layer 401 and a second insulating layer 402 from the inside to the outside, and the outer surfaces of its bottom electrode 502, the selection layer 600 and the intermediate electrode 503 are sequentially covered with a third insulating layer 403 and a fourth insulating layer 404 from the inside to the outside.

[0218] The phase change memory chip provided in Example 4, on the one hand, has a phase change material layer 100 using the improved phase change material provided in the above embodiment of the present disclosure, and on the other hand, an adhesion layer 200 is added between the phase change material layer 100 and the electrode layer, which can further enhance the adhesion between the phase change material layer 100 and the electrode layer.

[0219] The embodiments of the present disclosure, in combination with any of the above-mentioned phase change materials, exemplify the structural arrangement and preparation process of some 1S1R phase change memory chips.

[0220] As an example (1), a 1S1R phase change memory chip is provided, which is arranged on a silicon oxide substrate 004. The 1S1R phase change memory chip includes a plurality of memory subunits 001, a plurality of word lines 002, and a plurality of bit lines 003. As shown in FIG9 , each memory subunit 001 includes a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase change material layer 100, a barrier layer 300, and a top electrode 501 stacked in sequence from bottom to top. Adjacent memory subunits 001 are isolated by an insulating layer. The plurality of memory subunits 001 are arranged in an array, the plurality of word lines 002 are arranged in rows, and the plurality of bit lines 003 are arranged in columns. Each memory subunit 001 is connected to the bit line 003 of the corresponding column through its top electrode 501, and is connected to the word line 002 of the corresponding row through its bottom electrode 502.

[0221] For example, the word line 002 and the bit line 003 are both made of metal tungsten W, the top electrode 501, the bottom electrode 502, and the middle electrode 503 are all made of carbon C, and the barrier layer 300 is made of metal tungsten W. The gate tube material used in the gate layer 600 is the currently available SiGeAsSe gate material. The phase change material of the phase change material layer 100 can be the phase change material involved in the first embodiment above.

[0222] The preparation process of the 1S1R phase change memory chip is as follows:

[0223] As shown in FIG14 , a thin film precursor for a phase-change memory chip is provided. The thin film precursor includes: a substrate 004, a word line 002 layer, a bottom electrode 502, a gate layer 600, an intermediate electrode 503, a barrier layer 300, a phase-change material layer 100, a barrier layer 300, a top electrode 501, and a mask layer 005, which are stacked in order from bottom to top. The mask layer 005 is primarily used to protect the underlying material layers, preventing etching and other processes from affecting the underlying material layers.

[0224] As shown in FIG15 , the thin film precursor undergoes a first patterning process to form a first trench 701. The first patterning process includes photolithography and etching. In the vertical direction (i.e., the Z-axis direction in FIG15 ), the first trench 701 sequentially penetrates the mask layer 005, the top electrode 501, the barrier layer 300, the phase-change material layer 100, and the barrier layer 300 from top to bottom, exposing the intermediate electrode 503. In the first horizontal direction (i.e., the X-axis direction in FIG15 ), the first trench 701 is spaced apart to form a plurality of first memory cell precursors.

[0225] As shown in FIG16 , an insulating material is filled into the first trench 701 to form an insulating layer. This includes sequentially filling the first trench 701 with a first insulating material and a second insulating material. The first insulating material forms a first insulating layer 401 that covers the surface of the corresponding first memory cell precursor, and the second insulating material forms a second insulating layer 402 that covers the surface of the first insulating layer 401. The first insulating layer 401 is made of silicon nitride, and the second insulating layer 402 is made of silicon dioxide. Both of these materials can protect the phase change material layer 100 from being affected by subsequent etching processes.

[0226] As shown in FIG17 , the second patterning process is continued to make the first trench 701 extend downward in the vertical direction to form a second trench 702. The second patterning process includes photolithography and etching.

[0227] In the vertical direction, the second trench 702 sequentially penetrates the mask layer 005, the top electrode 501, the barrier layer 300, the phase-change material layer 100, the barrier layer 300, the intermediate electrode 503, the gate layer 600, the bottom electrode 502, and the word line 002. In the first horizontal direction, the second trench 702 is arranged in a plurality of intervals to form a plurality of second memory cell precursors.

[0228] As shown in FIG18 , the second trench 702 is filled with an insulating material to form an insulating layer. This includes sequentially filling the second trench 702 with a third insulating material and a fourth insulating material. The third insulating material forms a third insulating layer 403 and covers the surface of the corresponding second memory cell precursor. The fourth insulating material forms a fourth insulating layer 404 and covers the surface of the third insulating layer 403, thereby forming an integrated third memory cell precursor. The third insulating layer 403 is made of silicon nitride, and the fourth insulating layer 404 is made of silicon dioxide. The third insulating layer 403 and the fourth insulating layer 404 provide insulation isolation between the different second memory cell precursors and also provide mechanical support for them.

[0229] As shown in FIG19 , the third memory cell precursor is polished to remove the mask layer 005 and expose the top electrode 501. Then, a bit line 003 and a new mask layer 005 are sequentially formed on the surface of the top electrode 501, resulting in an integrated fourth memory cell precursor. The structure of a cross-section of the fourth memory cell precursor along the second horizontal direction is shown in FIG20 . The cross-section along the second horizontal direction is the cross-section indicated by the dashed line AB in FIG19 , and the second horizontal direction is the Y-axis in FIG20 , which is perpendicular to the aforementioned X-axis.

[0230] As shown in FIG21 , the fourth memory cell precursor undergoes a third patterning process to form a third trench 703. The third patterning process includes photolithography and etching. Vertically, the third trench 703 sequentially penetrates the mask layer 005, the bit line 003 layer, the top electrode 501, the barrier layer 300, the phase-change material layer 100, and the barrier layer 300, exposing the intermediate electrode 503. In the second horizontal direction, multiple third trenches 703 are arranged at intervals to form a plurality of fifth memory cell precursors.

[0231] As shown in FIG22 , an insulating material is filled into the third trench 703 to form an insulating layer, which includes: sequentially filling the third trench 703 with a first insulating material and a second insulating material, wherein the first insulating material forms a first insulating layer 401 and covers the corresponding surface of the fifth memory cell precursor, and the second insulating material forms a second insulating layer 402 and covers the surface of the first insulating layer 401, thereby obtaining an integrated sixth memory cell precursor.

[0232] As further shown in FIG. 22 , the sixth memory cell precursor is subjected to a fourth patterning process, such that the third trench 703 extends downward in a vertical direction to form a fourth trench. The fourth patterning process includes photolithography and etching. Vertically, the fourth trench sequentially penetrates the mask layer 005, the bit line 003 layer, the top electrode 501, the barrier layer 300, the phase change material layer 100, the barrier layer 300, the intermediate electrode 503, the gating layer 600, and the bottom electrode 502, exposing the word line 002. In the second horizontal direction, the fourth trench is arranged in a plurality of intervals, thereby forming a plurality of seventh memory cell precursors.

[0233] As shown in FIG22 , an insulating material is filled into the fourth trench to form an insulating layer, which includes: sequentially filling the fourth trench with a third insulating material and a fourth insulating material, wherein the third insulating material forms a third insulating layer 403 and covers the corresponding surface of the seventh memory cell precursor, and the fourth insulating material forms a fourth insulating layer 404 and covers the surface of the third insulating layer 403, thereby obtaining an integrated eighth memory cell precursor.

[0234] As shown in FIG23 , the eighth memory cell precursor is polished to remove the mask layer 005 and the third insulating layer 403 and the fourth insulating layer 404 above the bit line 003 to expose the bit line 003 , thereby preparing the phase change memory chip provided in Example 1.

[0235] The phase change memory chip provided in Example 1 effectively improves the bonding force between the phase change material layer 100 and the barrier layer 300 by improving the phase change material, preventing delamination, peeling, etc. between layers, which may lead to a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window, low latency, and high endurance characteristics.

[0236] For the phase change memory chip involved in this type of example, the bonding force between the phase change material layer 100 and the barrier layer 300 is effectively improved by improving the phase change material, preventing delamination, peeling, etc. between layers, which may lead to a decrease in the yield of the phase change memory chip. At the same time, the improved phase change material still helps the phase change memory chip to have advantages such as a large read window and high endurance characteristics.

[0237] As Example (2), a type of 1S1R phase change memory chip is provided. The 1S1R phase change memory chip involved in this type of example includes multiple memory sub-units 001, multiple word lines 002, and multiple bit lines 003. As shown in Figure 10, each memory sub-unit 001 includes a bottom electrode 502, a select layer 600, an intermediate electrode 503, a barrier layer 300, an adhesion layer 200, a phase change material layer 100, an adhesion layer 200, a barrier layer 300, and a top electrode 501, which are stacked in sequence from bottom to top. The adjacent memory sub-units 001 are isolated by an insulating layer. Compared with Example (1), an adhesion layer 200 is added to the memory sub-unit 001, and the arrangement of other layers is the same. Exemplarily, the thickness of the adhesion layer 200 can be 2 nm, and the material of the adhesion layer 200 can be WN or InGeSbTe. Among them, WN can be W2N, WN, WN2, or any component satisfying the following general formula: W x N 1-x , where x is the atomic percentage, and 0 < x < 1. The InGeSbTe compound can be, for example, In3%-Ge2Sb2Te5, that is, the atomic percentage of In is 3%, and in the GeSbTe phase change substrate, the ratio of the atomic percentage contents of Ge, Sb, and Te is 2:2:5.

[0238] The manufacturing process of the phase change memory chip involved in this type of Example (2) can refer to the above Example (1), except that when forming the memory sub-unit 001, an adhesion layer 200 is formed at a specific position.

[0239] The phase change memory chip involved in this type of example (2) effectively improves the bonding strength between the phase change material layer 100 and the barrier layer 300 by, on the one hand, improving the phase change material and, on the other hand, adding an adhesion layer 200 between the phase change material layer 100 and the barrier layer 300. In addition, since the total thickness of the two adhesion layers 200 can be 4 nm, which is only one tenth of the thickness of the phase change material layer 100, the performance of the phase change material layer 100 is relatively small.

[0240] As Example (3), a 1S1R type phase change memory chip is provided, and its structure and preparation process can be referred to Example (1). The difference from the phase change memory chip of Example (1) is that: referring to FIG12 , the barrier layer 300 in Example 1 is directly replaced by an adhesion layer 200, that is, an adhesion layer 200 is directly provided between the phase change material layer 100 and the top electrode 501, and an adhesion layer 200 is provided directly between the phase change material layer 100 and the intermediate electrode 503, respectively.

[0241] The phase change memory chip involved in this type of example (3) improves the phase change material on the one hand, and on the other hand, increases the bonding force between the phase change material layer 100 and the electrode layer by adding an adhesion layer 200 between the phase change material layer 100 and the electrode layer.

[0242] As example (4), a 1S1R type phase change memory chip is provided, and its structure and preparation process can be referred to example (1). The difference from the phase change memory chip of example (1) is that the doping elements in the phase change material used in the phase change material layer 100 are limited to Hf elements and In elements.

[0243] As example (5), a 1S1R type phase change memory chip is provided, and its structure and preparation process can be referred to example (1). The difference from the phase change memory chip of example (1) is that the phase change material of the phase change material layer 100 can be the phase change material involved in the second embodiment mentioned above.

[0244] For the 1S1R phase change memory chip involved in Example (5), the delay, life, high and low resistance characteristics, etc. of those phase change memory chips in which the atomic percentage ratio of each atom in the Ge-Sb-Te phase change substrate is: Ge:Sb:Te=1:4:7 (abbreviated as GST147) were tested. The test results are shown in Table 5, where NA involved in Table 5 means that the data has no meaning.

[0245] Table 5

[0246] Experiments have confirmed that when the atomic percentage of Sb in the Ge-Sb-Te phase-change matrix is ​​greater than 35% and less than 45%, the phase-change memory chip's latency can be reduced to less than 100ns. However, when the atomic percentage of Sb in the Ge-Sb-Te phase-change matrix exceeds 45%, the lifespan of the phase-change memory chip is somewhat reduced. When the atomic percentage of Ge exceeds 15%, the latency of the phase-change memory chip decreases to a certain extent. When the atomic percentage of Ge is less than 6%, the adhesion of the phase-change material layer is reduced.

[0247] As shown in Table 5, a combined atomic percentage of Hf and N exceeding 4% is essential for achieving a long lifespan in phase-change memory chips. However, when the atomic percentage of Hf is 6.5% and the atomic percentage of N is 5%, the combined atomic percentage exceeds 10%, resulting in abnormally high low-resistance and instability during cycling.

[0248] As shown in Table 5, when the atomic percentage of Hf is 8%, the high resistance of the phase-change memory chip decreases and the chip becomes unstable during cycling. When the atomic percentage of N is 8%, the low resistance of the phase-change memory chip increases but is unstable during cycling.

[0249] The phase change memory chip provided in the embodiments of the present disclosure has the potential to replace solid-state drives (SSDs) due to its high speed, high density, and non-volatility. If the operating speed is further improved, it has the potential to be applied to universal memory that combines the functions of internal and external storage.

[0250] On the other hand, an embodiment of the present disclosure further provides a storage device, which includes a controller and any one of the above-mentioned phase change memory chips, wherein the controller is used to store data in the phase change memory chip, wherein the controller reads and writes data stored in the storage device and interacts with an external interface.

[0251] The storage device (also referred to as a memory) may be configured to store various types of data, which may be contact data, phone book data, messages, pictures, videos, etc., or may be instructional data.

[0252] The storage devices involved in the embodiments of the present disclosure can be configured into various types, for example, including but not limited to: memory, hard disk, magnetic disk, optical disk, etc.

[0253] An embodiment of the present disclosure further provides an electronic device, which includes a processor and the above-mentioned storage device, wherein the processor is configured to store data generated by the electronic device in the storage device.

[0254] In some examples, the electronic device includes, but is not limited to, computers, mobile phones, music playing devices, digital broadcasting devices, messaging devices, game control devices, medical devices, fitness equipment, personal digital assistants, and the like.

[0255] The above description is only for the purpose of facilitating those skilled in the art to understand the technical solutions of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A phase change material, wherein: The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-6.5%; The second doping element includes at least one of N, C, In and Ga, and the atomic percentage of the second doping element in the phase change material is 1.0%-5%.

2. The phase change material according to claim 1, wherein: The phase change material also includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, and Ce element.

3. The phase change material according to any one of claims 1 to 2, wherein: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

4. A phase change material, wherein: The phase change material includes a Ge-Sb-Te phase change substrate, a first doping element and a second doping element doped in the Ge-Sb-Te phase change substrate; The first doping element includes Hf element, and the atomic percentage of the first doping element in the phase change material is 1.5%-7%; The second doping element includes at least one of N, C, In and Ga, and the atomic percentage of the second doping element in the phase change material is 1.0%-7%; The sum of the atomic percentages of the first doping element and the second doping element is greater than 4% and less than 10%.

5. The phase change material according to claim 4, wherein: The phase change material also includes: a third doping element, and the third doping element includes at least one of O element, Si element, B element, Sn element, Bi element, Cd element, Pb element, Zr element, Zn element, Cr element, Al element, Sc element, Y element, Ta element, Ti element, Er element, Lu element, Ho element, Tm element, Dy element, Tb element, Ca element, Nd element, Pr element, Yb element, Ca element, and Ce element.

6. The phase change material according to any one of claims 4 to 5, wherein: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1-a ) x (Sb2Te 3-b ) 1-x , where x is the atomic percentage and 0 < x < 1, a and b are parameters related to the atomic number ratio, 0 < a ≤ 1, 0 < b ≤ 3, and a = 1 and b = 3 do not exist simultaneously; Alternatively, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where x is the atomic percentage and 0 < x < 1, y, c, and d are parameters related to the atomic number ratio, y ≥ 2, 0 < c ≤ 1, 0 < d ≤ 1, and c = 1 and d = 1 do not exist simultaneously.

7. The phase change material according to claim 6, wherein: The chemical general formula of the Ge-Sb-Te phase change substrate is as follows: (GeTe 1- a ) x (Sb2Te 3-b ) 1-x , where 0.2 < x ≤ 0.4, or, (GeTe 1-c ) x (Sb y Te 1-d ) 1-x , where 0.2 < x ≤ 0.

4.

8. A phase change memory chip, wherein: The phase change memory chip comprises: a plurality of phase change memory units, wherein the phase change memory unit comprises a phase change material layer, wherein the phase change material layer is prepared from the phase change material according to any one of claims 1 to 3, or the phase change material layer is prepared from the phase change material according to any one of claims 4 to 7.

9. The phase change memory chip according to claim 8, wherein: The phase-change memory unit further includes an adhesion layer, which is stacked on at least one surface of the phase-change material layer and is used to increase adhesion between the phase-change material layer and an adjacent functional layer.

10. The phase change memory chip according to claim 9, wherein: The adhesion layer raw material used in the adhesion layer includes at least one of a nitride of a target element and a carbide of a target element; The target element is selected from at least one of W element, Ti element, Ge element, Ta element, Hf element, In element, Ga element, Al element, Cu element, Co element, and Mo element.

11. The phase change memory chip according to claim 9, wherein: The adhesion layer raw material used in the adhesion layer includes a Ge-Sb-Te phase change material doped with a fourth doping element, and the adhesion layer raw material is different from the phase change material; The fourth doping element is selected from at least one of Hf, N, C, In and Ga, and the atomic percentage of the fourth doping element in the raw material of the adhesion layer is 0.01%-20%.

12. The phase change memory chip according to any one of claims 9 to 11, wherein: The phase-change memory unit further includes a barrier layer. The adhesion layer is located between the phase-change material layer and the barrier layer, and is used to increase adhesion between the phase-change material layer and the barrier layer.

13. The phase change memory chip according to claim 12, wherein: The barrier layer material used in the barrier layer includes at least one of the simple substances, nitrides and carbides of W, Ti, Ge, Ta, Hf, In, Ga, Al, Cu, Co and Mo.

14. The phase change memory chip according to any one of claims 9 to 11, wherein: The phase change memory unit further includes an electrode layer. The adhesion layer is located between the phase change material layer and the electrode layer and is used to increase the adhesion between the phase change material layer and the electrode layer.

15. The phase change memory chip according to any one of claims 8 to 14, wherein: The phase-change memory chip further comprises: a plurality of gate tube units, wherein the gate tube units are arranged in series with the phase-change memory units; The gate tube unit includes a gate layer, and the gate tube material used in the gate layer includes at least one of an S series gate tube material, a Se series gate tube material, and a Te series gate tube material.

16. The phase change memory chip according to claim 15, wherein: The gate tube material also includes a fifth doping element, and the fifth doping element is selected from at least one of B element, Al element, Ga element, In element, C element, Si element, Ge element, Sn element, N element, P element, As element, Sb element, Bi element, O element, Au element, Hf element, Pd element, Cu element, Co element, Ag element, Pt element, Sc element, Ti element, and Ta element.

17. A storage device, wherein: The storage device comprises a controller and at least one phase-change memory chip as claimed in any one of claims 8 to 16, wherein the controller is used to store data in the phase-change memory chip.

18. An electronic device, wherein: The electronic device comprises a processor and the storage device according to claim 17, wherein the processor is used to store data generated by the electronic device in the storage device.

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