Video encoding method and apparatus thereof

Abstract

A video encoding method, comprising: acquiring a plurality of video frames; processing the plurality of video frames by means of an encoder to obtain an encoding result, the encoder comprising a first network layer, the first network layer comprising an inter-frame compression module, the plurality of video frames comprising M first video frames and N second video frames, and the inter-frame compression module being used for fusing feature representations of the M first video frames to feature representations of the N second video frames to obtain N feature representations; and, on the basis of the encoding result, executing a video-related task to obtain a processing result. The inter-frame compression module can perform aggregation on feature representations of similar video frames, thereby reducing the number of feature representations that need to be processed by a model, and further reducing the computing power overhead of the model.

Description

Video encoding method and device thereof

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on September 28, 2023, with application number 202311292413.7 and application name “A video encoding method and device thereof”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of artificial intelligence, and in particular to a video encoding method and apparatus thereof. Background Art

[0003] Artificial Intelligence (AI) is the theory, methods, techniques, and application systems that use digital computers or machines controlled by digital computers to simulate, extend, and expand human intelligence, to perceive the environment, acquire knowledge, and use that knowledge to achieve optimal results. In other words, AI is a branch of computer science that seeks to understand the essence of intelligence and develop new intelligent machines that can respond in a manner similar to human intelligence. AI also studies the design principles and implementation methods of various intelligent machines, enabling them to possess the capabilities of perception, reasoning, and decision-making.

[0004] The Video Transformer model applies the original Transformer model to the video domain, encoding video features by modeling temporal and spatial information. This model can then be used for downstream video understanding tasks such as video-to-text retrieval, video description generation, and video question-answering. The Video Transformer model effectively adapts to large-scale pre-training and has become the foundational model architecture for video understanding.

[0005] When inputting long videos into the Video Transformer model, they are broken into a large number of visual tokens. This results in excessively long input token sequences and high redundancy. This compromises video encoding efficiency and hinders the model's ability to learn key semantic information. For example, for a 96-frame video with a resolution of 224x224, the commonly used Video Transformer model will chop each frame into 16x16 patches. This will result in as many as (224 / 16)x(224 / 16)x96 = 19K visual tokens, placing a significant computational burden on subsequent feature encoding.

[0006] Therefore, there is an urgent need for a video encoding method with low computing power overhead.

[0007] Summary of the Invention

[0008] In a first aspect, the present application provides a video encoding method, the method comprising: obtaining multiple video frames; processing the multiple video frames through an encoder to obtain an encoding result; wherein the encoder comprises a first network layer; the first network layer comprises an inter-frame compression module, the multiple video frames comprise M first video frames and N second video frames, the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations; according to the encoding result, performing video-related tasks to obtain a processing result.

[0009] Among them, the inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process, thereby reducing the computing power overhead of the model.

[0010] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0011] In one possible implementation, fusing the feature representations of the M first video frames into the feature representations of the N second video frames includes: fusing the feature representation of each first video frame in the M first video frames into the feature representation of the second video frame that is most similar to the N second video frames.

[0012] The inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiments of the present application ensure that important timing information in the video is fully preserved. Therefore, the method of the embodiments of the present application can improve computational efficiency while still ensuring the quality and effectiveness of video encoding.

[0013] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0014] For the selection of objects that need to be fused (for example, M first video frames), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0015] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the plurality of video frames.

[0016] This application proposes a selection algorithm based on visual token geometry. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more precise and efficient, ensuring the quality and accuracy of the aggregation results.

[0017] In a possible implementation, the fusion is average pooling.

[0018] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks with feature representations of the Y second image blocks to obtain Y feature representations.

[0019] Among them, the intra-frame compression module can aggregate the feature representations of similar image blocks, thereby reducing the number of feature representations that the model needs to process, thereby reducing the computing power overhead of the model.

[0020] In a possible implementation, fusing the feature representations of the X first image blocks into the feature representations of the Y second image blocks includes:

[0021] The feature representation of each first image block in the X first image blocks is fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0022] The inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiments of the present application ensure that important timing information in the video is fully preserved. Therefore, the method of the embodiments of the present application can improve computational efficiency while still ensuring the quality and effectiveness of video encoding.

[0023] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

[0024] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0025] In a second aspect, the present application provides a video encoding device, the device comprising:

[0026] An acquisition module, used to acquire multiple video frames;

[0027] a processing module, configured to process the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames with feature representations of the N second video frames to obtain N feature representations;

[0028] According to the encoding result, video-related tasks are performed to obtain a processing result.

[0029] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0030] In a possible implementation, the processing module is specifically configured to:

[0031] The feature representation of each first video frame in the M first video frames is fused into the feature representation of the second video frame that is most similar to the N second video frames.

[0032] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0033] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the plurality of video frames.

[0034] In a possible implementation, the fusion is average pooling.

[0035] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks with feature representations of the Y second image blocks to obtain Y feature representations.

[0036] In a possible implementation, the processing module is specifically configured to:

[0037] The feature representation of each first image block in the X first image blocks is fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0038] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

[0039] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0040] In a third aspect, an embodiment of the present application provides a data processing device, which may include a memory, a processor, and a bus system, wherein the memory is used to store programs, and the processor is used to execute the programs in the memory to perform the first aspect and any optional method thereof.

[0041] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, in which a computer program is stored. When the computer-readable storage medium is run on a computer, the computer executes the above-mentioned first aspect and any optional method thereof.

[0042] In a fifth aspect, an embodiment of the present application provides a computer program, which, when executed on a computer, enables the computer to execute the above-mentioned first aspect and any optional method thereof.

[0043] In a sixth aspect, the present application provides a chip system comprising a processor configured to support the execution of a data processing device to implement the functions described in the aforementioned aspects, such as transmitting or processing the data or information described in the aforementioned methods. In one possible design, the chip system further comprises a memory configured to store program instructions and data necessary for executing the device or training the device. The chip system may consist of a single chip or may include a chip and other discrete components. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] FIG1A is a schematic diagram of a structure of an artificial intelligence main framework;

[0045] 1B and 1C are schematic diagrams of the application system framework of the present invention;

[0046] FIG1D is a schematic diagram of an optional hardware structure of a terminal;

[0047] FIG2 is a schematic diagram of the structure of a server;

[0048] FIG3 is a schematic diagram of a system architecture of the present application;

[0049] Figure 4 shows a process of cloud services;

[0050] FIG5 is a flowchart of a data processing method provided in an embodiment of the present application;

[0051] FIG6 is a schematic diagram of a network structure of the present application;

[0052] FIG7 is a flowchart of a data processing method provided in an embodiment of the present application;

[0053] FIG8 is a schematic diagram of a fusion method of the present application;

[0054] FIG9A is a schematic diagram of a pre-training method of the present application;

[0055] FIG9B is a schematic diagram showing a beneficial effect of the present application;

[0056] FIG10 is a schematic structural diagram of a data processing device provided in an embodiment of the present application;

[0057] FIG11 is a schematic diagram of the structure of an execution device provided in an embodiment of the present application;

[0058] FIG12 is a schematic diagram of a structure of a training device provided in an embodiment of the present application;

[0059] FIG13 is a schematic diagram of the structure of a chip provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] The following describes the embodiments of the present invention in conjunction with the accompanying drawings. The terms used in the embodiments of the present invention are only used to explain the specific embodiments of the present invention, and are not intended to limit the present invention.

[0061] The embodiments of the present application are described below in conjunction with the accompanying drawings. Those skilled in the art will appreciate that, with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0062] The terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, and this is merely a way of distinguishing the objects of the same attributes when describing them in the embodiments of the present application. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, so that the process, method, system, product or equipment comprising a series of units need not be limited to those units, but may include other units that are not clearly listed or inherent to these processes, methods, products or equipment.

[0063] As used herein, the terms "substantially," "about," and similar terms are used as terms of approximation, not as terms of degree, and are intended to take into account the inherent variations in measurements or calculations that one of ordinary skill in the art would recognize. Furthermore, the use of "may" when describing embodiments of the present invention refers to "one or more possible embodiments." As used herein, the terms "use," "using," and "used" may be considered synonymous with the terms "utilize," "utilizing," and "utilized," respectively. Additionally, the term "exemplary" is intended to refer to an example or illustration.

[0064] First, let's describe the overall workflow of an AI system. See Figure 1A, which shows a schematic diagram of the main AI framework. This AI framework will be explained from two perspectives: the "intelligent information chain" (horizontal axis) and the "IT value chain" (vertical axis). The "intelligent information chain" reflects the entire process from data acquisition to processing. For example, it could be the general process of intelligent information perception, intelligent information representation and formation, intelligent reasoning, intelligent decision-making, and intelligent execution and output. Throughout this process, data undergoes a condensed journey from "data-information-knowledge-wisdom." The "IT value chain," spanning the underlying infrastructure of human intelligence, information (provided and processed by technology), and the system's industrial ecosystem, reflects the value that AI brings to the information technology industry.

[0065] (1) Infrastructure

[0066] Infrastructure provides computing power for AI systems, enabling communication with the outside world and supporting this through a foundational platform. External communication occurs through sensors; computing power is provided by intelligent chips (CPUs, NPUs, GPUs, ASICs, FPGAs, and other hardware accelerators). The foundational platform includes a distributed computing framework and network-related platform guarantees and support, including cloud storage and computing, and interconnected networks. For example, sensors communicate with the outside world to acquire data, which is then fed into the intelligent chips within the distributed computing system provided by the foundational platform for computation.

[0067] (2) Data

[0068] Data above the infrastructure layer represents data sources for AI. This data includes graphics, images, voice, and text, as well as IoT data from traditional devices. This includes business data from existing systems and sensor data such as force, displacement, liquid level, temperature, and humidity.

[0069] (3) Data processing

[0070] Data processing generally includes data training, machine learning, deep learning, search, reasoning, decision-making, etc.

[0071] Among them, machine learning and deep learning can symbolize and formalize data for intelligent information modeling, extraction, preprocessing, and training.

[0072] Reasoning refers to the process of simulating human intelligent reasoning in computers or intelligent systems, using formalized information to perform machine thinking and solve problems based on reasoning control strategies. Typical functions are search and matching.

[0073] Decision-making refers to the process of making decisions after intelligent information is reasoned, and usually provides functions such as classification, sorting, and prediction.

[0074] (4) General ability

[0075] After the data has undergone the data processing mentioned above, some general capabilities can be further formed based on the results of the data processing, such as algorithms or a general system, for example, translation, text analysis, computer vision processing, speech recognition, image recognition, etc.

[0076] (5) Smart products and industry applications

[0077] Smart products and industry applications refer to the products and applications of artificial intelligence systems in various fields. They are the encapsulation of the overall artificial intelligence solution, which productizes intelligent information decision-making and realizes practical application. Its application areas mainly include: smart terminals, smart transportation, smart medical care, autonomous driving, smart cities, etc.

[0078] This application can be applied to the field of natural language processing in the field of artificial intelligence. Taking natural language processing as an example, the following will introduce multiple application scenarios that have been implemented in products.

[0079] First, we will introduce the application scenarios of this application. This application can be applied to, but is not limited to, applications with video understanding functions (hereinafter referred to as video understanding applications) or cloud services provided by cloud servers. The following are introduced separately:

[0080] 1. Video Understanding Applications

[0081] The product form of the embodiment of the present application can be a video understanding application. The video understanding application can be run on a terminal device or a cloud-side server.

[0082] In a possible implementation, a video understanding application can implement video-related processing tasks and obtain processing results.

[0083] For example, a video understanding application may implement at least video understanding tasks including video classification tasks, video search tasks, video recommendation tasks, video positioning tasks, and advertisement matching tasks, but is not limited thereto.

[0084] In one possible implementation, the user can open a video understanding application installed on the terminal device and input a video (the video may be triggered by an instruction, not necessarily actively input by the user). The video understanding application can process the video using the method provided in the embodiment of the present application and present the processing results to the user (the presentation method can be but is not limited to display, saving, uploading to the cloud side, etc.).

[0085] In one possible implementation, a user can open a video understanding application installed on a terminal device and input a video. The video understanding application can send the video to a server on the cloud side. The server on the cloud side processes the video using the method provided in an embodiment of the present application and transmits the processing result back to the terminal device. The terminal device can present the processing result to the user (the presentation method can be but is not limited to display, saving, uploading to the cloud side, etc.).

[0086] Next, the video understanding application in the embodiment of this application is introduced from the functional architecture and the product architecture that implements the function.

[0087] Referring to FIG. 1B , FIG. 1B is a schematic diagram of the functional architecture of a video understanding application program according to an embodiment of the present application:

[0088] In one possible implementation, as shown in FIG1B , a video understanding application 102 may receive input parameters 101 (e.g., including an image) and generate a processing result 103. The video understanding application 102 may be executed on, for example, at least one computer system and include computer code that, when executed by one or more computers, causes the computers to execute the method provided by the embodiments of the present application.

[0089] Referring to FIG. 1C , FIG. 1C is a schematic diagram of the physical architecture for running a video understanding application in an embodiment of the present application:

[0090] Referring to FIG1C , FIG1C shows a schematic diagram of a system architecture. The system may include a terminal 100 and a server 200. The server 200 may include one or more servers (FIG1C illustrates one server as an example), and the server 200 may provide video understanding functionality for one or more terminals.

[0091] Among them, the terminal 100 can be installed with a video understanding application, or a web page related to the video understanding function can be opened. The above application and web page can provide an interface. The terminal 100 can receive the relevant parameters entered by the user on the video understanding function interface and send the above parameters to the server 200. The server 200 can obtain the processing results based on the received parameters and return the processing results to the terminal 100.

[0092] It should be understood that in some optional implementations, the terminal 100 can also complete the action of obtaining the processing result based on the received parameters by itself without the need for the cooperation of the server, and the embodiments of the present application are not limited to this.

[0093] Next, the product form of the terminal 100 in FIG1C is described;

[0094] The terminal 100 in the embodiment of the present application can be a mobile phone, a tablet computer, a wearable device, an in-vehicle device, an augmented reality (AR) / virtual reality (VR) device, a laptop computer, an ultra-mobile personal computer (UMPC), a netbook, a personal digital assistant (PDA), etc., and the embodiment of the present application does not impose any restrictions on this.

[0095] FIG1D shows a schematic diagram of an optional hardware structure of the terminal 100 .

[0096] 1D , the terminal 100 may include components such as a radio frequency unit 110, a memory 120, an input unit 130, a display unit 140, a camera 150 (optional), an audio circuit 160 (optional), a speaker 161 (optional), a microphone 162 (optional), a processor 170, an external interface 180, and a power supply 190. Those skilled in the art will appreciate that FIG1D is merely an example of a terminal or multi-function device and does not limit the terminal or multi-function device. The terminal or multi-function device may include more or fewer components than shown, or may combine certain components or have different components.

[0097] The input unit 130 can be used to receive input digital or character information and generate key signal input related to user settings and function control of the portable multifunction device. Specifically, the input unit 130 may include a touch screen 131 (optional) and / or other input devices 132. The touch screen 131 can detect user touch operations on or near it (for example, operations performed on or near the touch screen using a finger, joint, stylus, or any other suitable object) and drive corresponding connected devices according to pre-set programs. The touch screen can detect user touch actions on the touch screen, convert the touch actions into touch signals and transmit them to the processor 170. It can also receive and execute commands sent by the processor 170; the touch signals include at least touch point coordinate information. The touch screen 131 provides an input interface and an output interface between the terminal 100 and the user. Touch screens can be implemented using various types, including resistive, capacitive, infrared, and surface acoustic wave. In addition to the touch screen 131, the input unit 130 may also include other input devices. Specifically, the other input devices 132 may include, but are not limited to, one or more of a physical keyboard, function keys (such as a volume control button 132 , a switch button 133 , etc.), a trackball, a mouse, a joystick, and the like.

[0098] The input device 132 can receive input video.

[0099] The display unit 140 may be used to display information input by the user or provided to the user, various menus of the terminal 100, interactive interfaces, file display, and / or playback of any multimedia file. In an embodiment of the present application, the display unit 140 may be used to display the interface of a video understanding application, processing results, etc.

[0100] Memory 120 can be used to store instructions and data. It primarily includes an instruction storage area and a data storage area. The data storage area can store various data, such as multimedia files and text. The instruction storage area can store software units such as the operating system, applications, and instructions required for at least one function, or subsets or extensions thereof. It may also include non-volatile random access memory (RAM). It provides processor 170 with management functions for the hardware, software, and data resources within the computing and processing device, supporting control software and applications. It is also used to store multimedia files and running programs and applications.

[0101] The processor 170 is the control center of the terminal 100. It connects all components of the terminal 100 using various interfaces and circuits. By executing instructions stored in the memory 120 and accessing data stored therein, it executes various functions of the terminal 100 and processes data, thereby providing overall control of the terminal device. Optionally, the processor 170 may include one or more processing units. Preferably, the processor 170 may integrate an application processor and a modem processor, with the application processor primarily processing the operating system, user interface, and application programs, while the modem processor primarily handles wireless communications. It is understood that the modem processor may not be integrated into the processor 170. In some embodiments, the processor and memory may be implemented on a single chip; in other embodiments, they may be implemented on separate chips. The processor 170 may also generate corresponding operational control signals and send them to the corresponding components of the computing and processing device. It may also read and process data in the software, particularly the data and programs in the memory 120, to enable the various functional modules therein to perform their corresponding functions, thereby controlling the corresponding components to operate as instructed.

[0102] Among them, the memory 120 can be used to store software codes related to the data processing method, the processor 170 can execute the steps of the chip's data processing method, and can also schedule other units (such as the above-mentioned input unit 130 and display unit 140) to achieve corresponding functions.

[0103] The RF unit 110 (optional) can be used to send and receive information or receive and send signals during a call. For example, after receiving downlink information from the base station, it is passed to the processor 170 for processing; in addition, it sends the designed uplink data to the base station. Generally, the RF circuit includes but is not limited to an antenna, at least one amplifier, a transceiver, a coupler, a low noise amplifier (LNA), a duplexer, etc. In addition, the RF unit 110 can also communicate with network devices and other devices via wireless communication. This wireless communication can use any communication standard or protocol, including but not limited to Global System of Mobile communication (GSM), General Packet Radio Service (GPRS), Code Division Multiple Access (CDMA), Wideband Code Division Multiple Access (WCDMA), Long Term Evolution (LTE), email, Short Messaging Service (SMS), etc.

[0104] In this embodiment of the present application, the RF unit 110 can send the video to the server 200 and receive the processing result sent by the server 200.

[0105] It should be understood that the radio frequency unit 110 is optional and can be replaced by other communication interfaces, such as a network port.

[0106] The terminal 100 also includes a power supply 190 (such as a battery) for supplying power to various components. Preferably, the power supply can be logically connected to the processor 170 through a power management system, thereby implementing functions such as charging, discharging, and power consumption management through the power management system.

[0107] The terminal 100 further includes an external interface 180 , which may be a standard Micro USB interface or a multi-pin connector, and may be used to connect the terminal 100 to other devices for communication, or to connect a charger to charge the terminal 100 .

[0108] Although not shown, the terminal 100 may also include a flash, a wireless fidelity (WiFi) module, a Bluetooth module, sensors with different functions, etc., which are not described in detail here. Some or all of the methods described below may be applied to the terminal 100 shown in FIG1D .

[0109] Next, the product form of the server 200 in FIG1C is described;

[0110] FIG2 provides a schematic diagram of the structure of a server 200. As shown in FIG2, the server 200 includes a bus 201, a processor 202, a communication interface 203, and a memory 204. The processor 202, the memory 204, and the communication interface 203 communicate with each other via the bus 201.

[0111] Bus 201 may be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus. Buses can be categorized as address buses, data buses, and control buses. For ease of illustration, FIG2 shows only one thick line, but this does not imply that there is only one bus or only one type of bus.

[0112] The processor 202 may be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP).

[0113] The memory 204 may include volatile memory, such as random access memory (RAM). The memory 204 may also include non-volatile memory, such as read-only memory (ROM), flash memory, hard drive (HDD), or solid state drive (SSD).

[0114] The memory 204 may be used to store software codes related to the data processing method, and the processor 202 may execute the steps of the data processing method of the chip, and may also schedule other units to implement corresponding functions.

[0115] It should be understood that the above-mentioned terminal 100 and server 200 can be centralized or distributed devices, and the processors in the above-mentioned terminal 100 and server 200 (such as processor 170 and processor 202) can be hardware circuits (such as application specific integrated circuit (ASIC), field-programmable gate array (FPGA), general-purpose processor, digital signal processor (DSP), microprocessor or microcontroller, etc.), or a combination of these hardware circuits. For example, the processor can be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0116] It should be understood that the steps related to the model reasoning process in the embodiments of this application involve AI-related operations. When performing AI operations, the instruction execution architecture of the terminal device and server is not limited to the processor-memory architecture described above. The system architecture provided in the embodiments of this application is described in detail below with reference to Figure 3.

[0117] FIG3 is a schematic diagram of the system architecture provided by an embodiment of the present application. As shown in FIG3 , the system architecture 500 includes an execution device 510 , a training device 520 , a database 530 , a client device 540 , a data storage system 550 , and a data acquisition system 560 .

[0118] The execution device 510 includes a calculation module 511, an I / O interface 512, a pre-processing module 513, and a post-processing module 514. The calculation module 511 may include the target model / rule 501, and the pre-processing module 513 and the post-processing module 514 are optional.

[0119] The execution device 510 may be a terminal device or a server that runs the aforementioned video comprehension application.

[0120] The data acquisition device 560 is used to collect training samples. The training samples can be videos, etc. After collecting the training samples, the data acquisition device 560 stores these training samples in the database 530.

[0121] The training device 520 can train the neural network to be trained (such as the model in the embodiment of the present application (such as an image encoder, a text encoder, etc.)) based on the training samples maintained in the database 530 to obtain the target model / rule 501.

[0122] It should be understood that the training device 520 can perform a pre-training process on the neural network to be trained based on the training samples maintained in the database 530, or fine-tune the model based on the pre-training.

[0123] It should be noted that, in actual applications, the training samples maintained in the database 530 may not all be collected by the data acquisition device 560, but may also be received from other devices. It should also be noted that the training device 520 may not train the target model / rule 501 entirely based on the training samples maintained in the database 530, but may also obtain training samples from the cloud or other places for model training. The above description should not be used as a limitation on the embodiments of the present application.

[0124] The target model / rule 501 obtained through training with the training device 520 can be applied to different systems or devices, such as the execution device 510 shown in FIG3 . The execution device 510 can be a terminal, such as a mobile phone terminal, a tablet computer, a laptop computer, an augmented reality (AR) / virtual reality (VR) device, an in-vehicle terminal, etc., or a server, etc.

[0125] Specifically, the training device 520 may transfer the trained model to the execution device 510 .

[0126] In Figure 3, the execution device 510 is configured with an input / output (I / O) interface 512 for data interaction with external devices. The user can input data (such as video in the embodiment of the present application) to the I / O interface 512 through the client device 540.

[0127] Preprocessing module 513 and preprocessing module 514 are used to preprocess the input data received by I / O interface 512. It should be understood that preprocessing module 513 and preprocessing module 514 may be absent or only one preprocessing module may be present. If preprocessing module 513 and preprocessing module 514 are absent, computing module 511 may be used directly to process the input data.

[0128] When the execution device 510 preprocesses the input data, or when the computing module 511 of the execution device 510 performs calculations and other related processing, the execution device 510 can call the data, code, etc. in the data storage system 550 for corresponding processing, and can also store the data, instructions, etc. obtained from the corresponding processing in the data storage system 550.

[0129] Finally, the I / O interface 512 provides the processed results to the client device 540 and thus to the user.

[0130] In the scenario shown in FIG3 , the user can manually input data, and this "manual input data" can be operated through the interface provided by I / O interface 512. In another scenario, client device 540 can automatically send input data to I / O interface 512. If user authorization is required for client device 540 to automatically send input data, the user can set the corresponding permissions in client device 540. The user can view the results output by execution device 510 on client device 540, and the specific presentation form can be a display, sound, action, or other specific method. Client device 540 can also serve as a data acquisition terminal, collecting input data input into I / O interface 512 and output results output from I / O interface 512 as new sample data, and storing them in database 530. Of course, collection can also be performed without client device 540, and instead the I / O interface 512 directly stores the input data input into I / O interface 512 and output results output from I / O interface 512 as new sample data in database 530.

[0131] It is worth noting that FIG3 is merely a schematic diagram of a system architecture provided by an embodiment of the present application, and the positional relationships between the devices, components, modules, etc. shown in the figure do not constitute any limitation. For example, in FIG3 , the data storage system 550 is an external memory relative to the execution device 510. In other cases, the data storage system 550 can also be placed in the execution device 510. It should be understood that the execution device 510 can be deployed in the client device 540.

[0132] From the inference side of the model:

[0133] In the embodiment of the present application, the computing module 511 of the above-mentioned execution device 510 can obtain the code stored in the data storage system 550 to implement the steps related to the model reasoning process in the embodiment of the present application.

[0134] In an embodiment of the present application, the computing module 511 of the execution device 510 may include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 may be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0135] Specifically, the computing module 511 of the execution device 510 can be a hardware system with an execution instruction function, and the steps related to the model reasoning process provided in the embodiment of the present application can be software codes stored in the memory. The computing module 511 of the execution device 510 can obtain the software code from the memory and execute the obtained software code to implement the steps related to the model reasoning process provided in the embodiment of the present application.

[0136] It should be understood that the computing module 511 of the execution device 510 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some of the steps related to the model reasoning process provided in the embodiment of the present application can also be implemented by the hardware system that does not have the function of executing instructions in the computing module 511 of the execution device 510, which is not limited here.

[0137] From the training side of the model:

[0138] In an embodiment of the present application, the above-mentioned training device 520 can obtain the code stored in the memory (not shown in Figure 3, which can be integrated into the training device 520 or deployed separately from the training device 520) to implement the steps related to model training in the embodiment of the present application.

[0139] In an embodiment of the present application, the training device 520 may include a hardware circuit (such as an application specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a general-purpose processor, a digital signal processor (DSP), a microprocessor or a microcontroller, etc.), or a combination of these hardware circuits. For example, the training device 520 may be a hardware system with an instruction execution function, such as a CPU, DSP, etc., or a hardware system without an instruction execution function, such as an ASIC, FPGA, etc., or a combination of the above-mentioned hardware systems without an instruction execution function and hardware systems with an instruction execution function.

[0140] It should be understood that the training device 520 can be a combination of a hardware system that does not have the function of executing instructions and a hardware system that has the function of executing instructions. Some of the steps related to model training provided in the embodiments of the present application can also be implemented by the hardware system in the training device 520 that does not have the function of executing instructions, which is not limited here.

[0141] 2. Video understanding cloud services provided by the server:

[0142] In a possible implementation, the server may provide a video understanding service to the terminal through an application programming interface (API).

[0143] Among them, the terminal device can send relevant parameters (such as images, text and other data) to the server through the API provided by the cloud. The server can obtain processing results based on the received parameters, etc., and return the processing results to the terminal.

[0144] The description of the terminal and the server can be the same as that of the above embodiments, and will not be repeated here.

[0145] FIG4 shows a process of using a video understanding function cloud service provided by a cloud platform.

[0146] 1. Activate and purchase content review services.

[0147] 2. Users can download the software development kit (SDK) corresponding to the content review service. Usually, the cloud platform provides multiple development versions of the SDK for users to choose according to the requirements of the development environment, such as JAVA version SDK, Python version SDK, PHP version SDK, Android version SDK, etc.

[0148] 3. After downloading the corresponding version of the SDK locally as needed, the user imports the SDK project into the local development environment, configures and debugs it in the local development environment. The local development environment can also be used to develop other functions, forming an application that integrates video understanding functional capabilities.

[0149] 4. When a video understanding application is used and needs to perform video understanding, it can trigger an API call for the video understanding function. When the application triggers the video understanding function, it initiates an API request to the running instance of the video understanding service in the cloud environment. The API request includes an image, and the running instance in the cloud environment processes the image and obtains the processing result.

[0150] 5. The cloud environment returns the processing results to the application, thus completing a video understanding function call.

[0151] Since the embodiments of the present application involve the application of a large number of neural networks, in order to facilitate understanding, the relevant terms and related concepts such as neural networks involved in the embodiments of the present application are first introduced below.

[0152] (1) Neural Network

[0153] A neural network can be composed of neural units. A neural unit can refer to an operation unit that takes xs (i.e., input data) and intercept 1 as input. The output of the operation unit can be:

[0154] Where s = 1, 2, ... n, n is a natural number greater than 1, Ws is the weight of xs, and b is the bias of the neural unit. f is the activation function of the neural unit, which is used to introduce nonlinear characteristics into the neural network to convert the input signal of the neural unit into the output signal. The output signal of the activation function can be used as the input of the next convolutional layer, and the activation function can be a sigmoid function. A neural network is a network formed by connecting multiple single neural units mentioned above, that is, the output of one neural unit can be the input of another neural unit. The input of each neural unit can be connected to the local receptive field of the previous layer to extract the features of the local receptive field. The local receptive field can be an area composed of several neural units.

[0155] (2) Transformer layer

[0156] The neural network includes an embedding layer and at least one transformer layer, and the at least one transformer layer can be N transformer layers (N is an integer greater than 0), wherein each transformer layer includes an attention layer, an add&norm layer, a feed forward layer, and an add&norm layer that are adjacent in sequence. In the embedding layer, the current input is embedded to obtain multiple embedding vectors; in the attention layer, P input vectors are obtained from the previous layer of the first transformer layer, and with any first input vector among the P input vectors as the center, based on the correlation between each input vector within a preset attention window and the first input vector, the intermediate vector corresponding to the first input vector is obtained, thereby determining the P intermediate vectors corresponding to the P input vectors; in the pooling layer, the P intermediate vectors are merged into Q output vectors, wherein the multiple output vectors obtained by the last transformer layer in the transformer layer are used as feature representations of the current input.

[0157] (3) Attention mechanism

[0158] The attention mechanism mimics the internal process of biological observation behavior, namely, a mechanism that aligns internal experience and external sensations to increase the observation precision of certain areas. It can quickly filter out high-value information from a large amount of information using limited attention resources. The attention mechanism can quickly extract important features from sparse data and is therefore widely used in natural language processing tasks, especially machine translation. The self-attention mechanism is an improvement on the attention mechanism, which reduces dependence on external information and is better at capturing the internal correlation of data or features. The essential idea of ​​the attention mechanism can be rewritten as the following formula:

[0159] Here, Lx = ||Source|| represents the length of the Source. This formula implies that the elements in the Source are imagined to consist of a series of data pairs. Given a Query element in the target, the similarity or correlation between the Query and each Key is calculated to obtain the weight coefficient for each Key's corresponding Value. The weighted sum of the Values ​​is then taken to obtain the final Attention value. Essentially, the Attention mechanism performs a weighted sum of the Values ​​of the Source elements, with the Query and Key used to calculate the weight coefficient for the corresponding Value. Conceptually, Attention can be understood as selectively filtering out a small amount of important information from a large amount of information and focusing on this important information, while ignoring the majority of less important information. This focusing process is reflected in the calculation of the weight coefficients: the larger the weight, the more focus is placed on the corresponding Value. In other words, the weight represents the importance of the information, while the Value represents the corresponding information. The self-attention mechanism can be understood as internal attention. The attention mechanism occurs between the Query element of the Target and all elements of the Source. The self-attention mechanism refers to the attention mechanism that occurs between the internal elements of the Source or the internal elements of the Target. It can also be understood as the attention calculation mechanism in the special case of Target = Source. The specific calculation process is the same, only the calculation object has changed.

[0160] (4) Natural language processing (NLP)

[0161] Natural language refers to human language, and natural language processing (NLP) is the processing of human language. Natural language processing is the process of systematically analyzing, understanding, and extracting information from text data in an intelligent and efficient manner. By using NLP and its components, we can manage very large amounts of text data, perform a large number of automated tasks, and solve a wide variety of problems, such as automatic summarization, machine translation (MT), named entity recognition (NER), relation extraction (RE), information extraction (IE), sentiment analysis, speech recognition, question answering, and topic segmentation.

[0162] (5) Backpropagation algorithm

[0163] Convolutional neural networks can use the back propagation (BP) algorithm to correct the size of the parameters in the initial super-resolution model during training, reducing the reconstruction error loss of the super-resolution model. Specifically, the forward propagation of the input signal to the output generates an error loss. This error loss information is then backpropagated to update the parameters of the initial super-resolution model, thereby converging the error loss. The BP algorithm is a backward propagation movement dominated by the error loss, aiming to obtain the optimal super-resolution model parameters, such as the weight matrix.

[0164] (6) Loss function

[0165] During the training of a deep neural network, because we want the output of the deep neural network to be as close as possible to the desired predicted value, we can compare the current network's predicted value with the desired target value and then update the weight vector of each layer of the neural network based on the difference between the two. (Of course, there is usually an initialization process before the first update, which is to pre-configure the parameters for each layer in the deep neural network.) For example, if the network's predicted value is too high, the weight vector is adjusted to make it predict a lower value. This adjustment is continued until the deep neural network can predict the desired target value or a value very close to the desired target value. Therefore, it is necessary to predefine "how to compare the difference between the predicted value and the target value." This is the loss function (or objective function), which is an important equation used to measure the difference between the predicted value and the target value. For example, the loss function output value (loss) indicates a greater difference, so training a deep neural network becomes a process of minimizing this loss as much as possible.

[0166] (7) Transformer: A network that can process sequence data in parallel based on a multi-head attention mechanism, including residual connections, layer normalization, and full connections. It was originally used to encode text features.

[0167] (8) Video Transformer: A Transformer network modified for the video domain, which models temporal and spatial information through spatiotemporal attention and can be used to encode video features.

[0168] (9) Token: The smallest unit in the input sequence of the Video Transformer model. Like the Transformer, the Video Transformer accepts a sequence of Tokens as input. The video input is 3-dimensional, including the number of frames T, the width W of each frame, and the height H. In order to encode the video, the model generally divides the video into several smallest units (i.e., Tokens), and then inputs them as a sequence. The Token here can be 3-dimensional (i.e., a small cube, obtained by directly dividing the 3-dimensional video) or 2-dimensional (i.e., a small square patch, obtained by dividing each frame of the picture). The Token in this technology corresponds to a 2-dimensional small square patch, i.e., a Patch.

[0169] (10) Patch: A 2D patch is a small square obtained by splitting each frame of an image in the Video Transformer. A picture (e.g., 224x224, where 224 is the side length of the picture) is cut into several small squares of the same size (e.g., 16x16, where 16 is the side length of the small square), which is called a patch.

[0170] The Video Transformer model applies the original Transformer model to the video domain, encoding video features by modeling temporal and spatial information. This model can then be used for downstream video understanding tasks such as video-to-text retrieval, video description generation, and video question-answering. The Video Transformer model effectively adapts to large-scale pre-training and has become the foundational model architecture for video understanding.

[0171] When inputting long videos into the Video Transformer model, they are broken into a large number of visual tokens. This results in excessively long input token sequences and high redundancy. This compromises video encoding efficiency and hinders the model's ability to learn key semantic information. For example, for a 96-frame video with a resolution of 224x224, the commonly used Video Transformer model will chop each frame into 16x16 patches. This will result in as many as (224 / 16)x(224 / 16)x96 = 19K visual tokens, placing a significant computational burden on subsequent feature encoding.

[0172] Therefore, there is an urgent need for a video encoding method with low computing power overhead.

[0173] In order to solve the above problems, the present invention provides a data processing method. The data processing method of the present invention is described in detail below with reference to the accompanying drawings.

[0174] Refer to Figure 5, which is a flow chart of a data processing method provided in an embodiment of the present application. As shown in Figure 5, a data processing method provided in an embodiment of the present application may include steps 501 to 505, and these steps are described in detail below.

[0175] 501. Acquire multiple video frames;

[0176] In one possible implementation, the video including multiple video frames can be pre-stored locally in the terminal, or obtained by the terminal from the outside world (such as the Internet), or collected by the terminal in real time, for example, through the terminal's camera.

[0177] Videos can be long. Short videos are generally defined as those less than 30 seconds long, while long videos are defined as those longer than 30 seconds. The average length of long videos in many academic datasets is around 150 seconds, over five times that of short videos. Given a fixed frame rate, long videos naturally contain more input frames than short videos.

[0178] 502. Process the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse the feature representations of the M first video frames into the feature representations of the N second video frames to obtain N feature representations.

[0179] In the current Video Transformer model, long videos are divided into a large number of visual tokens (the number of visual tokens is the number of frames * the number of patches per frame), which results in the input token sequence being too long and also having a large redundancy. This situation has an adverse effect on the efficiency of video coding and brings a huge computational burden to the subsequent feature coding process. At the same time, due to the existence of redundancy, the input sequence may contain a large amount of similar or repeated visual information, which further increases the redundancy of the calculation. These problems together lead to a decrease in the efficiency of video coding, making the subsequent feature coding process face a huge computational burden and complexity. Therefore, the embodiments of the present application aim to solve these technical problems triggered when long videos are input, so as to improve the efficiency of video coding and reduce the computational burden of feature coding.

[0180] The encoder may include multiple network layers, each network layer may receive the feature representation output by the adjacent previous network layer, and perform feature extraction on the feature representation output by the adjacent previous network layer.

[0181] In one possible implementation, an encoder includes a first network layer, which may include an inter-frame compression module. Specifically, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames with feature representations of the N second video frames to obtain N feature representations. That is, during encoding, the inter-frame compression module may fuse feature representations of some video frames among the multiple video frames with feature representations of another portion of video frames, thereby reducing the number of feature representations.

[0182] Among them, the feature representation can be expressed as a token, that is, the inter-frame compression module is used to convert the M tokens corresponding to the M first video frames (each first video frame corresponds to a token) to N tokens corresponding to the N second video frames to obtain N tokens.

[0183] For example, referring to Figure 6, the video encoder block in Figure 6 can be the first network layer, the temporal aggregation in the video encoder block is an inter-frame compression module, and the input of the temporal aggregation is a feature of size T*L*D, where T is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since the temporal aggregation fuses the feature representations of Rt video frames in T video frames into the feature representation of (T-Rt) video frames, a feature representation of size (T-Rt)*L*D can be obtained.

[0184] Next, we will introduce how to determine the video frame that needs to be fused into the feature representation of other video frames:

[0185] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0186] Among them, the least important M first video frames among multiple video frames can be selected and divided into Set A, and the remaining N second video frames can be divided into Set B. The feature representations of the least important M first video frames can be fused into the feature representations of the N second video frames, which can reduce the information loss of the fusion.

[0187] For the selection of objects that need to be fused (for example, M first video frames), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0188] In a possible implementation, it can be considered that a video frame with a lower correlation with other video frames is a video frame with lower importance.

[0189] Optionally, the importance of a video frame is calculated as follows:

[0190] Among them, A ji Is from token x j (that is, the feature representation of the j-th video frame) to token x i The attention score (i.e., the feature representation of the i-th video frame) can be used to indicate the relevance between video frames. Q and K represent the query and key in the self-attention mechanism.

[0191] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the plurality of video frames.

[0192] Adjacent video frames often have higher similarities and should be divided into different sets to encourage their fusion. Therefore, adjacent first and second video frames can be divided into different sets. For example, odd-numbered first video frames can be divided into Set A, and even-numbered second video frames can be divided into Set B. The feature representation of the first video frame in Set A is fused with the feature representation of the second video frame in Set B.

[0193] This application proposes a selection algorithm based on visual token geometry. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more precise and efficient, ensuring the quality and accuracy of the aggregation results.

[0194] In a possible implementation, each of the M first video frames may be fused with a feature representation of the most similar second video frame among the N second video frames.

[0195] The inter-frame compression module can aggregate the feature representations of similar video frames, thereby reducing the number of feature representations that the model needs to process. By aggregating similar video frames, the embodiments of the present application ensure that important timing information in the video is fully preserved. Therefore, the method of the embodiments of the present application can improve computational efficiency while still ensuring the quality and effectiveness of video encoding.

[0196] In the time dimension, the embodiment of the present application can integrate multiple similar video frames into one frame for processing. To this end, a pseudo-token (proxy token) called a frame token can be defined to represent a frame. Optionally, the frame token can be obtained by performing mean pooling on the features of all patches in the frame. The similarity between the frame tokens (such as cosine similarity) is calculated to determine which frames to aggregate. When two frames are aggregated, their corresponding patches will be aggregated one by one, that is, the L patches in the first frame and L patches in the second frame Will be aggregated separately to obtain L aggregated patches Among them, optional, It is through and The feature representation is obtained by average pooling.

[0197] As shown on the left side of Figure 7, the initial input video contains 96 frames, which are reduced by 8 frames at each layer through aggregation, reducing to 52 frames by the 6th layer and to 8 frames by the 12th layer.

[0198] Taking the example of representing the feature corresponding to each video frame as a token, given L tokens, the embodiment of the present application reduces R tokens through each aggregation. Therefore, the basic strategy of the aggregation algorithm is: first select R tokens, and then merge them into the remaining LR tokens based on similarity. The algorithm process may include:

[0199] Divide the tokens in the input sequence into two parts, record them as Set A and Set B. For each token in Set A, find the most similar token in Set B and connect them. The similarity is calculated as follows: for two tokens x i and x j , respectively get the features K of their attention Key i and K j , and then use cosine similarity to calculate norm(K i )norm(K j ). Retain the R edges with the highest similarity and aggregate the tokens at both ends of the edge. The aggregation method is to perform mean pooling on the features of the tokens at both ends. The remaining tokens in the two sets are pieced together to form a sequence as the output sequence.

[0200] Refer to Figure 8, which is a schematic diagram of a fusion process, which may include 8 tokens, each token may correspond to a video frame, and adjacent frames are divided into different sets (for example, in Figure 8, token1, token3, token5, and token7 are divided into setA, and token2, token4, token6, and token8 are divided into setB). Through similarity calculation, token1 and token2 are most similar, token3 and token2 are most similar, token5 and token6 are most similar, and token7 and token8 are most similar. Therefore, token1 and token3 can be fused to token2 to obtain token123, and token5 can be fused to token6 to obtain token56.

[0201] The above introduces the inter-frame fusion process. Next, the intra-frame fusion process will be introduced.

[0202] The encoder may include multiple network layers, each network layer may receive the feature representation output by the adjacent previous network layer, and perform feature extraction on the feature representation output by the adjacent previous network layer.

[0203] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks with feature representations of the Y second image blocks to obtain Y feature representations.

[0204] The feature representation can be expressed as a token, that is, the intra-frame compression module is used to convert the X tokens corresponding to the X first image blocks (each first image block corresponds to a token) to the Y tokens corresponding to the Y second image blocks to obtain Y tokens.

[0205] For example, referring to Figure 6, the video encoder block in Figure 6 can be the second network layer, the spatial aggregation in the video encoder block is an intra-frame compression module, and the input of the spatial aggregation is a feature of size (T-Rt)*L*D, where T-Rt is the number of video frames, L is the number of image blocks included in the video frame, and D is the dimension of the feature representation of each image block. Since spatial aggregation fuses the feature representation of Rs image blocks in each video frame into the feature representation of (L-Rs) video frames, a feature representation of size (T-Rt)*(L-Rs)*D can be obtained.

[0206] Next, we will introduce how to determine the image blocks that need to be fused into the feature representations of other image blocks:

[0207] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks.

[0208] Among them, the least important X first image blocks among multiple image blocks can be selected and divided into Set A, and the remaining Y second image blocks can be divided into Set B. The feature representations of the least important X first image blocks can be fused into the feature representations of the Y second image blocks, which can reduce the information loss of the fusion.

[0209] For the selection of objects that need to be fused (e.g., X first image blocks), the embodiment of the present application proposes a selection algorithm based on the importance of visual tokens. By evaluating and ranking the importance of each token, tokens with higher importance are selected as representative tokens.

[0210] In a possible implementation, it can be considered that an image block with a lower correlation with other image blocks is an image block with lower importance.

[0211] Optionally, the importance of an image block is calculated as follows:

[0212] Among them, A ji is from tokeY x j (that is, the feature representation of the j-th image block) to tokeY x i The attention score (i.e., the feature representation of the i-th image patch) indicates the relevance between image patches. Q and K represent the query and key in the self-attention mechanism.

[0213] In a possible implementation, the first image block and the second image block are interleaved with each other in the multiple image blocks.

[0214] Adjacent image blocks often have higher similarities and should be divided into different sets to encourage their fusion. Therefore, adjacent first image blocks and second image blocks can be divided into different sets. For example, odd-numbered first image blocks can be divided into Set A, and even-numbered second image blocks can be divided into Set B. The feature representation of the first image block in Set A is fused with the feature representation of the second image block in Set B.

[0215] This application proposes a selection algorithm based on visual token geometry. By considering the position and distribution of tokens in space, it selects tokens with a reasonable spatial distribution as representative tokens. The introduction of these selection algorithms makes the aggregation process more precise and efficient, ensuring the quality and accuracy of the aggregation results.

[0216] In a possible implementation, the feature representation of each first image block among the X first image blocks may be fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0217] In this embodiment, semantically similar patches within each frame can be aggregated into a single patch. As shown on the right side of Figure 7, the initial video contains 196 patches per frame. Aggregation reduces this number by 16 patches per layer, reducing it to 101 patches by the 6th layer and 11 patches by the 12th layer.

[0218] The intra-frame compression module automatically aggregates similar patches within each frame, merging them into a larger patch, further reducing the number of visual tokens. Aggregating similar patches within each frame also ensures that important visual features and details are not lost. Therefore, the method of the embodiment of the present application improves computational efficiency while still maintaining the quality and effectiveness of video encoding.

[0219] Next, a specific implementation diagram of the embodiment of the present application is described using FIG6 as an example:

[0220] 6 , the video encoder is a Video Transformer. In each layer of the video encoder, an embodiment of the present application introduces a temporal aggregation module (Temporal Aggregation) and a spatial aggregation module (Spatial Aggregation). The temporal aggregation module reduces the RT frame in each aggregation, and the spatial aggregation module reduces RS patches in each aggregation, where RT and RS are hyperparameters used to control the final acceleration ratio. In this way, the size of the video features is reduced layer by layer, reducing the computational overhead of subsequent layers. For example, for the Video Transformer in the figure, the input of its i-th layer is a video feature of size Ti*Li*D, where Ti is the number of frames, Li is the number of patches per frame, and D is the feature dimension of the token. After passing through the temporal aggregation module, the RT frame can be reduced by frame aggregation, so that the size of the video feature is reduced to (Ti-RT)*Li*D. After passing through the spatial aggregation module, RS patches can be reduced by patch aggregation within each frame, so that the size of the video feature is reduced to (Ti-RT)*(Li-RS)*D. After passing through the M layers of the Video Transformer, the number of visual tokens is reduced from T*L to (TM*RT)*(LM*RS). By setting appropriate hyperparameters RT and RS, the total number of visual tokens can be reduced by 75%, speeding up video encoding by 1.7 times.

[0221] During inference, the method provided by the embodiment of the present application can achieve quantitative aggregation and reduction layer by layer based on the number of frames of the input video and the number of patches per frame. Specifically, during the aggregation process of each layer, the number of visual tokens reduced by aggregation can be controlled according to the set hyperparameters. In this way, as the network advances layer by layer, the number of visual tokens in the input sequence will gradually decrease, thereby achieving aggregation and reduction operations during the video encoding process.

[0222] 503. Perform video-related tasks according to the encoding result to obtain a processing result.

[0223] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0224] Based on the spatiotemporal aggregation algorithm of visual tokens, refer to Figure 9A, which shows a video-language pre-training model, including a video encoder, a text encoder, a cross-modal encoder, and a text decoder. The three encoders and the decoder are all based on the Transformer architecture.

[0225] Next, the beneficial effects of the embodiments of the present application are described in conjunction with experiments:

[0226] The left side of Figure 9B shows the effect of reducing the number of frames on GFlops and Recall. It can be seen that reducing 5 frames per layer can reduce GFlops by 800 with almost no loss in performance.

[0227] Figure 9B (center) shows the effect of reducing the number of patches on GFlops and Recall. It can be seen that reducing 10 frames per layer can reduce GFlops by 800 with almost no performance loss.

[0228] The right side of Figure 9B shows the relationship between reducing the number of frames,patches and GFlops / Recall.

[0229] Table 1

[0230] As shown in Table 1, the embodiment of this application (TESTA) achieves optimal results in Paragraph-to-Video Retrieval. Task Description: Given a text query, find the top K semantically closest videos from a video database. The target datasets are QuerYD and CondenseMovie; the automatic evaluation metric is Recall@K.

[0231] As shown in Table 1, for 32-frame video input, TESTA achieves R@1 of 77.0 and 21.5, respectively, surpassing the SOTA by 7.3 and 3.1. Furthermore, TESTA's computational overhead (GFLOPs) is only 420, significantly less than Frozen and VINDLU. When using 96-frame video input, TESTA further improves R@1 to 83.4 and 24.9, demonstrating its excellent scalability.

[0232] Table 2

[0233] As shown in Table 2, the results on the target datasets, DiDeMo and ActivityNet Caption, are similar to those reported above. For 32-frame video input, TESTA achieved an R@1 of 56.6 on DiDeMo using only 5MB of pre-training data, surpassing methods using over 100MB of pre-training data. When using 96-frame video input, TESTA improved R@1 to 59.2 and 53.7, surpassing the SOTA by 2.7 and 2.6, respectively.

[0234] Table 3

[0235] As shown in Table 3, this embodiment achieved optimal results on Long-form VideoQA (Long Video Question Answering). Target dataset: ActivityNet-QA; Automatic evaluation metric: Accuracy. Conclusion: TESTA achieved an accuracy of 45.0%, 3.2% higher than the SOTA.

[0236] Table 4

[0237] As shown in Table 4, the bipartite graph matching-based aggregation algorithm outperforms the pruning algorithm. In addition, geometry-based aggregation achieves the best performance.

[0238] 10 , which is a schematic diagram of the structure of a data processing device provided in an embodiment of the present application. As shown in FIG10 , a data processing device provided in an embodiment of the present application, the device 1000 includes:

[0239] An acquisition module 1001 is configured to acquire multiple video frames;

[0240] For a detailed description of the acquisition module 1001 , reference may be made to the description of step 501 in the above embodiment, which will not be repeated here.

[0241] A processing module 1002 is configured to process the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames with feature representations of the N second video frames to obtain N feature representations;

[0242] According to the encoding result, video-related tasks are performed to obtain a processing result.

[0243] For a detailed description of the processing module 1002 , reference may be made to the description of steps 502 to 503 in the above embodiment, which will not be repeated here.

[0244] In a possible implementation, the video-related task is video retrieval, video question answering, or video description generation.

[0245] In a possible implementation, the processing module 1002 is specifically configured to:

[0246] The feature representation of each first video frame in the M first video frames is fused into the feature representation of the second video frame that is most similar to the N second video frames.

[0247] In a possible implementation, the M first video frames are M video frames having the lowest correlation with other video frames among the multiple video frames.

[0248] In a possible implementation, the first video frame and the second video frame are interlaced with each other in the plurality of video frames.

[0249] In a possible implementation, the fusion is average pooling.

[0250] In one possible implementation, the encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks with feature representations of the Y second image blocks to obtain Y feature representations.

[0251] In a possible implementation, the processing module 1002 is specifically configured to:

[0252] The feature representation of each first image block in the X first image blocks is fused into the feature representation of the second image block that is most similar to the Y second image blocks.

[0253] In a possible implementation, the X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

[0254] In a possible implementation, the first image block and the second image block are interlaced with each other in the third video frame.

[0255] In one possible implementation, the task network is used to implement at least one of the following tasks: a video retrieval task, a video classification task, a video positioning task, and a video generation task (such as video question answering and video title generation).

[0256] Next, an execution device provided in an embodiment of the present application is introduced. Please refer to Figure 11. Figure 11 is a structural diagram of an execution device provided in an embodiment of the present application. The execution device 1100 can be specifically manifested as a virtual reality VR device, a mobile phone, a tablet, a laptop computer, a smart wearable device, a monitoring data processing device or a server, etc., which is not limited here. Specifically, the execution device 1100 includes: a receiver 1101, a transmitter 1102, a processor 1103 and a memory 1104 (wherein the number of processors 1103 in the execution device 1100 can be one or more, and Figure 11 takes one processor as an example), wherein the processor 1103 may include an application processor 11031 and a communication processor 11032. In some embodiments of the present application, the receiver 1101, the transmitter 1102, the processor 1103 and the memory 1104 may be connected via a bus or other means.

[0257] The memory 1104 may include a read-only memory and a random access memory, and provides instructions and data to the processor 1103. A portion of the memory 1104 may also include non-volatile random access memory (NVRAM). The memory 1104 stores processor and operation instructions, executable modules, or data structures, or subsets or extended sets thereof. The operation instructions may include various operation instructions for implementing various operations.

[0258] Processor 1103 controls the operation of the execution device. In specific applications, the various components of the execution device are coupled together via a bus system. In addition to a data bus, the bus system may also include a power bus, a control bus, and a status signal bus. However, for clarity, all of these buses are referred to as a bus system in the figure.

[0259] The methods disclosed in the above embodiments of the present application can be applied to or implemented by processor 1103. Processor 1103 can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits or software instructions in processor 1103. The above processor 1103 can be a general-purpose processor, a digital signal processor (DSP), a microprocessor, or a microcontroller, and can further include an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The processor 1103 can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of the present application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in conjunction with the embodiments of the present application can be directly implemented as being executed by a hardware decoding processor, or can be executed by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium well-known in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, or registers. This storage medium is located in memory 1104. Processor 1103 reads information from memory 1104 and, in conjunction with its hardware, completes the steps involved in the model inference process in the above method.

[0260] Receiver 1101 can be used to receive input digital or character information and generate signal input related to executing device-related settings and function control. Transmitter 1102 can be used to output digital or character information through the first interface. Transmitter 1102 can also be used to send instructions to the disk pack through the first interface to modify data in the disk pack. Transmitter 1102 can also include a display device such as a display screen.

[0261] The present application also provides a training device. Please refer to FIG. 12 , which is a schematic diagram of the structure of a training device provided by an embodiment of the present application. Specifically, the training device 1200 is implemented by one or more servers. The training device 1200 may vary significantly due to different configurations or performance. It may include one or more central processing units (CPUs) 1212 (e.g., one or more processors), a memory 1232, and one or more storage media 1230 (e.g., one or more mass storage devices) storing application programs 1242 or data 1244. The memory 1232 and storage medium 1230 may be either ephemeral or persistent storage. The program stored in the storage medium 1230 may include one or more modules (not shown), each of which may include a series of instruction operations on the training device. Furthermore, the CPU 1212 may be configured to communicate with the storage medium 1230 to execute the series of instruction operations in the storage medium 1230 on the training device 1200.

[0262] The training device 1200 may also include one or more power supplies 1226, one or more wired or wireless network interfaces 1250, one or more input and output interfaces 1258; or, one or more operating systems 1241, such as Windows Server™, Mac OS X™, Unix™, Linux™, FreeBSD™, etc.

[0263] In the embodiment of the present application, the central processing unit 1212 is used to execute actions related to model training in the above embodiment.

[0264] An embodiment of the present application also provides a computer program product, which, when running on a computer, enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0265] A computer-readable storage medium is also provided in an embodiment of the present application, which stores a program for signal processing. When the computer-readable storage medium is run on a computer, it enables the computer to execute the steps executed by the aforementioned execution device, or enables the computer to execute the steps executed by the aforementioned training device.

[0266] The execution device, training device or terminal device provided in the embodiments of the present application can specifically be a chip, and the chip includes: a processing unit and a communication unit, the processing unit can be, for example, a processor, and the communication unit can be, for example, an input / output interface, a pin or a circuit, etc. The processing unit can execute the computer execution instructions stored in the storage unit, so that the chip in the execution device executes the data processing method described in the above embodiment, or so that the chip in the training device executes the data processing method described in the above embodiment. Optionally, the storage unit is a storage unit in the chip, such as a register, a cache, etc. The storage unit can also be a storage unit located outside the chip in the wireless access device, such as a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM), etc.

[0267] Specifically, see Figure 13 , which is a schematic diagram of the structure of a chip provided in an embodiment of the present application. The chip may be a neural network processor (NPU) 1300. NPU 1300 is mounted on a host CPU (host CPU) as a coprocessor, with tasks assigned by the host CPU. The core of the NPU is arithmetic circuit 1303, which is controlled by controller 1304 to extract matrix data from memory and perform multiplication operations.

[0268] In some implementations, the arithmetic circuit 1303 includes multiple processing units (PEs). In some implementations, the arithmetic circuit 1303 is a two-dimensional systolic array. The arithmetic circuit 1303 can also be a one-dimensional systolic array or other electronic circuitry capable of performing mathematical operations such as multiplication and addition. In some implementations, the arithmetic circuit 1303 is a general-purpose matrix processor.

[0269] For example, assume there are input matrix A, weight matrix B, and output matrix C. The computation circuit retrieves the corresponding data of matrix B from weight memory 1302 and caches it on each PE in the computation circuit. The computation circuit then retrieves the data of matrix A from input memory 1301 and performs a matrix operation on it with matrix B. The partial or final matrix result is stored in accumulator 1308.

[0270] Unified memory 1306 is used to store input and output data. Weight data is directly transferred to weight memory 1302 through the Direct Memory Access Controller (DMAC) 1305. Input data is also transferred to unified memory 1306 through the DMAC.

[0271] BIU stands for Bus Interface Unit 1310 , which is used for interaction between the AXI bus, DMAC, and instruction fetch buffer (IFB) 1309 .

[0272] The bus interface unit 1310 (BIU) is used for the instruction fetch memory 1309 to obtain instructions from the external memory, and is also used for the storage unit access controller 1305 to obtain the original data of the input matrix A or the weight matrix B from the external memory.

[0273] DMAC is mainly used to move input data in the external memory DDR to the unified memory 1306 or to move weight data to the weight memory 1302 or to move input data to the input memory 1301.

[0274] The vector calculation unit 1307 includes multiple operation processing units. When necessary, it further processes the output of the operation circuit 1303, such as vector multiplication, vector addition, exponential operation, logarithmic operation, size comparison, etc. It is mainly used for non-convolutional / fully connected layer network calculations in neural networks, such as batch normalization, pixel-level summation, and upsampling of feature planes.

[0275] In some implementations, the vector calculation unit 1307 can store the processed output vector in the unified memory 1306. For example, the vector calculation unit 1307 can apply a linear function or a nonlinear function to the output of the operation circuit 1303, such as linear interpolation of the feature plane extracted by the convolution layer, or accumulate a vector of values ​​to generate an activation value. In some implementations, the vector calculation unit 1307 generates a normalized value, a pixel-level summed value, or both. In some implementations, the processed output vector can be used as an activation input to the operation circuit 1303, for example, for use in subsequent layers in a neural network.

[0276] An instruction fetch buffer 1309 connected to the controller 1304 is used to store instructions used by the controller 1304;

[0277] Unified memory 1306, input memory 1301, weight memory 1302, and instruction fetch memory 1309 are all on-chip memories. External memories are private to the NPU hardware architecture.

[0278] The processor mentioned in any of the above places can be a general-purpose central processing unit, a microprocessor, an ASIC, or one or more integrated circuits for controlling the execution of the above program.

[0279] It should also be noted that the device embodiments described above are merely illustrative, wherein the units described as separate components may or may not be physically separate, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present embodiment. In addition, in the drawings of the device embodiments provided in this application, the connection relationship between the modules indicates that there is a communication connection between them, which can be specifically implemented as one or more communication buses or signal lines.

[0280] Through the description of the above embodiments, those skilled in the art can clearly understand that the present application can be implemented by means of software plus necessary general hardware, and of course can also be implemented by special hardware including application-specific integrated circuits, special CPUs, special memories, special components, etc. In general, all functions performed by computer programs can be easily implemented with corresponding hardware, and the specific hardware structures used to implement the same function can also be diverse, such as analog circuits, digital circuits or special circuits, etc. However, for the present application, software program implementation is a better implementation method in most cases. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a readable storage medium, such as a computer's floppy disk, USB flash drive, mobile hard disk, ROM, RAM, magnetic disk or optical disk, etc., and includes a number of instructions to enable a computer device (which can be a personal computer, training equipment, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0281] In the above embodiments, all or part of the embodiments may be implemented by software, hardware, firmware, or any combination thereof. When implemented by software, all or part of the embodiments may be implemented in the form of a computer program product.

[0282] The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website, a computer, a training device or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website, a computer, a training device or a data center. The computer-readable storage medium can be any available medium that a computer can store or a data storage device such as a training device, a data center, etc. that includes one or more available media integrations. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive (SSD)).

Claims

1. A video encoding method, characterized in that: The method comprises: Get multiple video frames; Processing the multiple video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the multiple video frames include M first video frames and N second video frames, and the inter-frame compression module is used to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; According to the encoding result, video-related tasks are performed to obtain a processing result.

2. The method according to claim 1, characterized in that The video-related tasks are video retrieval, video question answering or video description generation.

3. The method according to claim 1 or 2, characterized in that: The step of fusing the feature representations of the M first video frames into the feature representations of the N second video frames includes: The feature representation of each of the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

4. The method according to any one of claims 1 to 3, characterized in that: The M first video frames are the M video frames having the lowest correlation with other video frames among the multiple video frames.

5. The method according to any one of claims 1 to 4, characterized in that: The first video frame and the second video frame are interlaced with each other in the plurality of video frames.

6. The method according to any one of claims 1 to 5, characterized in that: The fusion is average pooling.

7. The method according to any one of claims 1 to 6, characterized in that: The encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

8. The method according to claim 7, characterized in that The step of fusing the feature representations of the X first image blocks into the feature representations of the Y second image blocks includes: The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

9. The method according to claim 7 or 8, characterized in that: The X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

10. The method according to any one of claims 7 to 9, characterized in that: The first image block and the second image block are interlaced with each other in the third video frame.

11. A video encoding device, characterized in that: The device comprises: An acquisition module, used for acquiring multiple video frames; A processing module, configured to process the plurality of video frames through an encoder to obtain an encoding result; wherein the encoder includes a first network layer; the first network layer includes an inter-frame compression module, the plurality of video frames include M first video frames and N second video frames, and the inter-frame compression module is configured to fuse feature representations of the M first video frames into feature representations of the N second video frames to obtain N feature representations; According to the encoding result, video-related tasks are performed to obtain a processing result.

12. The device according to claim 11, characterized in that The video-related tasks are video retrieval, video question answering or video description generation.

13. The device according to claim 11 or 12, characterized in that The processing module is specifically used for: The feature representation of each of the M first video frames is fused to the feature representation of the second video frame that is most similar to the N second video frames.

14. The device according to any one of claims 11 to 13, characterized in that: The M first video frames are the M video frames having the lowest correlation with other video frames among the multiple video frames.

15. The device according to any one of claims 11 to 14, characterized in that: The first video frame and the second video frame are interlaced with each other in the plurality of video frames.

16. The device according to any one of claims 11 to 15, characterized in that The fusion is average pooling.

17. The device according to any one of claims 11 to 16, characterized in that The encoder includes a second network layer; the first network layer and the second network layer are the same or different network layers, the second network layer includes an intra-frame compression module, the multiple video frames include a third video frame, the third video frame includes X first image blocks and Y second image blocks, and the intra-frame compression module is used to fuse feature representations of the X first image blocks into feature representations of the Y second image blocks to obtain Y feature representations.

18. The device according to claim 17, characterized in that The processing module is specifically used for: The feature representation of each first image block in the X first image blocks is fused to the feature representation of the second image block that is most similar to the Y second image blocks.

19. The device according to claim 17 or 18, characterized in that The X first image blocks are X image blocks having the lowest correlation with other image blocks among the multiple image blocks included in the third video frame.

20. The device according to any one of claims 17 to 19, characterized in that The first image block and the second image block are interlaced with each other in the third video frame.

21. A computer storage medium, characterized in that The computer storage medium stores one or more instructions which, when executed by one or more computers, cause the one or more computers to perform the operations of the method of any one of claims 1 to 10.

22. A computer program product, characterized in that The method comprises computer-readable instructions, and when the computer-readable instructions are executed on a computer device, the computer device is caused to execute the method according to any one of claims 1 to 10.

23. A system comprising at least one processor and at least one memory; the processor and the memory are connected via a communication bus and communicate with each other; The at least one memory is used to store code; The at least one processor is configured to execute the code to perform the method according to any one of claims 1 to 10.

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