Etching method and plasma processing apparatus

Abstract

This etching method includes: (a) a step for providing a substrate that includes a multilayer film including a silicon oxide film and a silicon nitride film; (b) a step for etching the silicon nitride film with a first plasma that is generated from a first processing gas which contains a hydrofluorocarbon gas, while applying a first bias voltage to a substrate support part; and (c) a step for etching the silicon oxide film with a second plasma that is generated from a second processing gas which contains a fluorocarbon gas, while applying a second bias voltage to the substrate support part, wherein the absolute value of the voltage value of the second bias voltage is greater than the absolute value of the voltage value of the first bias voltage. Each of the first bias voltage and the second bias voltage is a pulse wave in which the ON and OFF of the pulse of the DC voltage are periodically repeated, and the ON time of the pulse is 0.5 microseconds or less.

Description

Etching method and plasma processing apparatus

[0001] SUMMARY OF THE INVENTION Exemplary embodiments of the present disclosure relate to an etching method and a plasma processing apparatus.

[0002] In the manufacture of electronic devices, plasma etching is sometimes performed on a film on a substrate to form recesses in the film. Patent Document 1 discloses a plasma processing apparatus used for plasma etching, in which an electric bias is applied to a substrate support to attract ions to the substrate. Patent Document 1 discloses a pulse wave, which is a series of pulsed voltages, as an example of the electric bias.

[0003] International Publication No. 2022 / 234643

[0004] The present disclosure provides a technique for suppressing shape abnormalities in recesses formed by etching.

[0005] In one exemplary embodiment, an etching method is provided, the etching method including the steps of: (a) providing a substrate, the substrate including a stacked film including a silicon oxide film and a silicon nitride film; (b) etching the silicon nitride film with a first plasma generated from a first process gas including a hydrofluorocarbon gas while applying a first bias voltage to a substrate support supporting the substrate; and (c) etching the silicon oxide film with a second plasma generated from a second process gas including a fluorocarbon gas while applying a second bias voltage to the substrate support, the absolute value of the second bias voltage being greater than the absolute value of the first bias voltage, wherein each of the first bias voltage and the second bias voltage is a pulse wave in which on- and off-pulses of a DC voltage are periodically repeated, and the on-time of the pulse is 0.5 microseconds or less.

[0006] According to one exemplary embodiment, it is possible to suppress irregularities in the shape of recesses formed by etching.

[0007] FIG. 1 is a diagram schematically illustrating a plasma processing apparatus according to an exemplary embodiment. FIG. 2 is a diagram schematically illustrating a plasma processing apparatus according to an exemplary embodiment. FIG. 3 is a flowchart of an etching method according to an exemplary embodiment. FIG. 4 is a cross-sectional view of an example substrate to which the method of FIG. 3 can be applied. FIG. 5 is a cross-sectional view illustrating a process of the etching method according to an exemplary embodiment. FIG. 6 is a cross-sectional view illustrating another process of the etching method according to an exemplary embodiment. FIG. 7 is an example timing chart showing temporal changes in source power and bias voltage. FIG. 8 is an enlarged view of a portion of the timing chart of FIG. 7. FIG. 9(a) is a diagram illustrating an example of a first bias voltage and a substrate potential when the on-time is longer than 0.5 microseconds. FIG. 9(b) is a diagram illustrating an example of a first bias voltage and a substrate potential when the on-time is 0.5 microseconds or less. FIG. 10 is a diagram illustrating experimental results of etching performed using the etching method according to an exemplary embodiment.

[0008] Various exemplary embodiments will be described in detail below with reference to the drawings, in which the same or equivalent parts are designated by the same reference numerals.

[0009] FIG. 1 is a schematic diagram illustrating a plasma processing apparatus according to an exemplary embodiment. In this embodiment, the plasma processing system includes a plasma processing apparatus 1 and a controller 2. The plasma processing system is an example of a substrate processing system, and the plasma processing apparatus 1 is an example of a substrate processing apparatus. The plasma processing apparatus 1 includes a plasma processing chamber 10, a substrate support 11, and a plasma generation unit 12. The plasma processing chamber 10 has a plasma processing space. The plasma processing chamber 10 also has at least one gas supply port for supplying at least one processing gas to the plasma processing space and at least one gas exhaust port for exhausting gas from the plasma processing space. The gas supply port is connected to a gas supply unit 20 (described later), and the gas exhaust port is connected to an exhaust system 40 (described later). The substrate support 11 is disposed in the plasma processing space and has a substrate support surface for supporting a substrate.

[0010] The plasma generating unit 12 is configured to generate plasma from at least one processing gas supplied into the plasma processing space. The plasma generated in the plasma processing space may be capacitively coupled plasma (CCP), inductively coupled plasma (ICP), electron-cyclotron-resonance plasma (ECR plasma), helicon wave plasma (HWP), or surface wave plasma (SWP). Various types of plasma generators may be used, including alternating current (AC) plasma generators and direct current (DC) plasma generators. In one embodiment, the AC signal (AC power) used in the AC plasma generator has a frequency in the range of 100 kHz to 10 GHz. Thus, AC signals include radio frequency (RF) signals and microwave signals. In one embodiment, the RF signal has a frequency in the range of 100 kHz to 150 MHz.

[0011] The control unit 2 processes computer-executable instructions that cause the plasma processing apparatus 1 to perform various processes described in this disclosure. The control unit 2 may be configured to control each element of the plasma processing apparatus 1 to perform various processes described herein. In one embodiment, part or all of the control unit 2 may be included in the plasma processing apparatus 1. The control unit 2 may include a processing unit 2a1, a storage unit 2a2, and a communication interface 2a3. The control unit 2 may be implemented by, for example, a computer 2a. The processing unit 2a1 may be configured to read a program from the storage unit 2a2 and execute the read program to perform various control operations. This program may be stored in the storage unit 2a2 in advance or may be acquired via a medium when needed. The acquired program is stored in the storage unit 2a2 and read from the storage unit 2a2 by the processing unit 2a1 for execution. The medium may be various storage media readable by the computer 2a or a communication line connected to the communication interface 2a3. The processing unit 2a1 may be a CPU (Central Processing Unit). The storage unit 2a2 may include a random access memory (RAM), a read-only memory (ROM), a hard disk drive (HDD), a solid state drive (SSD), or a combination thereof. The communication interface 2a3 may communicate with the plasma processing apparatus 1 via a communication line such as a local area network (LAN).

[0012] The following describes a configuration example of a capacitively coupled plasma processing apparatus as an example of the plasma processing apparatus 1. Fig. 2 is a diagram schematically showing a plasma processing apparatus according to an exemplary embodiment.

[0013] The capacitively coupled plasma processing apparatus 1 includes a plasma processing chamber 10, a gas supply 20, a power supply 30, and an exhaust system 40. The plasma processing apparatus 1 also includes a substrate support 11 and a gas inlet. The gas inlet is configured to introduce at least one process gas into the plasma processing chamber 10. The gas inlet includes a showerhead 13. The substrate support 11 is disposed within the plasma processing chamber 10. The showerhead 13 is disposed above the substrate support 11. In one embodiment, the showerhead 13 forms at least a portion of the ceiling of the plasma processing chamber 10. The plasma processing chamber 10 has a plasma processing space 10s defined by the showerhead 13, a sidewall 10a of the plasma processing chamber 10, and the substrate support 11. The plasma processing chamber 10 is grounded. The showerhead 13 and the substrate support 11 are electrically insulated from the housing of the plasma processing chamber 10.

[0014] The substrate support 11 includes a main body 111 and a ring assembly 112. The main body 111 has a central region 111a for supporting a substrate W and an annular region 111b for supporting the ring assembly 112. A wafer is an example of a substrate W. The annular region 111b of the main body 111 surrounds the central region 111a of the main body 111 in a plan view. The substrate W is disposed on the central region 111a of the main body 111, and the ring assembly 112 is disposed on the annular region 111b of the main body 111 so as to surround the substrate W on the central region 111a of the main body 111. Therefore, the central region 111a is also called a substrate support surface for supporting the substrate W, and the annular region 111b is also called a ring support surface for supporting the ring assembly 112.

[0015] In one embodiment, the main body 111 includes a base 1110 and an electrostatic chuck 1111. The base 1110 includes a conductive member. The conductive member of the base 1110 can function as a lower electrode. The electrostatic chuck 1111 is disposed on the base 1110. The electrostatic chuck 1111 includes a ceramic member 1111a and an electrostatic electrode 1111b disposed within the ceramic member 1111a. The ceramic member 1111a has a central region 111a. In one embodiment, the ceramic member 1111a also has an annular region 111b. Note that the annular region 111b may also be provided by another member surrounding the electrostatic chuck 1111, such as an annular electrostatic chuck or an annular insulating member. In this case, the ring assembly 112 may be disposed on the annular electrostatic chuck or the annular insulating member, or may be disposed on both the electrostatic chuck 1111 and the annular insulating member. Furthermore, at least one RF / DC electrode coupled to an RF power supply 31 and / or a DC power supply 32, which will be described later, may be disposed within the ceramic member 1111a. In this case, the at least one RF / DC electrode functions as a lower electrode. When a bias RF signal and / or a DC signal, which will be described later, is supplied to the at least one RF / DC electrode, the RF / DC electrode is also called a bias electrode. Note that the conductive member of the base 1110 and the at least one RF / DC electrode may function as multiple lower electrodes. Furthermore, the electrostatic electrode 1111b may function as a lower electrode. Therefore, the substrate support 11 includes at least one lower electrode.

[0016] The ring assembly 112 includes one or more annular members. In one embodiment, the one or more annular members include one or more edge rings and at least one cover ring. The edge rings are formed of a conductive or insulating material, and the cover rings are formed of an insulating material.

[0017] The substrate support 11 may also include a temperature adjustment module configured to adjust at least one of the electrostatic chuck 1111, the ring assembly 112, and the substrate to a target temperature. The temperature adjustment module may include a heater, a heat transfer medium, a flow passage 1110a, or a combination thereof. A heat transfer fluid such as brine or a gas flows through the flow passage 1110a. In one embodiment, the flow passage 1110a is formed in the base 1110, and one or more heaters are disposed in the ceramic member 1111a of the electrostatic chuck 1111. The substrate support 11 may also include a heat transfer gas supply configured to supply a heat transfer gas to a gap between the backside of the substrate W and the central region 111a.

[0018] The showerhead 13 is configured to introduce at least one process gas from the gas supply unit 20 into the plasma processing space 10s. The showerhead 13 has at least one gas supply port 13a, at least one gas diffusion chamber 13b, and multiple gas inlets 13c. The process gas supplied to the gas supply port 13a passes through the gas diffusion chamber 13b and is introduced into the plasma processing space 10s from the multiple gas inlets 13c. The showerhead 13 also includes at least one upper electrode. In addition to the showerhead 13, the gas inlet may also include one or more side gas injectors (SGIs) attached to one or more openings formed in the sidewall 10a.

[0019] The gas supply unit 20 may include at least one gas source 21 and at least one flow controller 22. In one embodiment, the gas supply unit 20 is configured to supply at least one process gas from a corresponding gas source 21 to the showerhead 13 via a corresponding flow controller 22. Each flow controller 22 may include, for example, a mass flow controller or a pressure-controlled flow controller. Additionally, the gas supply unit 20 may include at least one flow modulation device that modulates or pulses the flow rate of the at least one process gas.

[0020] The power supply 30 includes an RF power supply 31 coupled to the plasma processing chamber 10 via at least one impedance matching circuit. The RF power supply 31 is configured to supply at least one RF signal (RF power) to at least one lower electrode and / or at least one upper electrode. This generates a plasma from at least one processing gas supplied to the plasma processing space 10s. Therefore, the RF power supply 31 can function as at least a part of the plasma generation unit 12. Furthermore, by supplying a bias RF signal to the at least one lower electrode, a bias potential is generated on the substrate W, thereby attracting ion components in the formed plasma to the substrate W.

[0021] In one embodiment, the RF power supply 31 includes a first RF generating unit 31a and a second RF generating unit 31b. The first RF generating unit 31a is coupled to at least one lower electrode and / or at least one upper electrode via at least one impedance matching circuit and is configured to generate a source RF signal (source RF power) for plasma generation. In one embodiment, the source RF signal has a frequency in the range of 10 MHz to 150 MHz. In one embodiment, the first RF generating unit 31a may be configured to generate multiple source RF signals having different frequencies. The generated one or more source RF signals are supplied to at least one lower electrode and / or at least one upper electrode.

[0022] The second RF generator 31b is coupled to at least one lower electrode via at least one impedance matching circuit and is configured to generate a bias RF signal (bias RF power). The frequency of the bias RF signal may be the same as or different from the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency lower than the frequency of the source RF signal. In one embodiment, the bias RF signal has a frequency in the range of 100 kHz to 60 MHz. In one embodiment, the second RF generator 31b may be configured to generate multiple bias RF signals having different frequencies. The generated one or more bias RF signals are supplied to at least one lower electrode. In various embodiments, at least one of the source RF signal and the bias RF signal may be pulsed.

[0023] The power supply 30 may also include a DC power supply 32 coupled to the plasma processing chamber 10. The DC power supply 32 includes a first DC generator 32a and a second DC generator 32b. In one embodiment, the first DC generator 32a is connected to the at least one lower electrode and configured to generate a first DC signal. The generated first DC signal is applied to the at least one lower electrode. In one embodiment, the second DC generator 32b is connected to the at least one upper electrode and configured to generate a second DC signal. The generated second DC signal is applied to the at least one upper electrode.

[0024] In various embodiments, the first and second DC signals may be pulsed. In this case, a sequence of voltage pulses is applied to at least one lower electrode and / or at least one upper electrode. The voltage pulses may have a rectangular, trapezoidal, triangular, or combination thereof pulse waveform. In one embodiment, a waveform generator for generating the sequence of voltage pulses from the DC signal is connected between the first DC generator 32a and at least one lower electrode. Thus, the first DC generator 32a and the waveform generator constitute a voltage pulse generator. When the second DC generator 32b and the waveform generator constitute a voltage pulse generator, the voltage pulse generator is connected to at least one upper electrode. The voltage pulses may have either positive or negative polarity. Furthermore, the sequence of voltage pulses may include one or more positive voltage pulses and one or more negative voltage pulses within one period. The first and second DC generating units 32a and 32b may be provided in addition to the RF power supply 31, or the first DC generating unit 32a may be provided instead of the second RF generating unit 31b.

[0025] The exhaust system 40 may be connected to, for example, a gas exhaust port 10e provided at the bottom of the plasma processing chamber 10. The exhaust system 40 may include a pressure regulating valve and a vacuum pump. The pressure in the plasma processing space 10s is regulated by the pressure regulating valve. The vacuum pump may include a turbomolecular pump, a dry pump, or a combination thereof.

[0026] 3 is a flowchart of an etching method according to one exemplary embodiment. The etching method MT shown in FIG. 3 (hereinafter referred to as "method MT") can be performed by the plasma processing apparatus 1 according to the above embodiment. The method MT can be applied to a substrate W.

[0027] FIG. 4 is a cross-sectional view of an example substrate W to which the method MT can be applied. The substrate W shown in FIG. 4 may be used in the manufacture of semiconductor devices. The semiconductor devices may include, for example, memory devices such as DRAMs and 3D-NANDs, and logic devices. The substrate W has a silicon-containing film EF. The substrate W may further have an underlayer film UF. The silicon-containing film EF may be provided on the underlayer film UF. The underlayer film UF may include a material different from the material included in the silicon-containing film EF. The underlayer film UF may include silicon.

[0028] The silicon-containing film EF is a silicon oxide film (SiO ｘ ) EF2 and silicon nitride film (SiN ｘ ) EF1. x is a positive real number. In the example of FIG. 4, a silicon oxide film EF2 is provided on an underlayer UF. A silicon nitride film EF1 is provided on the silicon oxide film EF2. The thickness of the silicon nitride film EF1 may be the same as or different from the thickness of the silicon oxide film EF2. When the thicknesses are different, the thickness of the silicon nitride film EF1 may be thicker or thinner than the thickness of the silicon oxide film EF2.

[0029] 4, the silicon-containing film EF has a two-layer structure of a silicon oxide film EF2 and a silicon nitride film EF1. The silicon-containing film EF may be, for example, a multilayer film including one or more silicon oxide films and one or more silicon nitride films that are alternately stacked. The silicon-containing film EF may be, for example, a multilayer film including a plurality of silicon oxide films and a plurality of silicon nitride films that are alternately stacked.

[0030] The substrate W may further include a mask MF having openings OP. The openings OP may have a hole pattern or a line pattern. The mask MF may be provided on the silicon-containing film EF. The mask MF may include at least one selected from the group consisting of a carbon-containing film and a metal-containing film. The carbon-containing film may include an amorphous carbon film. The metal-containing film may include at least one metal selected from the group consisting of tungsten (W), titanium (Ti), and ruthenium (Ru).

[0031] Method MT will be described below with reference to FIGS. 3 to 8, taking as an example a case where method MT is applied to a substrate W using the plasma processing apparatus 1 of the above embodiment. Each of FIGS. 5 and 6 is a cross-sectional view showing a step of an etching method according to one exemplary embodiment. When the plasma processing apparatus 1 is used, method MT can be performed in the plasma processing apparatus 1 by controlling each part of the plasma processing apparatus 1 with a controller 2. In method MT, a substrate W on a substrate support 11 disposed in a plasma processing chamber 10 is processed, as shown in FIG. 2.

[0032] 3, the method MT may include steps ST1, ST2, and ST3. Steps ST1, ST2, and ST3 may be performed in order. After step ST3, steps ST2 and ST3 may be repeated.

[0033] (Step ST1) In step ST1, a substrate W shown in Fig. 4 is provided. The substrate W can be supported by a substrate support 11 in a plasma processing chamber 10.

[0034] (Step ST2) In step ST2, a first plasma PM1 is generated from a first process gas, and the silicon nitride film EF1 is etched by the first plasma PM1. As shown in FIG. 5, a recess RE1 is formed in the silicon nitride film EF1 by etching. The recess RE1 corresponds to the opening OP. The top surface of the silicon oxide film EF2 may be exposed at a bottom BT1 of the recess RE1. That is, the silicon nitride film EF1 may be etched until the bottom BT1 of the recess RE1 reaches the silicon oxide film EF2.

[0035] The first process gas is a hydrofluorocarbon gas (C ｘ H ｙ F ｚ Each of x, y, and z is a natural number. The hydrofluorocarbon gas includes CHF ３ Gas, CH ２ F ２ Gas, CH ３ F gas, C ２ HF ５ Gas, C ２ H２ F ４ Gas, C ２ H ３ F ３ Gas, C ２ H ４ F ２ Gas, C ３ HF ７ Gas, C ３ H ２ F ２ Gas, C ３ H ２ F ４ Gas, C ３ H ２ F ６ Gas, C ３ H ３ F ５ Gas, C ４ H ２ F ６ Gas, C ４ H ５ F ５ Gas, C ４ H ２ F ８ Gas, C ５ H ２ F ６ Gas, C ５ H ２ F １０ Gas, and C ５ H ３ F ７ The first process gas may be at least one selected from the group consisting of fluorocarbon gas (C ｘ F ｙ Each of x and y is a natural number. The fluorocarbon gas may further include C ４ F ６ Gas and C ４ F ８ The first process gas may be at least one selected from the group consisting of nitrogen trifluoride gas (NF ３ The first process gas may further include oxygen gas (O ２ The gas may further comprise:

[0036] In step ST2, the temperature of the substrate support part 11 that supports the substrate W may be, for example, 50° C. The temperature of the substrate support part 11 may be set to 100° C. or less, 80° C. or less, or 60° C. or less.

[0037] In step ST2, the pressure in the plasma processing chamber 10 may be, for example, 10 mTorr (1.3 Pa). The pressure in the plasma processing chamber 10 may be set to 50 mTorr (6.5 Pa) or less, or 30 mTorr (3.9 Pa) or less.

[0038] (Step ST3) In step ST3, a second plasma PM2 is generated from the second process gas, and the silicon oxide film EF2 is etched by the second plasma PM2. As shown in FIG. 6, a recess RE2 is formed in the silicon oxide film EF2 by etching. The recess RE2 corresponds to the recess RE1. The recess RE2 may be formed continuously from the recess RE1. The upper surface of the base film UF may be exposed at the bottom BT2 of the recess RE2. That is, the silicon oxide film EF2 may be etched until the bottom BT2 of the recess RE2 reaches the base film UF.

[0039] The second process gas is a fluorocarbon gas (C ｘ F ｙ Fluorocarbon gases include C ２ F ２ Gas, C ２ F ４ Gas, C ３ F ６ Gas, C ３ F ８ Gas, C ４ F ６ Gas, C ４ F ８ Gas, and C ５ F ８ The second process gas may be at least one selected from the group consisting of hydrofluorocarbon gas (C ｘ H ｙ F ｚ The second process gas may further contain C. ｘ H ｙ F ｚAn example of the gas is C contained in the first processing gas. ｘ H ｙ F ｚ The second process gas may be the same as the example gas. The second process gas may further include nitrogen trifluoride gas. The second process gas may further include oxygen gas.

[0040] In step ST3, the temperature of the substrate support part 11 that supports the substrate W may be, for example, 70° C. The temperature of the substrate support part 11 may be set to 100° C. or less, or 80° C. or less.

[0041] In step ST3, the pressure in the plasma processing chamber 10 may be, for example, 10 mTorr (1.3 Pa). The pressure in the plasma processing chamber 10 may be set to 50 mTorr (6.5 Pa) or less, or 30 mTorr (3.9 Pa) or less.

[0042] Next, with reference to FIGS. 7 and 8, the source RF power (hereinafter also referred to as source power) and bias voltage supplied to the plasma processing apparatus 1 in steps ST2 and ST3 will be described. The source power may be generated by the first RF generator 31a and supplied to at least one lower electrode and / or at least one upper electrode. The bias voltage may be generated by a voltage pulse generator and supplied to the substrate support 11. FIG. 7 is an example of a timing chart showing the temporal changes in the source power WS and the bias voltage VB. The horizontal axis of FIG. 7 represents time. The vertical axis of FIG. 7 represents the magnitude of the source power WS and the bias voltage VB. That is, the vertical axis of FIG. 7 represents the power level (effective value of the power value) of the source power WS and the voltage value of the bias voltage VB.

[0043] The source power WS includes a first source power WS1 supplied in step ST2 and a second source power WS2 supplied in step ST3. The first source power WS1 may include a first power level PL1 and a second power level PL2 lower than the first power level PL1. The first power level PL1 and the second power level PL2 may be periodically repeated. The second power level PL2 may be a state in which the first source power WS1 is off (0 W). While the first source power WS1 is at the first power level PL1, the first source power WS1 may promote the generation of the first plasma PM1. While the first source power WS1 is at the second power level PL2, the generation of the first plasma PM1 may be stopped, or a plasma having a lower plasma density than the first plasma PM1 may be generated.

[0044] The second source power WS2 may include a third power level PL3 and a fourth power level PL4 lower than the third power level PL3. The third power level PL3 and the fourth power level PL4 may be periodically repeated. The third power level PL3 may be higher than the first power level PL1. The fourth power level PL4 may be in a state where the second source power WS2 is off (0 W). The fourth power level PL4 may be the same as or different from the second power level PL2. In the example of FIG. 7 , the fourth power level PL4 is the same as the second power level PL2. While the second source power WS2 is at the third power level PL3, the second source power WS2 may promote the generation of the second plasma PM2. While the second source power WS2 is at the fourth power level PL4, the generation of the second plasma PM2 may be stopped, or a plasma having a lower plasma density than the second plasma PM2 may be generated.

[0045] The bias voltage VB includes a first bias voltage VB1 applied to the substrate support member 11 in step ST2 and a second bias voltage VB2 applied to the substrate support member 11 in step ST3. In step ST2, a first period T1 and a second period T2 following the first period T1 are periodically repeated. The first bias voltage VB1 is applied during the first period T1. The first bias voltage VB1 may be a negative voltage. Application of the first bias voltage VB1 may attract ions contained in the first plasma PM1 to a bottom portion BT1 of the RE1 formed in the silicon nitride film EF1, thereby progressing etching of the silicon nitride film EF1. Meanwhile, the first bias voltage VB1 is not applied during the second period T2. This may suppress etching of the silicon nitride film EF1 during the second period T2.

[0046] In step ST3, a third period T3 and a fourth period T4 following the third period T3 are periodically repeated. In this embodiment, the third period T3 follows the second period T2 in step ST2. In the third period T3, a second bias voltage VB2 is applied. The second bias voltage VB2 may be a negative voltage. Application of the second bias voltage VB2 may attract ions contained in the second plasma PM2 to a bottom portion BT2 of the RE2 formed in the silicon oxide film EF2, thereby progressing etching of the silicon oxide film EF2. On the other hand, in the fourth period T4, the second bias voltage VB2 is not applied. As a result, etching of the silicon oxide film EF2 may be suppressed in the fourth period T4.

[0047] As shown in FIG. 7 , in process ST2, the first source power WS1 may have a first power level PL1 during the first period T1. That is, the period during which the first source power WS1 has the first power level PL1 may be synchronized with the period during which the first bias voltage VB1 is applied during the first period T1. In this case, generation of the first plasma PM1 is promoted during the first period T1, thereby accelerating the progress of etching of the silicon nitride film EF1. In process ST2, the first source power WS1 may have a second power level PL2 during the second period T2. That is, the period during which the first source power WS1 has the second power level PL2 may be synchronized with the period during which the first bias voltage VB1 is not applied during the second period T2. In this case, in the second period T2, the generation of the second plasma PM2 is stopped or the plasma density is reduced, so that etching of the silicon nitride film EF1 may be suppressed.

[0048] As shown in FIG. 7 , in process ST3, the second source power WS2 may have a third power level PL3 during the third period T3. That is, the period during which the second source power WS2 has the third power level PL3 may be synchronized with the period during which the second bias voltage VB2 is applied during the third period T3. In this case, generation of the second plasma PM2 is promoted during the third period T3, thereby accelerating the progress of etching of the silicon oxide film EF2. In process ST2, the second source power WS2 may have a fourth power level PL4 during the fourth period T4. That is, the period during which the second source power WS2 has the fourth power level PL4 may be synchronized with the period during which the second bias voltage VB2 is not applied during the fourth period T4. In this case, in the fourth period T4, the generation of the second plasma PM2 is stopped or the plasma density is reduced, so that etching of the silicon oxide film EF2 may be suppressed.

[0049] Next, the first bias voltage VB1 and the second bias voltage VB2 will be described in more detail with reference to Fig. 8. Fig. 8 is an enlarged view of a portion of the timing chart of Fig. 7. The horizontal axis of Fig. 8 represents time. The vertical axis of Fig. 8 represents voltage value. The first bias voltage VB1 is a pulse wave in which a DC voltage pulse PS1 is periodically turned on and off. In this embodiment, since the first bias voltage VB1 is a negative voltage, the voltage value of the pulse PS1 is ＯＮ 1, the negative first DC voltage value (−V1) is reached, and the OFF time T ＯＦ The second bias voltage VB2 is a pulse wave in which the on-time and off-time of the pulse PS2 of the DC voltage are periodically repeated. In this embodiment, since the second bias voltage VB2 is a negative voltage, the voltage value of the pulse PS2 is 0 V during the on-time T ＯＮ 2, the negative second DC voltage value (−V2) is reached, and the OFF time T ＯＦ At 2, the voltage value is 0V.

[0050] The absolute value V2 of the second DC voltage value (-V2) which is the voltage value of the second bias voltage VB2 is greater than the absolute value V1 of the first DC voltage value (-V1) which is the voltage value of the first bias voltage VB1. The absolute value V1 of the first DC voltage value (-V1) may be 1 kV or more and 5 kV or less. The absolute value V2 of the second DC voltage value (-V2) may be 5 kV or more and 20 kV or less.

[0051] The frequency FR2 that defines the period CY2 of the pulse PS2 of the second bias voltage VB2 may be higher than the frequency FR1 that defines the period CY1 of the pulse PS1 of the first bias voltage VB1. Alternatively, the frequency FR2 that defines the period CY2 of the pulse PS2 of the second bias voltage VB2 may be equal to or higher than the frequency FR1 that defines the period CY1 of the pulse PS1 of the first bias voltage VB1. Here, the period CY1 is determined by the on-time T ＯＮ 1 and off time T ＯＦ Similarly, CY2 is the sum of the on-time T ＯＮ 2 and off time T ＯＦThe frequency FR1 is the sum of the period of FR1 and FR2. The frequency FR1 may be 200 kHz or more and 400 kHz or less, or 300 kHz or more and 500 kHz or less. The frequency FR2 may be 200 kHz or more and 500 kHz or less, or 300 kHz or more and 600 kHz or less.

[0052] The on-time T of the pulse PS1 of the first bias voltage VB1 ＯＮ 1 is the on-time T of the pulse PS2 of the second bias voltage VB2 ＯＮ 2. On time T ＯＮ 1 and on time T ＯＮ Each of the on-times T2 may be 0.5 microseconds (μs) or less, 0.4 μs or less, or 0.2 μs or more. As mentioned above, when the frequency FR2 is higher than the frequency FR1, the on-time T ＯＮ 1 and on time T ＯＮ 2 are the same, so that the off time T ＯＦ 1 is the off time T of the pulse PS2 ＯＦ It will be longer than 2.

[0053] The duty ratio of each of the first bias voltage VB1 and the second bias voltage VB2 may be 5% or more, 10% or more, 25% or less, or 20% or less. Here, the duty ratio of the first bias voltage VB1 is determined by the ratio of the ON time T ＯＮ The duty ratio of the second bias voltage VB2 is expressed as a percentage of the ON time T ＯＮ 2 ratio expressed as a percentage.

[0054] On time T ＯＮ The on-time T1 is started at the same time as the power supply 30 of the plasma processing apparatus 1 starts to output the first bias voltage VB1, and is ended at the same time as the power supply 30 stops outputting the first bias voltage VB1. The on-time T1 is determined by the impedance of the wiring path from the voltage pulse generating unit to the substrate support unit 11, etc. ＯＮAfter a certain time has elapsed since the start of ON time T1, the first bias voltage VB1 supplied to the substrate support 11 may reach a peak voltage value. ＯＮ The on-time T2 starts at the same time that the power supply 30 of the plasma processing apparatus 1 starts to output the second bias voltage VB2, and ends at the same time that the power supply 30 stops outputting the second bias voltage VB2. ＯＮ After a certain time has elapsed since the start of the second bias voltage VB2, the second bias voltage VB2 supplied to the substrate support 11 may reach a peak voltage value.

[0055] Next, referring to FIGS. 9 and 10, the ON time T ＯＮ 1 and on time T ＯＮ The effect of the ON time T2 being a short time of 0.5 microseconds or less will be described. Note that the effect described here is merely an example and is not intended to be limiting. ＯＮ 9B is a diagram illustrating an example of the first bias voltage VB1 and the potential WV1 of the substrate W when the ON time T 1 exceeds 0.5 microseconds. ＯＮ 9 is a diagram for explaining an example of the first bias voltage VB1 and the potential WV2 of the substrate W when the ON time T1 of the first bias voltage VB1 is 0.5 microseconds or less. ＯＮ 1 will be described as an example, but the description in FIG. 9 will be made based on the ON time T ＯＮ The same applies to 2.

[0056] As shown in FIG. 9, the on-time T ＯＮ In FIG. 1, the potentials WV1 and WV2 gradually change toward 0 V after reaching the first DC voltage value (−V1). Specifically, the potentials WV1 and WV2 of the substrate W change in a direction in which the absolute values ​​of the potentials WV1 and WV2 of the substrate W decrease. ＯＮ 1 to off time T ＯＦWhen the potentials WV1 and WV2 are switched to 0V, the potentials WV1 and WV2 of the substrate W change sharply toward 0V. Compared to the change ΔV of the potential WV1 shown in FIG. 9A, the change ΔV of the potential WV2 shown in FIG. 9B is smaller. The change ΔV of the potential WV1 is, for example, within 10% of the absolute value of the first DC voltage value (−V1). The change ΔV of the potential WV2 is, for example, within 5% of the absolute value of the first DC voltage value (−V1). The smaller the change ΔV, the more likely it is that the absolute value of the potential of the substrate W is maintained at a large value. This makes it easier for ions contained in the first plasma PM1 to be attracted to the bottom BT1 of the recess RE1 formed in the silicon nitride film EF1 by etching. As a result, it is possible to suppress a reduction in the pattern width of the bottom BT1 of the recess RE1. Similarly, it is possible to suppress reduction in the pattern width of the bottom portion BT2 of the recess portion RE2 formed in the silicon oxide film EF2 by etching.

[0057] 9B, the period T5 in which the potential WV2 of the substrate W changes significantly from the first DC voltage value (-V1) is excluded. In the period T5, the absolute value of the potential is smaller than the absolute value of the first DC voltage value (-V1), so that ions contained in the first plasma PM1 have difficulty reaching the bottom BT1 and tend to collide with the upper portion of the recess RE1. ＯＮ When the on-time T1 is 0.5 microseconds or less, it becomes easier to suppress the collision of ions with the upper portion, and therefore it becomes easier to suppress the expansion of the pattern width at the upper portion of the recessed portion RE1. ＯＮ When 1 is 0.5 microseconds or less, it is possible to suppress the reduction in the pattern width of the bottom portion BT1 of the recessed portion RE1, while suppressing the expansion of the pattern width of the upper portion of the recessed portion RE1. This makes it possible to suppress the shape abnormality of the recessed portion RE1. Similarly, it is possible to suppress the shape abnormality of the recessed portion RE2.

[0058] 8, the frequency FR2 that defines the period CY2 of the pulse PS2 of the second bias voltage VB2 may be higher than the frequency FR1 that defines the period CY1 of the pulse PS1 of the first bias voltage VB1. ＯＮ 1 is the on-time T of the pulse PS2 of the second bias voltage VB2ＯＮ 2. In this case, the off time T ＯＦ 1 is the off time T of the pulse PS2 of the second bias voltage VB2 ＯＦ The OFF time T of the pulses PS1 and PS2 is longer than that of the pulses PS2. ＯＦ 1. T ＯＦ In the off-time T2, the attraction of ions into the silicon oxide film EF2 or the silicon nitride film EF1 is suppressed, and deposits tend to easily adhere to the side walls of the recesses RE1 and RE2. ＯＦ 1 is the off time T ＯＦ If it is longer than 2, the sidewalls are more easily protected in etching the silicon nitride film EF1 than in etching the silicon oxide film EF2.

[0059] Although various exemplary embodiments have been described above, various additions, omissions, substitutions, and modifications may be made without being limited to the above-described exemplary embodiments. In the silicon-containing film EF, a silicon nitride film EF1 may be provided on the underlayer film UF, and a silicon oxide film EF2 may be provided on the silicon nitride film EF1. In the method MT, step ST3 may be performed before step ST2. In this case, after step ST1, a third period T3 and a fourth period T4 following the third period T3 may be periodically repeated in step ST3. Thereafter, in step ST2, the first period T1 may follow the final fourth period T4 in step ST3. In step ST2, the first period T1 and a second period T2 following the first period T1 may be periodically repeated.

[0060] The following describes experiments performed to evaluate Method MT, but the experiments described below are not intended to limit the present disclosure.

[0061] FIG. 10 shows experimental results of etching performed using an etching method according to one exemplary embodiment. In the experiment, a substrate was prepared, including a silicon oxide film as a film to be etched and a mask on the silicon oxide film. The mask had a hole pattern opening. After the substrate was loaded into a plasma processing chamber, the film to be etched was etched using plasma generated from a process gas containing fluorocarbon gas while a bias voltage was applied to the substrate support. The bias voltage was a pulse wave in which DC voltage pulses were periodically turned on and off. The bias voltage value was 7 kV. The frequency defining the bias voltage pulse period was 400 kHz or 500 kHz. At each frequency, the on-time of the bias voltage pulse was varied between 0.4 microseconds and 0.6 microseconds. After etching, the pattern width (CD: critical dimension) of the bottom of the recess formed in the silicon oxide film was measured on a cross section of the substrate. The pattern width at the top of the recess (the pattern width of the recess at the interface between the silicon oxide film and the mask) was also measured.

[0062] As shown in Figure 10, at a frequency of 500 kHz, the bottom pattern width when the pulse on-time is 0.5 microseconds is approximately 2.1% wider than the bottom pattern width when the pulse on-time is 0.6 microseconds. At a frequency of 500 kHz, the bottom pattern width when the pulse on-time is 0.4 microseconds is approximately 2.5% wider than the bottom pattern width when the pulse on-time is 0.5 microseconds. At a frequency of 400 kHz, the bottom pattern width when the pulse on-time is 0.5 microseconds is approximately 2.1% wider than the bottom pattern width when the pulse on-time is 0.6 microseconds. The bottom pattern width when the pulse on-time is 0.4 microseconds is approximately 1.5% wider than the bottom pattern width when the pulse on-time is 0.5 microseconds. From these results, it was found that the bottom pattern width of the recess formed in the silicon oxide film increases as the pulse on-time of the bias voltage decreases. Furthermore, the pattern width above the recessed portion was approximately 25.5 nm for all frequencies and on-times. This indicates that the increase in the pattern width above the recessed portion can be suppressed even if the on-time of the bias voltage pulse is reduced.

[0063] Various exemplary embodiments included in the present disclosure are now described in [E1] to [E11] below.

[0064] [E1] An etching method comprising: (a) providing a substrate, the substrate including a stacked film including a silicon oxide film and a silicon nitride film; (b) etching the silicon nitride film with a first plasma generated from a first process gas including a hydrofluorocarbon gas while applying a first bias voltage to a substrate support member that supports the substrate; and (c) etching the silicon oxide film with a second plasma generated from a second process gas including a fluorocarbon gas while applying a second bias voltage to the substrate support member, the absolute value of the second bias voltage being greater than the absolute value of the first bias voltage; wherein each of the first bias voltage and the second bias voltage is a pulse wave in which on and off pulses of a DC voltage are periodically repeated, and the on time of the pulse is 0.5 microseconds or less.

[0065] [E2] The etching method according to [E1], wherein the duty ratio of each of the first bias voltage and the second bias voltage is 20% or less.

[0066] [E3] The etching method according to [E1] or [E2], wherein the duty ratio of each of the first bias voltage and the second bias voltage is 5% or more.

[0067] [E4] The etching method according to any one of [E1] to [E3], wherein a frequency that defines the period of the pulse of the second bias voltage is equal to or greater than a frequency that defines the period of the pulse of the first bias voltage.

[0068] [E5] The etching method according to any one of [E1] to [E3], wherein a frequency that defines the period of the pulse of the second bias voltage is higher than a frequency that defines the period of the pulse of the first bias voltage.

[0069] [E6] The etching method according to [E5], wherein the on-time of the pulse of the first bias voltage is the same as the on-time of the pulse of the second bias voltage.

[0070] [E7] The etching method according to any one of [E1] to [E6], wherein a frequency defining the period of the pulse of the first bias voltage is 200 kHz or more and 400 kHz or less, and a frequency defining the period of the pulse of the second bias voltage is 200 kHz or more and 500 kHz or less.

[0071] [E8] The etching method according to any one of [E1] to [E7], wherein the absolute value of the voltage value of the first bias voltage is 1 kV or more and 5 kV or less, and the absolute value of the voltage value of the second bias voltage is 5 kV or more and 20 kV or less.

[0072] [E9] The etching method according to any one of [E1] to [E8], wherein in (b), a first period and a second period following the first period are periodically repeated, the first bias voltage is applied in the first period, and the first bias voltage is not applied to the substrate support portion in the second period; and in (c), a third period and a fourth period following the third period are repeated, the second bias voltage is applied in the third period, and the second bias voltage is not applied to the substrate support portion in the fourth period.

[0073] [E10] The etching method according to [E9], wherein in (b), a first source RF power is supplied to generate the first plasma, the first source RF power having a first power level and a second power level lower than the first power level, and the first power level and the second low power level are periodically repeated, a period during which the first source RF power is at the first power level is synchronized with the first period during which the first bias voltage is applied, and in (c), a second source RF power is supplied to generate the second plasma, the second source RF power having a third power level and a fourth power level lower than the third power level, and the third power level and the fourth power level are periodically repeated, and a period during which the second source RF power is at the third power level is synchronized with the third period during which the second bias voltage is applied.

[0074] [E11] A plasma processing apparatus comprising: a chamber; a substrate support for supporting a substrate in the chamber, the substrate including a stacked film including a silicon oxide film and a silicon nitride film; a gas supply unit configured to supply a first process gas including a hydrofluorocarbon gas and a second process gas including a fluorocarbon gas into the chamber; a plasma generation unit configured to generate a first plasma from the first process gas and a second plasma from the second process gas; and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit so as to etch the silicon nitride film with the first plasma while applying a first bias voltage to the substrate support unit, and to etch the silicon oxide film with the second plasma while applying a second bias voltage to the substrate support unit, an absolute value of the second bias voltage being greater than an absolute value of the first bias voltage, and each of the first bias voltage and the second bias voltage being a pulse wave in which pulses are periodically turned on and off, The plasma processing apparatus, wherein the pulse on time is 0.5 microseconds or less.

[0075] 1... plasma processing apparatus, 10... plasma processing chamber, 11... substrate support part, 12... plasma generation part, 2... control part, 20... gas supply part, EF1... silicon nitride film, EF2... silicon oxide film, PS1... first bias voltage pulse, PS2... second bias voltage pulse, PM1... first plasma, PM2... second plasma, T ＯＮ 1...on time of the first bias voltage pulse, T ＯＮ 2...on time of the pulse of the second bias voltage, VB1...first bias voltage, VB2...second bias voltage, W...substrate.

Claims

1. An etching method comprising: (a) providing a substrate, the substrate including a laminated film including a silicon oxide film and a silicon nitride film; (b) etching the silicon nitride film with a first plasma generated from a first process gas including a hydrofluorocarbon gas while applying a first bias voltage to a substrate support that supports the substrate; and (c) etching the silicon oxide film with a second plasma generated from a second process gas including a fluorocarbon gas while applying a second bias voltage to the substrate support, the absolute value of the second bias voltage being greater than the absolute value of the first bias voltage, wherein each of the first bias voltage and the second bias voltage is a pulse wave in which a DC voltage pulse is periodically turned on and off, and the on-time of the pulse is 0.5 microseconds or less.

2. The etching method according to claim 1, wherein the duty ratio of each of the first bias voltage and the second bias voltage is 20% or less.

3. The etching method according to claim 1 or 2, wherein the duty ratio of each of the first bias voltage and the second bias voltage is 5% or more.

4. An etching method according to claim 1 or 2, wherein a frequency defining the period of the pulse of the second bias voltage is equal to or greater than a frequency defining the period of the pulse of the first bias voltage.

5. An etching method according to claim 1 or 2, wherein a frequency defining the period of the pulse of the second bias voltage is higher than a frequency defining the period of the pulse of the first bias voltage.

6. The etching method of claim 5, wherein the on-time of the pulse of the first bias voltage is the same as the on-time of the pulse of the second bias voltage.

7. An etching method according to claim 1 or 2, wherein a frequency defining the period of the pulse of the first bias voltage is not less than 200 kHz and not more than 400 kHz, and a frequency defining the period of the pulse of the second bias voltage is not less than 200 kHz and not more than 500 kHz.

8. The etching method according to claim 1 or 2, wherein the absolute value of the voltage value of the first bias voltage is 1 kV or more and 5 kV or less, and the absolute value of the voltage value of the second bias voltage is 5 kV or more and 20 kV or less.

9. The etching method according to claim 1 or 2, wherein in (b), a first period and a second period following the first period are repeated periodically, the first bias voltage is applied in the first period, and the first bias voltage is not applied to the substrate support portion in the second period; and in (c), a third period and a fourth period following the third period are repeated, the second bias voltage is applied in the third period, and the second bias voltage is not applied to the substrate support portion in the fourth period.

10. The etching method according to claim 9, wherein in (b), a first source RF power for generating the first plasma is supplied, the first source RF power having a first power level and a second power level lower than the first power level, and the first power level and the second power level are periodically repeated, a period during which the first source RF power is at the first power level is synchronized with the first period during which the first bias voltage is applied, and in (c), a second source RF power for generating the second plasma is supplied, the second source RF power having a third power level and a fourth power level lower than the third power level, and the third power level and the fourth power level are periodically repeated, and a period during which the second source RF power is at the third power level is synchronized with the third period during which the second bias voltage is applied.

11. A plasma processing apparatus comprising: a chamber; a substrate support for supporting a substrate in the chamber, the substrate including a laminated film including a silicon oxide film and a silicon nitride film; a gas supply unit configured to supply a first process gas including a hydrofluorocarbon gas and a second process gas including a fluorocarbon gas into the chamber; a plasma generation unit configured to generate a first plasma from the first process gas and generate a second plasma from the second process gas; and a control unit, wherein the control unit is configured to control the gas supply unit and the plasma generation unit to etch the silicon nitride film with the first plasma while applying a first bias voltage to the substrate support unit, and to etch the silicon oxide film with the second plasma while applying a second bias voltage to the substrate support unit, an absolute value of the voltage value of the second bias voltage being greater than an absolute value of the voltage value of the first bias voltage, and each of the first bias voltage and the second bias voltage is a pulse wave in which pulses are periodically turned on and off, The plasma processing apparatus, wherein the pulse on-time is 0.5 microseconds or less.

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