Three-dimensional random access memory with improved performance

Abstract

Provided is a three-dimensional random access memory with improved performance, comprising: gate electrodes and interlayer insulating layers alternately stacked in the vertical direction while extending in the horizontal direction on a substrate; and vertical structures penetrating the gate electrodes and extending in the vertical direction, each of the vertical structures including a vertical electrode and a polarization generation dielectric pattern encompassing the outer surface of the vertical electrode, wherein each of the vertical structures has a protrusion protruding in the horizontal direction from each of the interlayer insulating layers.

Description

3D random access memory with improved performance

[0001] The following examples describe a three-dimensional random access memory that improves performance by increasing the capacitor area or preventing program malfunctions.

[0002] Semiconductor devices such as DRAM (Dynamic Random Access Memory) have a MOS transistor including a source and a drain, a capacitor electrically connected to the source of the MOS transistor, and wiring such as a bit line electrically connected to the drain of the MOS transistor.

[0003] These DRAMs began to be implemented in a three-dimensional structure, moving away from the two-dimensional structure, in line with the trend toward high integration to secure storage space.

[0004] A 3D DRAM is implemented to support and operate random access based on two terminals of the gate electrode and the vertical electrode within the memory cell string, including a semiconductor structure including interlayer insulating layers and gate electrodes that are alternately stacked in the vertical direction and a memory cell string that extends vertically through the semiconductor structure.

[0005] However, existing 3D DRAMs have a problem in that they cannot meet the capacitance required for memory devices because the capacitor area of ​​the ferroelectric film used as a data storage element with respect to the gate electrode is small.

[0006] In addition, conventional 3D random access memory has a problem in that some unselected memory cells may be programmed due to the voltage applied through the vertical electrode affecting the unselected memory cells.

[0007] Therefore, there is a need to propose a technology to increase the capacitor area and a technology to prevent program malfunction.

[0008]

[0009] One embodiment proposes a three-dimensional random access memory having a structure in which a vertical structure protrudes in a horizontal direction and a method for manufacturing the same, in order to achieve the technical task of increasing a capacitor area.

[0010] At this time, one embodiment proposes a three-dimensional random access memory and a method for manufacturing the same by implementing a structure in which a protrusion of a vertical structure is interposed between gate electrodes, so that a polarization generating dielectric pattern used as a data storage element has contact surfaces of an outer lower surface, an outer side surface, an outer upper surface, and an inner side surface for each of the gate electrodes.

[0011] In addition, one embodiment proposes a three-dimensional random access memory and a method for manufacturing the same, in which a polarization-generating dielectric pattern has contact surfaces on an outer side, an inner upper surface, an inner side, and an inner lower surface for each of the gate electrodes through a structure in which a protrusion of a vertical structure is implemented on each of the gate electrodes with the same thickness as each of the gate electrodes.

[0012] In addition, one embodiment proposes a three-dimensional random access memory having a structure of a data storage pattern including at least one insulating pattern and a memory operating method thereof to solve the problem that unselected memory cells may be partially programmed by being affected by a voltage applied through a vertical electrode.

[0013] However, the technical problems to be solved by the present invention are not limited to the above problems, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0014] According to one embodiment, a three-dimensional random access memory includes gate electrodes and interlayer insulating layers that are formed to extend horizontally on a substrate and are alternately stacked in a vertical direction; and vertical structures formed to extend vertically through the gate electrodes, each of the vertical structures including a vertical electrode and a polarization-generating dielectric pattern surrounding an outer surface of the vertical electrode, wherein each of the vertical structures may have a protrusion protruding in the horizontal direction from each of the interlayer insulating layers.

[0015] According to one aspect, the protrusions of each of the vertical structures may be formed to have the same thickness as the thickness of each of the interlayer insulating layers.

[0016] According to another aspect, the polarization generating dielectric pattern may be characterized in that it has a contact surface of an outer lower surface, an outer side surface, an outer upper surface, and an inner side surface for each of the gate electrodes, as each of the protrusions of the vertical structures is implemented in a structure in which the protrusions are interposed between the gate electrodes.

[0017] According to one embodiment, a three-dimensional random access memory includes gate electrodes and interlayer insulating layers that are formed to extend horizontally on a substrate and are alternately stacked in a vertical direction; and vertical structures formed to extend vertically through the gate electrodes, each of the vertical structures including a vertical electrode and a polarization-generating dielectric pattern surrounding an outer surface of the vertical electrode, wherein each of the vertical structures may have a protrusion protruding in the horizontal direction from each of the gate electrodes.

[0018] According to one aspect, the protrusions of each of the vertical structures may be formed to have the same thickness as the thickness of each of the gate electrodes.

[0019] According to another aspect, the polarization generating dielectric pattern may be characterized in that each of the protrusions of the vertical structures is implemented on each of the gate electrodes with the same thickness as each of the gate electrodes, thereby having a contact surface of an outer side surface, an inner upper surface, an inner side surface, and an inner lower surface for each of the gate electrodes.

[0020] According to another aspect, the three-dimensional random access memory may be characterized by having a structure in which the gate electrodes, the polarization generating dielectric pattern, and the vertical electrode are sequentially contacted and connected.

[0021] According to another aspect, the protrusions of each of the vertical structures may be characterized by including a protrusion of the polarization generating dielectric pattern and a protrusion of the vertical electrode.

[0022] According to another aspect, the polarization-generating dielectric pattern may be characterized by being formed of either a ferroelectric material or an anti-ferroelectric material.

[0023] According to one embodiment, a three-dimensional random access memory may include gate electrodes that are formed to extend horizontally on a substrate and are vertically spaced apart from each other and stacked; and vertical structures that penetrate the gate electrodes and extend vertically, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern including at least one insulating pattern and forming memory cells corresponding to the gate electrodes.

[0024] According to one aspect, the data storage pattern may be characterized by including at least one insulating pattern on the outer wall, the inner wall or the interior.

[0025] According to another aspect, the at least one insulating pattern may be characterized as being used for the purpose of preventing a memory operation on unselected memory cells excluding the target memory cell among the memory cells during a memory operation on the target memory cell.

[0026] According to another aspect, the at least one insulating pattern may be characterized in that it increases an operating voltage required for the memory operation or increases a coercive field in the unselected memory cells, thereby preventing a polarization phenomenon from occurring in the unselected memory cells.

[0027] According to another aspect, the thickness of the at least one insulating pattern may be determined to be a value that satisfies a condition that enables a memory operation for the target memory cell and a condition that prevents a memory operation for the non-selected memory cells.

[0028] According to another aspect, the at least one insulating pattern may be formed of a material that satisfies a condition for enabling a memory operation for the target memory cell and a condition for preventing a memory operation for the non-selected memory cells.

[0029] According to another aspect, the at least one insulating pattern may be formed of at least one material selected from the group consisting of a silicon-based material, a high-k material, a low-k material, and an oxide semiconductor material.

[0030] One embodiment can achieve the technical task of increasing the capacitor area by proposing a three-dimensional random access memory having a structure in which a protrusion of a vertical structure protrudes in a horizontal direction and a method for manufacturing the same.

[0031] At this time, one embodiment can propose a three-dimensional random access memory and a method for manufacturing the same by implementing a structure in which a protrusion of a vertical structure is interposed between gate electrodes, so that a polarization generating dielectric pattern used as a data storage element has contact surfaces of an outer lower surface, an outer side surface, an outer upper surface, and an inner side surface for each of the gate electrodes.

[0032] In addition, one embodiment can propose a three-dimensional random access memory and a method for manufacturing the same, in which a polarization generating dielectric pattern has contact surfaces on an outer side, an inner upper surface, an inner side, and an inner lower surface for each of the gate electrodes through a structure in which a protrusion of a vertical structure is implemented on each of the gate electrodes with the same thickness as each of the gate electrodes.

[0033] In addition, one embodiment proposes a three-dimensional random access memory having a structure of a data storage pattern including at least one insulating pattern and a memory operation method thereof, thereby solving a problem in which unselected memory cells are affected by a voltage applied through a vertical electrode and thus some of the unselected memory cells may be programmed.

[0034] However, the effects of the present invention are not limited to the above effects, and can be expanded in various ways without departing from the technical spirit and scope of the present invention.

[0035]

[0036] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0037] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0038] FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0039] FIG. 4 is an enlarged cross-sectional view of a portion of a three-dimensional random access memory to illustrate an increased capacitor area in the three-dimensional random access memory according to one embodiment.

[0040] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0041] FIGS. 6A to 6G are cross-sectional views illustrating a three-dimensional random access memory to explain a method of manufacturing a three-dimensional random access memory according to one embodiment.

[0042] FIG. 7 is a plan view illustrating a three-dimensional random access memory according to another embodiment.

[0043] FIG. 8 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2.

[0044] FIG. 9 is an enlarged cross-sectional view of a portion of a three-dimensional random access memory to illustrate an increased capacitor area in a three-dimensional random access memory according to another embodiment.

[0045] FIG. 10 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0046] FIGS. 11A to 11G are cross-sectional views illustrating a three-dimensional random access memory to explain a method of manufacturing a three-dimensional random access memory according to another embodiment.

[0047] FIG. 12 is a plan view illustrating a three-dimensional random access memory according to one embodiment.

[0048] Fig. 13 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of Fig. 12.

[0049] FIGS. 14A to 14B are diagrams illustrating the effect of at least one insulating pattern of a three-dimensional random access memory according to one embodiment.

[0050] FIGS. 15A to 15B are cross-sectional views illustrating a three-dimensional random access memory to explain the arrangement structure of at least one insulating pattern according to another embodiment.

[0051] FIG. 16 is a flow chart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment.

[0052] FIG. 17 is a diagram for explaining a memory operation method of a three-dimensional random access memory according to one embodiment.

[0053] FIG. 18 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0054] Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings. However, the present invention is not limited or restricted by these embodiments. In addition, the same reference numerals in each drawing represent the same components.

[0055] In addition, the terminology used in this specification is a term used to appropriately express the preferred embodiments of the present invention, and this may vary depending on the intention of the viewer or operator, or the customs of the field to which the present invention belongs. Therefore, the definition of these terms should be determined based on the contents throughout this specification. For example, in this specification, the singular also includes the plural unless specifically stated in the phrase. In addition, the terms "comprises" and / or "comprising" as used herein do not exclude the presence or addition of one or more other components, steps, operations, and / or elements with respect to the mentioned components, steps, operations, and / or elements. In addition, although the terms first, second, etc. are used in this specification to describe various regions, directions, shapes, etc., these regions, directions, and shapes should not be limited by these terms. These terms are only used to distinguish a certain region, direction, or shape from another region, direction, or shape. Therefore, a part referred to as a first part in one embodiment may be referred to as a second part in another embodiment.

[0056] It should also be understood that the various embodiments of the present invention, while different, are not necessarily mutually exclusive. For example, specific shapes, structures, and characteristics described herein may be implemented in other embodiments without departing from the spirit and scope of the present invention. Furthermore, it should be understood that the location, arrangement, or configuration of individual components within each of the disclosed embodiments may be modified without departing from the spirit and scope of the present invention.

[0057] Hereinafter, with reference to the drawings, a three-dimensional random access memory having a structure in which a protrusion of a vertical structure protrudes in a horizontal direction and a method for manufacturing the same will be described in detail.

[0058]

[0059] FIG. 1 is a simplified circuit diagram illustrating a three-dimensional random access memory according to one embodiment.

[0060] Referring to FIG. 1, a three-dimensional random access memory according to an embodiment includes a plurality of bit line horizontal parts (BL1_horizontal part, BL2_horizontal part, BL3_horizontal part; BLH) and a plurality of bit line vertical parts (BL1_vertical part (BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part (BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part (BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and a plurality of word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3(WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm(WLm / 1, WLm / 2, ..., WLm / n)), multiple bit line vertical parts (BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV) and multiple word lines (WL1(WL1 / 1, WL1 / 2, ..., WL1 / n), WL2(WL2 / 1, WL2 / 2, ..., WL2 / n), A plurality of memory cells can be configured to be arranged at the intersection of WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm (WLm / 1, WLm / 2, ..., WLm / n)).Accordingly, the plurality of memory cells may include a plurality of memory cell strings (CSTR; hereinafter, cell strings) along a plurality of bit line vertical parts ((BL1_vertical part(BL1 / 1_Vertical part, BL1 / 2_Vertical part, BL1 / 3_Vertical part), BL2_vertical part(BL2 / 1_Vertical part, BL2 / 2_Vertical part, BL2 / 3_Vertical part), BL3_vertical part(BL3 / 1_Vertical part, BL3 / 2_Vertical part, BL3 / 3_Vertical part); BLV).

[0061] The bit line horizontal portions (BLH) can be arranged two-dimensionally while being spaced apart from each other along the first direction (D1) and extending in the second direction (D2). Here, the first direction (D1), the second direction (D2), and the third direction (D3) are each orthogonal to each other and can form a rectangular coordinate system defined by the X, Y, and Z axes.

[0062] Each of the bit line horizontal portions (BLH) may have a plurality of cell strings (CSTR) connected in parallel. Each of the cell strings (CSTR) includes a bit line vertical portion (BLV), and each of the bit line horizontal portions (BLH) may have a plurality of bit line vertical portions (BLV) connected in parallel.

[0063] The cell strings (CSTR) may be arranged to be spaced apart from each other along the second direction (D2) for each bit line while being formed to extend in the third direction (D3). According to an embodiment, each of the cell strings (CSTR) may include memory cell transistors (MCT) arranged corresponding to word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm (WLm / 1, WLm / 2, ..., WLm / n)) and string select transistors (SST; hereinafter, select transistors) arranged corresponding to string select lines (SSL1, SSL2, SSL3). Each of the memory cell transistors (MCT) may include a data storage element.

[0064] More specifically, one cell string (CSTR) may be composed of one select transistor (SST) located at the top of the string closest to the bit line horizontal portions (BLH) and a plurality of memory cell transistors (MCT) located at different distances from the bit line horizontal portions (BLH). That is, the memory cell transistors (MCT) may be connected in series while being arranged along the third direction (D3).

[0065] The select transistor (SST) can be controlled by a string select line (SSL), and the memory cell transistors (MCT) can be controlled by word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm (WLm / 1, WLm / 2, ..., WLm / n)).

[0066] Here, the gate electrode (EL-SSL) of the selection transistor (SST) may be connected to the string selection line (SSL) and may be in an equipotential state, and the gate electrodes (EL-WL) of the memory cell transistors (MCT) may be commonly connected to one of the word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm (WLm / 1, WLm / 2, ..., WLm / n)) and may be in an equipotential state.

[0067]

[0068] FIG. 2 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 3 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 4 is an enlarged cross-sectional view illustrating a portion of a three-dimensional random access memory to explain an increased capacitor area in the three-dimensional random access memory according to one embodiment.

[0069] The substrate (SUB) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0070] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0071] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0072] Referring again to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1, 2, ..., WLn-1, WLn) sequentially stacked on the substrate (SUB).

[0073] Each of the gate electrodes (EL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL) may be formed of a conductive material. For example, each of the gate electrodes (EL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0074] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a step structure (not shown) along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the gate electrode positioned at the uppermost position among the gate electrodes (EL) may have the shortest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). On the other hand, the gate electrode positioned at the lowermost position among the gate electrodes (EL) may have the longest length in the first direction (D1) and the closest distance from the substrate (SUB) in the third direction (D3).

[0075] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0076] A plurality of vertical holes (H) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the vertical holes (H). The vertical structures (VS) may be a plurality of cell strings (CSTR) illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0077] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL). For example, as illustrated in FIG. 2, twelve vertical structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited thereto.

[0078] As vertical structures (VS) are formed in a plate shape to form an array of multiple columns and rows on a horizontal plane of gate electrodes (EL), the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved.

[0079] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0080] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0081] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 1.

[0082] To this end, each of the vertical structures (VS) may include a polarization-generating dielectric pattern (PDP) and a vertical electrode (VE; corresponding to the bit line vertical portion (BLV) illustrated in FIG. 1). In each of the vertical structures (VS), the polarization-generating dielectric pattern (PDP) may have a pipe shape or a macaroni shape with an open top, and the vertical electrode (VE) may have a shape that fills a space from the bottom to a certain height among the inner spaces of the polarization-generating dielectric pattern (PDP) while the outer surface is wrapped by the polarization-generating dielectric pattern (PDP). However, without being limited thereto, the polarization-generating dielectric pattern (PDP) in each of the vertical structures (VS) may also have a pipe shape or a macaroni shape that is open to the bottom.

[0083] At this time, although not shown in the drawing, a selection transistor (not shown) may be placed at the uppermost part (upper part of the vertical electrode (VE)) of the inner space of the polarization generating dielectric pattern (PDP).

[0084] A polarization-generating dielectric pattern (PDP) surrounds the outer surface of the vertical electrode (VE) and can be in contact with the sides of the gate electrodes (EL) toward the outside. Accordingly, regions of the polarization-generating dielectric pattern (PDP) corresponding to the gate electrodes (EL-WL) can form memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the vertical electrode (VE). Hereinafter, applying a voltage to the vertical electrode (VE) means that a voltage is applied to a bit line horizontal portion (BLH) connected to the vertical electrode (VE) and transmitted to the vertical electrode (VE).

[0085] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 1. To this end, the polarization generating dielectric pattern (PDP) may be a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a vertical electrode (VE), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0086] For example, a ferroelectric material can be used as a polarization-generating dielectric pattern (PDP), and as a ferroelectric material, at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0087] As another example, an antiferroelectric material can be used as a polarizable dielectric pattern (PDP), and an antiferroelectric material is ZrO. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0088] Although the drawing illustrates that the polarization generating dielectric pattern (PDP) extends in a vertical direction (e.g., in the third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer surface of the vertical electrode (VE).

[0089] The lower surface of the polarization generating dielectric pattern (PDP) may be positioned at a lower level than the lower surface of the lowest one among the gate electrodes (EL-WL) and may be formed to be in contact with the substrate (SUB).

[0090] The vertical electrode (VE) may be connected to each of the bit line horizontal portions (BLH) positioned on the upper portions of the vertical structures (VS) while being included in each of the vertical structures (VS). To this end, the upper surface of the vertical electrode (VE) may be substantially coplanar with the polarization generating dielectric pattern (PDP) so as to directly contact the bit line horizontal portions (BLH).

[0091] At this time, at least two bit line horizontal parts (BLH) are positioned at the same height on the upper portion of the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS) so as to be respectively connected to different bit line horizontal parts (BLH). That is, the vertical structures (VS) arranged in the same row in the array may be respectively connected to different bit line horizontal parts (BLH) through the bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS).

[0092] The vertical electrode (VE) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0093] The lower surface of the vertical electrode (VE) may be positioned at a level lower than the lower surface of the lowest of the gate electrodes (EL) and may be spaced apart from the substrate (SUB) by a certain amount or more, but is not limited thereto.

[0094] Each of these vertical structures (VS) may have a protrusion (VS-PP) protruding in a horizontal direction (e.g., in the first direction (D1) and the second direction (D2)) from each of the interlayer insulating layers (ILD) to increase the capacitor area.

[0095] In more detail, the protrusion (VS-PP) of each of the vertical structures (VS) is formed with the same thickness as the thickness of each of the interlayer insulating layers (ILD), and is composed of the protrusion (PDP-PP) of the polarization generating dielectric pattern (PDP) and the protrusion (VE-PP) of the vertical electrode (VE), so that it can be implemented as a structure interposed between the gate electrodes (EL).

[0096] As the protrusions (VS-PP) of each of the vertical structures (VS) are implemented in a structure in which they protrude horizontally from each of the interlayer insulating layers (ILD) and are interposed between the gate electrodes (EL), the polarization generating dielectric pattern (PDP) can have contact surfaces of an outer lower surface (410), an outer side surface (420), an outer upper surface (430), and an inner side surface (440) for each of the gate electrodes (EL).

[0097] Considering that the conventional two-terminal based three-dimensional random access memory only has contact surfaces on the outer side and the inner side for each of the gate electrodes (EL), a three-dimensional random access memory having a structure including a protrusion (VS-PP) of each of the vertical structures (VS) can have the effect of having a significantly increased capacitor area compared to the conventional two-terminal based three-dimensional random access memory.

[0098] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench, thereby isolating the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0099] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0100] Bit line horizontal portions (BLH) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0101] The three-dimensional random access memory described above is not limited or restricted to the described structure, and can be implemented in various structures based on vertical structures (VS) including protrusions (VS-PP) protruding in the horizontal direction from each of the interlayer insulating layers (ILD) according to an implementation example.

[0102] A three-dimensional random access memory such as this can perform a memory operation in response to a voltage applied between a first terminal of the vertical electrode (VE) and a second terminal of the gate electrode (EL), based on a structure (e.g., MFM) in which gate electrodes (EL), a polarization generating dielectric pattern (PDP), and vertical electrodes (VE) are sequentially contacted and connected.

[0103] A detailed description of a manufacturing method for manufacturing a three-dimensional random access memory having the described structure will be described with reference to FIGS. 5 and 6a to 6g below.

[0104]

[0105] FIG. 5 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to one embodiment, and FIGS. 6a to 6g are cross-sectional views illustrating a three-dimensional random access memory to explain a method for manufacturing a three-dimensional random access memory according to one embodiment.

[0106] The manufacturing method described below is for manufacturing a three-dimensional random access memory having the structure described above with reference to FIGS. 1 to 4, and is assumed to be performed by an automated and mechanized manufacturing system, and may utilize a gate replacement process method.

[0107] Referring to the drawings, in step S510, the manufacturing system can prepare a semiconductor structure (SEMI-STR) as illustrated in FIG. 6a. Here, the semiconductor structure (SEM-STR) can include memory cell layers (MEM) and interlayer insulating layers (ILD) that are alternately stacked in the vertical direction while being formed in a plate shape extending horizontally on the substrate (SUB).

[0108] Memory cell layers (MEM) refer to sacrificial layers that secure space for gate electrodes (EL) to be formed, and can be formed of, for example, silicon nitride.

[0109] In step (S520), the manufacturing system can extend vertical holes (H) penetrating the semiconductor structure (SEMI-STR) in a vertical direction (e.g., a third direction (D3)) as illustrated in FIG. 6b so as to form an array in which the vertical structures (VS) are composed of a plurality of columns and rows on a horizontal plane.

[0110] In step (S530), the manufacturing system can recess a portion (ILD-P1) of each of the interlayer insulating layers (ILD) in a horizontal direction (e.g., a first direction (D1) and a second direction (D2)) through vertical holes (H) as illustrated in FIG. 6c.

[0111] More specifically, the manufacturing system can recess a horizontal portion (ILD-P1) of each of the interlayer insulating layers (ILD) such that at least a horizontal portion (ILD-P2) remains in each of the interlayer insulating layers (ILD).

[0112] As a portion (ILD-P1) of each of the interlayer insulating layers (ILD) in the horizontal direction is recessed in this way, the protrusions (VS-PP) formed in the recessed spaces (RS) of each of the interlayer insulating layers (ILD) can have the same thickness as the thickness of each of the interlayer insulating layers (ILD) and can have a structure interposed between the gate electrodes (EL).

[0113] At this time, gate electrodes (EL) are formed in a horizontal portion (ILD-P1) recessed in each of the interlayer insulating layers (ILD) through a step (S570) described below, and the manufacturing system can control the depth of the horizontal portion (ILD-P1) recessed according to the design parameter (horizontal thickness) of the gate electrode required in the 3D random access memory.

[0114] In step (S540), the manufacturing system can form a polarization generating dielectric pattern (PDP) on the inner upper surface, inner side surface, inner lower surface of each of the recessed spaces (RS) and the inner surface of each of the vertical holes (H), as illustrated in FIG. 6d.

[0115] In step (S550), the manufacturing system can remove memory cell layers (MEM) as illustrated in FIG. 6e.

[0116] In step (S560), the manufacturing system can form vertical electrodes (VE) in each of the spaces (PDP-S) in which a polarization-generating dielectric pattern (PDP) is formed and in each of the vertical holes (PDP-H) in which a polarization-generating dielectric pattern (PDP) is formed, as illustrated in FIG. 6f.

[0117] In step (S570), the manufacturing system can form gate electrodes (EL) in spaces (MEM-S) from which memory cell layers (MEM) have been removed, as illustrated in FIG. 6g.

[0118] Instead of being performed sequentially, the steps (S510 to S570) described above may be performed with the order of some steps reversed. For example, steps (S550) and (S570) may be performed sequentially after step (S560) is performed before step (S550).

[0119] Instead of being performed sequentially, the steps (S510 to S570) described above may be performed with the order of some steps reversed. For example, steps (S550) and (S570) may be performed sequentially after step (S560) is performed before step (S550).

[0120] Here, steps (S560, S570) are performed simultaneously in batches, so that the entire manufacturing process can be simplified.

[0121] In this way, the manufacturing system forms a polarization generating dielectric pattern (PDP) on the inner upper surface, inner side surface, and inner lower surface of each of the recessed spaces (RS) through steps (S540) and (S560), and then forms a vertical electrode (VE) in each of the spaces (PDP-S) where the polarization generating dielectric pattern (PDP) is formed, thereby forming a protrusion (VE-PP) of the vertical electrode (VE) and a protrusion (VS-PP) of each of the vertical structures (VS) including the polarization generating dielectric pattern (PDP-PP).

[0122] In addition, the manufacturing system can implement a structure in which gate electrodes (EL), a polarization generating dielectric pattern (PDP), and a vertical electrode (VE) are sequentially contacted and connected through steps (S540), (S560), and (S570).

[0123] Although not depicted as a separate step, the manufacturing system can form bit line horizontal portions (BLH) extending horizontally on top of the vertical structures (VS) after step (S570). During this process, the manufacturing system can connect the vertical electrode (VE) included in each of the vertical structures (VS) to each of the bit line horizontal portions (BLH) via a bit line plug (BLPG).

[0124]

[0125] FIG. 7 is a plan view illustrating a three-dimensional random access memory according to another embodiment, FIG. 8 is a cross-sectional view illustrating a three-dimensional random access memory according to another embodiment, corresponding to a cross-section taken along line A-A' of FIG. 2, and FIG. 9 is an enlarged cross-sectional view illustrating a portion of a three-dimensional random access memory to explain an increased capacitor area in a three-dimensional random access memory according to another embodiment.

[0126] The substrate (SUB) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0127] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0128] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0129] Referring again to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1, 2, ..., WLn-1, WLn) sequentially stacked on the substrate (SUB).

[0130] Each of the gate electrodes (EL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL) may be formed of a conductive material. For example, each of the gate electrodes (EL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0131] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a step structure (not shown) along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the gate electrode positioned at the uppermost position among the gate electrodes (EL) may have the shortest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). On the other hand, the gate electrode positioned at the lowermost position among the gate electrodes (EL) may have the longest length in the first direction (D1) and the closest distance from the substrate (SUB) in the third direction (D3).

[0132] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0133] A plurality of vertical holes (H) penetrating through a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the vertical holes (H). The vertical structures (VS) may be a plurality of cell strings (CSTR) illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0134] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL). For example, as illustrated in FIG. 2, twelve vertical structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited thereto.

[0135] As vertical structures (VS) are formed in a plate shape to form an array of multiple columns and rows on a horizontal plane of gate electrodes (EL), the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved.

[0136] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0137] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0138] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 1.

[0139] To this end, each of the vertical structures (VS) may include a polarization-generating dielectric pattern (PDP) and a vertical electrode (VE; corresponding to the bit line vertical portion (BLV) illustrated in FIG. 1). In each of the vertical structures (VS), the polarization-generating dielectric pattern (PDP) may have a pipe shape or a macaroni shape with an open top, and the vertical electrode (VE) may have a shape that fills a space from the bottom to a certain height among the inner spaces of the polarization-generating dielectric pattern (PDP) while the outer surface is wrapped by the polarization-generating dielectric pattern (PDP). However, without being limited thereto, the polarization-generating dielectric pattern (PDP) in each of the vertical structures (VS) may also have a pipe shape or a macaroni shape that is open to the bottom.

[0140] At this time, although not shown in the drawing, a selection transistor (not shown) may be placed at the uppermost part (upper part of the vertical electrode (VE)) of the inner space of the polarization generating dielectric pattern (PDP).

[0141] A polarization-generating dielectric pattern (PDP) surrounds the outer surface of the vertical electrode (VE) and can be in contact with the sides of the gate electrodes (EL) toward the outside. Accordingly, regions of the polarization-generating dielectric pattern (PDP) corresponding to the gate electrodes (EL-WL) can form memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the vertical electrode (VE). Hereinafter, applying a voltage to the vertical electrode (VE) means that a voltage is applied to a bit line horizontal portion (BLH) connected to the vertical electrode (VE) and transmitted to the vertical electrode (VE).

[0142] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 1. To this end, the polarization generating dielectric pattern (PDP) may be a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a vertical electrode (VE), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0143] For example, a ferroelectric material can be used as a polarization-generating dielectric pattern (PDP), and as a ferroelectric material, at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0144] As another example, an antiferroelectric material can be used as a polarizable dielectric pattern (PDP), and an antiferroelectric material is ZrO. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0145] Although the drawing illustrates that the polarization generating dielectric pattern (PDP) extends in a vertical direction (e.g., in the third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer surface of the vertical electrode (VE).

[0146] The lower surface of the polarization generating dielectric pattern (PDP) may be positioned at a lower level than the lower surface of the lowest one among the gate electrodes (EL-WL) and may be formed to be in contact with the substrate (SUB).

[0147] The vertical electrode (VE) may be connected to each of the bit line horizontal portions (BLH) positioned on the upper portions of the vertical structures (VS) while being included in each of the vertical structures (VS). To this end, the upper surface of the vertical electrode (VE) may be substantially coplanar with the polarization generating dielectric pattern (PDP) so as to directly contact the bit line horizontal portions (BLH).

[0148] At this time, at least two bit line horizontal parts (BLH) are positioned at the same height on the upper portion of the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS) so as to be respectively connected to different bit line horizontal parts (BLH). That is, the vertical structures (VS) arranged in the same row in the array may be respectively connected to different bit line horizontal parts (BLH) through the bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS).

[0149] The vertical electrode (VE) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0150] The lower surface of the vertical electrode (VE) may be positioned at a level lower than the lower surface of the lowest of the gate electrodes (EL) and may be spaced apart from the substrate (SUB) by a certain amount or more, but is not limited thereto.

[0151] Each of these vertical structures (VS) may have a protrusion (VS-PP) protruding in a horizontal direction (e.g., in the first direction (D1) and the second direction (D2)) from each of the gate electrodes (EL) to increase the capacitor area.

[0152] More specifically, the protrusion (VS-PP) of each of the vertical structures (VS) can be formed with the same thickness as the thickness of each of the gate electrodes (EL), and is composed of a protrusion (PDP-PP) of a polarization generating dielectric pattern (PDP) and a protrusion (VE-PP) of a vertical electrode (VE).

[0153] In this way, since the protrusions (VS-PP) of each of the vertical structures (VS) are implemented with the same thickness as each of the gate electrodes (EL) while protruding horizontally from each of the gate electrodes (EL), the polarization generating dielectric pattern (PDP) can have contact surfaces of an outer side surface (910), an inner upper surface (920), an inner side surface (930), and an inner lower surface (940) for each of the gate electrodes (EL).

[0154] Considering that the conventional two-terminal based three-dimensional random access memory only has contact surfaces on the outer side and the inner side for each of the gate electrodes (EL), a three-dimensional random access memory having a structure including a protrusion (VS-PP) of each of the vertical structures (VS) can have the effect of having a significantly increased capacitor area compared to the conventional two-terminal based three-dimensional random access memory.

[0155] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench, thereby isolating the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0156] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0157] Bit line horizontal portions (BLH) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0158] The three-dimensional random access memory described above is not limited or restricted to the described structure, and can be implemented in various structures based on vertical structures (VS) including protrusions (VS-PP) protruding horizontally from each of the gate electrodes (EL) according to an implementation example.

[0159] A three-dimensional random access memory such as this can perform a memory operation in response to a voltage applied between a first terminal of the vertical electrode (VE) and a second terminal of the gate electrode (EL), based on a structure (e.g., MFM) in which gate electrodes (EL), a polarization generating dielectric pattern (PDP), and vertical electrodes (VE) are sequentially contacted and connected.

[0160] A detailed description of a manufacturing method for manufacturing a three-dimensional random access memory having the described structure is described with reference to FIGS. 10 and 11a to 11g below.

[0161]

[0162] FIG. 10 is a flow chart illustrating a method for manufacturing a three-dimensional random access memory according to another embodiment, and FIGS. 11a to 11g are cross-sectional views illustrating a three-dimensional random access memory to explain a method for manufacturing a three-dimensional random access memory according to another embodiment.

[0163] The manufacturing method described below is for manufacturing a three-dimensional random access memory having the structure described above with reference to FIGS. 1 and 7 to 9, and is assumed to be performed by an automated and mechanized manufacturing system, and may utilize a gate replacement process method.

[0164] Referring to the drawings, in step S1010, the manufacturing system can prepare a semiconductor structure (SEMI-STR) as illustrated in FIG. 11a. Here, the semiconductor structure (SEM-STR) can include memory cell layers (MEM) and interlayer insulating layers (ILD) that are alternately stacked in the vertical direction while being formed in a plate shape extending horizontally on a substrate (SUB).

[0165] Memory cell layers (MEM) refer to sacrificial layers that secure space for gate electrodes (EL) to be formed, and can be formed of, for example, silicon nitride.

[0166] In step (S1020), the manufacturing system can extend vertical holes (H) penetrating the semiconductor structure (SEMI-STR) in a vertical direction (e.g., a third direction (D3)) as illustrated in FIG. 11b to form an array in which the vertical structures (VS) are composed of a plurality of columns and rows on a horizontal plane.

[0167] In step (S1030), the manufacturing system can recess a portion (MEM-P1) of each of the memory cell layers (MEM) in a horizontal direction (e.g., a first direction (D1) and a second direction (D2)) through vertical holes (H) as illustrated in FIG. 11c.

[0168] More specifically, the manufacturing system can recess a horizontal portion (MEM-P1) of each of the memory cell layers (MEM) such that at least a horizontal portion (MEM-P2) remains in each of the memory cell layers (MEM).

[0169] As a portion (MEM-P1) of each of the memory cell layers (MEM) in the horizontal direction is recessed in this way, the protrusions (VS-PP) to be formed in the recessed spaces (RS) of each of the memory cell layers (MEM) can have the same thickness as the thickness of each of the memory cell layers (MEM) and the thickness of each of the gate electrodes (EL) to be formed in at least a portion (MEM-2) remaining after the recessing of each of the memory cell layers (MEM).

[0170] At this time, gate electrodes (EL) are formed in a horizontal portion (ILD-P1) recessed in each of the interlayer insulating layers (ILD) through a step (S570) described below, and the manufacturing system can control the depth of the horizontal portion (ILD-P1) recessed according to the design parameter (horizontal thickness) of the gate electrode required in the 3D random access memory.

[0171] In each of the memory cell layers (MEM), gate electrodes (EL) are formed in at least a portion (MEM-P2) of the remaining horizontal direction through a step (S570) described below, and the manufacturing system can recess a portion (MEM-P1) of the horizontal direction of each of the memory cell layers (MEM) so that at least a portion (MEM-P2) of the horizontal thickness according to the design parameter (horizontal thickness) of the gate electrode required in the three-dimensional random access memory remains.

[0172] In step (S1040), the manufacturing system can form a polarization generating dielectric pattern (PDP) on the inner upper surface, inner side surface, inner lower surface of each of the recessed spaces (RS) and the inner surface of each of the vertical holes (H), as illustrated in FIG. 11d.

[0173] In step (S1050), the manufacturing system can remove the memory cell layers (MEM) as illustrated in FIG. 11e. Specifically, the manufacturing system can remove at least a portion (MEM-P2) remaining in each of the memory cell layers (MEM).

[0174] In step (S1060), the manufacturing system can form vertical electrodes (VE) in each of the spaces (PDP-S) in which a polarization-generating dielectric pattern (PDP) is formed and in each of the vertical holes (PDP-H) in which a polarization-generating dielectric pattern (PDP) is formed, as illustrated in FIG. 11f.

[0175] In step (S1070), the manufacturing system can form gate electrodes (EL) in spaces (MEM-S) from which memory cell layers (MEM) have been removed, as illustrated in FIG. 11g.

[0176] Instead of being performed sequentially, the steps (S1010 to S1070) described above may be performed with the order of some steps reversed. For example, steps (S1050) and (S1070) may be performed sequentially after step (S1060) is performed before step (S1050).

[0177] Here, steps (S1060, S1070) are performed simultaneously in batches, so that the entire manufacturing process can be simplified.

[0178] In this way, the manufacturing system forms a polarization-generating dielectric pattern (PDP) on the inner upper surface, inner side surface, and inner lower surface of each of the recessed spaces (RS) through steps (S1040) and (S1060), and then forms a vertical electrode (VE) in each of the spaces (PDP-S) where the polarization-generating dielectric pattern (PDP) is formed, thereby forming a protrusion (VE-PP) of the vertical electrode (VE) and a protrusion (VS-PP) of each of the vertical structures (VS) including the polarization-generating dielectric pattern (PDP-PP).

[0179] In addition, the manufacturing system can implement a structure in which gate electrodes (EL), a polarization generating dielectric pattern (PDP), and a vertical electrode (VE) are sequentially contacted and connected through steps (S1040), (S1060), and (S1070).

[0180] Although not depicted as a separate step, the manufacturing system can form bit line horizontal portions (BLH) extending horizontally on top of the vertical structures (VS) after step (S1070). During this process, the manufacturing system can connect the vertical electrode (VE) included in each of the vertical structures (VS) to each of the bit line horizontal portions (BLH) via a bit line plug (BLPG).

[0181]

[0182] Hereinafter, with reference to the drawings, a memory operation method of a three-dimensional random access memory having a structure in which each of the gate electrodes is formed in a plate shape extending in a horizontal direction and vertical structures formed to extend vertically while penetrating the gate electrodes form an array composed of a plurality of columns and rows on a horizontal plane will be described in detail.

[0183] The three-dimensional random access memory described below is based on a GAA (Gate-All-Around) based three-terminal selection element-based memory.

[0184]

[0185] FIG. 12 is a plan view illustrating a three-dimensional random access memory according to one embodiment, FIG. 13 is a cross-sectional view illustrating a three-dimensional random access memory according to one embodiment, corresponding to a cross-section taken along line A-A' of FIG. 12, FIGS. 14a and 14b are drawings for explaining the effect of at least one insulating pattern of a three-dimensional random access memory according to one embodiment, and FIGS. 15a and 15b are cross-sectional views illustrating a three-dimensional random access memory to explain the arrangement structure of at least one insulating pattern according to another embodiment.

[0186] The substrate (SUB) may be a semiconductor substrate, such as a silicon-germanium substrate, a germanium substrate, or a single-crystal epitaxial layer grown on a monocrystalline silicon substrate. The substrate (SUB) may be doped with a first conductivity type impurity (e.g., a P-type impurity).

[0187] Stacked structures (ST) may be arranged on a substrate (SUB). The stacked structures (ST) may be two-dimensionally arranged along a second direction (D2) while extending in a first direction (D1). In addition, the stacked structures (ST) may be spaced apart from each other in the second direction (D2).

[0188] Each of the stacked structures (ST) may include gate electrodes (EL; EL-SSL, EL-WL) and interlayer insulating layers (ILD) alternately stacked in a vertical direction (e.g., a third direction (D3)) perpendicular to the upper surface of the substrate (SUB). The stacked structures (ST) may have a substantially flat upper surface. That is, the upper surfaces of the stacked structures (ST) may be parallel to the upper surface of the substrate (SUB). Hereinafter, the vertical direction means the third direction (D3) or the opposite direction of the third direction (D3).

[0189] Referring back to FIG. 1, the gate electrode (EL-SSL) may be a string select line (SSL), and each of the gate electrodes (EL-WL) may be one of the word lines (WL1 (WL1 / 1, WL1 / 2, ..., WL1 / n), WL2 (WL2 / 1, WL2 / 2, ..., WL2 / n), WL3 (WL3 / 1, WL3 / 2, ..., WL3 / n), ..., WLm (WLm / 1, WLm / 2, ..., WLm / n)) sequentially stacked on the substrate (SUB), and may be a component used as a conductor in a three-dimensional random access memory.

[0190] Each of the gate electrodes (EL) may be formed in a plate shape extending in the first direction (D1) and also extending in the second direction (D2), and may have substantially the same thickness in the third direction (D3). Hereinafter, the thickness means the thickness in the third direction (D3). Each of the gate electrodes (EL) may be formed of a conductive material. For example, each of the gate electrodes (EL) may include at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.). Each of the gate electrodes (EL) may include at least one of all metal materials that can be formed by ALD in addition to the described metal materials.

[0191] Although not shown, one of the upper and lower ends of each of the stacked structures (ST) may have a stepwise structure along the first direction (D1). More specifically, the gate electrodes (EL) of the stacked structures (ST) may have a length in the first direction (D1) that decreases as they move away from the substrate (SUB). For example, the gate electrode positioned at the uppermost position among the gate electrodes (EL) may have the shortest length in the first direction (D1) and the largest distance from the substrate (SUB) in the third direction (D3). On the other hand, the gate electrode positioned at the lowermost position among the gate electrodes (EL) may have the longest length in the first direction (D1) and the closest distance from the substrate (SUB) in the third direction (D3).

[0192] Although each of the interlayer insulating layers (ILDs) is illustrated as having the same thickness, it is not limited thereto and may have different thicknesses. For example, the lowermost and uppermost interlayer insulating layers (ILDs) may have a smaller thickness than other interlayer insulating layers (ILDs). However, this is merely an example and is not limiting, and the thickness of each interlayer insulating layer (ILD) may be adaptively set according to the characteristics of the semiconductor device. The interlayer insulating layers (ILDs) may be formed of an insulating material for insulation between gate electrodes (EL). For example, the interlayer insulating layers (ILDs) may be formed of silicon oxide.

[0193] A plurality of holes (H) penetrating a portion of the stacked structures (ST) and the substrate (SUB) may be provided. Vertical structures (VS) may be provided within the holes (H). The vertical structures (VS) may be a plurality of cell strings (CSTR) illustrated in FIG. 1, and may be formed to extend in a third direction (D3) while being connected to the substrate (SUB). The connection of the vertical structures (VS) to the substrate (SUB) may be achieved by a lower surface of each of the vertical structures (VS) being in contact with an upper surface of the substrate (SUB), but is not limited thereto and may also be achieved by being embedded in the substrate (SUB). When a portion of each of the vertical structures (VS) is embedded in the substrate (SUB), the lower surfaces of the vertical structures (VS) may be located at a level lower than the upper surface of the substrate (SUB).

[0194] The rows of vertical structures (VS) penetrating one of the stacked structures (ST) may be provided in multiple numbers. As described above, since the gate electrodes (EL) are formed in a plate shape, the vertical structures (VS) may form an array composed of multiple columns and rows on a horizontal plane formed by the gate electrodes (EL). For example, as illustrated in FIG. 12, twelve vertical structures (VS) may form six columns and four rows and penetrate one of the stacked structures (ST). However, the number of vertical structures (VS) forming the array is not limited or restricted thereto.

[0195] As vertical structures (VS) are formed in a plate shape to form an array of multiple columns and rows on a horizontal plane of gate electrodes (EL), the three-dimensional random access memory can have a structure in which the integration of memory cell strings is improved.

[0196] At this time, the vertical structures (VS) included in a pair of adjacent columns may be arranged in shifted manners to form different rows on the horizontal plane and to be misaligned with each other. For example, the vertical structures (VS) included in the first column may be arranged in the first and third rows, and the vertical structures (VS) included in the second column may be arranged in the second and fourth rows, such that the vertical structures (VS) included in the pair of adjacent columns may be arranged in a zigzag shape along the first direction (D1). Accordingly, the integration of the memory cell string may be further improved compared to the case where the vertical structures (VS) included in the pair of adjacent columns are arranged side by side in the same row on the horizontal plane.

[0197] Each of the vertical structures (VS) may be formed to extend from the substrate (SUB) in a third direction (D3). In the drawing, each of the vertical structures (VS) is depicted as having a columnar shape with the same width at the top and bottom, but is not limited thereto and may have a shape in which the width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3). The upper surface of each of the vertical structures (VS) may have a circular shape, an oval shape, a square shape, or a bar shape.

[0198] These vertical structures (VS) may correspond to the cell strings (CSTR) illustrated in FIG. 1.

[0199] To this end, each of the vertical structures (VS) may include a data storage pattern (DSP), a bit line vertical portion (BLV), and a selection transistor (SST). In each of the vertical structures (VS), the data storage pattern (DSP) may have a pipe shape or a macaroni shape with an open top, the bit line vertical portion (BLV) may have a shape that fills a space from the bottom to a certain height among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP), and the selection transistor (SST) may have a shape that fills a space from the top to a certain depth among the inner spaces of the data storage pattern (DSP) while being surrounded on the outside by the data storage pattern (DSP). That is, the selection transistor (SST) may be positioned at the uppermost end of the inner spaces of the data storage pattern (DSP) and thus may be arranged on the upper part of the bit line vertical portion (BLV).

[0200] The data storage pattern (DSP) surrounds the outer wall of the bit line vertical portion (BLV) and can be in contact with the outer side walls of the gate electrodes (EL). Accordingly, regions corresponding to the gate electrodes (EL-WL) among the data storage pattern (DSP) can form memory cells in which a memory operation (a write operation including a program operation and an erase operation, and a read operation) is performed by a voltage applied through the gate electrodes (EL-WL) and a voltage applied to the bit line vertical portion (BLV). Hereinafter, applying a voltage to the bit line vertical portion (BLV) means that a voltage is applied to the bit line horizontal portion (BLH) connected to the bit line vertical portion (BLV) and transmitted to the bit line vertical portion (BLV).

[0201] The memory cells correspond to the memory cell transistors (MCT) illustrated in Fig. 1. To this end, the data storage pattern (DSP) may be a polarization-generating dielectric pattern, which is a data storage element that generates a polarization phenomenon by a voltage applied through gate electrodes (EL-WL) and a voltage applied to a bit line vertical portion (BLV), thereby representing a data value as a change in voltage, current, or resistance corresponding to the polarization state of charges.

[0202] For example, as a data storage pattern (DSP), at least one of HfOx having an orthorhombic crystal structure, HfOx doped with at least one of Al, Zr or Si, PZT (Pb(Zr, Ti)O3), PTO (PbTiO3), SBT (SrBi2Ti2O3), BLT (Bi(La, Ti)O3), PLZT (Pb(La, Zr)TiO3), BST (Bi(Sr, Ti)O3), barium titanate (BaTiO3), P(VDF-TrFE), PVDF, AlOx, ZnOx, TiOx, TaOx or InOx can be used.

[0203] As another example, antiferroelectric materials can be used as data storage patterns (DSPs), and ZrO is an antiferroelectric material. x , Zr a X b O x (X may include Hf, Si, Al, Ge or one of the elements in group 2 of the periodic table) may be used.

[0204] Although the drawing shows the data storage pattern (DSP) as extending in a vertical direction (e.g., a third direction (D3)), it is not limited thereto and may have a structure of multiple segments spaced apart only in areas corresponding to the gate electrodes (EL-WL) on the outer wall of the bit line vertical portion (BLV).

[0205] The bottom surface of the data storage pattern (DSP) may be positioned at a lower level than the bottom surface of the lowest one among the gate electrodes (EL-WL) and may be formed to be in contact with the substrate (SUB).

[0206] In a conventional 3D random access memory, when a memory operation is performed on a target memory cell, the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) containing the target memory cell is grounded, and an operating voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. OP ) and pass voltage (V) through the unselected gate electrode (Unsel EL) corresponding to the unselected memory cell. PASS ) by applying an operating voltage (V) to the target memory cell. OP ) can be applied. In this case, the pass voltage (V PASS ) may cause problems in which the target memory cell is affected.

[0207] Accordingly, during a memory operation on a target memory cell, an operating voltage (V) is applied through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) containing the target memory cell. OP) with at least some value of bit line voltage (V BL ) is applied, and a bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) by applying the operating voltage (V) to the target memory cell as shown in Equation 1 below. OP ) was proposed.

[0208] <Formula 1>

[0209] |V BL -V G |=V OP

[0210] However, the operating voltage (V) is determined through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). OP ) with at least some value of bit line voltage (V BL ) is applied, and a bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) is applied through the bit line vertical portion (BLV). BL ) has the disadvantage of causing some programmed memory malfunctions in some of the non-selected memory cells, as shown in Fig. 14a.

[0211] Therefore, in order to prevent the above-mentioned disadvantage, the data storage pattern (DSP) of the 3D random access memory according to one embodiment may include at least one insulating pattern (IP). The at least one insulating pattern (IP) may be used to prevent memory operations on unselected memory cells excluding the target memory cell among the memory cells during a memory operation on the target memory cell.

[0212] More specifically, at least one insulating pattern (IP) increases the operating voltage required for memory operation, as illustrated in FIG. 14b, or increases the coercive field (E) in unselected memory cells. C ) can be increased to prevent polarization from occurring in unselected memory cells, thereby preventing some unselected memory cells from being programmed.

[0213] Although the drawing illustrates that at least one insulating pattern (IP) is disposed on an outer wall of the data storage pattern (DSP) (hereinafter, the outer wall refers to an interface where the data storage pattern (DSP) contacts the gate electrodes (EL)), it is not limited or restricted thereto. For example, the at least one insulating pattern (IP) may be disposed on an inner wall of the data storage pattern (DSP) as illustrated in FIG. 15a (hereinafter, the inner wall refers to an interface where the data storage pattern (DSP) contacts the bit line vertical portion (BLV)), or may be embedded within the interior of the data storage pattern (DSP) as illustrated in FIG. 15b. Although not illustrated in a separate drawing, the at least one insulating pattern (IP) may be disposed on at least one of an outer wall, an inner wall, or the interior of the data storage pattern (DSP).

[0214] At least one such insulating pattern (IP) is configured to apply an operating voltage (V) through a bit line vertical portion (BLV) of a selected vertical structure (Sel VS) that enables memory operation for the target memory cell. OP) with at least some value of bit line voltage (V BL ) is applied and a bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) is applied to the target memory cell, the operating voltage (V OP ) and a condition for preventing memory operations on unselected memory cells (the operation voltage (V) is applied to the unselected memory cells included in the selected vertical structure (Sel VS) through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). OP ) with at least some value of bit line voltage (V BL ) can be formed into a material that satisfies the condition that does not affect it.

[0215] For example, at least one insulating pattern (IP) can be formed of at least one material among a silicon-based material, a high-k material, a low-k material, or an oxide semiconductor material (an oxide semiconductor material having a high band gap greater than a preset value).

[0216] Similarly, at least one insulating pattern (IP) is configured to apply an operating voltage (V) through a bit line vertical portion (BLV) of a selected vertical structure (Sel VS) that enables memory operation for the target memory cell. OP ) with at least some value of bit line voltage (V BL ) is applied and a bit line voltage (V) is applied through the selected gate electrode (Sel EL) corresponding to the target memory cell. BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) is applied to the target memory cell, the operating voltage (V OP) and a condition for preventing memory operations on unselected memory cells (the operation voltage (V) is applied to the unselected memory cells included in the selected vertical structure (Sel VS) through the bit line vertical portion (BLV) of the selected vertical structure (Sel VS). OP ) with at least some value of bit line voltage (V BL ) can be formed with a thickness determined as a value that satisfies the condition that does not affect it.

[0217] A bit line vertical portion (BLV) (hereinafter, the bit line vertical portion (BLV) may be referred to as a vertical electrode) is a component used as a conductor rather than a channel in a three-dimensional random access memory, and may be connected to each of the bit line horizontal portions (BLH) located on the upper portions of the vertical structures (VS) through a select transistor (SST) included in each of the vertical structures (VS). To this end, the bit line vertical portion (BLV) may be brought into contact with the bit line horizontal portions (BLH) through the select transistor (SST) thereon, and an upper surface of the select transistor (SST) may be substantially coplanar with a data storage pattern (DSP).

[0218] The bit line vertical portion (BLV) can be formed of a conductive material including at least one selected from a doped semiconductor (e.g., doped silicon, etc.), a metal (e.g., W (tungsten), Cu (copper), Al (aluminum), Ti (titanium), Ta (tantalum), Mo (molybdenum), Ru (ruthenium), Au (gold), etc.), or a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.).

[0219] The lower surface of the bit line vertical portion (BLV) may be positioned at a level lower than the lower surface of the lowest one of the gate electrodes (EL) and may be spaced apart from the substrate (SUB) by a certain amount or more, but is not limited thereto.

[0220] A select transistor (SST) may be configured to be positioned above the bit line vertical portion (BLV) and to connect the bit line vertical portion (BLV) to the bit line horizontal portion (BLH).

[0221] More specifically, the select transistor (SST) may serve as a selector that turns on a selected vertical structure (Sel VS; selected memory cell string) that includes a target memory cell to be the target of a memory operation among vertical structures (VS) connected to the same bit line horizontal portion (BLH) and turns off at least one unselected vertical structure (Unsel VS; unselected memory cell string) that does not include the target memory cell.

[0222] For example, a selection transistor (SST) can be used to apply an operating voltage only to a selected vertical structure (Sel VS) among vertical structures (VS) connected to the same bit line horizontal portion (BLH) during a memory operation for a target memory cell, and to prevent the application of an operating voltage to at least one unselected vertical structure (Unsel VS). In this way, the selection transistor (SST) can prevent parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS) by preventing the application of an operating voltage to at least one unselected vertical structure (Unsel VS).

[0223] To this end, the selection transistor (SST) may be formed of a semiconductor material (e.g., polycrystalline silicon or an oxide semiconductor material) that selectively forms a channel to be turned on or off depending on an applied voltage. For example, the channel of the selection transistor (SST) may be formed of a semiconductor material that is turned on or off depending on an applied voltage, and the drain and source of the transistor (SST) may be formed by doping the semiconductor material with impurities (N-type impurities) to improve contact resistance with a bit line vertical portion (BLV) or a bit line horizontal portion (BLH).

[0224] The described selection transistor (SST) can be used not only as a selector, but also to pre-charge a vertical structure (VS). Specifically, the selection transistor (SST) can be used to fill a pre-charge voltage to pre-charge a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS) during a read operation for the target memory cell.

[0225] Such a selection transistor (SST) is turned on or off under the control of a corresponding gate electrode (EL-SSL), and can activate or deactivate the included vertical structure (VS).

[0226] The selection transistor (SST) is not limited or restricted to the structure described above, and may have a structure further including a dielectric pattern (not shown). For example, the selection transistor (SST) may have a structure further including a dielectric pattern disposed on top of a data storage pattern (DSP) to correspond to the selection transistor (SST).

[0227] Additionally, the selection transistor (SST) may have a structure including a buried pattern (not shown) inside. For example, a buried pattern may be formed inside the selection transistor (SST) using a material that facilitates the diffusion of charges or holes (e.g., an intrinsic semiconductor material or a polycrystalline semiconductor material with excellent charge / hole mobility) to facilitate the formation of a channel by the selection transistor (SST).

[0228] Additionally, the select transistor (SST) may further include a barrier metal layer (not shown) arranged at a contact surface with the bit line vertical portion (BLV). The barrier metal layer may be optionally included or omitted depending on the material forming the bit line vertical portion (BLV). For example, the barrier metal layer may be formed of TiN when the material forming the bit line vertical portion (BLV) is tungsten (W).

[0229] At this time, at least two bit line horizontal parts (BLH) are positioned at the same height on the upper portion of the vertical structures (VS), and the vertical structures (VS) arranged in the same row in the array may further include a bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS) so as to be respectively connected to different bit line horizontal parts (BLH). That is, the vertical structures (VS) arranged in the same row in the array may be respectively connected to different bit line horizontal parts (BLH) through the bit line plug (BLPG) arranged at a position shifted from the center of each of the vertical structures (VS).

[0230] A separation trench (not shown) extending in a first direction (D1) may be provided between adjacent stacked structures (ST). Insulating spacers (not shown) may be formed in the separation trench, thereby isolating the adjacent stacked structures (ST) from each other. For example, the insulating spacers may be formed of silicon oxide, silicon nitride, silicon oxynitride, or a low-k material having a low dielectric constant.

[0231] A capping insulating film (CAP) may be provided on the stacked structures (ST) and the vertical structures (VS). The capping insulating film (CAP) may cover an upper surface of an uppermost one of the interlayer insulating layers (ILD). The capping insulating film (CAP) may be formed of an insulating material different from that of the interlayer insulating layers (ILD). A bit line contact plug (BLPG) may be provided inside the capping insulating film (CAP). The bit line contact plug (BLPG) may have a shape in which a width in the first direction (D1) and the second direction (D2) increases as it goes in the third direction (D3).

[0232] Bit line horizontal portions (BLH) may be provided on a capping insulating film (CAP) and a bit line contact plug (BLPG). The bit line horizontal portions (BLH) may be formed by extending along a second direction (D2) with a conductive material while being spaced apart from each other along a first direction (D2). The conductive material forming the bit line horizontal portions (BLH) may be the same material as the conductive material forming each of the aforementioned gate electrodes (EL).

[0233] The three-dimensional random access memory described above is not limited or restricted to the described structure, and can be implemented in various structures based on a vertical structure (VS) including a select transistor (SST) and a bit line vertical portion (BLV) according to an implementation example.

[0234] As described, the three-dimensional random access memory can perform memory operations in response to voltages applied between bit line horizontal portions (BLH) and bit line vertical portions (BLV) and gate electrodes (EL).

[0235] Here, the three-dimensional random access memory can perform a memory operation on the selected target memory cell in response to a voltage applied between the bit line vertical portion (BLV) of the selected vertical structure (Sel VS) and the selected gate electrode (Sel EL) among the gate electrodes (EL) while turning on (activating) only the selected vertical structure (Sel VS) including the target memory cell among the vertical structures (VS) connected to the same bit line horizontal portion (BLH) using a selection transistor (SST) and turning off (deactivating) at least one unselected vertical structure (Unsel VS).

[0236] In particular, the three-dimensional random access memory can prevent memory operations on unselected memory cells included in a selected vertical structure (Sel VS) during a memory operation on a target memory cell by using at least one insulating pattern (IP) included in a data storage pattern (DSP).

[0237]

[0238] FIG. 16 is a flow chart illustrating a memory operation method of a three-dimensional random access memory according to one embodiment, and FIG. 17 is a drawing for explaining a memory operation method of a three-dimensional random access memory according to one embodiment.

[0239] The memory operation method described below performs a memory operation on a target memory cell, and is assumed to be performed by a three-dimensional random access memory having the structure described above with reference to FIG. 1 and FIGS. 12 to 15b.

[0240] In step (S1610), the 3D random access memory applies an operating voltage (V) through a selected bit line horizontal portion (Sel BLH) connected to a selected vertical structure (Sel VS) including a target memory cell among the vertical structures (VS). OP ) with at least some value of bit line voltage (V BL ) is applied to the bit line vertical portion (Sel BLV) included in the selected vertical structure (Sel VS). OP ) with at least some value of bit line voltage (V BL ) can be applied. For example, a 3D random access memory can be applied with an operating voltage (V OP ) with a bit line voltage (V ) of half the value BL ) can be applied. In this case, the bit line voltage (V BL ) can be expressed as in Equation 2 below.

[0241] <Formula 2>

[0242] V BL =±1 / 2V OP

[0243] In particular, in step (S1610), the 3D random access memory increases the operating voltage required for the memory operation or increases the coercive field (E) in unselected memory cells by using at least one insulating pattern (IP) included in the outer wall, inner wall or interior of the data storage pattern (DSP). C ) can be prevented from occurring in unselected memory cells. By preventing the polarization phenomenon from occurring in unselected memory cells by at least one insulating pattern (IP), memory operation for unselected memory cells can be prevented.

[0244] In step (S1610), the three-dimensional random access memory can ground at least one unselected bit line horizontal portion (Unsel BLH) excluding a selected bit line horizontal portion (Sel BLH) among the bit line horizontal portions (BLH).

[0245] In step (S1620), the 3D random access memory applies a bit line voltage (V) to the selected vertical structure (Sel VS). BL ) can turn on the selection transistor (SST) of the selected vertical structure (Sel VS) to be applied.

[0246] Turning on the selection transistor (SST) of the selected vertical structure (Sel VS) can be accomplished by applying a turn-on voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of the selected vertical structure (Sel VS).

[0247] In step (S1630), the 3D random access memory applies a bit line voltage (V) to at least one unselected vertical structure (Unsel VS) that is connected to a bit line horizontal portion (Sel BLH) that is identical to a selected vertical structure (Sel VS) among unselected vertical structures (Unsel VS) that do not include a target memory cell. BL ) can be turned off to prevent at least one unselected vertical structure (Unsel VS) from being selected.

[0248] Turning on the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) can be accomplished by floating or grounding the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS), or by applying a turn-off voltage to the gate electrode (EL-SSL) corresponding to the selection transistor (SST) of at least one unselected vertical structure (Unsel VS).

[0249] In this way, the 3D random access memory is configured to apply a bit line voltage (V) to at least one unselected vertical structure (Unsel VS) in step (S1630). BL ) is turned off so that the selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is not applied, thereby preventing the parasitic capacitance from being generated in at least one unselected vertical structure (Unsel VS).

[0250] In step (S1640), the 3D random access memory applies a bit line voltage (V) to a selected gate electrode (Sel EL) corresponding to a target memory cell among the gate electrodes (EL-WL). BL ) and has opposite polarity and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) can be applied. For example, a 3D random access memory can be applied by applying a bit line voltage (V BL ) and has opposite polarity and operating voltage (V OP ) with a gate voltage (V ) of half the value G ) can be applied. In this case, the gate voltage (V G ) can be expressed as in Equation 3 below.

[0251] <Formula 3>

[0252] V G =±1 / 2V OP

[0253] For example, at step (S1610) +1 / 2V OP This bit line voltage (V BL ) is authorized, -1 / 2V at step (S1640) OP This gate voltage (V G ) can be authorized. For another example, -1 / 2 V in step (S1610) OP This bit line voltage (V BL ) is authorized, +1 / 2V at step (S1640) OP This gate voltage (V G ) can be authorized. For another example, in step (S1610) +1 / 3V OP This bit line voltage (V BL ) is authorized, -2 / 3V at step (S1640) OP This gate voltage (V G ) can be authorized. For another example, -1 / 3V in step (S1610) OP This bit line voltage (V BL ) is authorized, +2 / 3V at step (S1640) OP This gate voltage (V G ) can be authorized. For another example, in step (S1610) +3 / 4V OP This bit line voltage (V BL ) is authorized, -1 / 4V at step (S1640) OP This gate voltage (V G ) can be authorized. For another example, -3 / 4V in step (S1610) OP This bit line voltage (V BL ) is authorized, +1 / 4V at step (S1640) OP This gate voltage (V G ) can be authorized.

[0254] In this way, the steps (S1610) and (S1640) have opposite polarities and the operating voltage (V OP ) with at least some value of bit line voltage (V BL) and operating voltage (V OP ) with the remaining values ​​of the gate voltage (V G ) are applied to the target memory cell, as in Equation 1 above. BL , V G ) is the operating voltage (V) OP ) may be authorized.

[0255] That is, the 3D random access memory applies the operating voltage (V) to the target memory cell through steps (S1610 and S1640). OP ) can be used to perform a memory operation on the target memory cell.

[0256] The 3D random access memory is configured such that a gate voltage (V) is applied to a gate electrode (Sel EL) selected through step (S1640) while a selection transistor (SST) of at least one unselected vertical structure (Unsel VS) is turned off through step (S1630). G ), it is possible to prevent a memory operation from occurring for a memory cell corresponding to a selected gate electrode (Sel EL) among memory cells of at least one unselected vertical structure (Unsel VS).

[0257] In step (S1650), the 3D random access memory can ground at least one unselected gate electrode (Unsel EL) except for the selected gate electrode (Sel EL) among the gate electrodes (EL-WL). Therefore, the pass voltage (V) applied to the unselected gate electrode (Unsel EL) PASS ) can solve the problem of the target memory cell being affected.

[0258] Above, the described steps (S1610 to S1650) may be performed sequentially in ascending order of the drawing numbers, but are not limited or restricted thereto.

[0259] The memory operation described above may be a write operation for the target memory cell (a programming operation that writes data of "1" to the target memory cell or an erase operation that writes data of "0" to the target memory cell) or a read operation.

[0260] Although the gate electrodes (EL-WL) are shown as being divided by block in FIG. 17, the present invention is not limited thereto, and the gate electrodes (EL-WL) may have a structure in which they are connected substantially independently of the blocks. Even in this case, the gate electrode (EL-SSL) of the selection transistor (SST) may have a structure in which the gate electrode (EL-SSL) of the selection transistor (SST) is divided by block in order to turn on or off the selection transistor (SST) by block.

[0261]

[0262] FIG. 18 is a perspective view schematically illustrating an electronic system including a three-dimensional random access memory according to one embodiment.

[0263] Referring to FIG. 18, an electronic system (1800) including a three-dimensional random access memory according to embodiments may include a main substrate (1801), a controller (1802) mounted on the main substrate (1801), one or more semiconductor packages (1803), and a DRAM (1804).

[0264] The semiconductor package (1803) and DRAM (1804) can be interconnected with the controller (1802) by wiring patterns (1805) provided on the main substrate (1801).

[0265] The main board (1801) may include a connector (1806) having a plurality of pins that are coupled to an external host. The number and arrangement of the plurality of pins in the connector (1806) may vary depending on the communication interface between the electronic system (1800) and the external host.

[0266] The electronic system (1800) may communicate with an external host according to any one of interfaces, such as, for example, Universal Serial Bus (USB), Peripheral Component Interconnect Express (PCI Express), Serial Advanced Technology Attachment (SATA), and M-Phy for Universal Flash Storage (UFS). The electronic system (1800) may operate by power supplied from an external host, for example, through a connector (1806). The electronic system (1800) may further include a Power Management Integrated Circuit (PMIC) that distributes power supplied from the external host to a controller (1802) and a semiconductor package (1803).

[0267] The controller (1802) can write data to the semiconductor package (1803) or read data from the semiconductor package (1803), and can improve the operating speed of the electronic system (1800).

[0268] The DRAM (1804) may be a buffer memory to mitigate the speed difference between the semiconductor package (1803), which is a data storage space, and an external host. The DRAM (1804) included in the electronic system (1800) may also function as a type of cache memory and may provide a space for temporarily storing data in a control operation for the semiconductor package (1803). When the electronic system (1800) includes the DRAM (1804), the controller (1802) may further include a DRAM controller for controlling the DRAM (1804) in addition to the NAND controller for controlling the semiconductor package (1803).

[0269] A semiconductor package (1803) may include first and second semiconductor packages (1803a, 1803b) spaced apart from each other. The first and second semiconductor packages (1803a, 1803b) may each be a semiconductor package including a plurality of semiconductor chips (1820). Each of the first and second semiconductor packages (1803a, 1803b) may include a package substrate (1810), semiconductor chips (1820) on the package substrate (1810), adhesive layers (1830) disposed on a lower surface of each of the semiconductor chips (1820), connection structures (1840) electrically connecting the semiconductor chips (1820) and the package substrate (1810), and a molding layer (1850) covering the semiconductor chips (1820) and the connection structures (1840) on the package substrate (1810).

[0270] The package substrate (1810) may be a printed circuit board including package upper pads (1811). Each of the semiconductor chips (1820) may include input / output pads (1821). Each of the semiconductor chips (1820) may include the three-dimensional random access memory described above with reference to FIGS. 1 to 4, FIGS. 7 to 9, and FIGS. 12 to 17. More specifically, each of the semiconductor chips (1820) may include gate stack structures (1822) and memory structures (1823). The gate stack structures (1822) may correspond to the stack structures (ST) described above, and the memory structures (1823) may correspond to the vertical structures (VS) described above.

[0271] The connection structures (1840) may be, for example, bonding wires that electrically connect the input / output pads (1821) and the package upper pads (1811). Accordingly, in each of the first and second semiconductor packages (1803a, 1803b), the semiconductor chips (1820) may be electrically connected to each other in a bonding wire manner, and may be electrically connected to the package upper pads (1811) of the package substrate (1810). According to embodiments, in each of the first and second semiconductor packages (1803a, 1803b), the semiconductor chips (1820) may be electrically connected to each other by a through silicon via instead of the bonding wire-type connection structures (1840).

[0272] Unlike the illustration, the controller (1802) and the semiconductor chips (1820) may be included in a single package. The controller (1802) and the semiconductor chips (1820) may be mounted on a separate interposer substrate different from the main substrate (1801), and the controller (1802) and the semiconductor chips (1820) may be connected to each other by wiring provided on the interposer substrate.

[0273]

[0274] Although the embodiments described above have been described by way of limited examples and drawings, those skilled in the art will appreciate that various modifications and variations can be made based on the above teachings. For example, appropriate results can still be achieved even if the described techniques are performed in a different order than described, and / or components of the described systems, structures, devices, circuits, etc. are combined or combined in a different manner than described, or are replaced or substituted with other components or equivalents.

[0275] Therefore, other implementations, other embodiments, and equivalents to the claims also fall within the scope of the claims described below.

Claims

1. Gate electrodes and interlayer insulating layers are formed extending horizontally on the substrate and alternately stacked in the vertical direction; and Vertical structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical structures including a vertical electrode and a polarization-generating dielectric pattern surrounding the outer surface of the vertical electrode. Including, Each of the above vertical structures, A three-dimensional random access memory having a protrusion protruding in the horizontal direction from each of the interlayer insulating layers.

2. In paragraph 1, The protrusions of each of the above vertical structures are: A three-dimensional random access memory characterized in that it is formed with the same thickness as each of the interlayer insulating layers.

3. In paragraph 2, The above polarization generation dielectric pattern is, A three-dimensional random access memory characterized in that each of the gate electrodes has a contact surface of an outer lower surface, an outer side surface, an outer upper surface, and an inner side surface, as each of the vertical structures is implemented with a structure in which a protrusion is interposed between the gate electrodes.

4. Gate electrodes and interlayer insulating layers alternately stacked in the vertical direction while extending horizontally on the substrate; and Vertical structures extending in the vertical direction and penetrating the gate electrodes, each of the vertical structures including a vertical electrode and a polarization-generating dielectric pattern surrounding the outer surface of the vertical electrode. Including, Each of the above vertical structures, A three-dimensional random access memory having a protrusion protruding in the horizontal direction from each of the above gate electrodes.

5. In paragraph 4, The protrusions of each of the above vertical structures are: A three-dimensional random access memory characterized in that it is formed with the same thickness as each of the above gate electrodes.

6. In paragraph 5, The above polarization generation dielectric pattern is, A three-dimensional random access memory characterized in that each of the protrusions of the vertical structures is implemented on each of the gate electrodes with the same thickness as each of the gate electrodes, and thus has a contact surface on an outer side, an inner upper surface, an inner side, and an inner lower surface for each of the gate electrodes.

7. Gate electrodes that are formed horizontally on the substrate and are vertically spaced apart and stacked; and Vertical structures formed to extend in the vertical direction while penetrating the gate electrodes, each of the vertical structures including a data storage pattern and a bit line vertical portion, the data storage pattern including at least one insulating pattern, and forming memory cells corresponding to the gate electrodes. A three-dimensional random access memory containing .

8. In paragraph 7, The above data storage pattern is, A three-dimensional random access memory characterized by including at least one insulating pattern on an outer wall, an inner wall or an interior.

9. In paragraph 7, At least one insulating pattern, A three-dimensional random access memory characterized in that it is used for the purpose of preventing memory operations on non-selected memory cells excluding the target memory cell among the memory cells when a memory operation is performed on the target memory cell.

10. In paragraph 9, At least one insulating pattern, A three-dimensional random access memory characterized in that the polarization phenomenon is prevented from occurring in the unselected memory cells by increasing the operating voltage required for the memory operation or increasing the coercive field in the unselected memory cells.

11. In paragraph 9, The thickness of at least one insulating pattern is: A three-dimensional random access memory characterized in that the value is determined to satisfy a condition that enables a memory operation for the target memory cell and a condition that prevents a memory operation for the non-selected memory cells.

12. In paragraph 9, At least one insulating pattern, A three-dimensional random access memory characterized in that it is formed of a material that satisfies a condition that enables a memory operation for the target memory cell and a condition that prevents a memory operation for the non-selected memory cells.

13. In paragraph 9, At least one insulating pattern, A three-dimensional random access memory characterized by being formed of at least one material selected from the group consisting of a silicon-based material, a high-k material, a low-k material, and an oxide semiconductor material.

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