Systems and methods for regulating power output from a matchless plasma source

Abstract

Systems and methods for controlling power output from a matchless plasma source are described. One of the methods includes applying a direct current (DC) voltage across a half-bridge circuit, generating a digital pulsed signal having a plurality of pulses to provide to a gate driver of the matchless plasma source, and regulating output power of the matchless plasma source by controlling a duty cycle of the digital pulsed signal.

Description

SYSTEMS AND METHODS FOR REGULATING POWER OUTPUT FROM A MATCHLESS PLASMA SOURCEField

[0001] The present embodiments relate to systems and methods for regulating power output from a matchless plasma source.Background

[0002] The background description provided herein is for the purposes of generally presenting the context of the disclosure. Work of the presently named inventors, to the extent it is described in this background section, as well as aspects of the description that may not otherwise qualify as prior art at the time of filing, are neither expressly nor impliedly admitted as prior art against the present disclosure.

[0003] In plasma systems, there is a radio frequency (RF) generator, an impedance matching circuit, and a plasma chamber. A substrate is placed within the plasma chamber for processing. The RF generator supplies RF power via the impedance matching circuit to the plasma chamber. When process gases are supplied to the plasma chamber in addition to the RF power, the substrate is processed. However, impedance of plasma is dynamically changing and it is difficult for the RF generator and the impedance matching circuit to control the RF power with the dynamic change in the impedance.Summary

[0004] Embodiments of the disclosure provide systems, apparatus, methods and computer programs for regulating power output from a matchless plasma source. It should be appreciated that the present embodiments can be implemented in numerous ways, e.g., a process, an apparatus, a system, a device, or a method on a computer readable medium. Several embodiments are described below.

[0005] In an embodiment, power output to a plasma load is controlled by adjusting a direct current (DC) rail voltage, which is voltage supplied by a DC voltage source. When the power is controlled in this manner, multiple input gate signals operate at a constant duty cycle. The power output to the plasma load is increased or decreased by increasing or decreasing a level of the DC rail voltage that is applied across a half-bridge amplifier.

[0006] However, it is difficult to quickly control the power by controlling the DC rail voltage. For example, it takes a large amount of time for a DC rail to respond to an instruction for a change in the DC rail voltage.

[0007] In an embodiment, a method for power regulation on a matchless plasma source (MPS) is to use a radio frequency (RF) input gate signal, such as a digital pulsed signal, with a variable duty cycle. When the method is applied, the DC rail voltage does not need to be variable to change the output power. The output power to the plasma load can be increased or decreased by increasing or decreasing a duty cycle of the RF gate input signal. For example, a fast duty cycle transition is provided to achieve fast output power variation.

[0008] In one embodiment, a method for controlling power output from a matchless plasma source is described. The method includes applying a DC voltage to a half-bridge circuit, generating a digital pulsed signal having a plurality of pulses to provide to a gate driver associated with a half-bridge circuit. The half-bridge circuit has an output. The method includes modifying a duty cycle of the digital pulsed signal to control the power provided from the output of the half-bridge circuit to a plasma load.

[0009] In an embodiment, a matchless plasma source is described. The matchless plasma source includes a half-bridge circuit having an output, a DC voltage source coupled to the half-bridge circuit to apply DC voltage to the half-bridge circuit, and a pulse train generator that generates a digital pulsed signal having a plurality of pulses. The matchless plasma source includes a gate driver coupled to the pulse train generator and to the half-bridge circuit. The gate driver provides a plurality of reversely synchronized signals based on the digital pulsed signal. The plurality of reversely synchronized signals are provided to the half-bridge circuit. The pulse train generator modifies a duty cycle of the digital pulsed signal to control power provided from the output of the half-bridge circuit to a plasma load.

[0010] In one embodiment, a system is described. The system includes a controller and the matchless plasma source coupled to the controller.

[0011] Some advantages of the herein described systems and methods include adjusting the output power quickly. It takes longer for the DC rail voltage to change, as filtering capacitors on the DC rail charge and discharge. For example, by controlling the DC rail voltage, power transition time, which is a time of transition of a level, such as a state, of the power output to the plasma load, is in a range of 10 microseconds to 100 microseconds. When the RF input gate signal with the variable duty cycle is used, the duty cycle can be changed within 1 microsecond and the level of power output to the plasma load is changed is within a time period of less than 10 microseconds.

[0012] Additional advantages of the herein described systems and methods include reducing a level of noise of the power output to the plasma load. There is some noise level on the power output created by ripples on the DC rail, and there is a trade-off for power transition time, which limits additional filtering on the DC rail. When the duty cycle is used to control the poweroutput to the plasma load, the trade-off does not exist, so additional filtering on the DC rail can be added as needed. This results a reduction in the level of noise.

[0013] Other aspects will become apparent from the following detailed description, taken in conjunction with the accompanying drawings.BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The embodiments may best be understood by reference to the following description taken in conjunction with the accompanying drawings.

[0015] Figure 1 is a diagram of an embodiment of a system to illustrate a method for controlling power that is output from a matchless plasma source (MPS).

[0016] Figure 2 is a diagram of an embodiment of a system to illustrate details of a pulse train generator.

[0017] Figure 3 is a diagram of an embodiment of a system to illustrate a method for modifying a duty cycle of a digital pulsed signal based on feedback of power provided at an output of the MPS.

[0018] Figure 4 is an embodiment of a graph to illustrate a relationship between duty cycles of the digital pulsed signal and radio frequency (RF) power provided at the output of the MPS when a DC voltage source has a constant voltage.

[0019] Figure 5 is an embodiment of a graph and an embodiment of another graph to illustrate a change in a state of the RF power provided at the output with a change in a duty cycle of the digital pulsed signal.

[0020] Figure 6 is a diagram of an embodiment of a system to illustrate a dead time adjuster for providing or adjusting a dead time overlapping between a digital pulsed signal at an output of a logic gate and a reverse digital pulsed signal at an output of another logic gate.

[0021] Figure 7A is an embodiment of a graph and an embodiment of another graph to illustrate a fixed dead time between the digital pulsed signal at the output of the logic gate and the reverse digital pulsed signal at the output of the other logic gate.

[0022] Figure 7B is an embodiment of a graph and an embodiment of another graph to illustrate a variable dead time between the digital pulsed signal at the output of the logic gate and the reverse digital pulsed signal at the output of the other logic gate.DETAILED DESCRIPTION

[0023] The following embodiments describe systems and methods for regulating power output from a matchless plasma source. It will be apparent that the present embodiments may be practiced without some or all of these specific details. In other instances, well known process operations have not been described in detail in order not to unnecessarily obscure the present embodiments.

[0024] Figure 1 is a diagram of an embodiment of a system 100 to illustrate a method for controlling power that is output from a matchless plasma source (MPS) 102. The system 100 includes the MPS 102, a plasma load 106, and a reactive circuit 115. An example of the plasma load 106 includes a plasma chamber, such as, a capacitively coupled plasma (CCP) chamber or an inductively coupled plasma (ICP) chamber. The system 100 includes a host computer 105, such as a desktop computer, a laptop computer, or a tablet.

[0025] The MPS 102 includes a controller 104, a pulse train generator 108, a gate driver 110, a direct current (DC) voltage source 112, and a half-bridge circuit 114. An example of the pulse train generator 108 is an integrated circuit. An example of an integrated circuit includes a programmable logic device (PLD). To illustrate, the pulse train generator 108 is a field programmable gate array (FPGA). The DC voltage source 112 is coupled to the half-bridge circuit 114.

[0026] The gate driver 110 includes multiple logic gates, such as a pass-through gate 116 and an inverter 118, which is a NOT gate. An example of the pass-through gate 116 is a buffer or a series of buffers. The half-bridge circuit 114 includes a transistor 120 and another transistor 122. An example of a transistor is a field effect transistor (FET), such as an N-type metal oxide semiconductor FET (MOSFET). An example of the reactive circuit 115 is a capacitor or a set of capacitors that are coupled to each other. The pass-through gate 116 is sometimes referred to herein as a logic gate 116 and the inverter 118 is sometimes referred to herein as a logic gate 118.

[0027] The host computer 105 is coupled to the controller 104. The controller 104 is coupled to the pulse train generator 108 via a connection 124. An output 126 of the pulse train generator 108 is coupled to each of the logic gates 116 and 118. The output 126 is sometimes referred to herein as an input of the logic gates 116 and 118. The logic gate 116 is coupled to a gate terminal (G) of the transistor 120 and the logic gate 118 is coupled to a gate terminal (G) of the transistor 122.

[0028] A drain terminal (D) of the transistor 120 is coupled to the DC voltage source 112 and a source terminal (S) of the transistor 120 is coupled via an output 128 of the half-bridge circuit 114 to a drain terminal (D) of the transistor 122. A source terminal (S) of the transistor 122 is coupled to a ground potential. The output 128 is also sometimes referred to herein as an output of the MPS 102. The output 128 of the MPS 102 is coupled to the reactive circuit 115, which has an output 129. The output 129 is coupled to the plasma load 106. The reactive circuit 115 is coupled to an electrode of the plasma load 106. Examples of the electrode include a bottom electrode of the CCP chamber, a bottom electrode of the ICP chamber, a top electrode of the CCP chamber, and an RF coil of the ICP chamber.

[0029] The DC voltage source 112 applies a DC voltage to a DC rail of the halfbridge circuit 114. For example, the DC voltage is applied between the drain terminal of the transistor 120 and the source terminal of the transistor 122 to apply the DC voltage across the half-bridge circuit 114. Moreover, the controller 104 generates a control signal 130 and sends the control signal 130 via the connection 124 to the pulse train generator 108. The control signal 130 includes one or more duty cycles of a digital pulsed signal 132 to be generated by the pulse train generator 108. Upon receiving the control signal 130, the pulse train generator 108 generates the digital pulsed signal 132 having the duty cycle and sends the digital pulsed signal 132 to the output 126. As an example, the digital pulsed signal 132 has a radio frequency (RF), such as 400 kilohertz (kHz) or 2 megahertz (MHz) or 13.56 MHz or 60 MHz.

[0030] At the output 126, power of the digital pulsed signal 132 is split to generate a digital pulsed signal 132A and another digital pulsed signal 132B. Each digital pulsed signal 132A and 132B has the same duty cycle as that of the digital pulsed signal 132. The digital pulsed signal 132A is provided to the logic gate 116 and the digital pulsed signal 132B is provided to the logic gate 118. The logic gate 116 receives the digital pulsed signal 132A and provides the digital pulsed signal 132A to the gate terminal of the transistor 120. For example, the logic gate 116 buffers the digital pulsed signal 132A to add a pre-determined amount of delay to the digital pulsed signal 132A. To illustrate, the pre-determined amount of delay is equal to a time period taken by the logic gate 118 to invert the digital pulsed signal 132B. As such, the digital pulsed signal 132A output from the logic gate 116 is delayed compared to the digital pulsed signal 132A received by the logic gate 116.

[0031] Also, the logic gate 118 receives the digital pulsed signal 132B and inverts the digital pulsed signal 132B to output a reverse digital pulsed signal 134, which is reversely synchronized compared to the digital pulsed signal 132A. For example, when the digital pulsed signal 132A output from the logic gate 116 transitions from a low logic level to a high logic level, the reverse digital pulsed signal 134 transitions from the high logic level to the low logic level. On the other hand, when the digital pulsed signal 132A output from the logic gate 116 transitions from the high logic level to the low logic level, the digital pulsed signal 134 transitions from the low logic level to the high logic level.

[0032] An example of a low logic level of a digital pulsed signal is a low voltage amplitude or a low power amplitude and an example of a high voltage level of the digital pulsed signal is a high voltage amplitude or a high power amplitude. The high voltage amplitude is greater than the low voltage amplitude and the high power amplitude is greater than the low power amplitude.

[0033] The transistor 122 operates in reverse synchronization with the transistor 120 based on the digital pulsed signals 132A and 134. For example, when the transistor 120 is turned on in response to the digital pulsed signal 132 A, the transistor 122 is turned off in response to the digital pulsed signal 134. On the other hand, when the transistor 120 is turned off in response to the digital pulsed signal 132 A, the transistor 122 is turned on in response to the digital pulsed signal 134.

[0034] When the transistors 120 and 122 operate in reverse synchronization with each other and the DC current is supplied from the DC voltage source 112, an RF pulsed signal 136 is generated at the output 128. To illustrate, the RF pulsed signal 136 is not a sinusoidal RF signal. The RF pulsed signal 136 is sent from the output 128 to the reactive circuit 115. The reactive circuit 115 removes harmonics from the RF pulsed signal to generate a sinusoidal RF signal 138 and sends the sinusoidal RF signal 138 to the electrode.

[0035] When one or more process gases, such as a fluorine-containing gas or an oxygen-containing gas or a combination thereof, are supplied to the plasma load 106 in addition to the sinusoidal RF signal 138, plasma is generated within the plasma chamber. A substrate, such as a semiconductor wafer, placed within the plasma chamber is processed with the plasma. For example, one or more materials are deposited on the semiconductor wafer or the semiconductor wafer is etched or cleaned.

[0036] The digital pulsed signal 132 has a variable duty cycle. For example, a duty cycle of the digital pulsed signal 132 is varied, such as increased or decreased by the pulse train generator 108 under control of the controller 104. This facilitates a change, such as an increase or decrease, in an amount of power of the RF pulsed signal 136 that is provided at the output 128. With the change in the amount of power of the RF pulsed signal 136, there is a change in an amount of power of the sinusoidal RF signal 138 provided to the plasma load 106.

[0037] It should be noted that the DC voltage source 112, controlled by the controller 104, can stay constant while the power output 128 changes. For example, the controller 104 does not adjust a voltage output from the DC voltage source 112 to increase or decrease the power at the output 128. To illustrate, the controller 104 is decoupled from the DC voltage source 112. As another illustration, the controller 104 is coupled to the DC voltage source 112 but is not programmed to increase or decrease power output from the DC voltage source 112.

[0038] In an embodiment, there is control of the DC voltage source 112 by the controller 104 to control power at the output 128 in addition to a change in a duty cycle of the digital pulsed signal 132. For example, the controller 104 is coupled to the DC voltage source 112 to adjust a voltage output from the DC voltage source 112 to increase or decrease the power at the output 128.

[0039] Figure 2 is a diagram of an embodiment of a system 200 to illustrate details of a pulse train generator 202. The pulse train generator 202 is an example of the pulse train generator 108 (Figure 1). The system 200 includes the pulse train generator 202 and the controller 104. The controller 104 includes a processor 204 and a memory device 206. The processor 204 is coupled to the host computer 105.

[0040] The pulse train generator 202 includes a processing circuit 208, such as a digital signal processor (DSP) or an FPGA. The processing circuit 208 includes a timer 210 and a driver and pulse signal generator circuit 218. As an example, each of the timer 210 and the driver and pulse signal generator circuit 218 is implemented as a portion of the integrated circuit of the processing circuit 208. For example, the timer 210 is a first portion of the integrated circuit and the driver and pulse signal generator circuit 218 is a second portion of the integrated circuit.

[0041] The driver and pulse signal generator circuit 218 includes a driver and a pulse signal generator. As an example, the pulse signal generator of the driver and pulse signal generator circuit 218 is a clock source, such as an electronic oscillator, that generates a digital clock signal, which is an example of the digital pulsed signal 132. An example of the driver includes one or more transistors. The driver is coupled to the pulse signal generator.

[0042] The timer 210 of the processing circuit 208 is coupled to the processor 204 via the connection 124. The timer 210 is coupled to the driver and pulse signal generator circuit 218, which has an output 220 that is coupled to the output 126 (Figure 1).

[0043] Within the memory device 206, multiple duty cycle values, such as a duty cycle 222 and a duty cycle 224 are stored. Also stored, within the memory device 206, are parameter setpoints 230 and 232 of multiple states 234 and 236 of a parameter provided at the output 128 or at the output 129 (Figure 1). Examples of the parameter include power, voltage, and current. The parameter at the output 128 or 129 is an example of the parameter provided to the plasma load 106. An example of a state of the parameter provided to the plasma load 106 is a statistical amplitude, such as a peak-to-peak amplitude or a zero-to-peak amplitude or a combination of a maximum amplitude and a minimum amplitude. For example, a first state of the parameter is exclusive of a second state of the parameter. To illustrate, the first state has a maximum amplitude of the parameter that is different, such as greater than or less than, by at least a pre-determined percentage, e.g., 10%, from a maximum amplitude of the parameter of the second state. Also, the first state has a minimum amplitude of the parameter that is different, such as greater than or less than, by at least a pre-determined percentage, e.g., 10%, from a minimum amplitude of the parameter of the second state.

[0044] An example of a duty cycle includes a percentage for which a pulse of the digital pulsed signal 132 has the high logic level compared to a total amount of time for which the pulse has the high logic level and the low logic level. To illustrate, the pulse of the digital pulsed signal 132 has a 50% duty cycle or a 20% duty cycle or a 10% duty cycle or any other duty cycle greater than zero and less than hundred percent.

[0045] The state 234 includes the parameter setpoint 230, which is a parameter level, such as, a peak-to-peak voltage amplitude or a peak-to-peak power amplitude or a peak-to-peak current amplitude, of the parameter at the output 128 or 129 when the pulses of the digital pulsed signal 132 have the duty cycle 222. The parameter setpoint 230 defines the state 234. Similarly, the state 236 includes the parameter setpoint 232, such as a peak-to-peak voltage amplitude or a peak-to-peak power amplitude or a peak-to-peak current amplitude, of the parameter at the output 128 or 129 when the pulses of the digital pulsed signal 132 have the duty cycle 224. The parameter setpoint 232 defines the state 236. In this manner, an association is provided between the state 234 and the duty cycle 222 and an association is provided between the state 236 and the duty cycle 224. An example of an association is a one-to-one relationship or a unique relationship or a link.

[0046] The processor 204 receives the parameter setpoints 230 and 232 from the host computer 105 and determines the duty cycles 222 and 224 of the pulses of the digital pulsed signal 132 based on the parameter setpoints 230 and 232 and feedback from a power sensor, which is described below with reference to Figure 3. For example, when the parameter setpoint 230 is greater than the parameter setpoint 232, the duty cycle 222 is greater compared to the duty cycle 224. On the other hand, when the parameter setpoint 232 is lower than the parameter setpoint 232, the duty cycle 222 is less than the duty cycle 224. The parameter setpoints 230 and 232 are received by the host computer 105 from a user via an input device. The processor 204 stores the duty cycles 222 and 224 and the parameter setpoints 230 and 232 in the memory device 206. The processor 204 includes, within the control signal 130, first input information, such as the duty cycle 222 for which a number of pulses of the digital pulsed signal 132 are to occur. The processor 204 further includes, within the control signal 130, second input information, such as the duty cycle 224 for which a number of pulses of the digital pulsed signal 132 are to occur. Examples of input device include a mouse, a combination of the mouse and a keyboard, a stylus, and a touchscreen.

[0047] The processor 204 generates the control signal 130 having input information, such as the first input information or the second input information, and sends the control signal 130 via the connection 124 to the processing circuit 208. In response to receiving the control signal 130, the processing circuit 208 obtains the input information from the control signal 130,and identifies, from the control signal 130, the duty cycle 222 of a number of pulses of the digital pulsed signal 132 or the duty cycle 224 of a number of pulses of the digital pulsed signal 132.

[0048] The processing circuit 208 provides a duty cycle, such as the duty cycle 222 or 224, to the timer 210. Based on the duty cycle, such as the duty cycle 222 or 224, received from the processing circuit 208, the timer 210 determines a time period for which a pulse of the digital pulsed signal 132 is to have the high logic level and a time at which the pulse is to transition from the high logic level to the low logic level, and counts the time period. For example, when the duty cycle is 40%, the timer 210 determines that the pulse of the digital pulsed signal 132 is to have the high logic level for a time period of 40% of the total time period of the pulse. In the example, the timer 210 determines that at a time at an end of the time period of 40%, the pulse is to transition from the high logic level to the low logic level. Similarly, based on the duty cycle, the timer 210 determines the remaining time period of the duty cycle 222 for which the pulse of the digital pulsed signal 132 is to have the low logic level and a time at which the pulse is to transition from the low logic level to the high logic level. For example, when the duty cycle is 40%, the timer 210 determines that the pulse of the digital pulsed signal 132 is to have the low logic level for a time period of 60% of the total time period of the pulse. In the example, the timer 210 determines that at a time at an end of the time period of 60%, the pulse is to transition from the low logic level to the high logic level.

[0049] Also, simultaneous to the provision of the duty cycle to the timer 210, the processing circuit 208 provides the high and low logic levels to the driver and pulse signal generator circuit 218. In response to receiving the high logic level, the driver of the driver pulse signal generator circuit 218 generates a drive signal, such as a current signal, based on the high logic level and provides the drive signal to the pulse signal generator of the driver pulse signal generator circuit 218. Upon receiving the drive signal from the driver, the pulse signal generator of the driver and pulse signal generator circuit 218 generates, such as produces, a pulse of the digital pulsed signal 132 having the high logic level.

[0050] When the time period for which the pulse of the digital pulsed signal 132 is to have the high logic level ends and the time at which the pulse is to transition from the high logic level to the low logic level occurs, the timer 210 sends a signal to the driver of the driver pulse signal generator circuit 218 to drive the pulse signal generator circuit 218. Upon receiving the signal from the timer 210, the driver of the driver pulse signal generator circuit 218 sends another drive signal to the pulse signal generator circuit of the driver pulse signal generator circuit 218. In response to receiving the other drive signal, the pulse signal generator stopsgenerating the high logic level of the pulse of the duty cycle and the pulse transitions from the high logic level to the logic level.

[0051] When the time period for which the pulse of the digital pulsed signal 132 is to have the high logic level ends and the time at which the pulse is to transition from the high logic level to the low logic level occurs, the timer 210 sends a signal to the driver and counts the remaining time period of the total time period of the duty cycle of the pulse. In response to receiving the signal from the timer 210, the driver generates a drive signal, such as a current signal, based on the low logic level and provides the drive signal to the pulse signal generator. Upon receiving the drive signal from the driver, after transitioning the pulse from the high logic level to the low logic level, the pulse signal generator maintains the pulse at the low logic level.

[0052] When the time period for which the pulse of the digital pulsed signal 132 is to have the low logic level ends and the time at which the pulse is to transition from the low logic level to the high logic level occurs, the timer 210 sends a signal to the driver to drive the pulse signal generator circuit. Upon receiving the signal from the timer 210, the driver generates another drive signal, and in response to receiving the other drive signal, the pulse signal generator stops generating the low logic level and transitions from the low logic level to the high logic level.

[0053] Figure 3 is a diagram of an embodiment of a system 300 to illustrate a method for modifying a duty cycle of the digital pulsed signal 132 based on feedback of power provided at the output 128. The system 300 includes the MPS 102, the reactive circuit 115, the load 106, and a power sensor 302. The power sensor 302 is coupled to the output 128 of the MPS 102 and to the processor 204. The power sensor 302 is located within the MPS 102. The power sensor 302 measures power of the RF pulsed signal 136 to generate a power measurement 304 and provides the power measurement 304 to the processor 204. An example of the power measurement 304 is multiple power values over a time period.

[0054] Upon receiving the power measurement 304, the processor 204 compares the power measurement 304 with a predetermined threshold of error with respect to a power setpoint to control the pulse signal generator circuit 218. For example, in response to receiving the power measurement 304, the processor 204 determines whether the power measurement 304 is outside, such as greater than or less than, the predetermined threshold of error with respect to the power setpoint.

[0055] In response to determining that the power measurement 304 is outside the predetermined threshold of error to the power setpoint, the processor 204 controls the pulse train generator 108 to modify, such as increase or decrease, the duty cycle of the digital pulsed signal 132 from the duty cycle 222 to the duty cycle 224 (Figure 2). On the other hand, upondetermining that the power measurement 304 is within the predetermined threshold of error with respect to the power setpoint, the processor 204 controls the pulse train generator 108 to maintain the duty cycle of the digital pulsed signal 132. The processor 204 continues to control the pulse train generator 108 to modify the duty cycle of the digital pulsed signal 132 until the power measurement 304 is within the predetermined threshold of error with respect to the power setpoint. The power setpoint is an example of the parameter setpoint 230 or 232 (Figure 2).

[0056] In one embodiment, the power sensor 302 is coupled to the output 129 instead of being coupled to the output 128.

[0057] In an embodiment, instead of the power sensor 302, a voltage sensor is used and the method for modifying the duty cycle of the RF pulse signal 132 is equally applicable to a voltage measured by the voltage sensor as it is to the power measured by the power sensor 302. In an embodiment, instead of the power sensor 302, a current sensor is used and the method for modifying the duty cycle of the RF pulse signal 132 is equally applicable to a current measured by the current sensor as it is to the power measured by the power sensor 302.

[0058] In one embodiment, the power sensor 302 is located outside the MPS 102.

[0059] Figure 4 is an embodiment of a graph 400 to illustrate a relationship between the duty cycles of the digital pulsed signal 132 (Figure 1) and the RF power provided at the output 128 (Figure 1) or 129 (Figure 1) when the DC voltage source 112 (Figure 1) has a constant voltage. The graph 400 plots the RF power provided at the output 128 (Figure 1) or 129 (Figure 1) on a y-axis and the duty cycles of the digital pulsed signal 132 on an x-axis. With an increase in a duty cycle of the digital pulsed signal 132, there is an increase in a level, such as an amount, of the RF power at the output 128 or 129. On the other hand, with a decrease in the duty cycle of the digital pulsed signal 132, there is a decrease in the level of the RF power at the output 128 or 129.

[0060] Figure 5 is an embodiment of a graph 500 to illustrate the change in a state of the RF power provided at the output 128 (Figure 1) or 129 (Figure 1) with a change in a duty cycle of the digital pulsed signal 132 (Figure 1). For example, with a sudden change in a duty cycle of the digital pulsed signal 132 from 50% to 20%, a power level transition is achieved at the output 128 or 129 in a few micro-seconds.

[0061] The graph 500 plots the duty cycles of the digital pulsed signal 132 (Figure 1) on a y-axis and time t, measured in microseconds (ps), on an x-axis. Moreover, the graph 502 plots a voltage measured at the output 128 or 129 (Figure 1) on a y-axis and the time t on an x- axis. The voltage measured at the output 128 or 129 is plotted using arbitrary units (a.u.). It should be noted that with a decrease in the duty cycle of the digital pulsed signal 132, a state of the RF power at the output 128 or 129 is changed quickly. For example, the state changes from afirst state SI to a second state S2 within a few microseconds, such as a time period between 2 to 4 microseconds, after the duty cycle decreases. As an example, the duty cycle is decreased within one microsecond, which is less than a time period of one RF cycle. The state SI is an example of the state 234 (Figure 2) and the state S2 is an example of the state 236 (Figure 2). As such, the RF power that is provided to the plasma load 106 (Figure 1) is modified quickly by changing the duty cycle of the digital pulsed signal 132.

[0062] Figure 6 is a diagram of an embodiment of a system 600 to illustrate dead time controllers (DTCs) 602A and 602B of a dead time controller system (DTCS) 602 for providing or adjusting a dead time overlapping between a digital pulsed signal 615 at an output of the DTC 602A and a reverse digital pulsed signal 614 at an output of the DTC 602B (Figure 1). As an example, during the dead time, both the transistors 120 and 122 (Figure 1) are turned off simultaneously.

[0063] The system 600 includes an MPS 604, the reactive circuit 115, and the plasma load 106. The MPS 604 is the same, in structure and function, as the MPS 102 (Figure 1) except that the MPS 604 includes the dead time controllers 602A and 602B. For example, the MPS 604 includes the pulse train generator 108, the controller 104, and the dead time controllers 602A and 602B, the gate driver 110, the DC voltage source 112, and the half-bridge circuit 114. The DTCS 602 is sometimes referred to herein as a dead time adjuster.

[0064] The DTCS 602 is located between the pulse train generator 108 and the gate terminals of the transistors 120 and 122. For example, the DTC 602A is coupled to an output of logic gate 116 and to the gate terminal of the transistor 120. Also, the DTC 602B is coupled to an output of the logic gate 118 and to the gate terminal of the transistor 122. The dead time controllers 602 A and 602B are coupled to the pulse train generator 108.

[0065] Within the memory device 206, multiple times, such as a dead time 608 and another dead time 610, of overlap between the digital pulsed signal 615 and the reverse digital pulsed signal 614 are stored. For example, the dead times 608 and 610 are received from the user via the input device by the host computer 105 (Figure 1). The dead times 608 and 610 are sent from the host computer 105 to the processor 204 and stored in the memory device 206 by the processor 204. An example of dead time is common time period for which the digital pulsed signal 615 has the low logic level, and the reverse digital pulsed signal 614 has the low logic level.

[0066] The processor 204 associates the dead time 608 with the duty cycle 222 (Figure 2) and the dead time 610 with the duty cycle 224 (Figure 2). For example, the host computer 105 receives the association between the dead time 608 and the duty cycle 222 and theassociation between the dead time 610 and the duty cycle 224 via the input device from the user, and provides the associations to the processor 204.

[0067] Within the period of time for which the pulses of the digital pulsed signal 132 are generated, the processor 204 generates a respective control signal, such as a control signal 612 or 616, to send to the pulse train generator 108. The control signal 612 includes the dead time 608, which is a time period, to add to each occurrence of the low logic level of the digital pulsed signal 132A, having the duty cycle 222, provided at the output of the logic gate 116 and to add to each occurrence of a low logic level of the reverse digital pulsed signal 134, having the duty cycle 222, provided at the output of the logic gate 118. The control signal 612 is sent by the processor 204 via the connection 124 to the pulse train generator 108. Similarly, the control signal 616 includes the dead time 610, which is a time period, to add to each occurrence of the low logic level of the digital pulsed signal 132A, having the duty cycle 224, provided at the output of the logic gate 116 and to add to each occurrence of the low logic level of the reverse digital pulsed signal 134, having the duty cycle 224, provided at the output of the logic gate 118. The control signal 616 is sent by the processor 204 via the connection 124 to the pulse train generator 108.

[0068] Upon receiving the control signal, such as the control signal 612 or 616, the pulse train generator 108 sends signals to the dead time controllers 602A and 602B to control, such as modify or adjust, the low logic levels of the digital pulsed signals 132A and 134 to achieve a respective dead time, such as the dead time 608 or 610. The respective dead time is controlled to output the digital pulsed signals 615 and 614.

[0069] Upon receiving the signals from the pulse train generator 108 for controlling the respective dead time, the dead time controllers 602A and 602B add the respective dead time, such as the dead time 608 or 610, to the digital pulsed signals 132A and 134 during which both the transistors 120 and 122 are in an off-state simultaneously. For example, the dead time is added to the digital pulsed signal 132A to output the digital pulsed signal 615 having the dead time and is added to the reverse digital pulsed signal 134 to output the reverse digital pulsed signal 614 having the dead time.

[0070] The digital pulsed signal 615 is provided from the dead time controller 602 A to the gate terminal of the transistor 120. The transistor 120 operates, such as turns on and off, according to the digital pulsed signal 615. Also, the reverse digital pulsed signal 614 is provided from the dead time controller 602B to the gate terminal of the transistor 122. The transistor 122 operates, such as turns on and off, according to the reverse digital pulsed signal 614.

[0071] When the dead time added varies with the duty cycles 222 and 224, the dead time is variable. On the other hand, when the dead time added is fixed regardless of a transitionfrom the duty cycle 222 to the duty cycle 224 or from the duty cycle 224 to the other duty cycle, the dead time is fixed.

[0072] Figure 7A is an embodiment of a graph 702 and an embodiment of a graph 704. The graph 702 plots a digital pulsed signal 706 output from the dead time controller 602A (Figure 6). The digital pulsed signal 706 is an example of the digital pulsed signal 615 (Figure 6). Also, the graph 704 plots a reverse digital pulsed signal 708 output from the dead time controller 602B (Figure 6). The reverse digital pulsed signal 708 is an example of the reverse digital pulsed signal 614 (Figure 6).

[0073] The digital pulsed signal 706 has a series of pulses 712 and 714 of a duty cycle, which is an example of the duty cycle 222 (Figure 2). Each pulse 712 and 714 has a low logic level 720 and a high logic level 722. Also, the pulses 712 and 714 are followed by a series of pulses 716 and 718. The pulses 716 and 718 have another duty cycle, which is an example of the duty cycle 224 (Figure 2). The duty cycle of the pulses 716 and 718 is different from the duty cycle of the pulses 712 and 714 and all the pulses 712 through 718 have the same low logic level 720 and the same high logic level 722.

[0074] Also, the reverse digital pulsed signal 708 has a series of pulses 724 and 726 of a first duty cycle. Each pulse 724 and 726 has a low logic level 728 and a high logic level 730. Also, the pulses 724 and 726 are followed by a series of pulses 732 and 734. The pulses 732 and 734 have a second duty cycle, which is different from the first duty cycle but have the same low logic level 728 and the same high logic level 730.

[0075] There is an overlap of a dead time 710 between an occurrence of the low logic level 720 of each of the pulses 712 and 714 and an occurrence of the low logic level 728 of each of the pulses 724 and 726. Similarly, there is an overlap of the dead time 710 between an occurrence of the low logic level 720 of each of the pulses 716 and 718 and an occurrence of the low logic level 728 of each of the pulses 732 and 734. When the dead time 710 is the same for the different duty cycles of the digital pulsed signal 706 and the first and second duty cycles of the reverse digital pulsed signal 708, the dead time 710 is fixed.

[0076] In an embodiment, the duty cycle 222 is less than the duty cycle 224.

[0077] In one embodiment, the low logic level 728 is equal to the low logic level 720 and the high logic level 730 is equal to the high logic level 722.

[0078] Figure 7B is an embodiment of the graph 702 and an embodiment of a graph 750. The graph 750 plots a reverse digital pulsed signal 752 output from the dead time controller 602B (Figure 6). The reverse digital pulsed signal 752 is an example of the reverse digital pulsed signal 614 (Figure 6).

[0079] The reverse digital pulsed signal 752 has the series of pulses 724 and 726 of the first duty cycle. Also, the pulses 724 and 726 are followed by a series of pulses 756 and 758. The pulses 756 and 758 have a third duty cycle, which is different from the first duty cycle but have the same low logic level 728 and the same high logic level 730.

[0080] There is an overlap of the dead time 760 between an occurrence of the logic low level 720 of each of the pulses 716 and 718 and an occurrence of the logic low level 728 of each of the pulses 756 and 758. When the dead time 760 for the duty cycle of the pulses 716 and 718 (Figure 7A) and for the third duty cycle is unequal to the dead time 710 for the duty cycle of the pulses 712 and 714 (Figure 7A) and for the first duty cycle, a dead time of the reverse digital pulsed signal 752 is variable.

[0081] Embodiments described herein may be practiced with various computer system configurations including hand-held hardware units, microprocessor systems, microprocessor-based or programmable consumer electronics, minicomputers, mainframe computers and the like. The embodiments can also be practiced in distributed computing environments where tasks are performed by remote processing hardware units that are linked through a network.

[0082] In some embodiments, a controller, described herein, is a part of a system, which may be part of the above-described examples. Such systems include semiconductor processing equipment, including a processing tool or tools, chamber or chambers, a platform or platforms for processing, and / or specific processing components (a wafer pedestal, a gas flow system, etc.). These systems are integrated with electronics for controlling their operation before, during, and after processing of a semiconductor wafer or substrate. The electronics is referred to as the “controller,” which may control various components or subparts of the system or systems. The controller, depending on the processing requirements and / or the type of system, is programmed to control any of the processes disclosed herein, including the delivery of process gases, temperature settings (e.g., heating and / or cooling), pressure settings, vacuum settings, power settings, RF generator settings, RF matching circuit settings, frequency settings, flow rate settings, fluid delivery settings, positional and operation settings, wafer transfers into and out of a tool and other transfer tools and / or load locks coupled to or interfaced with a system.

[0083] Broadly speaking, in a variety of embodiments, the controller is defined as electronics having various integrated circuits, logic, memory, and / or software that receive instructions, issue instructions, control operation, enable cleaning operations, enable endpoint measurements, and the like. The integrated circuits include chips in the form of firmware that store program instructions, digital signal processors (DSPs), chips defined as application specific integrated circuits (ASICs), PLDs, and / or one or more microprocessors, or microcontrollers thatexecute program instructions (e.g., software). The program instructions are instructions communicated to the controller in the form of various individual settings (or program files), defining the parameters, the factors, the variables, etc., for carrying out a particular process on or for a semiconductor wafer or to a system. The program instructions are, in some embodiments, a part of a recipe defined by process engineers to accomplish one or more processing steps during the fabrication of one or more layers, materials, metals, oxides, silicon, silicon dioxide, surfaces, circuits, and / or dies of a wafer.

[0084] The controller, in some embodiments, is a part of or coupled to a computer that is integrated with, coupled to the system, otherwise networked to the system, or a combination thereof. For example, the controller is in a “cloud” or all or a part of a fab host computer, which allows for remote access of the wafer processing. The computer enables remote access to the system to monitor current progress of fabrication operations, examines a history of past fabrication operations, examines trends or performance metrics from a plurality of fabrication operations, to change parameters of current processing, to set processing steps to follow a current processing, or to start a new process.

[0085] In some embodiments, a remote computer (e.g., a server) provides process recipes to a system over a network, which includes a local network or the Internet. The remote computer includes a user interface that enables entry or programming of parameters and / or settings, which are then communicated to the system from the remote computer. In some examples, the controller receives instructions in the form of data, which specify the parameters, factors, and / or variables for each of the processing steps to be performed during one or more operations. It should be understood that the parameters, factors, and / or variables are specific to the type of process to be performed and the type of tool that the controller is configured to interface with or control. Thus, as described above, the controller is distributed, such as by including one or more discrete controllers that are networked together and working towards a common purpose, such as the processes and controls described herein. An example of a distributed controller for such purposes includes one or more integrated circuits on a chamber in communication with one or more integrated circuits located remotely (such as at the platform level or as part of a remote computer) that combine to control a process on the chamber.

[0086] Without limitation, in various embodiments, example systems to which the methods are applied include a plasma etch chamber or module, a deposition chamber or module, a spin-rinse chamber or module, a metal plating chamber or module, a clean chamber or module, a bevel edge etch chamber or module, a physical vapor deposition (PVD) chamber or module, a chemical vapor deposition (CVD) chamber or module, an atomic layer deposition (ALD) chamber or module, an atomic layer etch (ALE) chamber or module, an ion implantationchamber or module, a track chamber or module, and any other semiconductor processing systems that is associated or used in the fabrication and / or manufacturing of semiconductor wafers.

[0087] It is further noted that in some embodiments, the above-described operations apply to several types of plasma chambers, e.g., a plasma chamber including an inductively coupled plasma (ICP) reactor, a capacitively coupled plasma (CCP) chamber, a transformer coupled plasma chamber, conductor tools, dielectric tools, a plasma chamber including an electron cyclotron resonance (ECR) reactor, etc. For example, one or more RF generators are coupled to an inductor within the ICP reactor. Examples of a shape of the inductor include a solenoid, a dome-shaped coil, a flat-shaped coil, etc.

[0088] As noted above, depending on the process step or steps to be performed by the tool, the host computer communicates with one or more of other tool circuits or modules, other tool components, cluster tools, other tool interfaces, adjacent tools, neighboring tools, tools located throughout a factory, a main computer, another controller, or tools used in material transport that bring containers of wafers to and from tool locations and / or load ports in a semiconductor manufacturing factory.

[0089] With the above embodiments in mind, it should be understood that some of the embodiments employ various computer-implemented operations involving data stored in computer systems. These operations are those physically manipulating physical quantities. Any of the operations described herein that form part of the embodiments are useful machine operations.

[0090] Some of the embodiments also relate to a hardware unit or an apparatus for performing these operations. The apparatus is specially constructed for a special purpose computer. When defined as a special purpose computer, the computer performs other processing, program execution or routines that are not part of the special purpose, while still being capable of operating for the special purpose.

[0091] In some embodiments, the operations may be processed by a computer selectively activated or configured by one or more computer programs stored in a computer memory, cache, or obtained over the computer network. When data is obtained over the computer network, the data may be processed by other computers on the computer network, e.g., a cloud of computing resources.

[0092] One or more embodiments can also be fabricated as computer-readable code on a non-transitory computer-readable medium. The non-transitory computer-readable medium is any data storage hardware unit, e.g., a memory device, etc., that stores data, which is thereafter be read by a computer system. Examples of the non-transitory computer-readable mediuminclude hard drives, network attached storage (NAS), read-only memory (ROM), random access memory (RAM), compact disc-ROMs (CD-ROMs), CD-recordables (CD-Rs), CD-rewritables (CD-RWs), magnetic tapes and other optical and non-optical data storage hardware units. In some embodiments, the non-transitory computer-readable medium includes a computer-readable tangible medium distributed over a network-coupled computer system so that the computer- readable code is stored and executed in a distributed fashion.

[0093] Although the method operations above were described in a specific order, it should be understood that in various embodiments, other housekeeping operations are performed in between operations, or the method operations are adjusted so that they occur at slightly different times, or are distributed in a system which allows the occurrence of the method operations at various intervals, or are performed in a different order than that described above.

[0094] It should further be noted that in an embodiment, one or more features from any embodiment described above are combined with one or more features of any other embodiment without departing from a scope described in various embodiments described in the present disclosure.

[0095] Although the foregoing embodiments have been described in some detail for purposes of clarity of understanding, it will be apparent that certain changes and modifications can be practiced within the scope of appended claims. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the embodiments are not to be limited to the details given herein.

Claims

IN THE CLAIMS1. A method for controlling power output from a matchless plasma source, comprising: applying a direct current (DC) voltage to a half-bridge circuit; generating a digital pulsed signal having a plurality of pulses to provide to a gate driver of the matchless plasma source; outputting, from the gate driver, a plurality of reversely synchronized signals based on the digital pulsed signal to provide to the half-bridge circuit, wherein the half-bridge circuit has an output; and modifying a duty cycle of the digital pulsed signal to control the power provided from the output to a plasma load.

2. The method of claim 1, wherein the duty cycle is a first duty cycle, the method comprising: generating one or more signals indicating a second duty cycle, wherein the first duty cycle is modified to the second duty cycle; and determining, from the second duty cycle, a first time at which one of the plurality of pulses transition from a high logic level to a low logic level and a second time at which the one of the plurality of pulses transition from the low logic level to the high logic level.

3. The method of claim 2, comprising: driving a pulse signal generator circuit to transition the digital pulsed signal from the high logic level to the low logic level at the first time; and driving the pulse signal generator circuit to transition the digital pulsed signal from the low logic level to the high logic level at the second time to achieve the second duty cycle.

4. The method of claim 1, wherein said modifying the duty cycle occurs based on an amount of power measured by a power sensor that is coupled to the output of the halfbridge circuit.

5. The method of claim 1, wherein the duty cycle is modified to modify a state of the power provided from the output to the plasma load.

6. The method of claim 1, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, the method comprising: receiving a dead time to be applied to the first and second signals when the digital pulsed signal has the first and second duty cycles; andmodifying a duty cycle of the first signal and a duty cycle of the second signal to include the dead time when the digital pulsed signal has the first and second duty cycles.

7. The method of claim 1, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, the method comprising: receiving a first dead time to be applied to the first and second signals when the digital pulsed signal has the first duty cycle; modifying a duty cycle of the first signal and a duty cycle of the second signal to include the first dead time when the digital pulsed signal has the first duty cycle; receiving a second dead time to be applied to the first and second signals when the digital pulsed signal has the second duty cycle; modifying the duty cycle of the first signal and the duty cycle of the second signal to include the second dead time when the digital pulsed signal has the second duty cycle.

8. A matchless plasma source comprising: a half-bridge circuit having an output; a direct current (DC) voltage source coupled to the half-bridge circuit to apply DC voltage across the half-bridge circuit; a pulse train generator configured to generate a digital pulsed signal having a plurality of pulses; and a gate driver coupled to the pulse train generator and to the half-bridge circuit, wherein the gate driver is configured to provide a plurality of reversely synchronized signals based on the digital pulsed signal, wherein the plurality of reversely synchronized signals are provided to the half-bridge circuit, wherein the pulse train generator is configured to modify a duty cycle of the digital pulsed signal to control power provided from the output of the half-bridge circuit to a plasma load.

9. The matchless plasma source of claim 8, wherein the duty cycle is a first duty cycle, wherein the pulse train generator includes: a timer configured to receive one or more signals indicating a second duty cycle, wherein the first duty cycle is modified to the second duty cycle, wherein the timer is configured to determine, from the second duty cycle, a first time at which one of the plurality of pulses transition from a high logic level to a low logic level and a second time at which the one of the plurality of pulses transition from the low logic level to the high logic level.

10. The matchless plasma source of claim 9, wherein the pulse train generator includes: a pulse signal generator; a driver coupled to the pulse signal generator and to the timer, wherein the driver is configured to drive the pulse signal generator to transition the digital pulsed signal from the high logic level to the low logic level at the first time, wherein the driver is configured to drive the pulse signal generator to transition the digital pulsed signal from the low logic level to the high logic level at the second time to achieve the second duty cycle.

11. The matchless plasma source of claim 8, wherein the duty cycle is modified based on an amount of power measured by a power sensor that is coupled to the output of the halfbridge circuit.

12. The matchless plasma source of claim 8, wherein the duty cycle is modified to modify a state of the power provided from the output of the half-bridge circuit to the plasma load.

13. The matchless plasma source of claim 8, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, the matchless plasma source comprising: a dead time adjuster coupled to the gate driver and the half-bridge circuit, wherein the dead time adjuster is configured to receive a dead time to be applied to the first and second signals when the digital pulsed signal has the first and second duty cycles, wherein the dead time adjuster is configured to modify a duty cycle of the first signal and a duty cycle of the second signal to include the dead time.

14. The matchless plasma source of claim 8, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, the matchless plasma source comprising: a dead time adjuster coupled to the gate driver and the half-bridge circuit, wherein the dead time adjuster is configured to receive a first dead time to be applied to the first signal and the second signal when the digital pulsed signal has the first duty cycle, wherein the dead time adjuster is configured to receive a second dead time to be applied to the first signal and the second signal to be applied when the digital pulsed signal has the second duty cycle, wherein the dead time adjuster is configured to modify a duty cycle of the first signal and a duty cycle of the second signal to include the first dead time when the digital pulsed signal has the first duty cycle and modify the duty cycle of the first signal and the duty cycle of the second signal to include the second dead time when the digital pulsed signal has the second duty cycle.

15. A system comprising: a host computer; and a matchless plasma source coupled to the host computer, wherein the matchless plasma source includes: a half-bridge circuit having an output; a direct current (DC) voltage source coupled to the half-bridge circuit to applyDC voltage across the half-bridge circuit; a pulse train generator configured to generate a digital pulsed signal having a plurality of pulses; a gate driver coupled to the pulse train generator and to the half-bridge circuit, wherein the gate driver is configured to provide a plurality of reversely synchronized signals based on the digital pulsed signal, wherein the plurality of reversely synchronized signals are provided to the half-bridge circuit, wherein the host computer is configured to control the pulse train generator to modify a duty cycle of the digital pulsed signal, wherein the duty cycle is modified to change power provided from the output of the half-bridge circuit to a plasma load.

16. The system of claim 15, wherein the duty cycle is a first duty cycle, wherein the matchless plasma source includes a controller configured to provide one or more signals indicating a second duty cycle, wherein the first duty cycle is modified to the second duty cycle, wherein the pulse train generator includes: a timer configured to receive the one or more signals from the controller, wherein in response to receiving the one or more signals, the timer is configured to determine, from the second duty cycle, a first time at which one of the plurality of pulses transition from a high logic level to a low logic level and a second time at which the one of the plurality of pulses transition from the low logic level to the high logic level.

17. The system of claim 16, wherein the pulse train generator includes: a pulse signal generator; a driver coupled to the pulse signal generator circuit and to the timer, wherein the driver is configured to drive the pulse signal generator to transition the digital pulsed signal from the high logic level to the low logic level at the first time, wherein the driver is configured to drive the pulse signal generator to transition the digital pulsed signal from the low logic level to the high logic level at the second time to achieve the second duty cycle.

18. The system of claim 15, wherein the duty cycle is modified based on an amount of power measured by a power sensor that is coupled to the output of the half-bridge circuit.

19. The system of claim 15, wherein the duty cycle is modified to modify a state of the power provided from the output of the half-bridge circuit to the plasma load.

20. The system of claim 15, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, wherein the matchless plasma source comprises: a dead time adjuster coupled to the gate driver and the half-bridge circuit, wherein the dead time adjuster is configured to modify a duty cycle of the first signal and a duty cycle of the second signal to include a dead time.

21. The system of claim 15, wherein the duty cycle is a first duty cycle and is modified to a second duty cycle, wherein the plurality of reversely synchronized signals include a first signal and a second signal, wherein the second signal is reversely synchronized compared to the first signal, wherein the matchless plasma source comprises: a dead time adjuster coupled to the gate driver and the half-bridge circuit, wherein the dead time adjuster is configured to modify a duty cycle of the first signal and a duty cycle of the second signal to include a first dead time when the digital pulsed signal has the first duty cycle, and the dead time adjuster is configured modify the duty cycle of the first signal and the duty cycle of the second signal to include a second dead time when the digital pulsed signal has the second duty cycle.

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