Multi-node computing system with configurable host to device ratios

Abstract

A computing system includes multiple compute nodes, at least one input / output add-in device (e.g., a GPU, an accelerator), and at least one programmable switch communicatively coupled to the compute nodes, the device(s) (e.g., via bus connectors), and / or other switches. The switch may be programmed to assign a variable number of devices to each compute node as desired. For example, the switch may assign each compute node any number of devices ranging from zero devices to all the devices in the computing system. In this manner, the allocation of computing resources of the computing system (i.e., the devices) to each compute node may be reconfigurable during operation, thus improving overall utilization of the computing resources according to a user's needs.

Description

MULTI-NODE COMPUTING SYSTEM WITH CONFIGURABLE HOST TO DEVICERATIOSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims the benefit of and priority to U.S. Provisional ApplicationNo. 63 / 585,590, filed September 26, 2023, which is hereby incorporated by reference in its entirety.BACKGROUND

[0002] A data center includes multiple networked computer servers to process, store, and distribute large amounts of data. Conventional data centers often use central processing units (CPUs) to perform a wide array of tasks, such as database management and providing applications and services to a large user base. More recently, data centers have introduced graphics processing units (GPUs) as workload accelerators to perform more computationally intensive tasks that benefit from the high levels of parallelism provided by a GPU, such as training machine learning models, running simulations, or performing data analytics. For example, training a machine learning model, such as a large language model, is often performed using multiple GPUs distributed across multiple networked GPU servers.

[0003] Conventional data centers typically offer users (e.g., customers) access to their computing resources as a service. Depending on the user’s needs and the services provided by the data center, conventional data centers may provide varying levels of control over the infrastructure of the data center. For example, data centers may provide users with access to computational, storage, and networking infrastructure to perform the user’s workload(s) (e.g., a program, a software application).SUMMARY

[0004] The Inventors have recognized and appreciated different workloads by a single user often require appreciably different amounts of computing power. The Inventors have also recognized and appreciated the computing power for a particular workload may also vary over time. For example, the computing power required to train a machine learning model may vary appreciably depending on the type of the machine model, the underlying algorithms used within the model, the types of data being processed, and so on. Additionally, the overall size of a model may increase over time, particularly as progressively larger training datasets are used.[0005 [ However, the Inventors have further recognized conventional data centers typically provide users access to computing resources in relatively large increments, leading to excesscomputing resources being allocated to users. For example, conventional data centers often include servers that provide a single compute node with a fixed number of Peripheral Component Interconnect Express (PCIe) devices (e.g., GPUs, accelerators). When a user pays to use the computing resources of the data center, they typically do so by purchasing access to one (or more) compute nodes where each compute node has a fixed number of PCIe devices. If a user does not require all of the PCIe devices available for a single compute node, they may pay for more computing power than is needed for their particular workload. Moreover, any unused PCIe devices may become stranded, i.e., unused for other workloads by the same user or a different user. The inefficient use of the PCIe devices may, in turn, lead to a higher overall total cost of ownership for the user.10006] In some conventional data centers, a networked architecture may be implemented where the computing resources provided by one server (e.g., the PCIe devices) are shared with another server, thus allowing for more efficient utilization of computing resources. However, networked architectures are often complex and expensive to implement. For example, networked architectures are often prone to issues related to, for example, the compatibility of network protocols for data transmission and bandwidth limitations.10007] In view of the foregoing limitations of conventional data centers, the present disclosure is directed to various inventive implementations of a computing system (e.g., a server) that includes multiple compute nodes, at least one input / output add-in device (also referred to herein as a “device”), and at least one programmable switch (hereafter referred to as a “switch”) communicatively coupled to the compute nodes, the device(s) (e.g., via bus connectors), and / or other switches. The devices contemplated here in may include, but are not limited to, a graphics processing unit (GPU), an accelerator, an application-specific integrated circuit (ASIC), a field- programmable gate array (FPGA), and a storage device. The switch may be programmed to assign a variable number of devices to each compute node as desired. For example, the switch may assign each compute node any number of devices ranging from zero devices to all the devices in the computing system.

[0008] In this manner, the allocation of computing resources for each compute node of the computing system may be reconfigurable during operation (e.g., between the execution of workloads) to adapt to the user’s needs. This, in turn, may lead to more efficient utilization of the computing resources (e.g., by reducing the number of unused devices). Compared to conventional data centers with a networked architecture, the computing systems disclosed herein similarly allows computing resources to be shared between multiple compute nodes, but with appreciably greater simplicity and lower cost of deployment.

[0009] Additionally, the inclusion of the compute nodes, the devices, and the switches in a single system may allow for greater architectural flexibility. For example, the computing systems disclosed herein may readily allow alterations in the way the switches, the devices, and the compute nodes are connected to one another during manufacture and assembly without altering the design of the components in the system. This may be accomplished, for example, by connecting the switch to the compute nodes and the devices using a combination of cables and ports. In one example, the computing system may be configured where all the devices are communicatively coupled to one another via one or more switches. Thus, the devices may transmit or receive data to and from one another without using the compute nodes. In another example, the computing system may be configured where each switch is communicatively coupled to all the compute nodes, thus providing higher bandwidth and lower latency between each compute node and the devices since each device only has to go through one switch to communicate with a compute node.[0010| It should be appreciated that all combinations of the foregoing concepts and additional concepts discussed in greater detail below (provided such concepts are not mutually inconsistent) are contemplated as being part of the inventive subject matter disclosed herein. In particular, all combinations of claimed subject matter appearing at the end of this disclosure are contemplated as being part of the inventive subject matter disclosed herein. It should also be appreciated that terminology explicitly employed herein that also may appear in any disclosure incorporated by reference should be accorded a meaning most consistent with the particular concepts disclosed herein.BRIEF DESCRIPTION OF THE DRAWINGS(0011] The skilled artisan will understand that the drawings primarily are for illustrative purposes and are not intended to limit the scope of the inventive subject matter described herein. The drawings are not necessarily to scale; in some instances, various aspects of the inventive subject matter disclosed herein may be shown exaggerated or enlarged in the drawings to facilitate an understanding of different features. In the drawings, like reference characters generally refer to like features (e.g., functionally similar and / or structurally similar elements).

[0012] FIG. 1 shows a logical diagram of an example computing system with a single layer of programmable switches to configure the connectivity between multiple compute nodes and multiple devices. In this example, each switch is communicatively coupled to every compute node and a subset of the devices are communicatively coupled directly to each another via the switches.10013] FIG. 2 shows a logical diagram of another example computing system with a single layer of programmable switches, multiple compute nodes, and multiple devices. In this example, eachswitch is communicatively coupled to a subset of the compute nodes and all the devices are communicatively coupled directly to each another via the switches.

[0014] FIG. 3 shows a logical diagram of another example computing system with a single layer of programmable switches, multiple compute nodes, and multiple devices. In this example, each switch is communicatively coupled to every compute nodes and all the devices are communicatively coupled directly to each another via the switches.

[0015] FIG. 4 shows a flow chart for an example method of operating a computing system.

[0016] FIG. 5 shows a logical diagram of another example computing system with two layers of programmable switches, multiple compute nodes, and multiple devices. In this example, a subset of the devices is communicatively coupled directly to compute nodes via a first layer of switches and the remaining devices are communicatively coupled to the subset of devices via a second layer of switches.

[0017] FIG. 6 shows a logical diagram of another example computing system with two layers of programmable switches, multiple compute nodes, and multiple devices. In this example, all the devices are communicatively coupled together by a second layer of switches.DETAILED DESCRIPTION

[0018] Following below are more detailed descriptions of various concepts related to, and implementations of, a computing system (e.g., a server) that can be configured to allocate a different number of devices (e.g., a GPU, an accelerator) to different compute nodes during operation (e.g., between execution of workloads) using at least one switch communicatively coupled to the compute nodes, the device(s) (e.g., via bus connectors), and / or other switches. It should be appreciated that various concepts introduced above and discussed in greater detail below may be implemented in multiple ways. Examples of specific implementations and applications are provided primarily for illustrative purposes so as to enable those skilled in the art to practice the implementations and alternatives apparent to those skilled in the art.[0019 [ The figures and example implementations described below are not meant to limit the scope of the present implementations to a single embodiment. Other implementations are possible by way of interchange of some or all of the described or illustrated elements. Moreover, where certain elements of the disclosed example implementations may be partially or fully implemented using known components, in some instances only those portions of such known components that are necessary for an understanding of the present implementations are described, and detailed descriptions of other portions of such known components are omitted so as not to obscure the present implementations.

[0020] In the discussion below, various examples of a computing system are provided, wherein a given example or set of examples showcases a compute node, a programmable switch, a bus connector for a device, a device, and a lane to communicatively couple the switch to another component. It should be appreciated that one or more features discussed in connection with a given example of a computing system may be employed in other examples of computing systems, respectively, according to the present disclosure, such that the various features disclosed herein may be readily combined in a given computing system according to the present disclosure (provided that respective features are not mutually inconsistent).

[0021] Certain features of the computing system are described herein using the terms “approximately,” “about,” “substantially,” and / or “similar.” As used herein, the terms “approximately,” “about,” “substantially,” and / or “similar” indicates that each of the described dimensions or features is not a strict boundary or parameter and does not exclude functionally similar variations therefrom. Unless context or the description indicates otherwise, the use of the terms “approximately,” “about,” “substantially,” and / or “similar” in connection with a numerical parameter indicates that the numerical parameter includes variations that, using mathematical and industrial principles accepted in the art (e.g., rounding, measurement or other systematic errors, manufacturing tolerances, etc.), would not vary the least significant digit.1. Examples of Computing Systems with Programmable Switches[00221 The computing systems disclosed herein may generally support one or more devices. This may be accomplished by the computing system providing one or more bus connectors (also referred to herein as a “connector”) to communicatively couple a device to the computing system. The bus connector facilitates connection of a device to a printed circuit board (PCB). The bus connector also provides features to mechanically couple the device to the computing system and / or supply electrical power to a device. For example, a PCB may include multiple bus connectors to support multiple add-in cards. Examples of bus connectors include, but are not limited to, bus slots and bus sockets. The bus connectors may generally support various computer component interconnections (communicative couplings) including, but not limited to, Universal Serial Bus (USB), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIe), Compute Express Link (CXL), and the like.

[0023] The device may generally be an input / output device communicatively coupled to a compute node in the computing system. The device may include a card and / or a module. For example, a card may comply with a PCIe card electromechanical specification (CEM) standard and / or the like. The card may conform to various form factor solutions including, but not limited to, a half-height, half length (HHHL) form factor, a full height, half length (FHHL) form factor, ahalf-height, full length (HHFL) form factor, and a full height, full length (FHFL) form factor. In another example, a module may include a custom or standard module board device, such as an Open Compute Project Accelerator Module (OAM), a SXM module, and / or the like. Modules are typically smaller in size than cards and have different input and output interface connectors. Each device may generally provide various electronic circuitry including, but not limited to, a graphics processing unit (GPU), an accelerator, an application-specific integrated circuit (ASIC), a field- programmable gate array (FPGA), and a storage device.

[0024] In the following, several examples of computing systems with programmable switches and multiple bus connectors to support multiple devices are described. It should be appreciated that the computing systems described below are non-limiting examples and that the features of each computing system may be readily implemented in other example computing systems that support various types of devices (e.g., PCIe devices, OAM devices, SXM devices, and so on).1.1 Examples of Computing Systems with a Single Layer of Switches

[0025] FIG. 1 shows an example computing system 100a. As shown, the computing system 100a includes multiple compute nodes, multiple bus connectors that are each configured to support a device, and multiple programmable switches. The compute nodes, the switches, and the bus connectors may be disposed on a single printed circuit board (PCB) or multiple PCBs. For example, the compute nodes may be mounted to a first PCB, the switches may be mounted to a second PCB, and the bus connectors maybe mounted to a third PCB. The first, second, and third PCBs may be connected together via one or more cables.

[0026] In this example, the switches are arranged in a single logical layer between the compute nodes and the devices. Each switch may be communicatively coupled to all the compute nodes and a subset of the bus connectors. However, it should be appreciated that collectively the switches are communicatively coupled to all the bus connectors. In some implementations, the computing system 100a may be implemented to support PCIe devices using PCIe compatible switches and PCIe bus connectors. However, it should be appreciated that the computing system 100a may be implemented to support other types of devices (OAM, SXM, and / or the like).

[0027] Each compute node may include one or more microprocessors communicatively coupled to each other. During operation, the microprocessor s) of a compute node may work together and, in some instances, with communicatively coupled devices allocated to that compute node on a particular workload or computational task, e.g., training an artificial intelligence (Al) inference model, running an application, communicating with a user, such as a customer, and / or the like. Other microprocessors of other compute nodes and other devices that are not allocated to thatcompute node in the computing system 100a do not work on the same workload. Example microprocessors that may be used in a compute node in the computing system 100a include, but is not limited to, a 4th generation Intel® Xeon® Scalable Processor, Max Series, available from Intel Corporation® of Santa Clara, California, an Intel 5th generation Xeon® processor (currently codenamed Emerald Rapids), and the like. It should be appreciated that the compute nodes of the computing system 100a is not limited only to Intel microprocessors. Rather, the compute nodes may include other types of microprocessors.

[0028] In the example computing system 100a depicted in FIG. 1, each compute node may include two sockets to support a pair of microprocessors. The computing system 100a further includes four compute nodes resulting in a total of eight microprocessors. More generally, each compute node may include one or more sockets that supports one or more corresponding microprocessors. The computing system 100a may include less than four compute nodes or more than four compute nodes. For example, the number of compute nodes in the computing system 100a may range from 2 to 8. The compute nodes may further include other hardware including, but not limited to, memory (e.g., volatile memory, non-volatile memory) and a network interface controller (NIC) to facilitate communication (e.g., with a user) over a network, such as a local area network or wide area network.

[0029] The switch is a component that controls and manages communications between the compute nodes and the devices via the bus connectors. Herein, each switch may be programmable, thus providing a way to redirect communications between the devices and the compute nodes. In this manner, the switches may be used to allocate a variable number of devices for use with a particular compute node. For example, the switches may allocate a first subset of bus connectors for one compute node to execute a first workload. After the first workload is completed, the switches may allocate a second subset of bus connectors containing a different number of bus connectors than the first subset for that same compute node to execute a second workload. It should be appreciated that some of the bus connectors in the first subset may also be in the second subset. As an illustrative example, the switch may be a Broadcom PEX family PCIe Gen5 switch (PN: PEX89144).

[0030] FIG. 1 shows the computing system 100a may further include a baseboard management controller (BMC) communicatively coupled to the switches. In some implementations, the BMC may be responsible for assigning workloads to the different compute nodes and / or assigning a variable number of devices to each compute node to execute a particular workload. The BMC may include, for example, a microcontroller, programmable logic controller, microprocessor, field- programmable gate array, logic circuitry, memory, or some combination thereof.

[0031] FIG. 1 further shows each switch may be communicatively coupled to the compute nodes, the bus connectors, and / or other switches via a plurality of lanes connected to corresponding ports of the switch. Each lane may provide an electrical connection between the switch and another component of the computing system. It should be appreciated that, in some implementations, lanes may be provided directly between devices. In other words, one device may directly communicate with another device without using a switch. For example, the lane may include a pair of traces formed on a printed circuit board with one trace to transmit data from the switch and another trace to transmit data to the switch. In another example, the lane may be an electrical cable with a pair of wires with one wire to transmit data from the switch and another wire to transmit data to the switch.10032] The computing system 100a may include one or more printed circuit boards (PCBs) supporting the compute the nodes, the switches, the bus connectors, and the lanes. In some implementations, the one or more PCBs may be housed within a chassis to facilitate assembly, handling, and installation (e.g., into a tank of an immersion cooling system). Thus, the computing system 100a may be a standalone system (e.g., a standalone server). Compared to servers with a networked architecture, the computing system 100a is appreciably simpler while still providing a way to allocate computing resources for different workloads as desired.[00331 Each switch has a finite number of ports, thus limiting the number of lanes connected to that switch. This, in turn, limits the number of compute nodes, bus connectors, and / or switches that may be connected to each switch. For example, in the computing system 100a, each switch may have 144 ports. Each bus connectors may further provide 16 lanes for each device, which is typical for PCIe bus connectors and devices. Accordingly, the switch may be connected to a compute node and / or another switch with 16 lanes to provide sufficient bandwidth for communication between a device and a compute node. As a result, each switch may be communicatively coupled up to nine other components (e.g., compute nodes, bus connectors, switches).

[0034] This means each switch may not be communicatively coupled to all the compute nodes, all other switches, and all the bus connectors. As a result, the performance of the computing system may be affected by the components that are selected for connection to each switch. For example, a switch that is directly connected to a compute node and a bus connector may provide a higher bandwidth and lower latency for communication between that compute node and a device connected to that bus connector since the device only has to go through one switch to communicate with that compute node. In another example, certain workloads (e.g., a workload involving highly parallel computations) may be executed more quickly if the devices communicate directly witheach other without using a compute node. This may be facilitated, in part, by a switch being connected to a first subset of bus connectors and / or another switch connected to a second subset of bus connectors such that communications between devices in the first or second subsets may occur using only the switches.

[0035] The selection of components for connection to each switch also depends on the number of compute nodes, the number of switches, and the number of bus connectors in the computing system. For example, the computing system 100a includes four compute nodes, four switches, and sixteen bus connectors as shown in FIG. 1. This selection is based, in part, on constraints on the overall size of the computing system 100a. For example, the computing system 100a may be installed into a tank of a two-phase immersion cooling system. The tank may impose size constraints that limit the number of compute nodes and / or bus connectors in the computing system.

[0036] It should be appreciated that the number of compute nodes, the number of switches, and the number of bus connectors in the computing system 100a is non-limiting. More generally, the computing systems disclosed herein may include at least two compute nodes, at least one switch, and at least one bus connector. For example, the number of compute nodes may range from 2 to 8, the number of switches may range from 2 to 8, and / or the number of bus connectors may range from 4 to 32. In some implementations, the ratio of the number of compute nodes and the number of bus connectors in a computing system is preferably divisible by a factor of 2.

[0037] For the computing system 100a, each switch is directly connected to all the compute nodes, a subset of the bus connectors, and one other switch. Thus, the devices connected to the pair of switches may communicate with each other without using a compute node. The architecture of the computing system 100a may thus provide greater bandwidth between each device and the compute nodes. However, each device may only communicate directly to a subset of the devices.[0038| FIG. 2 shows another example computing system 100b where each device is directly connected to a pair of compute nodes, a subset of the bus connectors, and all other switches. In this example, each device may communicate with every other device (e.g., via one or two switches) without using the compute nodes. For this architecture, a lower bandwidth is expected between a subset of the devices and compute nodes (e.g., devices and compute nodes that are communicatively coupled via two switches). However, this lower bandwidth may be compensated, for example, by communicatively coupling devices directly to one another, e.g., by providing lanes directly between the bus connectors supporting the devices.10039] It should be appreciated that the architecture of the computing systems 100a and 100b are non-limiting examples. In some implementations, the computing system may achieve highbandwidth and lower latency between every compute node and device and allow communication between all the devices without using a compute node. This may be accomplished, for example, by using a switch with more ports. In another example, the computing system may include a larger number of switches. In yet another example, the computing system may have relatively fewer compute nodes and / or devices. For example, FIG. 3 shows a computing system 100c with two compute nodes, four switches, and sixteen bus connectors. As shown, each switch is connected to all the compute nodes, all other switches, and a subset of the bus connectors, thus providing high bandwidth and low latency communication between each device and each compute node while allowing each device to communicate with every other device without using a compute node.

[0040] As described above, the switches in the computing systems disclosed herein may be used to allocate a different number of bus connectors and, hence a different number of devices to each compute node during operation. This, in turn, provides a way to more efficiently utilize the computing resources available on the computing system by improving the distribution of resources amongst multiple workloads, thus reducing the number of devices that are unused at any given moment in time. Generally, each compute node may be allocated from zero bus connectors up to all the bus connectors (provided they are available for use). Referring back to the computing system 100a, this means the number of bus connectors that may be assigned to each compute node ranges from 0 to 16. For example, each of the four compute nodes may be allocated four bus connectors. In another example, two compute nodes may be allocated eight bus connectors and the remaining two compute node may be allocated zero bus connectors. The allocation of bus connectors to each compute node may change over time depending on the workloads assigned for execution.[00411 It should be appreciated that certain workloads may be executed by a compute node without any allocation of devices (i.e., zero bus connectors). For example, the workload may involve preprocessing and / or postprocessing of data, which is typically less computationally expensive to perform using a compute node than a device.

[0042] In some implementations, the computing systems disclosed herein may be controlled by a single user. Thus, the user may run multiple workloads (e.g., via different compute nodes) and, in doing so, may allocate a different number of bus connectors to each compute node accordingly as desired. The allocation of resources may further be adjusted over time. For example, if a workload initially requires two GPUs and later requires 10 GPUs, the user can simply reconfigure the resources allocated for that particular workload from the pool of resources available on the computing system.

[0043] It should be appreciated that, in some implementations, multiple users may use the computing systems disclosed herein. For example, a first user may access two compute nodes in the computing system 100a (e.g., via their respective NICs) and a second user may access the remaining two compute nodes of the computing system 100a (e.g., via their respective NICs). The first and second users may thus share the computational resources available on the computing system 100a. It should be appreciated, however, that if multiple users share the same computational resources of the computing system 100a, the compute node, the switches, and the devices may be allocated and configured such that data flows within the computing system 100a are isolated between the users. In other words, no user may have access to the resources allocated to another user. Further, no user may have access to any data or information associated with another user.1.2 An Example Method of Operating the Computing System

[0044] FIG. 4 shows an example method 200 for reconfiguring the number of bus connectors and, by extension, the number of devices allocated to a compute node for different workloads. The method 200 begins at step 202 with a first switch of a plurality of switches receiving a first instruction to assign a first subset of bus connectors of a plurality of bus connectors to a first compute node of a plurality of compute nodes. The instruction may be provided, for example, by an out of band method (e.g., using the BMC), or a secure in band method (e.g., using a compute node).[0045[ At step 204, the first switch may thereafter assign the first subset of bus connectors to the first compute node. For example, the first switch may include onboard memory to store a record indicating a correspondence between the compute node and the first subset of bus connectors. The record may be used by the first switch to determine where to direct communication to and from the compute node and the first subset of bus connectors.[0046[ At step 206, the first switch may receive a second instruction (e.g., from the BMC) to assign a second subset of bus connectors of a plurality of bus connectors to the first compute node. At step 208, the first switch may thereafter assign the second subset of bus connectors to the first compute node. This may be accomplished, for example, by overwriting the record stored in the onboard memory of the first switch such that the record now indicates a correspondence between the compute node and the second subset of bus connectors.

[0047] Steps 206 and 208 may occur after the first compute node finishes execution of a first workload and is instructed to execute a second workload. For example, the first compute node may be temporarily suspended after completing execution of the first workload where no data is transmitted to or from the first compute node and no workloads are assigned to the first computenode. During this time, the allocation of devices to the first compute node may be changed by adding or removing a device that is also temporarily suspended by the BMC before sending instructions to the first compute node to execute the second workload.1.3 Examples of Computing Systems with Two Layers of Switches[0048 [ The computing systems lOOa-lOOc described in Section 1.1 include a single layer of switches to assign and allocate a variable number of devices to the compute nodes. It should be appreciated that these are non-limiting examples. More generally, the computing systems disclosed herein may support other architectures with two (or more) layers of switches, which provides greater flexibility to configure the computing system.[00491 FIG. 5 shows an example computing system lOOd that includes programmable switches connected to multiple bus connectors supporting corresponding devices. Specifically, the computing system lOOd includes a switch A located in a first layer that communicatively couples two compute nodes to switches B located in a second layer. The switches B, in turn, are communicatively coupled to the bus connectors and, hence, the devices. Herein, the first layer and the second layer refer to a logical arrangement in the architecture of the computing system lOOd and not a physical arrangement. In particular, the first layer refers to switches that communicatively couple the compute nodes to the bus connectors. The second layer refers to switches that communicatively couple the bus connectors to one another. In this example, the switches A and B may be identical or different. The computing system lOOd may further include a baseboard management controller (BMC) communicatively coupled to the switches A and B. As described in Section 1.1, the BMC may be responsible for assigning workloads to the different compute nodes and / or assigning a variable number of devices to each compute node to execute a particular workload.[0050| In some implementations, the computing system lOOd may be implemented to support 0AM devices using 0AM compatible switches and 0AM bus connectors. Compared to PCIe devices, 0AM devices typically have more lanes available for communication, which may also provide greater flexibility to configure the computing system lOOd by providing more options to connect devices to other devices and / or switches. For example, an 0AM bus connector and, by extension, the 0AM device, may have 128 lanes (e.g., 8 by 16 lanes) available for communication. Further, 0AM devices often support PCIe serializers / deserializers (serdes). In some implementations, the switches used to support a computing system with PCIe devices may also be used to support a computing system with 0AM devices. Accordingly, the switches in the computing system lOOd may be Broadcom PEX family PCIe Gen5 switches (PN: PEX89144). However, it should be appreciated that the switches may not be PCIe-based switches. Moregenerally, other types of programmable high speed serdes switches may be used specifically supporting OAM devices, SXM devices, and / or the like. It should also be appreciated that the computing system 1 OOd may be implemented to support other types of devices (PCIe, SXM, and / or the like).[00511 Each bus connector may be communicatively coupled to a subset of the switches B. For example, FIG. 5 shows each bus connector may be communicatively coupled to two of the four switches B in the computing system lOOd with four of the eight bus connectors communicatively coupled to one pair of switches B (see Group 1 in FIG. 5) and the remaining four bus connectors communicatively coupled to the remaining pair of switches B (see Group 2 in FIG. 5). The bus connectors may each be coupled to a switch using 32 lanes. Accordingly, the devices in Group A may communicate with one another through the switches B in Group A. Similarly, the devices in Group B may communicate with one another through the switches B in Group B. The devices in Groups A and B may communicate with one another through the switch A. Thus, the devices in the computing system lOOd may each communicate with one another either through the switches B in the second layer and / or the switch A in the first layer without using any of the compute nodes.

[0052] It should be appreciated that the architecture of the computing system lOOd in FIG. 5 is a non-limiting example. In other examples, multiple layers of switches may be implemented with different connections to the bus connectors. For example, FIG. 6 shows a computing system lOOe where each bus connector is communicatively coupled to each switch B in the second layer. Thus, the devices connected to the bus connectors may communicate with one another using only the switches B (i.e., without using the switch A or the compute nodes). More generally, the computing system lOOd may include two or more compute nodes, at least one switch A in the first layer, at least one switch B in the second layer, and at least one device. In some implementations, the computing system lOOd may include additional layers of switches to communicatively couple yet more bus connectors and devices to each other, other switches, and / or the compute nodes.10053] The computing system lOOd may operate in a similar manner to the computing systems 100a- 100c described in Section 1.1. In particular, the switches A and B may control and manage communications between the compute nodes and the devices via the bus connectors. In doing so, the switches A and / or B may be used to configure the computing system lOOd to change the number of devices allocated for use by each compute node.2. Conclusion10054] All parameters, dimensions, materials, and configurations described herein are meant to be example and the actual parameters, dimensions, materials, and / or configurations will depend uponthe specific application or applications for which the inventive teachings is / are used. It is to be understood that the foregoing embodiments are presented primarily by way of example and that, within the scope of the appended claims and equivalents thereto, inventive embodiments may be practiced otherwise than as specifically described and claimed. Inventive embodiments of the present disclosure are directed to each individual feature, system, article, material, kit, and / or method described herein.|0055] In addition, any combination of two or more such features, systems, articles, materials, kits, and / or methods, if such features, systems, articles, materials, kits, and / or methods are not mutually inconsistent, is included within the inventive scope of the present disclosure. Other substitutions, modifications, changes, and omissions may be made in the design, operating conditions and arrangement of respective elements of the example implementations without departing from the scope of the present disclosure. The use of a numerical range does not preclude equivalents that fall outside the range that fulfill the same function, in the same way, to produce the same result.

[0056] The above-described embodiments can be implemented in multiple ways. For example, embodiments may be implemented using hardware, software or a combination thereof. When implemented in software, the software code can be executed on a suitable processor or collection of processors, whether provided in a single computer or distributed among multiple computers.[0057[ Further, it should be appreciated that a computer may be embodied in any of a number of forms, such as a rack-mounted computer, a desktop computer, a laptop computer, or a tablet computer. Additionally, a computer may be embedded in a device not generally regarded as a computer but with suitable processing capabilities, including a Personal Digital Assistant (PDA), a smart phone or any other suitable portable or fixed electronic device.[0058| Also, a computer may have one or more input and output devices. These devices can be used, among other things, to present a user interface. Examples of output devices that can be used to provide a user interface include printers or display screens for visual presentation of output and speakers or other sound generating devices for audible presentation of output. Examples of input devices that can be used for a user interface include keyboards, and pointing devices, such as mice, touch pads, and digitizing tablets. As another example, a computer may receive input information through speech recognition or in other audible format.

[0059] Such computers may be interconnected by one or more networks in a suitable form, including a local area network or a wide area network, such as an enterprise network, an intelligent network (IN) or the Internet. Such networks may be based on a suitable technology, may operateaccording to a suitable protocol, and may include wireless networks, wired networks or fiber optic networks.

[0060] The various methods or processes outlined herein may be coded as software that is executable on one or more processors that employ any one of a variety of operating systems or platforms. Additionally, such software may be written using any of a number of suitable programming languages and / or programming or scripting tools, and also may be compiled as executable machine language code or intermediate code that is executed on a framework or virtual machine. Some implementations may specifically employ one or more of a particular operating system or platform and a particular programming language and / or scripting tool to facilitate execution.

[0061] Also, various inventive concepts may be embodied as one or more methods, of which an example has been provided. The acts performed as part of the method may be ordered in any suitable way. Accordingly, embodiments may be constructed in which acts are performed in an order different than illustrated, which may include performing some acts simultaneously, even though shown as sequential acts in illustrative embodiments.

[0062] All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.1 063] All definitions, as defined and used herein, should be understood to control over dictionary definitions, definitions in documents incorporated by reference, and / or ordinary meanings of the defined terms.

[0064] The indefinite articles “a” and “an,” as used herein in the specification and in the claims, unless clearly indicated to the contrary, should be understood to mean “at least one.”|0065] The phrase “and / or,” as used herein in the specification and in the claims, should be understood to mean “either or both” of the elements so conjoined, i.e., elements that are conjunctively present in some cases and disjunctively present in other cases. Multiple elements listed with “and / or” should be construed in the same fashion, i.e., “one or more” of the elements so conjoined. Other elements may optionally be present other than the elements specifically identified by the “and / or” clause, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, a reference to “A and / or B”, when used in conjunction with open-ended language such as “comprising” can refer, in one embodiment, to A only (optionally including elements other than B); in another embodiment, to B only (optionally including elements other than A); in yet another embodiment, to both A and B (optionally including other elements); etc.

[0066] As used herein in the specification and in the claims, “or” should be understood to have the same meaning as “and / or” as defined above. For example, when separating items in a list, “or” or “and / or” shall be interpreted as being inclusive, i.e., the inclusion of at least one, but also including more than one, of a number or list of elements, and, optionally, additional unlisted items. Only terms clearly indicated to the contrary, such as “only one of’ or “exactly one of,” or, when used in the claims, “consisting of,” will refer to the inclusion of exactly one element of a number or list of elements. In general, the term “or” as used herein shall only be interpreted as indicating exclusive alternatives (i.e., “one or the other but not both”) when preceded by terms of exclusivity, such as “either,” “one of,” “only one of,” or “exactly one of.” “Consisting essentially of,” when used in the claims, shall have its ordinary meaning as used in the field of patent law.10067] As used herein in the specification and in the claims, the phrase “at least one,” in reference to a list of one or more elements, should be understood to mean at least one element selected from any one or more of the elements in the list of elements, but not necessarily including at least one of each and every element specifically listed within the list of elements and not excluding any combinations of elements in the list of elements. This definition also allows that elements may optionally be present other than the elements specifically identified within the list of elements to which the phrase “at least one” refers, whether related or unrelated to those elements specifically identified. Thus, as a non-limiting example, “at least one of A and B” (or, equivalently, “at least one of A or B,” or, equivalently “at least one of A and / or B”) can refer, in one embodiment, to at least one, optionally including more than one, A, with no B present (and optionally including elements other than B); in another embodiment, to at least one, optionally including more than one, B, with no A present (and optionally including elements other than A); in yet another embodiment, to at least one, optionally including more than one, A, and at least one, optionally including more than one, B (and optionally including other elements); etc.

[0068] In the claims, as well as in the specification above, all transitional phrases such as “comprising,” “including,” “carrying,” “having,” “containing,” “involving,” “holding,” “composed of,” and the like are to be understood to be open-ended, i.e., to mean including but not limited to. Only the transitional phrases “consisting of’ and “consisting essentially of’ shall be closed or semi-closed transitional phrases, respectively, as set forth in the United States Patent Office Manual of Patent Examining Procedures, Section 2111.03.

Claims

CLAIMS1. A computing system, comprising: a plurality of compute nodes; a plurality of bus connectors; a plurality of devices, each device of the plurality of devices being coupled to one bus connector of the plurality of bus connectors; and a plurality of switches, communicatively coupled to the plurality of compute nodes and the plurality of bus connectors, to assign each compute node of the plurality of compute nodes a variable number of bus connectors from the plurality of bus connectors for communication with that compute node during operation of the computing system, the variable number of bus connectors ranging from zero to a total number of the plurality of bus connectors.

2. The computing system of claim 1, wherein the plurality of devices comprises at least one of a Peripheral Component Interconnect Express (PCIe) device, an Open Compute Project Accelerator Module (OAM) device, or a SXM module.

3. The computing system of claim 1, wherein the plurality of devices includes at least one of a graphics processing unit (GPU), an accelerator, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a storage device.

4. The computing system of claim 1, wherein the plurality of devices consists of at least one of a graphics processing unit (GPU) or an accelerator.

5. The computing system of claim 1, wherein a ratio of a first total number of the plurality of bus connectors and a second total number of the plurality of compute nodes is divisible by a factor of 2.

6. The computing system of claim 5, wherein: the first total number is 16; and the second total number is 4.

7. The computing system of claim 1, further comprising: a chassis to mechanically support the plurality of compute nodes, the plurality of switches, and the plurality of bus connectors.

8. The computing system of claim 1, wherein: at least a subset of bus connectors of the plurality of bus connectors are communicatively coupled to each other via at least one switch of the plurality of switches such that communication from one bus connector in the subset of bus connectors to another bus connector in the subset of bus connectors occurs without the plurality of compute nodes.

9. The computing system of claim 1, wherein each switch of the plurality of switches is communicatively coupled to: a subset of bus connectors in the plurality of bus connectors; a subset of other switches in the plurality of switches; and all of the plurality of compute nodes.

10. The computing system of claim 1, wherein each switch of the plurality of switches is communicatively coupled to: a subset of bus connectors in the plurality of bus connectors; all other switches in the plurality of switches; and a subset of compute nodes in the plurality of compute nodes.

11. The computing system of claim 1, wherein each switch of the plurality of switches is communicatively coupled to: a subset of bus connectors in the plurality of bus connectors; all other switches in the plurality of switches; and all of the plurality of compute nodes.

12. The computing system of claim 1, further comprising: a first printed circuit board (PCB) supporting the plurality of compute nodes; a second PCB supporting the plurality of switches; and a third PCB supporting the plurality of bus connectors.

13. A computing system, comprising: a plurality of compute nodes; a plurality of bus connectors; a plurality of devices, each device of the plurality of devices being coupled to one bus connector of the plurality of bus connectors; anda plurality of switches, communicatively coupled to the plurality of compute nodes and the plurality of bus connectors, to assign each compute node of the plurality of compute nodes a variable number of bus connectors from the plurality of bus connectors for communication with that compute node during operation, the plurality of switches comprising: a first layer of switches, each switch in the first layer of switches being communicatively coupled to all of the plurality of compute nodes; and a second layer of switches communicatively coupled to the first layer of switches and all of the plurality of the plurality of bus connectors.

14. The computing system of claim 13, wherein the plurality of devices comprises at least one of a Peripheral Component Interconnect Express (PCIe) device, an Open Compute Project Accelerator Module (OAM) device, or a SXM module.

15. The computing system of claim 13, wherein the plurality of devices includes at least one of a graphics processing unit (GPU), an accelerator, an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or a storage device.

16. The computing system of claim 13, wherein each switch in the first layer of switches is communicatively coupled to all of the plurality of bus connectors.

17. A method for operating a computing system comprising: a plurality of compute nodes; a plurality of bus connectors; a plurality of devices, each device of the plurality of devices being coupled to one bus connector of the plurality of bus connectors; and a plurality of switches, communicatively coupled to the plurality of compute nodes and the plurality of bus connectors, the method comprising: receiving, by a first switch in the plurality of switches, a first instruction to assign a first subset of bus connectors of the plurality of bus connectors to a first compute node of the plurality of compute nodes; assigning, by the first switch, the first subset of bus connectors to the first compute node so that the first subset of bus connectors is communicatively coupled only to the first compute node;receiving, by the first switch, a second instruction to assign a second subset of bus connectors of the plurality of bus connectors to the first compute node; and assigning, by the first switch, the second subset of bus connectors to the first compute node so that the second subset of bus connectors is communicatively coupled only to the first compute node, wherein the first and second subsets of bus connectors are different.

18. The method of claim 17, wherein: a first total number of the first subset of bus connectors ranges from zero to a total number of the plurality of bus connectors; and a second total number of the second subset of bus connectors ranges from zero to the total number of the plurality of bus connectors.

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