Display substrate and preparation method therefor, and display screen

Abstract

The embodiments of the present application belong to the technical field of display. Provided are a display substrate and a preparation method therefor, and a display screen. In the display substrate, a first over coat can be filled into a first interval area and a second interval area, and the refractive index of the first over coat can be less than a first refractive index of a first isolation layer and can be less than a second refractive index of a second isolation layer. In this way, when emergent light rays enter the side faces of the first isolation layer and the second isolation layer through the first over coat, due to an increase in the refractive index, light rays with relatively large incident angles on the side faces of the first isolation layer and the second isolation layer can be totally reflected. That is, for the display substrate, emergent light with relatively large angles is totally reflected on the side surfaces of the first isolation layer and the second isolation layer, such that the angle between the reflected emergent light and the display substrate in a vertical direction is decreased, thereby implementing small-angle emergent light of a second-type pixel area; in addition, because there is more small-angle emergent light, the brightness of the small-angle emergent light can be increased.

Description

Display substrate and preparation method thereof, and display screen

[0001] This disclosure claims priority to Chinese patent application No. 202311286895.5, filed on October 7, 2023, entitled “Display Substrate, Display Substrate Preparation Method and Display Screen,” the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present application relates to the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display screen. Background Art

[0003] With the continuous development of display technology, the application of display screens is becoming more and more extensive. In some cases, when using electronic devices with display functions such as mobile phones or tablets, users want to share the information displayed on the screen with others. However, in other cases, users also want privacy. For example, when users are processing company confidential information or entering personal information on their mobile phones, they hope to reduce the risk of others viewing the information. Therefore, the switching between display sharing and privacy is gradually becoming a functional trend.

[0004] In related technologies, in order to achieve the switchability between anti-peeping and sharing of the display screen, the entire pixel area is divided into an anti-peeping pixel area and a normal pixel area. The normal pixel area has a larger light emission angle (the angle in the direction perpendicular to the display screen), and the emitted light can be observed from both the side and the front of the display screen. The anti-peeping pixel area has a very small light emission angle, and the emitted light can only be observed from the front of the display screen. In anti-peeping mode, only the pixels in the anti-peeping pixel area are lit, and the emitted light cannot be observed from the side of the display screen, thereby achieving the anti-peeping function. However, how to achieve the small-angle emitted light in the anti-peeping pixel area has become an urgent problem to be solved.

[0005] Summary of the Invention

[0006] The purpose of the embodiments of the present application is to provide a display substrate and a method for manufacturing the same, and a display screen. The technical solution is as follows:

[0007] In a first aspect, an embodiment of the present application provides a display substrate, wherein the display substrate is divided into a first type of pixel region and a second type of pixel region, wherein the first type of pixel region is a normal pixel region, and the second type of pixel region is an anti-peeping pixel region; and the display substrate includes:

[0008] A substrate, a pixel portion and a touch portion; the pixel portion is arranged on the substrate, and the touch portion is arranged on a side of the pixel portion away from the substrate;

[0009] The touch portion includes a first isolation layer, a second isolation layer and a first protective layer, wherein the second isolation layer is arranged on a side of the first isolation layer away from the substrate;

[0010] In the second type of pixel area, the first isolation layer has a plurality of first spacing regions, and the second isolation layer has a plurality of second spacing regions, and the first spacing regions and the second spacing regions correspond to projections of the pixel light emitting regions in the pixel portion on the substrate;

[0011] The first protective layer is provided on a side of the second isolation layer away from the substrate, and the first spacing region and the second spacing region are filled with the first protective layer;

[0012] The third refractive index of the first protective layer is smaller than the first refractive index of the first isolation layer, and the third refractive index of the first protective layer is smaller than the second refractive index of the second isolation layer.

[0013] In one possible embodiment, the first isolation layer is patterned into a plurality of first trapezoidal structures, and the first spacing region is formed between two adjacent first trapezoidal structures; the angle between the bottom of the first trapezoidal structure close to the substrate and the bottom of the substrate is in a range of 45 degrees to 75 degrees;

[0014] The second isolation layer is patterned into a plurality of second trapezoidal structures, and a second spacing region is formed between two adjacent second trapezoidal structures; a lower bottom angle formed by the second trapezoidal structure close to the substrate and the substrate is in a range of 45 degrees to 75 degrees;

[0015] The length of the first trapezoidal structure away from the upper base of the substrate is not less than the length of the second trapezoidal structure close to the lower base of the substrate.

[0016] In a possible implementation, the ratio of the second refractive index to the third refractive index is greater than 1.10; and / or the ratio of the first refractive index to the third refractive index is greater than 1.10.

[0017] In a possible implementation, the touch portion further includes a buffer layer, a first metal layer, a second metal layer, an optical control layer, a black matrix layer, and a second protective layer;

[0018] The buffer layer is arranged on a side of the pixel portion away from the substrate; the first isolation layer is arranged on a side of the buffer layer away from the substrate; the first metal layer is arranged between the first isolation layer and the second isolation layer; the second metal layer is arranged between the second isolation layer and the first protective layer; the optical control layer is arranged on a side of the first protective layer away from the substrate; and the black matrix layer is arranged on a side of the optical control layer away from the substrate.

[0019] The black matrix layer has a plurality of third spacing areas, and the third spacing areas correspond to the projections of the pixel light-emitting areas in the pixel portion on the substrate; the second protective layer is arranged on a side of the black matrix layer away from the substrate, and the third spacing areas are filled with the second protective layer.

[0020] In one possible embodiment, in the second type of pixel area, the touch part also includes a third metal layer, and the third metal layer is arranged between the first isolation layer and the buffer layer. The routing width of the third metal layer is greater than the routing width of the first metal layer, and the routing width of the third metal layer is greater than the routing width of the second metal layer.

[0021] In a possible implementation manner, the third metal layer is connected to a ground of the display substrate.

[0022] In a possible implementation, the normal pixels in the first type of pixel area and the anti-privacy pixels in the second type of pixel area are arranged alternately, and each sub-pixel in the anti-privacy pixels includes a plurality of anti-privacy pixel units.

[0023] In a possible embodiment, each sub-pixel in the display substrate includes multiple anti-peeping pixel units and at least one normal pixel unit, the area where the anti-peeping pixel units are located is the second type of pixel area, and the area where the normal pixel units are located is the first type of pixel area.

[0024] In a possible implementation, the size of the privacy protection pixel unit does not exceed 15 um.

[0025] In a possible embodiment, the touch portion further includes a first metal layer and a second metal layer, and the first metal layer and the second metal layer include a plurality of touch traces; in the projection direction of the substrate, the touch traces are located in the gaps between adjacent sub-pixels, and in the gaps between adjacent anti-peep pixel units and normal pixel units.

[0026] In one possible implementation, the pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures;

[0027] For any sub-pixel in the anti-peeping pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel shares an anode structure.

[0028] In one possible implementation, the pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures;

[0029] For any sub-pixel in the anti-peeping pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel is connected to a different anode structure.

[0030] In a possible implementation, the touch portion further includes a first metal layer and a second metal layer, the first metal layer and the second metal layer include a plurality of touch traces; in the projection direction of the substrate, the touch traces are located in the gaps between adjacent sub-pixels.

[0031] In one possible implementation, the pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures;

[0032] For any sub-pixel, the sub-pixel is divided into multiple anti-peeping pixel units and one normal pixel unit through the pixel isolation structure, and the normal pixel unit of the sub-pixel is connected to one anode structure, and each anti-peeping pixel unit of the sub-pixel shares another anode structure.

[0033] In one possible implementation, the pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures;

[0034] For any sub-pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units and a normal pixel unit through the pixel isolation structure, and the normal pixel unit and each anti-peeping pixel unit of the sub-pixel are respectively connected to different anode structures.

[0035] In a possible implementation, the first isolation layer is a third protective layer, and the second isolation layer is a fourth protective layer.

[0036] In a possible implementation manner, the first isolation layer is a first interlayer dielectric layer, and the second isolation layer is a second interlayer dielectric layer.

[0037] In a second aspect, an embodiment of the present application provides a method for preparing a display substrate, the method comprising:

[0038] A buffer layer is formed on a side of a prefabricated plate away from the substrate, wherein the prefabricated plate includes a substrate and a pixel portion, and the pixel portion is provided on the substrate;

[0039] preparing a first isolation layer on the buffer layer;

[0040] Performing a patterning operation on the first isolation layer in the second type pixel region to form a plurality of first spacing regions in the first isolation layer in the second type pixel region; wherein the first spacing regions correspond to projections of pixel light emitting regions in the pixel portion on the substrate;

[0041] forming a patterned first metal layer on the first isolation layer, and forming a second isolation layer on the first isolation layer and the first metal layer;

[0042] performing a patterning operation on the second isolation layer in the second type pixel region to form a plurality of second spacing regions in the second isolation layer in the second type pixel region; wherein the second spacing regions correspond to projections of the pixel light emitting regions in the pixel portion on the substrate;

[0043] A patterned second metal layer is formed on the second isolation layer, and a first protective layer is formed on the second isolation layer and the second metal layer; wherein the first spacing region and the second spacing region are filled with the first protective layer; the third refractive index of the first protective layer is less than the first refractive index of the first isolation layer, and the third refractive index of the first protective layer is less than the second refractive index of the second isolation layer;

[0044] Perform subsequent preparation processes for the display substrate.

[0045] In a possible implementation, before preparing the first isolation layer on the buffer layer, the method further includes:

[0046] Depositing a third metal layer on the buffer layer, and performing trace etching on the third metal layer to obtain a patterned first metal layer;

[0047] The wiring width of the third metal layer is greater than the wiring width of the first metal layer, and the wiring width of the third metal layer is greater than the wiring width of the second metal layer.

[0048] In a third aspect, an embodiment of the present application provides a display screen, comprising: a power supply component, and a display substrate as described in the first aspect;

[0049] The power supply component is connected to the display substrate and is used to supply power to the display substrate. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0051] FIG1 is a schematic diagram showing a partial structure of a display substrate in the related art;

[0052] FIG2 is a schematic diagram of a privacy screen display with a cutout design according to an embodiment of the present application;

[0053] FIG3 is a schematic diagram of a partitioned anti-peeping display screen according to an embodiment of the present application;

[0054] FIG4 is a first cross-sectional schematic diagram of a display substrate according to an embodiment of the present application;

[0055] FIG5 is a second cross-sectional schematic diagram of a display substrate according to an embodiment of the present application;

[0056] FIG6 is a third cross-sectional schematic diagram showing a substrate in an embodiment of the present application;

[0057] FIG7 a is a fourth cross-sectional schematic diagram showing a substrate in an embodiment of the present application;

[0058] FIG7 b is a fifth cross-sectional schematic diagram of a display substrate in an embodiment of the present application;

[0059] FIG8 is a first schematic diagram of a partitioned anti-peeping display screen according to an embodiment of the present application;

[0060] FIG9 is a second schematic diagram of a partitioned anti-peeping display screen according to an embodiment of the present application;

[0061] FIG10 is a sixth cross-sectional schematic diagram of a display substrate in an embodiment of the present application;

[0062] FIG11 is a seventh cross-sectional schematic diagram of a display substrate in an embodiment of the present application;

[0063] FIG12 is a first schematic diagram of a privacy screen display with a cutout design according to an embodiment of the present application;

[0064] FIG13 is a second schematic diagram of a privacy screen display with a cutout design according to an embodiment of the present application;

[0065] FIG14 is a first schematic diagram of a pixel circuit according to an embodiment of the present application;

[0066] FIG15 is a second schematic diagram of a pixel circuit according to an embodiment of the present application;

[0067] FIG16 a is a timing diagram of the pixel circuit shown in FIG14 in the anti-peeping mode according to an embodiment of the present application;

[0068] FIG16 b is a timing diagram of the pixel circuit shown in FIG14 in a sharing mode according to an embodiment of the present application;

[0069] FIG17 a is a timing diagram of the pixel circuit shown in FIG15 in the anti-peeping mode according to an embodiment of the present application;

[0070] FIG17 b is a first timing diagram of the pixel circuit shown in FIG15 in a sharing mode according to an embodiment of the present application;

[0071] FIG17c is a second timing diagram of the pixel circuit shown in FIG15 in the sharing mode according to an embodiment of the present application;

[0072] FIG18 is a first cross-sectional schematic diagram of a display substrate in a method for manufacturing a display substrate according to an embodiment of the present application;

[0073] FIG19 is a second cross-sectional schematic diagram of a display substrate in the method for preparing a display substrate according to an embodiment of the present application;

[0074] FIG20 is a third cross-sectional schematic diagram of a display substrate in the method for manufacturing a display substrate according to an embodiment of the present application;

[0075] FIG21 is a fourth cross-sectional schematic diagram of a display substrate in the method for preparing a display substrate according to an embodiment of the present application;

[0076] FIG22 is a fifth cross-sectional schematic diagram of a display substrate in the method for preparing a display substrate according to an embodiment of the present application;

[0077] FIG23 is a sixth cross-sectional schematic diagram of a display substrate in the method for preparing a display substrate according to an embodiment of the present application;

[0078] FIG24 is a seventh cross-sectional schematic diagram of a display substrate in the method for manufacturing a display substrate according to an embodiment of the present application;

[0079] FIG25 is a schematic cross-sectional view of an eighth embodiment of the display substrate in the method for manufacturing the display substrate according to an embodiment of the present application;

[0080] FIG. 26 is a ninth cross-sectional schematic diagram of a display substrate in the method for preparing a display substrate according to an embodiment of the present application. DETAILED DESCRIPTION

[0081] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field based on this application are within the scope of protection of this application.

[0082] In the related art, in order to achieve small-angle light emission from the anti-peeping pixel area, a multi-layer BM (Black Matrix) layer is generally used in the display substrate as an anti-peeping design. By using the BM layers at different heights, the purpose of blocking light at different angles is achieved.

[0083] For example, referring to Figure 1, on the light-emitting side of the display substrate, three BM layers and three Organic layers are set to block the large-angle output light. However, this requires adding multiple BM and Organic layer processes, and will make the thickness of the display substrate thicker, which may easily cause the problem of peeling between different film layers. Among them, Figure 1 also shows the PDL layer (Pixel Definition Layer) included in the display substrate. In addition, Figure 1 identifies the three BM layers as BM1, BM2 and BM3 respectively; and identifies the three Organic layers as Organic layer1, Organic layer2 and Organic layer3 respectively. It can be understood that the structure of the touch part is not shown in Figure 1, and the touch part can be set between the PDL and Organic layer1.

[0084] In order to achieve the switchable display screen privacy and sharing, the present application provides two different display substrate designs:

[0085] One is a cutting design, which is to cut the sub-pixel into an anti-peeping pixel area and a normal pixel area, as shown in FIG2 .

[0086] The other is a partition design, which directly divides pixels into anti-privacy pixels (the area where the anti-privacy pixels are located is called the anti-privacy pixel area) and normal pixels (the area where the normal pixels are located is called the normal pixel area), as shown in FIG3 .

[0087] Taking the OLED (Organic Light-Emitting Diode) display as an example, the two designs shown in Figures 2 and 3 both divide the original OLED into OLED1 (anti-peeping) and OLED2 (normal). OLED2's light emission angle is larger (the angle in the direction perpendicular to the display), and the emitted light can be observed from both the side and front of the display, while OLED1's light emission angle is very small, and the emitted light can only be observed from the front of the display. Therefore, in shared mode, both OLED1 and OLED2 are lit, or only OLED2 is lit, and the emitted light can be observed from the side of the display. In anti-peeping mode, only OLED1 is lit, and the emitted light cannot be observed from the side of the display, thus achieving an anti-peeping function.

[0088] First, an embodiment of the present application provides a display substrate. The display substrate is divided into a first type of pixel region and a second type of pixel region. Referring to FIG. 4 , the display substrate includes:

[0089] A substrate 01 , a pixel portion 02 and a touch portion 03 ; the pixel portion 02 is disposed on the substrate 01 , and the touch portion 03 is disposed on a side of the pixel portion 02 away from the substrate 01 .

[0090] The touch portion 03 includes a first isolation layer 301 , a second isolation layer 302 and a first overcoat (OC) layer 303 . Accordingly, the first overcoat 303 may also be referred to as OC1 . The second isolation layer 302 is disposed on a side of the first isolation layer 301 away from the substrate 01 .

[0091] In the above-mentioned second type of pixel area, the above-mentioned first isolation layer 301 has multiple first spacing areas 3011, and the above-mentioned second isolation layer 302 has multiple second spacing areas 3021. The above-mentioned first spacing areas 3011 and the above-mentioned second spacing areas 3021 correspond to the projections of the pixel light-emitting areas in the above-mentioned pixel part 02 on the above-mentioned substrate 01.

[0092] The first protection layer 303 is disposed on a side of the second isolation layer 302 away from the substrate 01 , and the first spacing region 3011 and the second spacing region 3021 are filled with the first protection layer 303 .

[0093] The third refractive index of the first protective layer 303 is smaller than the first refractive index of the first isolation layer 301 , and the third refractive index of the first protective layer 303 is smaller than the second refractive index of the second isolation layer 302 .

[0094] Optionally, the protective layer can be a photosensitive resin film, generally made of an organic material, such as a polyimide resin or an acrylic resin. The substrate 01 can be made of glass or a flexible material. The flexible material can be, for example, polyimide (PI). Accordingly, the substrate 01 can also be referred to as PI.

[0095] The first type of pixel area can be the normal pixel area described above, and the second type of pixel area can be the anti-peeping pixel area described above. The first spacing area 3011, the second spacing area 3021, and the projection of the pixel light-emitting area in the pixel portion 02 on the substrate 01 correspond to each other, which can mean that the projections of the first spacing area 3011, the second spacing area 3021, and the pixel light-emitting area in the pixel portion 02 on the substrate 01 have overlapping parts, or in other words, the centers of the projection areas of the three on the substrate 01 overlap (the distance between the centers is less than a preset distance value). In an example, the projection of the pixel light-emitting area in the pixel portion 02 on the substrate 01 is called the third projection, the projection of the first spacing area 3011 on the substrate 01 is called the first projection, and the projection of the second spacing area 3021 on the substrate 01 is called the second projection. Then, the first projection is included in the second projection, and the second projection is included in the third projection.

[0096] It can be understood that the dotted lines in FIG. 4 are only for the purpose of illustrating the first spacing area 3011 and the second spacing area 3021 , and are not actual structures.

[0097] In the embodiment of the present application, the first protective layer 303 is filled into the first spacing region 3011 and the second spacing region 3021. The third refractive index of the first protective layer 303 is less than the first refractive index of the first isolation layer 301, and the third refractive index of the first protective layer 303 is less than the second refractive index of the second isolation layer 302. As a result, when the outgoing light passes through the first protective layer 303 and is incident on the side surfaces of the first isolation layer 301 and the second isolation layer 302, due to the increased refractive index, the light with a larger incident angle on the side surfaces of the first isolation layer 301 and the second isolation layer 302 will experience total internal reflection. That is, for the display substrate, the outgoing light with a larger angle is totally reflected on the side surfaces of the first isolation layer 301 and the second isolation layer 302, so that the angle of the reflected outgoing light with respect to the perpendicular direction of the display substrate becomes smaller, thereby achieving small-angle outgoing light in the second type of pixel area. Moreover, because more small-angle outgoing light is emitted, the brightness of the small-angle outgoing light can also be increased.

[0098] Optionally, the first isolation layer 301 and the second isolation layer 302 may both be patterned structures, and the first spacer region 3011 and the second spacer region 3021 may be formed by etching or other processes. In one possible embodiment:

[0099] The first isolation layer 301 is patterned into a plurality of first trapezoidal structures, and the first spacing region 3011 is formed between two adjacent first trapezoidal structures. The bottom angle formed between the bottom of the first trapezoidal structure close to the substrate 01 and the substrate 01 ranges from 45 degrees to 75 degrees.

[0100] The second isolation layer 302 is patterned into a plurality of second trapezoidal structures, and the second spacing region 3021 is formed between two adjacent second trapezoidal structures. The bottom angle formed by the bottom of the second trapezoidal structure close to the substrate 01 and the substrate 01 ranges from 45 degrees to 75 degrees.

[0101] Optionally, the length of the upper base of the first trapezoidal structure away from the substrate 01 is not less than the length of the lower base of the second trapezoidal structure close to the substrate 01. Alternatively, the orthographic projection area of ​​the first trapezoidal structure on the substrate 01 is smaller than the orthographic projection area of ​​the second trapezoidal structure on the substrate 01.

[0102] It is understood that the portion of the first isolation layer 301 that is etched away can be referred to as the first spacing region 3011, and the portion remaining after etching can be referred to as the first trapezoidal structure. The portion of the second isolation layer 302 that is etched away can be referred to as the second spacing region 3021, and the portion remaining after etching can be referred to as the second trapezoidal structure. The length of the lower base of the first trapezoidal structure is greater than the length of the upper base of the first trapezoidal structure, the length of the lower base of the second trapezoidal structure is greater than the length of the upper base of the first trapezoidal structure, and the length of the upper base of the first trapezoidal structure is not less than the length of the lower base of the second trapezoidal structure, thereby facilitating the arrangement of the second trapezoidal structure on the first trapezoidal structure. The lower base angles of the first trapezoidal structure and the second trapezoidal structure can both range from 45 degrees to 75 degrees.

[0103] In the embodiment of the present application, by setting the bottom angle of the first and second trapezoidal structures to be within the range of 45 degrees to 75 degrees, the angle of the emitted light from the second type of pixel area (the angle in the direction perpendicular to the display substrate) can be reduced, while the amount of emitted light can be increased, thereby increasing the screen brightness. In other embodiments, the first and second trapezoidal structures can also be other shapes, such as rectangles and pentagons, all of which are within the scope of protection of the embodiments of the present application.

[0104] Optionally, in order to achieve as much total reflection of light as possible, there are certain requirements for the setting of the refractive index. In one possible embodiment, the ratio of the second refractive index to the third refractive index may be greater than 1.10; and / or, the ratio of the first refractive index to the third refractive index may be greater than 1.10.

[0105] In a possible embodiment, referring to FIG. 5 , the touch portion 03 may further include a buffer layer, namely, a buffer layer A (Buffer A), a first metal layer (M1), a second metal layer (M2), an optical control layer (Ink), a black matrix (BM) layer, and a second protective layer (OC2).

[0106] The above-mentioned buffer layer A can be arranged on the side of the above-mentioned pixel part 02 away from the above-mentioned substrate 01 (such as PI); the above-mentioned first isolation layer 301 can be arranged on the side of the above-mentioned buffer layer A away from the above-mentioned substrate 01; the above-mentioned first metal layer (M1) can be arranged between the above-mentioned first isolation layer 301 and the above-mentioned second isolation layer 302; the above-mentioned second metal layer (M2) can be arranged between the above-mentioned second isolation layer 302 and the above-mentioned first protective layer 303 (OC1); the above-mentioned optical control layer is arranged on the side of the above-mentioned first protective layer 303 (OC1) away from the above-mentioned substrate 01; the above-mentioned black matrix layer (BM) can be arranged on the side of the above-mentioned optical control layer (Ink) away from the above-mentioned substrate 01.

[0107] The black matrix layer (BM) may have multiple third spacing regions BM01, corresponding to the projection of the pixel light-emitting areas of the pixel portion 02 onto the substrate 01. The second protective layer (OC2) is disposed on a side of the black matrix layer (BM) away from the substrate 01, and the third spacing regions BM01 are filled with the second protective layer (OC2). The lengths of the first spacing regions 3011, the second spacing regions 3021, and the third spacing regions BM01 can be customized based on actual needs.

[0108] In one example, to ensure that the second isolation layer 302 can be stably disposed on the first isolation layer 301, the length of the second trapezoidal structure needs to be smaller than that of the first trapezoidal structure, that is, the length of the first spacing region 3011 can be smaller than that of the second spacing region 3021. To achieve low-angle light emission from the second type of pixel area, in one example, the length of the third spacing region BM01 can be equal to that of the second spacing region 3021. Accordingly, the length of the third spacing region BM01 can be greater than that of the first spacing region 3011.

[0109] In addition, FIG5 schematically shows that the display substrate may further include: a buffer layer BufferB, a gate insulator (GI), an interlayer dielectric layer ILD, a planarization layer (PLN), a pixel definition layer PDL, and an encapsulation layer (EN), which are located between the substrate 01 and the buffer A and stacked in sequence in a direction away from the substrate 01. Furthermore, a low-temperature polysilicon layer P-Si serving as an active layer located between the buffer layer BufferB and the gate insulator layer GI, a gate layer Gate located between the gate insulator layer GI and the interlayer dielectric layer ILD, a source / drain layer SD located between the interlayer dielectric layer ILD and the planarization layer PLN, and an organic light-emitting layer located between the planarization layer PLN and the encapsulation layer EN. The organic light-emitting layer shown in the figure is an anode structure. The organic light-emitting layer is connected to the source / drain layer SD, which is in turn connected to the low-temperature polysilicon layer P-Si. That is, in FIG6 , PLN represents a planar layer, GI represents an insulating layer, SD represents a source / drain layer, Gate represents a gate layer, PDL represents a pixel definition layer, P-Si represents a low-temperature polysilicon layer, and EN represents an encapsulation layer.

[0110] Alternatively, in one example, the structure of the first type pixel region can be as shown in FIG6 , where the first isolation layer 301 and the second isolation layer 302 of the first type pixel region do not need to be patterned. Compared to the second type pixel region shown in FIG1 (the touch portion is not shown in FIG1 ), the second type pixel region in the embodiment of the present application can reduce the number of BM layers, thereby reducing the thickness of the display substrate and reducing the risk of film peeling.

[0111] Optionally, in the embodiment of the present application, the first isolation layer 301 and the second isolation layer 302 may also be a protective layer OC, or may also be an interlayer dielectric layer (ILD).

[0112] In a possible implementation, for example as shown in FIG. 7 a , the first isolation layer 301 may be a third protection layer ( OC3 ), and the second isolation layer 302 may be a fourth protection layer ( OC4 ).

[0113] In one possible implementation, as shown in FIG7b , the first isolation layer 301 may be a first interlayer dielectric layer (ILD1), and the second isolation layer 302 may be a second interlayer dielectric layer (ILD2). Optionally, the interlayer dielectric layer is generally made of an inorganic material, such as silicon nitride (SiN).

[0114] It can be understood that both FIG. 5 and FIG. 6 are described by taking the first isolation layer 301 as the third protection layer OC3 and the second isolation layer 302 as the fourth protection layer OC4 as an example.

[0115] In one possible embodiment, referring to FIG. 7a or FIG. 7b , the touch portion 03 in the second type pixel area may further include a third metal layer (M3), and the third metal layer (M3) is disposed between the first isolation layer 301 (OC3) and the buffer layer Buffer A. The routing width of the third metal layer (M3) may be greater than the routing width of the first metal layer (M1), and the routing width of the third metal layer (M3) may be greater than the routing width of the second metal layer (M2).

[0116] Optionally, the first metal layer (M1), the second metal layer (M2) and the third metal layer (M3) may all be patterned into a plurality of traces.

[0117] The first metal layer (M1) and the second metal layer (M2) can serve as the horizontal and vertical touch wiring layers, respectively, for implementing touch functionality. By setting the wiring width of the third metal layer (M3) to be greater than the wiring width of the first metal layer (M1), and also setting the wiring width of the third metal layer (M3) to be greater than the wiring width of the second metal layer (M2), it is possible to block the wide-angle light emitted by the pixel light-emitting area in the pixel portion 02, thereby reducing the angle of the light emitted from the second-type pixel area.

[0118] In one possible embodiment, the third metal layer (M3) is connected to the ground of the display substrate. By connecting the wiring of the third metal layer (M3) to the ground of the display substrate, electrical signal isolation between the touch control portion 03 and the pixel portion 02 of the display substrate can be achieved, reducing the mutual influence of electrical signals between the touch control portion 03 and the pixel portion 02, thereby improving touch and display accuracy.

[0119] In one possible embodiment, the third metal layer (M3) can also be included in the first-type pixel area to ensure that normal pixels and anti-peeping pixels are relatively flat. Similarly, the third metal layer (M3) can be connected to the ground of the display substrate. This can also achieve electrical signal isolation between the touch portion 03 and the pixel portion 02 in the display substrate, reducing the mutual influence of electrical signals between the touch portion 03 and the pixel portion 02, thereby improving touch and display accuracy.

[0120] In a possible embodiment, the third metal layer (M3) may also be included in the first type of pixel area. In the first type of pixel area, the wiring width of the third metal layer (M3) may be less than or equal to the wiring width of the first metal layer (M1), and the wiring width of the third metal layer (M3) may be less than or equal to the wiring width of the second metal layer (M2). In this way, the light blocking of the third metal layer (M3) can be reduced.

[0121] Optionally, as an optional implementation, the display substrate in the embodiment of the present application may adopt a partition design:

[0122] In a possible implementation, referring to FIG. 8 , the normal pixels in the first type of pixel region and the privacy protection pixels in the second type of pixel region may be arranged alternately, and each sub-pixel in the privacy protection pixels may include a plurality of privacy protection pixel units.

[0123] Among them, A, A ， , and B, B ， Indicates the cross-sectional direction of the display substrate, that is, the layer diagram of the display substrate in the embodiment of the present application is along A, A ， or B, B ， The cross-section is shown in the direction of .

[0124] Unlike the zoning design methods used in the prior art, the zoning design in the embodiments of the present application further divides the sub-pixels in the privacy-protection pixels in the second type of pixel area. Each sub-pixel in the privacy-protection pixel includes multiple privacy-protection pixel units, thereby further reducing the size of the privacy-protection pixel. In one example, the size of the privacy-protection pixel unit does not exceed 15μm. It is understood that the size of the privacy-protection pixel unit refers to the length of the longest line segment in the privacy-protection pixel unit. For example, the diagonal of a rectangle or the diameter of a circle, etc.

[0125] In the implementation of the present application, each sub-pixel in the anti-peeping pixel may include multiple anti-peeping pixel units, thereby further reducing the size of the anti-peeping pixel and further reducing the angle of the emitted light from the second type of pixel area.

[0126] It is understandable that the layout of the traces (also called touch traces, including touch electrodes) in the first metal layer (M1) and the second metal layer (M2) directly determines the touch sensitivity. The denser the trace layout, the higher the touch sensitivity.

[0127] In one possible embodiment, referring to FIG9 , the touch portion 03 may further include a first metal layer (M1) and a second metal layer (M2), each of which may include multiple touch traces. Furthermore, in the projection direction of the substrate 01 , the touch traces may be located in the gaps between adjacent sub-pixels, and may be located in the gaps between adjacent anti-peep pixel units and normal pixel units. Tx represents transmission, RX represents reception, and TP Bonding Area represents the touch electrode area.

[0128] It can be understood that the number of pixel units after adjacent sub-pixels are cut can be the same or different, both falling within the protection scope of the embodiments of the present application.

[0129] (1) The segmentation of each sub-pixel in the anti-peeping pixel in the partition design can be achieved by segmenting the pixel definition layer (PDL):

[0130] In one possible embodiment, the pixel portion 02 may include an anode layer (Anode, AND) and a pixel definition layer (PDL), the anode layer (AND) includes a plurality of anode structures, see FIG10 , and the pixel definition layer (PDL) includes a plurality of pixel isolation structures. On this basis, for any sub-pixel in the anti-peeping pixel, the sub-pixel can be divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel can share an anode structure. Among them, the pixel isolation structure is the structure in the dotted box in FIG10 . It can be understood that the dotted box is only for the convenience of illustrating the anode structure, and does not actually exist in the display substrate.

[0131] (2) The segmentation of each sub-pixel in the anti-peeping pixel in the partition design can be achieved by segmenting the pixel definition layer (PDL) and the anode layer (AND):

[0132] In one possible embodiment, the pixel portion 02 may include an anode layer (AND) and a pixel definition layer (PDL). Referring to FIG11 , the anode layer (AND) may include a plurality of anode structures, and the pixel definition layer (PDL) may include a plurality of pixel isolation structures. On this basis, for any sub-pixel in the anti-peeping pixel, the sub-pixel may be divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel may be connected to a different anode structure. The anode structure is the structure within the dotted box in FIG11 . It can be understood that the dotted box is only for the convenience of illustrating the anode structure, and does not actually exist in the display substrate.

[0133] Alternatively, as another optional implementation, the display substrate in the embodiment of the present application may adopt a cutting design:

[0134] In a possible embodiment, referring to FIG12 , each sub-pixel in the display substrate may include a plurality of anti-peeping pixel units and at least one normal pixel unit, the area where the anti-peeping pixel units are located is the second type of pixel area, and the area where the normal pixel units are located is the first type of pixel area.

[0135] It is understandable that, unlike the related art in which a sub-pixel is divided into an anti-peeping pixel unit and a normal pixel unit, in the embodiment of the present application, a sub-pixel is divided into multiple anti-peeping pixel units. For example, as shown in Figure 12, a sub-pixel is divided into two anti-peeping pixel units and one normal pixel unit. The size of the anti-peeping pixel unit can be further reduced. In one possible embodiment, the size of the above-mentioned anti-peeping pixel unit may not exceed 15um. It is understandable that the size of the anti-peeping pixel unit refers to the length of the longest line segment in the anti-peeping pixel unit. For example, the diagonal of a rectangle or the diameter of a circle, etc.

[0136] In the implementation of the present application, the sub-pixel may include multiple anti-peeping pixel units, thereby further reducing the size of the anti-peeping pixel and further reducing the angle of the emitted light from the second type of pixel area.

[0137] It is understood that the layout of the traces (also called touch traces) in the first metal layer (M1) and the second metal layer (M2) directly determines touch sensitivity. The denser the trace layout, the higher the touch sensitivity. In one example, horizontal touch traces and vertical touch traces can be arranged in the first metal layer (M1) and the second metal layer (M2), respectively, to facilitate the layout of the touch traces. It is understood that the touch traces can include touch electrode structures.

[0138] In one possible implementation, referring to FIG13 , the touch portion 03 may further include a first metal layer (M1) and a second metal layer (M2), and both the first metal layer (M1) and the second metal layer (M2) may include a plurality of touch traces; and, in the projection direction of the substrate 01, the touch traces may be located in the gaps between adjacent sub-pixels.

[0139] (1) The segmentation of each sub-pixel in the privacy protection pixel in the cutting design can be achieved by segmenting the pixel definition layer (PDL):

[0140] Still referring to FIG. 10 , in one possible embodiment, the pixel portion 02 may include an anode layer (AND) and a pixel definition layer (PDL). The anode layer (AND) may include multiple anode structures, and the pixel definition layer (PDL) may include multiple pixel isolation structures. On this basis, for any sub-pixel, the sub-pixel may be divided into multiple privacy-preventing pixel units and one normal pixel unit via the pixel isolation structure. Furthermore, the normal pixel unit of the sub-pixel may be connected to one anode structure, while the privacy-preventing pixel units of the sub-pixel may share another anode structure.

[0141] (2) The segmentation of each sub-pixel in the privacy protection pixel in the cutting design can be achieved by segmenting the pixel definition layer and the anode layer:

[0142] Still referring to Figure 11, the pixel portion 02 may include an anode layer (AND) and a pixel definition layer (PDL). The anode layer (AND) may include multiple anode structures, and the pixel definition layer (PDL) may include multiple pixel isolation structures. Based on this, for any sub-pixel, the sub-pixel may be divided into multiple privacy-preventing pixel units and one normal pixel unit using the pixel isolation structure, and the normal pixel units and each privacy-preventing pixel unit of the sub-pixel may be connected to different anode structures.

[0143] Optionally, the first and second pixel areas can be driven one-to-one, i.e., the first pixel area corresponds to a separate set of pixel circuits, and the second pixel area corresponds to another separate set of pixel circuits. Furthermore, a one-to-two drive can be implemented by adding a scanning signal, i.e., the first and second pixel areas can share a set of pixel circuits, thereby achieving anti-peeping / sharing switching.

[0144] Alternatively, the pixel circuit may be as shown in FIG14 or FIG15 . OLED1 represents a pixel / pixel unit in the second type pixel region, and OLED2 represents a pixel / pixel unit in the first type pixel region. VDD represents the positive power supply voltage, VSS represents the negative power supply voltage, EM1, EM2, EM3, Re, and GT (Gate) represent different timing signals, Data represents a data signal, Vinit1 represents a first initial voltage signal, Vinit2 represents a second initial voltage signal, and T1-T9 represent transistors.

[0145] The timing diagrams for the pixel circuit shown in Figure 14 in anti-peeping and sharing modes are shown in Figures 16a and 16b, respectively. The timing diagram for the pixel circuit shown in Figure 15 in anti-peeping mode is shown in Figure 17a, and the timing diagrams in sharing mode can be shown in Figures 17b or 17c, respectively. Unlike the pixel circuit shown in Figure 14, the pixel circuit shown in Figure 15 can achieve separate control of OLED1 and OLED2. That is, under the timing shown in Figure 17b, OLED1 can be turned off while OLED2 is charged. The pixel circuit shown in Figure 14 cannot achieve this function.

[0146] In summary, an embodiment of the present application provides a display substrate. In the display substrate, a first protective layer is filled into the first spacing area and the second spacing area, and the third refractive index of the first protective layer is less than the first refractive index of the first isolation layer, and less than the second refractive index of the second isolation layer. In this way, when the outgoing light passes through the first protective layer and is incident on the side of the first isolation layer and the second isolation layer, due to the increase in refractive index, the light with a larger incident angle on the side of the first isolation layer and the second isolation layer will experience total reflection. That is, for the display substrate, the outgoing light with a larger angle is totally reflected on the side of the first isolation layer and the second isolation layer, so that the angle of the reflected outgoing light with respect to the vertical direction of the display substrate becomes smaller, thereby realizing the small-angle outgoing light of the second type of pixel area, and because there is more small-angle outgoing light, the brightness of the small-angle outgoing light can also be increased. Of course, implementing any product or method of the present application does not necessarily require achieving all the advantages described above at the same time.

[0147] The present application also provides a method for preparing a display substrate, which is used to prepare the display substrate provided in the embodiment of the present application as described above. The method comprises:

[0148] Step 1: fabricate a buffer layer A on a side of the prefabricated plate away from the substrate 01 .

[0149] The prefabricated board includes a substrate 01 and a pixel portion 02 , and the pixel portion 02 is disposed on the substrate 01 .

[0150] The prefabricated board includes a substrate 01 and a pixel portion 02. In one example, it can be manufactured in the following order according to the manufacturing process in the related art: PI→BufferB→P-Si→GI→Gate→ILD→SD→PLN→AND→PDL

[0151] As can be seen from FIG18 , a substrate (PI) can be fabricated first. The substrate can be made of glass or a flexible material. The flexible material can include the polyimide (PI) described above, or can include polyethylene naphthalate (PEN) or polyethylene terephthalate (PET). A substrate made of a flexible material can also be referred to as a flexible substrate. Furthermore, the flexible substrate can be a single-layer structure or a multi-layer structure. If it is a multi-layer structure, a buffer layer can be added between the layers. The buffer layer is an inorganic thin film, which can be a structure made of silicon nitride (SiNx), silicon oxide (SiOx) or a composite layer thereof on a substrate. Then, a buffer layer, namely a buffer layer B (BufferB), a patterned active layer (P-Si), an insulating layer (GI), a gate layer (Gate), a source / drain electrode layer (SD) and a planar layer (PLN) can be formed on the substrate (PI). Next, an anode (AND) pattern, a pixel definition layer (PDL), a support column structure and a retaining wall structure can be fabricated on the planar layer (PLN). Among them, the materials of the pixel definition layer (PDL), the support column structure and the retaining wall structure can be the same as the material of the flat layer (PLN). For example, they can all be organic insulating materials and can be made of polyimide photoresist. The support column structure can be mainly arranged in the display area AA, while the retaining wall structure can be located in the non-display area. The retaining wall structure can be formed by one or more layers of the flat layer (PLN), the pixel definition layer (PDL) and the support column structure. Next, the encapsulation layer EN and the buffer layer A (Buffer A) can be formed in sequence on the side of the pixel definition layer (PDL) away from the substrate 01.

[0152] Optionally, a vacuum evaporation process is used to form an organic light-emitting layer and a cathode layer on the backplane. The organic light-emitting layer may include, but is not limited to, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and other thin film encapsulation layers. The thin film encapsulation layer may include an inorganic thin film layer that blocks water and oxygen and an organic thin film layer that performs stress release and planarization. The inorganic thin film layer may be prepared by chemical vapor deposition or atomic layer deposition, and the material may be, but is not limited to, silicon nitride, silicon oxide, silicon oxynitride, aluminum oxide, or titanium oxide. The organic thin film layer may be prepared by inkjet printing, screen printing, or dispensing.

[0153] Optionally, first, a first inorganic layer can be deposited on the light-emitting device (i.e., the organic light-emitting layer). The first inorganic layer can be one of the aforementioned materials or a combination of multiple overlapping materials. The protection area of ​​the first inorganic layer can be larger than the display area of ​​the display area AA region. Generally speaking, the vertical projection of the coverage area of ​​the first inorganic layer can be outside the retaining wall structure. Then, a first organic layer can be prepared on the first inorganic layer. The coverage area of ​​the first organic layer can be smaller than the first inorganic layer, and the vertical projection of the coverage area of ​​the first organic layer can be larger than the cathode layer. Then, a second inorganic layer can be made on the first organic layer. The production method and materials of the second inorganic layer can be the same as those of the first inorganic layer, and the coverage area of ​​the second inorganic layer can be the same as that of the first inorganic layer or can also be larger than the first inorganic layer. Similarly, it can be composed of a single inorganic material or a combination of the aforementioned multiple inorganic layers (the figure does not show the first inorganic layer and the second inorganic layer). The final prefabricated board can be as shown in Figure 19.

[0154] It is understandable that the prefabricated board may also include an EL layer (electro luminescent layer) and a cathode layer, etc., which are not shown in Figure 19. The specific preparation method of the layer structure such as the EL layer and the cathode layer can be referred to the relevant technology and is not specifically limited in the embodiments of this application.

[0155] Step 2: Prepare a first isolation layer 301 on the buffer layer A.

[0156] In one example, the first isolation layer 301 may be directly formed on the buffer layer A.

[0157] In one possible embodiment, referring to FIG20 , the display substrate in the embodiment of the present application may further include a third metal layer (M3). In one possible embodiment, before forming the first isolation layer 301 on the buffer layer A, the method may further include: depositing a third metal layer on the buffer layer A, and performing trace etching on the third metal layer to obtain a patterned third metal layer (M3).

[0158] After forming a buffer layer A (the material can be SiNx) on the encapsulation layer EN, a third metal layer M3 (the material can be Ti / Ag / Ti) can be deposited and etched to form an M3 pattern. The M3 pattern is only in the second type of pixel area, as shown in Figure 20.

[0159] Step three: performing a patterning operation on the first isolation layer 301 in the second type pixel region to form a plurality of first spacing regions 3011 in the first isolation layer 301 in the second type pixel region.

[0160] The first spacing region 3011 may correspond to a projection of a pixel light emitting region in the pixel portion 02 on the substrate 01 .

[0161] A low-refractive index (ie, low-refractive index) first isolation layer 301 (OC3) is coated and patterned to cover the M3 pattern and / or Buffer A. The refractive index of OC3 may be 1.4-1.55, as shown in FIG21 .

[0162] Step 4: prepare a patterned first metal layer on the first isolation layer 301 , and prepare a second isolation layer 302 on the first isolation layer 301 and the first metal layer.

[0163] A first metal layer M1 (material may be Ti / Ag / Ti) may be deposited and etched to form an M1 pattern, and then a second isolation layer 302 (OC4) may be coated. The refractive index of OC2 may be 1.6-1.75, as shown in FIG. 22 .

[0164] Step five: performing a patterning operation on the second isolation layer 302 in the second type pixel region to form a plurality of second spacing regions 3021 in the second isolation layer 302 in the second type pixel region.

[0165] The second spacing region 3021 may correspond to a projection of a pixel light emitting region in the pixel portion 02 on the substrate 01 .

[0166] The coated OC4 is patterned, for example, as shown in FIG. 22 .

[0167] Step six: prepare a patterned second metal layer on the second isolation layer 302 , and prepare a first protection layer 303 on the second isolation layer 302 and the second metal layer.

[0168] 23 , the first spacing region 3011 and the second spacing region 3021 may be filled with the first protective layer 303; the third refractive index of the first protective layer 303 (OC1) may be smaller than the first refractive index of the first isolation layer 301, and the third refractive index of the first protective layer 303 (OC1) may be smaller than the second refractive index of the second isolation layer 302.

[0169] A second metal layer M2 (material may be Ti / Ag / Ti) is deposited and etched to form an M2 pattern, and a first protective layer 303 (OC1) is applied and OC1 is patterned, as shown in Figure 23. The refractive index of OC3 may be 1.6-1.75.

[0170] Step seven: perform subsequent preparation processes of the display substrate.

[0171] The subsequent preparation process of the display substrate may include: (1) coating a high-thickness organic layer Ink, which can be performed by multiple scraping or spin coating methods or a single inkjet method. The thickness of the Ink can be 8-17um, as shown in Figure 24. (2) Making a BM or color filter layer (COE, Color filter On Encapsulation), wherein, if the subsequent process does not attach a POL (Polarizer, polarizing plate), a color filter layer needs to be prepared; for example, as shown in Figure 25, the figure takes the preparation of a color filter layer as an example, and the width of the black matrix layer (BM) on the pixel definition layer (PDL) can be less than / equal to the width of the third metal layer (M3). (3) Complete the coating of the fourth protective layer OC4, as shown in Figure 26.

[0172] It is understandable that since the method for preparing the display substrate has substantially the same technical effects as the aforementioned display substrate, for the purpose of brevity, the technical effects of the method for preparing the display substrate will not be repeatedly described herein.

[0173] An embodiment of the present application further provides a display screen, which may include a power supply component and any of the display substrates described above in the present application.

[0174] The power supply component is connected to the display substrate and is used to supply power to the display substrate.

[0175] It is understandable that since the display screen and the aforementioned display substrate have substantially the same technical effects, for the purpose of brevity, the technical effects of the display screen will not be described repeatedly here.

[0176] It is understandable that the drawings of the embodiments of the present application do not illustrate the electroluminescent layer, cathode layer and other common layers. The specific structures of the electroluminescent layer, cathode layer and other common layers can be found in the relevant technology and are not specifically limited in the embodiments of the present application.

[0177] It should be understood that the drawings of the embodiments of the present application illustrate the first isolation layer 301 as an OC3 layer and the second isolation layer 302 as an OC4 layer, and do not limit the first isolation layer 301 and the second isolation layer 302 to being OC layers. For example, the first isolation layer 301 may be an ILD1 layer and the second isolation layer 302 may be an ILD2 layer, both of which are also within the scope of protection of the embodiments of the present application.

[0178] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device comprising the element.

[0179] The above description is only an optional embodiment of the present application and is not intended to limit the scope of protection of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the scope of protection of the present application.

Claims

1. A display substrate, the display substrate is divided into a first type of pixel area and a second type of pixel area, the first type of pixel area is a normal pixel area, and the second type of pixel area is an anti-peeping pixel area; and the display substrate comprises: A substrate, a pixel portion and a touch portion; the pixel portion is arranged on the substrate, and the touch portion is arranged on a side of the pixel portion away from the substrate; The touch control portion includes a first isolation layer, a second isolation layer and a first protection layer, wherein the second isolation layer is arranged on a side of the first isolation layer away from the substrate; In the second type of pixel area, the first isolation layer has a plurality of first spacing regions, the second isolation layer has a plurality of second spacing regions, and the first spacing regions and the second spacing regions correspond to projections of the pixel light emitting regions in the pixel portion on the substrate; The first protective layer is disposed on a side of the second isolation layer away from the substrate, and the first spacing region and the second spacing region are filled with the first protective layer; The third refractive index of the first protective layer is smaller than the first refractive index of the first isolation layer, and the third refractive index of the first protective layer is smaller than the second refractive index of the second isolation layer.

2. The display substrate according to claim 1, wherein: The first isolation layer is patterned into a plurality of first trapezoidal structures, and the first spacing area is between two adjacent first trapezoidal structures; the value range of the bottom angle formed by the bottom of the first trapezoidal structure close to the substrate and the substrate is 45 degrees to 75 degrees; The second isolation layer is patterned into a plurality of second trapezoidal structures, and the second spacing area is between two adjacent second trapezoidal structures; the value range of the bottom angle formed by the bottom of the second trapezoidal structure close to the substrate and the substrate is 45 degrees to 75 degrees; The length of the first trapezoidal structure away from the upper bottom of the substrate is not less than the length of the second trapezoidal structure close to the lower bottom of the substrate.

3. The display substrate according to claim 1 or 2, wherein: A ratio of the second refractive index to the third refractive index is greater than 1.10; and / or a ratio of the first refractive index to the third refractive index is greater than 1.

10.

4. The display substrate according to any one of claims 1 to 3, wherein: The touch control part further includes a buffer layer, a first metal layer, a second metal layer, an optical control layer, a black matrix layer and a second protective layer; The buffer layer is arranged on a side of the pixel portion away from the substrate; the first isolation layer is arranged on a side of the buffer layer away from the substrate; the first metal layer is arranged between the first isolation layer and the second isolation layer; the second metal layer is arranged between the second isolation layer and the first protective layer; the optical control layer is arranged on a side of the first protective layer away from the substrate; the black matrix layer is arranged on a side of the optical control layer away from the substrate; The black matrix layer has a plurality of third spacing regions, and the third spacing regions correspond to the projections of the pixel light-emitting regions in the pixel portion on the substrate; the second protective layer is arranged on a side of the black matrix layer away from the substrate, and the third spacing regions are filled with the second protective layer.

5. The display substrate according to claim 4, wherein: In the second type of pixel area, the touch part also includes a third metal layer, which is arranged between the first isolation layer and the buffer layer. The routing width of the third metal layer is greater than the routing width of the first metal layer, and the routing width of the third metal layer is greater than the routing width of the second metal layer.

6. The display substrate according to claim 5, wherein: The third metal layer is connected to the ground of the display substrate.

7. The display substrate according to any one of claims 1 to 6, wherein: The normal pixels in the first type of pixel area and the anti-peeping pixels in the second type of pixel area are arranged alternately, and each sub-pixel in the anti-peeping pixel includes a plurality of anti-peeping pixel units.

8. The display substrate according to any one of claims 1 to 6, wherein: Each sub-pixel in the display substrate includes a plurality of anti-peeping pixel units and at least one normal pixel unit. The area where the anti-peeping pixel units are located is the second type of pixel area, and the area where the normal pixel units are located is the first type of pixel area.

9. The display substrate according to claim 7 or 8, wherein: The size of the anti-peeping pixel unit does not exceed 15um.

10. The display substrate according to claim 7, wherein: The touch part also includes a first metal layer and a second metal layer, and the first metal layer and the second metal layer include a plurality of touch lines; in the projection direction of the substrate, the touch lines are located in the intervals between adjacent sub-pixels and in the intervals between adjacent anti-peep pixel units and normal pixel units.

11. The display substrate according to claim 7, wherein: The pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures; For any sub-pixel in the anti-peeping pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel shares an anode structure.

12. The display substrate according to claim 7, wherein: The pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures; For any sub-pixel in the anti-peeping pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units by the pixel isolation structure, and each anti-peeping pixel unit of the sub-pixel is connected to a different anode structure.

13. The display substrate according to claim 8, wherein: The touch control portion further includes a first metal layer and a second metal layer, wherein the first metal layer and the second metal layer include a plurality of touch control wirings; in the projection direction of the substrate, the touch control wirings are located in the intervals between adjacent sub-pixels.

14. The display substrate according to claim 8, wherein: The pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures; For any sub-pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units and a normal pixel unit through the pixel isolation structure, and the normal pixel unit of the sub-pixel is connected to an anode structure, and each anti-peeping pixel unit of the sub-pixel shares another anode structure.

15. The display substrate according to claim 8, wherein: The pixel portion includes an anode layer and a pixel defining layer, the anode layer includes a plurality of anode structures, and the pixel defining layer includes a plurality of pixel isolation structures; For any sub-pixel, the sub-pixel is divided into a plurality of anti-peeping pixel units and a normal pixel unit through the pixel isolation structure, and the normal pixel unit and each anti-peeping pixel unit of the sub-pixel are respectively connected to different anode structures.

16. The display substrate according to any one of claims 1 to 15, wherein: The first isolation layer is a third protective layer, and the second isolation layer is a fourth protective layer.

17. The display substrate according to any one of claims 1 to 15, wherein: The first isolation layer is a first interlayer dielectric layer, and the second isolation layer is a second interlayer dielectric layer.

18. A method for preparing a display substrate, the method comprising: A buffer layer is formed on a side of a prefabricated plate away from the substrate, wherein the prefabricated plate comprises a substrate and a pixel portion, and the pixel portion is arranged on the substrate; preparing a first isolation layer on the buffer layer; Performing a patterning operation on the first isolation layer in the second type pixel region to form a plurality of first spacing regions in the first isolation layer in the second type pixel region; wherein the first spacing regions correspond to projections of the pixel light emitting regions in the pixel portion on the substrate; Preparing a patterned first metal layer on the first isolation layer, and preparing a second isolation layer on the first isolation layer and the first metal layer; Performing a patterning operation on the second isolation layer in the second type pixel region to form a plurality of second spacing regions in the second isolation layer in the second type pixel region; wherein the second spacing regions correspond to projections of the pixel light emitting regions in the pixel portion on the substrate; A patterned second metal layer is prepared on the second isolation layer, and a first protective layer is prepared on the second isolation layer and the second metal layer; wherein the first spacing region and the second spacing region are filled with the first protective layer; the third refractive index of the first protective layer is less than the first refractive index of the first isolation layer, and the third refractive index of the first protective layer is less than the second refractive index of the second isolation layer; The subsequent preparation process of the display substrate is carried out.

19. The method according to claim 18, wherein: Before preparing the first isolation layer on the buffer layer, the method further comprises: Depositing a third metal layer on the buffer layer, and performing routing etching on the third metal layer to obtain an imaged first metal layer; The routing width of the third metal layer is greater than the routing width of the first metal layer, and the routing width of the third metal layer is greater than the routing width of the second metal layer.

20. A display screen, comprising: A power supply component, and a display substrate as claimed in any one of claims 1 to 17; The power supply component is connected to the display substrate and is used to supply power to the display substrate.

Images