Power switch monitoring based on threshold voltage and gate charge time duration

Abstract

A method of monitoring a power switch. The method comprises in a first and second test sessions, providing a defined current to a control terminal of the power switch, during the provision of the defined current, measuring a time required for a voltage at the control terminal of the power switch to change between voltage levels or a change in voltage of the control terminal of the power switch in response to the provision of the defined current for a defined time, and recording the measured time or the measured voltage. The method also comprises comparing the measured time or the measured voltage from the first test session with the measured time or the measured voltage from the second test session.

Description

POWER SWITCH MONITORING BASED ON THRESHOLD VOLTAGE AND GATECHARGE TIME DURATIONFIELD OF THE DISCLOSURE

[0001] The present invention relates to monitoring power switches and, more specifically, to monitoring the charging of the control terminal of a power switch.BACKGROUND INFORMATION

[0002] Semiconductor power switches such as insulated gate bipolar transistors (IGBTs) and field effect transistors (FETs) are often used in a variety of high power applications. The applications include, e.g., driving electric motors in automotive and other contexts, power conversion, power generation, and power transmission. Power switches are specifically designed to survive the high power conditions in such applications. For example, power switches are designed to withstand relatively large potential differences between the main terminals (e.g., drain-to-source or collector-to-emitter voltages) in the OFF state and to conduct relatively large currents (e.g., drain or collector currents) in the ON state while dissipating relatively low power.

[0003] A gate driver provides an interface between these high-power switches and low-power control circuitry. For instance, a gate driver may accept low power control signal from a controller or microprocessor and provide a high current gate drive to a power switch. Gate drivers can play different roles in different contexts, including, e.g., low-side drivers, high-side drivers, half-bridge drivers, and full-bridge drivers. Often, gate drivers include protection features such as desaturation (DESAT) protection, clamping, over current protection, and the like.BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Non-limiting and non-exhaustive embodiments of power switch monitoring based on threshold voltage and gate charge time duration are described with reference to the following figures, wherein like reference numerals refer to like parts throughout the various views unless otherwise specified.

[0005] FIG. 1 is a schematic illustration of a gate drive and monitoring system.

[0006] FIG. 2 is a flow chart of a process for implementing a test mode during which a power switch is monitored.

[0007] FIG. 3 is a schematic illustration of a gate drive and monitoring system.

[0008] FIG. 4 is a flow diagram of a process for monitoring a power switch.

[0009] FIG. 5 includes various waveforms that may arise during execution of the process of FIG. 4.

[0010] Corresponding reference characters indicate corresponding components throughout the several views of the drawings. Also, common but well-understood elements that are useful or necessary in a commercially feasible embodiment are often not depicted in order to facilitate a less obstructed view of these various embodiments of power switch monitoring based on threshold voltage and gate charge time duration.DETAILED DESCRIPTION

[0011] In the following description, numerous specific details are set forth in order to provide a thorough understanding of power switch monitoring based on threshold voltage and gate charge time duration. It will be apparent, however, to one having ordinary skill in the art that the specific detail need not be employed to practice the teachings herein. In other instances, well- known materials or methods have not been described in detail in order to avoid obscuring the present disclosure.

[0012] Reference throughout this specification to "one embodiment", "an embodiment", "one example" or "an example" means that a particular feature, structure or characteristic described in connection with the embodiment or example is included in at least one embodiment of a multiple output switch-mode power converter system. Thus, appearances of the phrases "in one embodiment", "in an embodiment", "one example" or "an example" in various places throughout this specification are not necessarily all referring to the same embodiment or example.Furthermore, the particular features, structures or characteristics may be combined in anysuitable combinations and / or subcombinations in one or more embodiments or examples. Particular features, structures or characteristics may be included in an integrated circuit, an electronic circuit, a logic circuit, or other suitable components that provide the described functionality. In addition, it is appreciated that the figures provided herewith are for explanation purposes to persons ordinarily skilled in the art and that the drawings, including waveforms, are not necessarily drawn to scale.

[0013] In the context of the present application, when a transistor is in an “off-state” or “off’ the transistor does not conduct a substantial amount of current. Conversely, when a transistor is in an “on-state” or “on” the transistor is able to conduct current with a relatively small resistance between the main terminals. By way of example, a power transistor can be implemented as an insulated gate bipolar transistor (IGBT) and, in the off-state, a high-voltage can be supported between the first main terminal (i.e., the collector terminal) and the second main terminal (i.e., the emitter terminal).

[0014] For purposes of this disclosure, “ground” or “ground potential” refers to a reference voltage or potential against which all other voltages or potentials of an electronic circuit or integrated circuit (IC) are defined or measured. Additionally, power is related to the rate of change of energy, i.e., “power” transfer accompanies “energy” transfer; conversely, “energy” transfer accompanies “power” transfer.

[0015] As mentioned above, gate drivers are used to drive power switches. Gate drivers may sense operational characteristics of the driven power switches that are used to determine if the power switches have become defective and / or require replacement. For instance, gate drivers sense operational characteristics of the driven power switches that can be used to determine a threshold voltage of a power switch or detect desaturation (DESAT) of a power switch.

[0016] Unfortunately, power switches can degrade or fail in several ways. Detecting DESAT may not identify some degradation or failure modes. For example, MOS-gated power devices are prone to degradation of the gate oxide over time. This degradation can result in a permanent drift of the gate threshold voltage toward 0V. In general, SiC MOSFETs are more prone to this type of degradation than Si MOSFETs. As another example, a power switch can suffer from localized defects in the gate-emitter / gate-collector (IGBT) or gate-source / gate-drain (MOSFET) structure. These defects can cause the gate leakage current to increase, resulting in an increase of the charge necessary to turn on the power switch.

[0017] Monitoring the threshold voltage and gate charging of a power switch is described herein. During a test mode that takes place outside of the normal power switching operation, a monitoring system may monitor and record a threshold voltage and one or more characteristics of the charging of a gate. The history of recorded threshold voltage and gate charging may be used to determine if the power switch is degrading or has become defective. For example, if the threshold voltage and / or the charge needed to achieve a given voltage on the gate drifts over time, then this can indicate that a power switch is degrading or has become defective. Remedial actions like replacing the power switch or tailoring the current that is conducted by the power switch can be undertaken.

[0018] FIG. 1 is a schematic illustration of a gate drive and monitoring system 100a. The gate drive and monitoring system 100a includes a power switch 101, a gate driver 102, and a microcontroller (MCU) 103. Monitoring system 100a can be part of a power converter, e.g., in the drive and control unit for an electric motor.

[0019] In the illustrated implementation, power switch 101 is an insulated gate bipolar transistor (IGBT). Other power switches, including field effect transistors (FETs) made from, e.g., silicon, silicon carbide, and gallium nitride can be used. Nevertheless, for the sake of brevity, terminology specific to IGBTs will be used. For example, power switch 101 is described herein as including a collector main terminal, a gate control terminal, and an emitter main terminal.

[0020] The gate driver 102 is circuitry that is configured to drive the gate of power switch 101 and to monitor that driving. In the illustrated implementation, gate driver 102 includes both gate driver functionality that drives the gate of power switch 101 during normal power switching operations and gate driver functionality that drives the gate of power switch 101 during a test mode. As described below, in the illustrated implementation, different circuit components are used in the illustrated implementation to drive power switch 101 during normal operations and during the test mode. However, this is not necessarily the case and in other implementations the same circuitry can be used. Further, in general, gate driver 102 will include protection features like desaturation (DESAT) protection, clamping, over current protection, and the like. In contrast with the longer-term monitoring described below, such protection features are often designed to protect against faults in individual switching transitions rather than degradation that occurs over the operational lifespan of a power switch.

[0021] The circuitry in gate driver 102 that drives the gate of power switch 101 during normal power switching operations includes a high gate buffer 114, a low gate buffer 112, and their associated gate impedances 104, 105. High gate buffer 114 is configured to source current through gate impedance 105 to the gate of power switch 101 in response to an input signal IN2. Low gate buffer 112 is configured to sink current through gate impedance 104 from the gate of power switch 101 in response to an input signal INI. In normal operation, buffers 112, 114 control the switching of power switch 101, e.g., to convert power, drive a motor, or the like. Input signals INI, IN2 can be provided, e.g., by a system controller (not shown), by the illustrated microcontroller (MCU) 103, or from another component depending on the application.

[0022] In the illustrated implementation, microcontroller (MCU) 103 controls the implementation of the test mode and records the test mode results for longer-term analysis. For example, microcontroller (MCU) 103 can be coupled, directly or indirectly, to a long-term memory that stores the test mode results during the operational lifespan of the power switch 101. In other implementations, a system controller or other circuitry can control the implementation of the test mode. For example, in some implementations, the implementation of the test mode can be controlled from circuitry that is internal to gate driver 102. Microcontroller (MCU) 103 can be implemented using, e.g., a microprocessor that executes instructions in accordance with the logic of machine-readable instructions, an application-specific integrated circuit, or a combinations of these or other processing functionality.

[0023] The circuitry in gate driver 102 that drives the gate of power switch 101 during a test mode includes bias control circuity 117, a first current source 118, and a switch 116. Gate monitor 110 and a timer 111 participate in the monitoring of power switch 101 during the test mode and communicate with microcontroller (MCU) 103.

[0024] First current source 118 is electrically coupled between a supply node NVP and a first terminal of switch 116 and is configured to provide a current II in response to a command signal C3 from bias control circuity 117. In general, first current source 118 is a constant current source and sources either a fixed or adjustable current. For example, in some implementations, a human user (e.g., using trimming functionality), microcontroller (MCU) 103, or bias control circuity 117 can adjust current II between one or more constant but discrete values.

[0025] In addition to command signal C3, bias control circuity 117 is also coupled to provide a control signal C2 that controls the switching of switch 116. When switch 116 is closed, thecurrent II provided by current source 118 is coupled through gate impedance 105 to the gate of power switch 101. With switch 116 closed and current source 118 providing current II, the gate of power switch 101 is charged and power switch 101 is biased into conduction.

[0026] Bias control circuity 117 is also coupled to provide a control signal Cl that controls the provision of current by second current source 122 to the collector of power switch 101. Second current source 122 is electrically coupled between supply node NVP and a main terminal of power switch 101 through a diode 108. In the illustrated implementation, diode 108 is external to gate driver 102. The anode of diode 108 is coupled to gate driver 102. The cathode of diode 108 is coupled to the main terminal of power switch 101. Diode 108 thus allows the current output by second current source 122 to flow to the main terminal of power switch 101 when the main terminal of power switch 101 is at a lower potential than the output of second current source 122 but protects gate driver 102 from high voltages on the main terminal of power switch 101 during normal power switching operations.

[0027] Also, in the illustrated implementation, bias control circuity 117 is coupled to sense the current output by second current source 122. This is schematically represented by a sense line 126. In other implementations, microcontroller (MCU) 103 is coupled to sense the current output by second current source 122. The provision of current by second current source 122 can be controlled in a variety of different ways. For example, current source 122 may be switchable on and off by control signal Cl. As another example, a switch may be coupled to divert current output from second current source 122 away from the collector of power switch 101, as illustrated below in Fig. 3.

[0028] Gate monitor 110 and timer 111 also participate in the implementation of the test mode under the control of microcontroller (MCU) 103. Timer 111 outputs a clock signal that is used by microcontroller (MCU) 103 to measure time during the test mode. The use of the clock signal is discussed further below.

[0029] Gate monitor 110 is coupled to the gate of power switch 101 and configured to monitor the voltage on the gate of power switch 101 in the test mode. In the illustrated implementation, gate monitor 110 is coupled to a node NB1 that is between gate impedance 104 and the output of buffer 112. In the test mode, buffer 112 presents a high output impedance and essentially no current flows through gate impedance 104. Node NB1 is in essence at the same voltage as the gate of power switch 101.

[0030] In some implementations, gate monitor 110 outputs a series of measurements of the gate voltage after switch 116 is closed and current II is coupled to the gate of power switch 101 to microcontroller (MCU) 103. The series of measurements of the gate voltage can be used by microcontroller (MCU) 103 to determine the threshold voltage of power switch 101. In other implementations, gate monitor 110 receives an indication that a threshold level of current has begun to flow between the main terminals of power switch 101 and outputs a single voltage measurement of the gate voltage at that time. Assuming that this threshold is chosen properly, the gate voltage can be the threshold voltage of power switch 101. As an aside, assuming that microcontroller (MCU) 103 is a digital data processor, the voltage measurements output by gate monitor 110 are digitized for input and processing by microcontroller (MCU) 103.

[0031] FIG. 2 is a flow chart of a process 500 for implementing a test mode during which a power switch is monitored. The test mode can be entered periodically during the operational lifespan of the power switch. For example, in some cases, the test mode can be entered every time a device that includes the power switch is started-up or reset. Since the operational lifespan of power switches can be years if not a decade or more, the test mode can monitor the characteristics of the power switch to identify long-term degradation. For the sake of convenience, process 500 is explained in the context of monitoring system 100a (FIG. 1). This is for didactic purposes and process 500 can be implemented in any of a variety of monitoring systems.

[0032] In contrast with the test mode, during normal operation, power switch 101 switches into and out of conduction in accordance with switching commands INI, IN2. In particular, in response to IN2, buffer 114 sources current to the gate of the power switch 101. In response to input signal INI, buffer 112 sinks current from the gate of the power switch 101.

[0033] In process 500, a test mode in which threshold voltage and gate charge time duration are monitored is initiated at step 505. The test mode can be initiated automatically (e.g., at start up or reset of a device that includes the power switch or passage of a defined period of time) or in response to a triggering event (e.g., a user-generated request). To initiate a test mode in the context of monitoring system 100a, the switching of power switch 101 into and out of conduction is halted with power switch 101 in the OFF state. Buffer 114 and buffer 112 are generally configured to present a high impedance output at nodes NB1, NB2 so as to not affect the threshold voltage and gate charge time duration.

[0034] In some implementations, a load or a portion of a load that is coupled to power switch 101 during normal operation may be decoupled or otherwise modified. For example, a capacitor (e.g., a DC link capacitor) that is coupled to power switch 101 may be isolated from power switch 101 or discharged to ensure that the voltage across power switch 101 starts from a low value. As another example, current flow paths that are in parallel with power switch 101 may be blocked. For example, if power switch 101 is coupled in a bridge configuration with other power switches, those other power switches may be turned off.

[0035] Various components of monitoring system 100a may also be powered on or otherwise activated to initiate a test mode. For example, gate monitor 110 may be powered up or otherwise triggered to begin monitoring the voltage on the gate of power switch 101 and outputting the results of the monitoring. Bias control block 117 may be powered on. Other actions may be taken to ensure that testing can be implemented.

[0036] After the test mode is initiated, a main terminal of power switch 101 is charged at step 510. In the context of monitoring system 100a, bias control block 117 toggles signal Cl so that the current 12 from current source 122 flows through diode 108 and charges the collector of (open) power switch 101. At some point, the potential at the collector rises high enough such that current source 122 is no longer able to drive meaningful current through diode 108. In some implementations, during the charging, bias control block 117 receives a current sense signal SI 26 from current sense element 126. By monitoring current flow through current source 122, bias control block 117 can detect the end of charging. In other implementations, the main terminal of power switch 101 is charged without monitoring the current that flows to the main terminal. For example, bias control block 117 may toggle signal Cl for a predefined period of time that is in excess of the time that is expected to be needed to charge the main terminal of power switch 101. As an aside, current source 122 is not a constant current source. Rather, current 12 from current source 122 falls from a current limit to zero as the collector of power switch 101 is charged, and then rises from zero to a current limit as power switch 101 switches into conduction.

[0037] In some implementations, bias control block 117 may limit current 12 to a specific value (e.g., in a range between one and ten milliamperes (1-lOmA)) to control the rate of charging and, as discussed below, the current that flows through power switch 101 as the threshold voltage is crossed.

[0038] After the main terminal of the power switch is charged, the control terminal of the power switch is charged and the power switch is monitored at step 515. Further, the threshold voltage of the power switch and the gate charging of the power switch can be determined at step 520.

[0039] As for charging the control terminal of the power switch in the context of monitoring system 100a, the control terminal of the power switch is charged by bias control block 117 closing switch 116 and current source 118 providing gate current IG to power switch 101 through gate impedance 105. Since buffer 112 presents a high output impedance, almost no current flows through gate impedance 104 and almost the entire charge in the current output by current source 118 charges the gate of power switch 101. As discussed above, the current that is sourced from current source 118 can either be fixed or adjustable. For instance, current source 118 may be adjustable to provide a specific value of II that is greater than zero (e.g., 0.5mA, 1mA, 3mA, and the like). Regardless, microcontroller (MCU) 103 is informed of the magnitude of the current provided to the gate of power switch 101.

[0040] Bias control block 117 also informs microcontroller (MCU) 103 of the closing of switch 116. Microcontroller (MCU) 103 is coupled to both timer 111 and gate monitor circuitry 110. Microcontroller (MCU) 103 uses the clock signal output by timer 111 and measurements of the voltage on the gate of power switch 101 made by gate monitor circuitry 110 to monitor the voltage increase at the gate of power switch 101 over time. The information provided by bias control block 117 and gate monitor circuitry 110, along with a clock signal provided by timer 111, is used to determine the threshold voltage of power switch 101 and the time required for the gate of power switch 101 to charge to one or more voltage levels.

[0041] As for the threshold voltage of the power switch: once the power switch starts to switch into conduction, the charge will start to flow between the main terminals. This flow of current can identify the threshold voltage of the power switch. The threshold voltage of the power switch can be determined from the magnitude of the voltage on the control terminal of the power switch when a threshold level of current flows between the main terminals of the power switch.

[0042] In the context of monitoring system 100a, microcontroller (MCU) 103 receives information characterizing the magnitude of the voltage on the gate of the power switch 101 from gate monitor circuitry 110. As power switch 101 switches into conduction, bias control block 117 senses an increased current output by second current source 122, e.g., using sense line 126. Bias control block 117 can compare the current output by second current source 122 with athreshold level and informs microcontroller (MCU) 103 of the time when the current output by second current source 122 reaches or crosses the threshold. The magnitude of the voltage on the gate of the power switch 101 when the current output by second current source 122 rises to or above a threshold level is the threshold voltage of power switch 101. As discussed above, in other implementations, bias control block 117 informs gate monitor circuitry 110 of the time when the current output by second current source 122 reaches or crosses the threshold and gate monitor circuitry 110 outputs a single measurement of the threshold voltage of power switch 101.

[0043] As for the gate charging: during charging of the control terminal, the voltage on the control terminal rises at a rate that is a function not only by the charge that is provided to the control terminal by the current that is provided to that control terminal, but also by the physical characteristics of the control terminal— and possibly other portions of the power switch. As discussed above, in power switches that include insulated control terminals, the quality of the control terminal insulation may degrade over time. In the face of such degradation, the rate of increase in the voltage on the control terminal over time for a given current may also change. By monitoring the voltage on the control terminal while a known current is provided, the charging of the gate can be characterized and used to identify changes in the physical characteristics of the power switch.

[0044] In the context of monitoring system 100a, bias control block 117 informs microcontroller (MCU) 103 of the time when switch 116 is closed and current source 118 begins providing gate current IG to power switch 101. This time is recorded. Gate monitor circuitry 110 informs microcontroller (MCU) 103 about the voltage on the gate of power switch 101. Either: the time required to charge the gate to a particular voltage using a known current or the voltage on the gate after charging using a known current for a known time can be determined at 520. For example, in some implementations, the time required to charge the gate to the threshold voltage of power switch 101 can be determined.

[0045] FIG. 3 is a schematic illustration of a gate drive and monitoring system 100b. Gate drive and monitoring system 100b shares many common features and components with gate drive and monitoring system 100a (FIG. 1). For the sake of brevity, only new features and components will be described in detail. Except when their function is interrelated, each of the newfeatures / components in independent in the sense that other gate drive and monitoring systems can include a proper subset of the new features / components without necessarily including all of the new features / components.

[0046] As a first example of the new features / components, in gate drive and monitoring system 100b, current source 122 is a constant current source that sources current continuously during operation in a DESAT monitoring scheme. Gate drive and monitoring system 100b also includes a switch 120 that is coupled between the output of current source 122 and the main terminal of power switch 101. Bias control block 117 is coupled to provide signal Cl to switch 120 and toggles the flow of current 12 from current source 122 to the main terminal of power switch 101 by diverting or ending the diversion of current 12 away from the main terminal of power switch 101.

[0047] As a second example of new features / components, additional components are coupled along the current flow path between the output of current source 122 and the main terminal of power switch 101. In the illustrated implementation, these additional components are a capacitance 106 and a resistance 107. Capacitance 106 is coupled between the current flow path and ground. Resistance 107 is part of the current flow path between current source 122 and the main terminal of power switch 101. Capacitance 106 and resistance 107 may be implemented by one or more discrete capacitors or resistors that are external to gate driver 102 and may be used, e.g., for monitoring desaturation (DESAT) events of power switch 101. An example of such monitoring is described in the datasheet of the Avago HCPL-316J Gate Drive Optocoupler.

[0048] Components such as capacitance 106 and resistance 107 may impact aspects of the operation of gate driver 102. For example, as discussed above, current source 122 charges the main terminal of power switch 101 in the test mode (i.e., step 510 in process 500, FIG. 2). With capacitance 106 present, the amount of charge that must be supplied by current source 122 to charge the main terminal of power switch 101 to the same voltage level is increased. In implementations where bias control block 117 senses current flow from current source 122, the end of charging will simply be delayed. However, in implementations where bias control block 117 toggles signal Cl for a predefined period of time, that period of time may be increased vis-a- vis implementations without capacitance 106 present.

[0049] As a third example of new features / components, power switch 101 is illustrated as an NMOS transistor rather than an IGBT. This change may also impact aspects of the operation ofgate driver 102. For example, the drive signals output by buffers 112, 114 and gate current source 118 may be adapted to driving a MOS transistor, as can the magnitudes of gate impedances 104, 105.

[0050] As a fourth example of new features / components, bias control circuity 117 is coupled to sense the current output by gate current source 116. This is schematically represented by a sense line 125. Measurements of the current output from gate current source 116 allow the charging of the control terminal of power switch 101 to be monitored more accurately. For example, temperature differences between different test modes can be accommodated.

[0051] As a fifth example of new features / components, gate drive and monitoring system 100b includes a watchdog timer 119. Watchdog timer 119 is a component that is configured to detect a fault in power switch 101. In particular, watchdog timer 119 can receive information regarding the closing of switch 116 from bias control 117 and information about the voltage on the control terminal of power switch 101 from gate monitor 110. At a defined time period after switch 116 is closed, watchdog timer 119 can compare the current flowing between the main terminals of power switch 101 with a threshold current level. If the current flowing between the main terminals of power switch 101 has not risen to that threshold, watchdog timer 119 can issue a signal indicative of a fault condition. The signal can trigger an end to the test mode.

[0052] In the illustrated implementation, watchdog timer 119 is internal to gate driver 102 and may be directly coupled to bias control 117, gate monitor 110, and timer 111. In other implementations, watchdog timer 119 may be implemented by microcontroller (MCU) 103.

[0053] FIG. 4 is a flow diagram of a process 200 for monitoring a power switch 101. Process 200 may correspond with implementation of a test mode in using gate drive and monitoring system 100b (FIG. 3). During the test mode, buffers 112, 114 are generally disabled and present a high impedance to nodes NB1, NB2, respectively. Also, other loads may be disconnected or modified to direct sense current IS to power switch 101. In general, MCU 103 will trigger the test mode and communicate with bias control module 117 to control implementation of the test mode by bias control module 117.

[0054] At step 202, bias control module 117 triggers the provision of sense current IS to a main terminal of power switch 101. In the context of gate drive and monitoring system 100b, bias control module 117 toggles control signal Cl to open switch 120. Before switch 120 is opened, voltage VC across capacitance 106 may be essentially zero volts. As discussed above, theprovision of current 12 to the main terminal of power switch 101 will also increase the voltage VC across capacitance 106 if it is present.

[0055] At decision step 206, bias control module 117 determines whether sense current IS has fallen below a threshold current level within a defined period of time. If the sense current IS does not fall below the threshold within the defined period, then this may indicate that power switch 101 has a short and / or is otherwise defective. In response to determining that sense current IS has not fallen below a threshold current level, bias control module 117 outputs a fault signal indicating detection of a short-circuit fault at step 208 and process 200 stops.

[0056] Alternatively, if the sense current IS does fall below the threshold current level, either bias control module 117 or MCU 103 starts timer 111 at step 210. Also, bias control module 117 starts charging the control terminal of power switch 101 by closing switch 116 and coupling gate current source 118 to the control terminal of power switch 101 at step 212. Bias control module 117 may close switch 116 in response to a command from MCU 103.

[0057] In some implementations, timer 111 is started at the same time that bias control module 117 starts charging the control terminal of power switch 101. For example, control module 117 can use the same single signal to start timer 111 and close switch 116. Alternatively, timer 111 may be started earlier and bias control module 117 may inform MCU 103 when signal C2 has toggled switch 116 to close. In either case, timer 111 provides a clock signal that can be used to measure time since signal C2 toggled switch 116 to close.

[0058] Also, either bias control module 117 or MCU 103 may start watchdog timer 119 at step 214. In some implementations, watchdog timer 119 may be started concurrently with the start of timer 111 and / or the closing switch 116. For example, the same single signal can be used to start watchdog timer 119 and timer 111 and to close switch 116.

[0059] At decision step 218, watchdog timer 119 determines whether the current flowing between the main terminals of power switch 101 has failed to rise to a threshold level within a period of time after the current from gate current source 118 starts charging the control terminal of power switch 101. In response to the current flowing between the main terminals failing to rise to the threshold level within the period of time, the watchdog timer 119 outputs a fault detection signal at step 220 and process 200 stops. Watchdog timer 119 can determine whether the current flowing between the main terminals of power switch 101 has failed to rise to thethreshold level based on information about the current flowing between the main terminals received from gate monitor 110 and sense line 126.

[0060] Both during the determination of whether the voltage on the control terminal of power switch 101 has failed to rise to a threshold level by watchdog timer 119 and after, gate monitor 110 monitors the voltage on the control terminal of power switch 101 at step 222. In the illustrated implementation, the monitoring is stopped after the current flowing between the main terminals of power switch 101 indicates that the threshold voltage of power switch 101 has been reached. In other words, with the control terminal of power switch 101 coupled to gate current source 118, the gate voltage will start to rise. Absent a fault, the gate voltage will rise to the threshold voltage of power switch 101 and a threshold level of current will flow between the main terminals of power switch 101. Bias control module 117 will sense the current flow, e.g., over sense line 126 and either bias control module 117 or MCU 103 can determine that the threshold voltage of power switch 101 has been reached at decision step 224. Further, the time required to reach the threshold voltage of power switch 101 can be measured by MCU 103 to characterize the charging of the gate of power switch 101.

[0061] In other implementations, gate monitor 110 continues to monitor the voltage on the control terminal of power switch 101 after the voltage on the control terminal of power switch 101 reaches the threshold voltage of power switch 101. For example, a gate voltage that is higher than the threshold voltage of power switch 101 but still within the safe operating area of power switch 101 can be chosen as a trigger for ending monitoring of the voltage on the control terminal of power switch 101. This may be useful in implementations where a voltage in excess of the threshold voltage of power switch 101 is used as a trigger for characterizing the charging of the gate of power switch 101.

[0062] Regardless of the threshold, not only is monitoring ended, but bias control module 117 also decouples gate current source 118 from the gate of power switch at step 228. This effectively ends the collection of data in the test mode. In some implementations, the end of data collection may trigger other activities. For example, the gate may be discharged by buffer 112 and normal switching operations may be resumed.

[0063] In some implementations, the test mode also includes data storage and recordation activities. For example, MCU 103 may record the determined threshold voltage of power switch 101 at step 228. Also, MCU 103 may record information characterizing the charging of thecontrol terminal of power switch 101 at 230. For example, either the time when the voltage at the control terminal of power switch 101 reaches a defined voltage or the voltage of the control terminal of power switch 101 after a defined time can be recorded.

[0064] In some implementations, the test mode also includes data analysis in which the recorded threshold voltage and charging information is processed to identify degradation or failure of power switch 101 at step 232. For example, the threshold voltage and charging information from the present execution of process 200 can be compared to threshold voltage(s) and charging information from previous execution(s) of process 200. Changes over time can be used to identify degradation or even failure.

[0065] FIG. 5 includes various waveforms 301-306 that may arise during execution of process 200 (FIG. 4). Waveform 301 represents control signal Cl. Waveform 302 represents capacitor voltage VC. Waveform 303 represents sense current IS. Waveform 304 represents control signal C2. Waveform 305 represents gate voltage VG. Waveform 306 represents gate current IG.

[0066] At time 310 the control signal Cl transitions from high to low, toggling switch 120 open. Concurrently, sense current IS increases to a value lx as capacitance 106 and the control terminal of power switch 101 charge. At time 311, sense current IS approaches zero as the voltage across capacitance 106 and at the control terminal of power switch 101 rise to their maximum value VH. In general, the maximum value VH is essentially equal to the supply voltage that powers current source 122. Prior to time tO, the control signal C2, the gate voltage VG, and the gate current IG are zero or substantially zero.

[0067] At time tO, the control signal C2 transitions from low to high. In response, switch 116 is closed and gate current source 118 is coupled to node NB2. Consequently, a fixed ( / .<?., a forced) gate current IG flows to the control terminal of power switch 101 and the voltage on the controller terminal rises. In general, the control terminal voltage will rise with an essentially linear slope.

[0068] At time 312, the sense current IS again increases as the control terminal voltage reaches the threshold voltage of power switch 101 and power switch 101 begins to turn on. At time tf, the sense current IS, which now represents the drain or collector current, reaches a threshold value Itarg. Accordingly, the threshold voltage VG(tf) of power switch 101 is the value of thegate voltage VG (waveform 305) at time tf. The charging behavior of power switch 101 can be characterized using the time needed to reach the threshold voltage.CONCLUSION

[0069] The above description of illustrated examples of the present disclosure, including what is described in the Abstract are not intended to be exhaustive or to be limitation to the precise forms disclosed. While specific embodiments of, and examples for power switch monitoring based on threshold voltage and gate charge time duration are described herein for illustrative purposes, various equivalent modifications are possible without departing from the broader spirit and scope of the present disclosure. Indeed, it is appreciated that the specific example voltages, currents, frequencies, power range values, times, etc., are provided for explanation purposes and that other values may also be employed in other embodiments and examples in accordance with the teachings herein.

[0070] The foregoing description may refer to elements or features as being “connected” or “coupled” together. As used herein, unless expressly stated otherwise, “connected” means that one element / feature is directly or indirectly connected to another element / feature, and not necessarily mechanically. Likewise, unless expressly stated otherwise, “coupled” means that one element / feature is directly or indirectly coupled to another element / feature, and not necessarily mechanically. Thus, although the various schematics shown in the figures depict example arrangements of elements and components, additional intervening elements, devices, features, or components may be present in an actual embodiment (assuming that the functionality of the depicted circuits is not adversely affected).

[0071] Moreover, conditional language used herein, such as, among others, “can,” “could,” “might,” “may,” “e.g.,” “for example,” “such as” and the like, unless specifically stated otherwise or otherwise understood within the context as used, is generally intended to convey that certain embodiments include, while other embodiments do not include, certain features, elements and / or states. Thus, such conditional language is not generally intended to imply that features, elements and / or states are in any way required for one or more embodiments or that one or more embodiments necessarily include logic for deciding whether these features, elements and / or states are included or are to be performed in any particular embodiment.

[0072] While certain embodiments have been described, these embodiments have been presented by way of example only, and are not intended to limit the scope of the disclosure. Indeed, the novel apparatus, methods, and systems described herein may be embodied in a variety of other forms; furthermore, various omissions, substitutions and changes in the form of the methods and systems described herein may be made without departing from the spirit of the disclosure. For example, while the disclosed embodiments are presented in a given arrangement, alternative embodiments may perform similar functionalities with different components and / or circuit topologies, and some elements may be deleted, moved, added, subdivided, combined, and / or modified. Each of these elements may be implemented in a variety of different ways. Any suitable combination of the elements and acts of the various embodiments described above can be combined to provide further embodiments. Accordingly, the scope of the present invention is defined only by reference to the appended claims.

[0073] The present invention is defined in the claims; however, it should be understood that the present invention can alternatively be defined in accordance with the following examples. Example 1. A method of monitoring a power switch, the method comprising: in a first test session, providing a defined current to a control terminal of the power switch, during the provision of the defined current, measuring a time required for a voltage at the control terminal of the power switch to change between voltage levels, and recording the measured time; in a second test session, providing a defined current to the control terminal of the power switch, during the provision of the defined current, measuring a time required for a voltage at the control terminal of the power switch to change between voltage levels, and recording the measured time; and comparing the measured time from the first test session with the measured time from the second test session.Example 2. A method of monitoring a power switch, the method comprising: in a first test session, providing a defined current to a control terminal of the power switch, during the provision of the defined current, measuring a change in voltage of the control terminal of the power switch in response to the provision of the defined current for a defined time, and recording the measured change in voltage; in a second test session, providing a defined current to the control terminal of the power switch, during the provision of the defined current, measuring a change in voltage of the control terminal of the power switch in response to the provision of the defined current for a defined time, and recording the measured change in voltage; and comparingmeasured change in voltage from the first test session with the measured change in voltage from the second test session.Example 3. The method of example 1 or 2, further comprising, in both the first test session and the second test session, establishing respective potentials across main terminals of the power switch prior to the provision of the defined currents.Example 4. The method of example 3, further comprising, in both the first test session and the second test session, monitoring for current flow between the main terminals of the power switch during the provision of the defined currents.Example 5. The method of example 4, wherein: monitoring for the current flow comprises measuring a threshold voltage of the power switch; and the method further comprises, in both the first test session and the second test session, recording the measured threshold voltages of the power switch.Example 6. The method of any one of examples 1 to 5, further comprising, in both the first test session and the second test session, adjusting a level of the defined current prior to the provision of the defined current.Example 7. The method of any one of examples 1 to 6, wherein the power switch is a silicon carbide field effect transistor.Example 8. The method of any one of examples 1 to 7, wherein, in both the first test session and the second test session, the time required for the voltage at the control terminal of the power switch to rise to the threshold voltage of the power switch is measured.Example 9. The method of example 8, wherein, in both the first test session and the second test session, the time required for a voltage at the control terminal of the power switch to rise from ground to the threshold voltage of the power switch is measured.Example 10. The method of any one of examples 1 to 9, further comprising, identifying degradation of the power switch based on the comparison of the measured times or the measured voltages.Example 11. A monitoring system configured to monitor charging of a control terminal of a power switch, the system comprising: a gate driver configured to be electrically coupled to the control terminal of the power switch, the gate driver configured to drive the control terminal with a defined current; control terminal monitoring circuitry configured to be electrically coupled to the control terminal of the power switch and to monitor a voltage thereof during driving by thegate driver with the defined current; and measurement circuitry coupled to the control terminal monitoring circuitry and configured to measure a time required for the gate driver to drive the control terminal of the power switch between voltage levels; and a processor that is configured to record the measured time.Example 12. A monitoring system configured to monitor charging of a control terminal of a power switch, the system comprising: a gate driver configured to be electrically coupled to the control terminal of the power switch, the gate driver configured to drive the control terminal with a defined current; control terminal monitoring circuitry configured to be electrically coupled to the control terminal of the power switch and to monitor a voltage thereof during driving by the gate driver with the defined current; and measurement circuitry coupled to the control terminal monitoring circuitry and configured to measure a change in voltage of the control terminal of the power switch in response to a the gate driver driving the control terminal for a predefined time; and a processor that is configured to record the measured change in voltage in a memory.Example 13. The monitoring system of example 11 or 12, wherein the gate driver comprises a constant current source.Example 14. The monitoring system of any one of examples 11 to 13, wherein the timer circuitry is configured to measure the time required for the gate driver to drive the control terminal of the power switch to a threshold voltage of the power switch.Example 15. The monitoring system of example 14, wherein the time is required for the gate driver to drive the control terminal of the power switch from a ground potential to the threshold voltage.Example 16. The monitoring system of any one of examples 11 to 15, further comprising: current sense circuitry configured to be coupled to sense an onset of current flow between main terminals of the power switch as the power switch switches into conduction in response to driving by the gate driver.Example 17. The monitoring system of any one of examples 11 to 26, further comprising: controller circuitry coupled to the gate driver and to the measurement circuitry, wherein the controller circuitry is configured to trigger the driving of the control terminal by the gate driver and measurement of time or measurement of voltage by the measurement circuitry.Example 18. The monitoring system of any one of examples 11 to 17, wherein the processor is configured to retrieve a plurality of measured times or a plurality of measured voltages from the memory.Example 19. The monitoring system of example 18, wherein the processor is configured to identify degradation of the power switch from the retrieved times or voltages.Example 20. The monitoring system of any one of examples 11 to 19, wherein the processor is further configured to record a threshold voltage of the power switch in the memory.Example 21. The monitoring system of any one of examples 11 to 20, further comprising: additional gate driver circuitry coupled to configured to be electrically coupled to the control terminal of the power switch and to drive the power switch during normal switching operations.Example 22. The monitoring system of any one of examples 11 to 21, further comprising: bias circuitry configured to be coupled to main terminals of the power switch and to establish a voltage across the main terminals prior to driving by the gate driver.Example 23. A system comprising: the monitoring system of any one of examples 11 to 22; and the power switch, wherein the power switch is a silicon carbide field effect transistor.

Claims

CLAIMSWhat is claimed is:

1. A method of monitoring a power switch, the method comprising: in a first test session, providing a defined current to a control terminal of the power switch, during the provision of the defined current, measuring a time required for a voltage at the control terminal of the power switch to change between voltage levels, and recording the measured time; in a second test session, providing a defined current to the control terminal of the power switch, during the provision of the defined current, measuring a time required for a voltage at the control terminal of the power switch to change between voltage levels, and recording the measured time; and comparing the measured time from the first test session with the measured time from the second test session.

2. A method of monitoring a power switch, the method comprising: in a first test session, providing a defined current to a control terminal of the power switch, during the provision of the defined current, measuring a change in voltage of the control terminal of the power switch in response to the provision of the defined current for a defined time, and recording the measured change in voltage; a in a second test session, providing a defined current to the control terminal of the power switch, during the provision of the defined current, measuring a change in voltage of the control terminal of the power switch in response to the provision of the defined current for a defined time, and recording the measured change in voltage; and comparing measured change in voltage from the first test session with the measured change in voltage from the second test session.

3. The method of claim 1 or 2, further comprising, in both the first test session and the second test session, establishing respective potentials across main terminals of the power switch prior to the provision of the defined currents.

4. The method of claim 3, further comprising, in both the first test session and the second test session, monitoring for current flow between the main terminals of the power switch during the provision of the defined currents.

5. The method of claim 4, wherein: monitoring for the current flow comprises measuring a threshold voltage of the power switch; and the method further comprises, in both the first test session and the second test session, recording the measured threshold voltages of the power switch.

6. The method of any one of claims 1 to 5, further comprising, in both the first test session and the second test session, adjusting a level of the defined current prior to the provision of the defined current.

7. The method of any one of claims 1 to 6, wherein the power switch is a silicon carbide field effect transistor.

8. The method of any one of claims 1 to 7, wherein, in both the first test session and the second test session, the time required for the voltage at the control terminal of the power switch to rise to the threshold voltage of the power switch is measured.

9. The method of claim 8, wherein, in both the first test session and the second test session, the time required for a voltage at the control terminal of the power switch to rise from ground to the threshold voltage of the power switch is measured.

10. The method of any one of claims 1 to 9, further comprising, identifying degradation of the power switch based on the comparison of the measured times or the measured voltages.

11. A monitoring system configured to monitor charging of a control terminal of a power switch, the system comprising: a gate driver configured to be electrically coupled to the control terminal of the power switch, the gate driver configured to drive the control terminal with a defined current;control terminal monitoring circuitry configured to be electrically coupled to the control terminal of the power switch and to monitor a voltage thereof during driving by the gate driver with the defined current; and measurement circuitry coupled to the control terminal monitoring circuitry and configured to measure a time required for the gate driver to drive the control terminal of the power switch between voltage levels; and a processor that is configured to record the measured time.

12. A monitoring system configured to monitor charging of a control terminal of a power switch, the system comprising: a gate driver configured to be electrically coupled to the control terminal of the power switch, the gate driver configured to drive the control terminal with a defined current; control terminal monitoring circuitry configured to be electrically coupled to the control terminal of the power switch and to monitor a voltage thereof during driving by the gate driver with the defined current; and measurement circuitry coupled to the control terminal monitoring circuitry and configured to measure a change in voltage of the control terminal of the power switch in response to a the gate driver driving the control terminal for a predefined time; and a processor that is configured to record the measured change in voltage in a memory.

13. The monitoring system of claim 11 or 12, wherein the gate driver comprises a constant current source.

14. The monitoring system of any one of claims 11 to 13, wherein the timer circuitry is configured to measure the time required for the gate driver to drive the control terminal of the power switch to a threshold voltage of the power switch.

15. The monitoring system of claim 14, wherein the time is required for the gate driver to drive the control terminal of the power switch from a ground potential to the threshold voltage.

16. The monitoring system of any one of claims 11 to 15, further comprising: current sense circuitry configured to be coupled to sense an onset of current flow between main terminals of the power switch as the power switch switches into conduction in response to driving by the gate driver.

17. The monitoring system of any one of claims 11 to 16, further comprising: controller circuitry coupled to the gate driver and to the measurement circuitry, wherein the controller circuitry is configured to trigger the driving of the control terminal by the gate driver and measurement of time or measurement of voltage by the measurement circuitry.

18. The monitoring system of any one of claims 11 to 17, wherein the processor is configured to retrieve a plurality of measured times or a plurality of measured voltages from the memory.

19. The monitoring system of claim 18, wherein the processor is configured to identify degradation of the power switch from the retrieved times or voltages.

20. The monitoring system of any one of claims 11 to 19, wherein the processor is further configured to record a threshold voltage of the power switch in the memory.

21. The monitoring system of any one of claims 11 to 20, further comprising: additional gate driver circuitry coupled to configured to be electrically coupled to the control terminal of the power switch and to drive the power switch during normal switching operations.

22. The monitoring system of any one of claims 11 to 21, further comprising: bias circuitry configured to be coupled to main terminals of the power switch and to establish a voltage across the main terminals prior to driving by the gate driver.

23. A system comprising: the monitoring system of any one of claims 11 to 22; and the power switch, wherein the power switch is a silicon carbide field effect transistor.

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