Semiconductor device

Abstract

The present invention provides a semiconductor device that is easily miniaturized. Provided is a semiconductor device with reduced parasitic capacitance. This semiconductor device has a first insulating layer, a second insulating layer, a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer. The first conductive layer is located on top of the second insulating layer and has a first opening that reaches the second insulating layer. The first insulating layer is located on top of the first conductive layer and has a second opening that overlaps the first opening. The second conductive layer is located on top of the first insulating layer. The semiconductor layer has: a portion in contact with the second conductive layer; a portion located inside the second opening, along the lateral surface of the first insulating layer; a portion inside the first opening, in contact with the lateral surface of the first conductive layer; and a portion at the bottom of the first opening, in contact with the top surface of the second insulating layer. The third insulating layer covers the semiconductor layer inside the first opening and inside the second opening. The third conductive layer covers the third insulating layer inside the first opening and inside the second opening.

Description

Semiconductor Devices

[0001] One embodiment of the present invention relates to a transistor, a semiconductor device, a memory device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] In recent years, the development of semiconductor devices has progressed, and CPUs, memories, and other large-scale integrated circuits (LSIs) are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) formed on chips by processing a semiconductor wafer, and on which electrodes serving as connection terminals are formed.

[0004] 2. Description of the Related Art A CPU, a memory, or other LSI semiconductor circuit (IC chip) is mounted on a circuit board, such as a printed wiring board, and is used as one of the components of various electronic devices.

[0005] Furthermore, a technique for constructing a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. Such transistors are widely applied to electronic devices such as integrated circuits and image display devices (also simply referred to as display devices). While silicon-based semiconductor materials are widely known as semiconductor thin films applicable to transistors, oxide semiconductors have also attracted attention as other materials.

[0006] Furthermore, it is known that a transistor including an oxide semiconductor has an extremely small leakage current in a non-conducting state. For example, Patent Document 1 discloses a low-power consumption CPU that utilizes the property of a small leakage current. Furthermore, Patent Document 2 discloses a memory device that can retain stored data for a long period of time.

[0007] In recent years, along with the trend toward smaller and lighter electronic devices, there has been an increasing demand for higher density integrated circuits. There is also a demand for improved productivity of semiconductor devices including integrated circuits. For example, Patent Document 3 discloses a technique for increasing the density of integrated circuits by stacking a first transistor using an oxide semiconductor film and a second transistor using an oxide semiconductor film to provide multiple memory cells in a superimposed manner. Patent Document 4 also discloses a vertical transistor in which a side surface of an oxide semiconductor is covered with a gate electrode via a gate insulator.

[0008] JP 2012-257187 A JP 2011-151383 A WO 2021 / 053473 JP 2013-211537 A

[0009] An object of one embodiment of the present invention is to provide a semiconductor device that can be easily miniaturized. Another object is to provide a semiconductor device that enables high integration. Another object is to provide a semiconductor device with reduced parasitic capacitance. Another object is to provide a semiconductor device with reduced wiring load. Another object is to provide a highly reliable semiconductor device. Another object is to provide a semiconductor device that exhibits favorable electrical characteristics. Another object is to provide a semiconductor device with high operating speed.

[0010] An object of one embodiment of the present invention is to provide a semiconductor device, a memory device, a display device, or an electronic device having a novel structure. An object of one embodiment of the present invention is to alleviate at least one of the problems of the prior art.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0012] One embodiment of the present invention is a semiconductor device including a transistor, a first insulating layer, and a second insulating layer. The transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and the third insulating layer. The first conductive layer has a portion located on the second insulating layer and has a first opening reaching the second insulating layer. The first insulating layer has a portion located on the first conductive layer and has a second opening overlapping the first opening. The second conductive layer has a portion located on the first insulating layer. The semiconductor layer has a portion in contact with the second conductive layer, a portion located along a side surface of the first insulating layer in the second opening, a portion in contact with a side surface of the first conductive layer in the first opening, and a portion in contact with an upper surface of the second insulating layer at the bottom of the first opening. A third insulating layer covers the semiconductor layer in the first opening and in the second opening, and a third conductive layer covers the third insulating layer in the first opening and in the second opening.

[0013] In the above, it is preferable that the semiconductor device further includes a fourth conductive layer. In this case, it is preferable that the second insulating layer is located on the fourth conductive layer, and the first conductive layer is in contact with the upper surface of the fourth conductive layer outside the end of the second insulating layer. In this case, it is preferable that the first conductive layer contains a metal oxide, and the fourth conductive layer contains a metal or an alloy. Furthermore, it is preferable that the second insulating layer includes a first insulating film in contact with the fourth conductive layer and a second insulating film thereon in contact with the semiconductor layer. In this case, it is preferable that the first insulating film contains one or more of silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, and hafnium oxide, and the second insulating film contains silicon oxide or silicon oxynitride.

[0014] In the above, it is preferable that the semiconductor device further includes a fifth conductive layer and a fourth insulating layer. The fourth insulating layer has a portion located on the third insulating layer and a third opening that overlaps with the first opening and reaches the third insulating layer. The fifth conductive layer has a portion located on the fourth insulating layer. The third conductive layer has a portion embedded in the third opening and has an upper surface in contact with the fifth conductive layer.

[0015] In the above, it is preferable that a fifth insulating layer be further provided. The fifth insulating layer is preferably provided along a side surface of the first insulating layer in the second opening and is preferably located between the first insulating layer and the semiconductor layer. In this case, it is preferable that the first insulating layer contains silicon oxide or silicon oxynitride. It is also preferable that the fifth insulating layer contains one or more of silicon nitride, aluminum oxide, silicon oxide, and hafnium oxide.

[0016] In the above, the semiconductor layer preferably has a cylindrical shape in the first opening and the second opening. The third insulating layer preferably has a portion in contact with the top surface of the second insulating layer at the bottom of the first opening. In this case, the semiconductor layer preferably contacts the side surface of the second conductive layer but does not contact the top surface of the second conductive layer.

[0017] According to one embodiment of the present invention, a semiconductor device that can be easily miniaturized can be provided. Alternatively, a semiconductor device that enables high integration can be provided. Alternatively, a semiconductor device with reduced parasitic capacitance can be provided. Alternatively, a semiconductor device with reduced wiring load can be provided. Alternatively, a highly reliable semiconductor device can be provided. Alternatively, a semiconductor device that exhibits favorable electrical characteristics can be provided. Alternatively, a semiconductor device with high operating speed can be provided.

[0018] According to one aspect of the present invention, it is possible to provide a semiconductor device, a memory device, a display device, or an electronic device having a novel configuration. According to one aspect of the present invention, it is possible to at least alleviate at least one of the problems of the prior art.

[0019] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0020] FIGS. 1A and 1B are structural examples of a semiconductor device. FIGS. 2A and 2B are structural examples of a semiconductor device. FIGS. 3A and 3B are structural examples of a semiconductor device. FIGS. 4A to 4D are structural examples of a semiconductor device. FIGS. 5A and 5B are structural examples of a semiconductor device. FIGS. 6A and 6B are structural examples of a semiconductor device. FIGS. 7A to 7E are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 8A to 8C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 9A to 9C are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 10A and 10B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 11A and 11B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 12A and 12B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 13A and 13B are diagrams illustrating a method for manufacturing a semiconductor device. FIGS. 14A to 14C are structural examples of a memory device. FIGS. 15A to 15C are structural examples of a memory device. FIGS. 16A and 16B are configuration examples of a storage device. FIGS. 17A and 17B are configuration examples of a storage device. FIGS. 18A and 18B are configuration examples of a storage device. FIG. 19 is a configuration example of a storage device. FIGS. 20A to 20D are diagrams illustrating a method for forming a metal oxide film. FIGS. 21A to 21D are diagrams illustrating a method for forming a metal oxide film. FIG. 22 is a configuration example of a storage device. FIGS. 23A and 23B are configuration examples of a storage device. FIGS. 24A to 24D are configuration examples of a storage device. FIG. 25 is a configuration example of a storage device. FIGS. 26A and 26B are configuration examples of a display device. FIG. 27 is a configuration example of a display device. FIG. 28 is a configuration example of a display device. FIG. 29 is a configuration example of a display device. FIGS. 30A to 30C are configuration examples of a display device. FIGS. 31A and 31B are configuration examples of a display device. FIGS. 32A to 32D are configuration examples of electronic devices. Fig. 33A to Fig. 33F are configuration examples of electronic equipment. Fig. 34A to Fig. 34G are configuration examples of electronic equipment. Fig. 35A and Fig. 35B are configuration examples of electronic components. Fig. 36A to Fig. 36C are configuration examples of mainframe computers. Fig. 37A is a configuration example of space equipment. Fig. 37B is a configuration example of a storage system.

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used and no particular reference numeral may be assigned.

[0023] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0024] In this specification, ordinal numbers such as "first" and "second" are used to avoid confusion of components and do not limit the number.

[0025] A transistor is a type of semiconductor element that can perform functions such as amplifying current or voltage and performing switching operations to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0026] Furthermore, the functions of "source" and "drain" may be interchangeable when transistors of different polarities are used, or when the direction of current flow changes during circuit operation, etc. For this reason, the terms "source" and "drain" may be used interchangeably in this specification.

[0027] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes or wiring, as well as switching elements such as transistors, resistive elements, coils, and other elements with various functions.

[0028] In this specification, when two nodes are connected via an insulator such as a dielectric of a capacitive element, a gate insulating film of a transistor, or an interlayer insulating film, this is not considered to be an "electrical connection."

[0029] In this specification, the phrase "top surface shapes generally match" refers to the overlap of at least a portion of the contours between stacked layers. For example, this includes cases where the upper and lower layers are processed using the same mask pattern or a portion of the same mask pattern. However, strictly speaking, the contours may not overlap, and the upper layer may be located inside the lower layer, or outside the lower layer. In these cases, the phrase "top surface shapes generally match" may also be used.

[0030] In this specification, the top surface shape of a certain component refers to the contour shape of the component in a plan view. The plan view refers to a view from the normal direction of the surface on which the component is formed or the surface of a support (e.g., a substrate) on which the component is formed.

[0031] In the following description, expressions indicating directions such as "upper" and "lower" are basically used in accordance with the directions in the drawings. However, for ease of explanation, the directions indicated by "upper" or "lower" in the specification may not match those in the drawings. For example, when explaining the stacking order (or formation order) of a laminate, etc., even if the surface on which the laminate is provided (such as a forming surface, a supporting surface, an adhesive surface, or a flat surface) is located above the laminate in the drawings, the forming surface side may be expressed as "lower" and the laminate side as "upper."

[0032] In this specification, the channel length direction of a transistor refers to one of the directions parallel to the line connecting the source region and the drain region at the shortest distance. In other words, the channel length direction corresponds to one of the directions of current flowing through the semiconductor layer when the transistor is in an on-state. The channel width direction refers to a direction perpendicular to the channel length direction. Depending on the structure or shape of the transistor, the channel length direction and the channel width direction may not be defined as a single direction.

[0033] In addition, in this specification and the like, the terms "film" and "layer" are interchangeable. For example, the term "insulating layer" may be interchangeable with the term "insulating film."

[0034] Embodiment 1 In this embodiment, a structure example of a semiconductor device according to one embodiment of the present invention and an example of a manufacturing method thereof will be described. Hereinafter, a transistor will be described as an example of a semiconductor device.

[0035] In a transistor according to one embodiment of the present invention, a source electrode and a drain electrode are located at different heights, and a current flows in a semiconductor layer in the height direction. That is, the channel length direction can be said to have a component in the height direction (vertical direction). Therefore, one embodiment of the present invention can be called a VFET (Vertical Field Effect Transistor), a vertical transistor, a vertical channel transistor, a vertical channel transistor, or the like.

[0036] More specifically, a first insulating layer is provided to cover a lower electrode, which is one of a source electrode and a drain electrode of a transistor, and to function as a first spacer. An upper electrode, which is the other of the source electrode and drain electrode, is provided on the first insulating layer. A semiconductor layer is provided inside an opening provided in the first insulating layer, in contact with the lower electrode and in which a channel is formed along a side surface of the first insulating layer. Furthermore, a gate insulating layer is provided inside the opening in the first insulating layer along the semiconductor layer, and a gate electrode is provided so as to overlap with the semiconductor layer via the gate insulating layer.

[0037] A portion of the lower electrode is located on the second insulating layer and has an opening that reaches the second insulating layer. The opening in the first insulating layer overlaps with the opening in the lower electrode. The semiconductor layer contacts the side surface of the lower electrode inside the opening in the lower electrode. The semiconductor layer also contacts the second insulating layer at the bottom of the opening in the lower electrode. In this way, by providing an opening in the lower electrode at the bottom of the opening in the first insulating layer, the overlapping area between the gate electrode and the lower electrode can be reduced, and the parasitic capacitance between them can be reduced. This makes it possible to realize a transistor that can be driven at high speed.

[0038] Furthermore, an opening may also be provided in the semiconductor layer at the bottom of the opening in the lower electrode. In other words, the semiconductor layer may have a cylindrical shape provided along each sidewall of the opening in the first insulating layer and the opening in the lower electrode. With this configuration, the parasitic capacitance between the gate electrode and the semiconductor layer can be reduced, thereby realizing a transistor that can be driven at higher speed.

[0039] Furthermore, it is preferable that an insulating layer functioning as a second spacer is provided between the upper electrode and a gate wiring connected to the gate electrode. In this case, it is preferable that the gate electrode is provided so as to be embedded in the second spacer, and its upper surface is in contact with the gate wiring. This reduces the parasitic capacitance between the gate wiring and the upper electrode, thereby realizing a transistor that can be driven at even higher speeds.

[0040] An oxide semiconductor is preferably used for the semiconductor layer. For example, silicon, which is a typical semiconductor material, needs to be doped with impurities that function as donors or acceptors to form source and drain regions. However, in the vertical transistor of one embodiment of the present invention, it may be difficult to dope impurities into the semiconductor layer with high precision because the source and drain regions are different in height and the channel formation region is located vertically relative to the substrate surface. On the other hand, an oxide semiconductor can form a low-resistance region without doping with such impurities and can provide good connection with the source and drain electrodes. Therefore, a transistor having a three-dimensional structure as in one embodiment of the present invention can be manufactured with high yield.

[0041] The transistor of one embodiment of the present invention can have an extremely short channel length, a reduced occupation area, a large current, a small parasitic capacitance, and can operate at high speed. The transistor of one embodiment of the present invention can be applied to various semiconductor devices, such as memory devices, computing devices, display devices, and imaging devices.

[0042] A more specific example will be described below with reference to the drawings.

[0043] [Configuration Example 1] Figures 1A and 1B each show a perspective view of a transistor 10. In each figure, arrows indicate the X, Y, and Z directions. Figure 1B is a perspective view with a portion cut away from Figure 1A. Note that in Figures 1A and 1B, only the outlines of insulating layers 41 and 42, which function as interlayer insulating layers, are shown by dashed lines.

[0044] 2A and 2B show cross-sectional views of the transistor 10. Fig. 2A shows a cross section cut along a plane perpendicular to the X direction, and Fig. 2B shows a cross section cut along a plane perpendicular to the Y direction.

[0045] The transistor 10 is provided on an insulating layer 11 provided on a substrate (not shown). The insulating layer 11 functions as a base insulating layer. The transistor 10 includes a semiconductor layer 21, an insulating layer 22 functioning as a gate insulating layer, a conductive layer 23 functioning as a gate electrode, a conductive layer 24 functioning as one of a source electrode and a drain electrode, and a conductive layer 25 functioning as the other. In FIGS. 2A and 2B , the conductive layer 23 includes a conductive layer 23a and a conductive layer 23b, the conductive layer 24 includes a conductive layer 24a and a conductive layer 24b, and the conductive layer 25 includes a conductive layer 25a and a conductive layer 25b.

[0046] Furthermore, the conductive layer 23 is connected to the conductive layer 31 which functions as a gate wiring. Furthermore, the conductive layers 24 and 25 each function as wiring. Here, an example is shown in which the conductive layers 31 and 24 extend in the X direction, and the conductive layer 25 extends in the Y direction. However, the extension direction of each conductive layer is not limited to this, and the conductive layers may extend in a direction other than the X direction or the Y direction.

[0047] An insulating layer 45 is provided on the insulating layer 11. The insulating layer 45 functions as a protective insulating layer and has a function of preventing impurities such as hydrogen from diffusing from the insulating layer 11 side into the semiconductor layer 21. For example, a film in which hydrogen is less likely to diffuse than in a silicon oxide film (having barrier properties against hydrogen), such as a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, or a gallium oxide film, can be used. Note that the insulating layer 45 does not have to be provided if it is not necessary.

[0048] A conductive layer 24a is provided on an insulating layer 45, an insulating layer 40 having an island shape is provided on the conductive layer 24a, and a conductive layer 24b is provided covering the conductive layer 24a and the insulating layer 40. An insulating layer 41 is provided on the conductive layer 24b and the insulating layer 45, and a conductive layer 25 is provided on the insulating layer 41. The insulating layer 41 has an opening 20a. The conductive layer 24b has an opening 20b that reaches the insulating layer 40 at a position overlapping with the opening 20a. In this example, the conductive layer 25 also has an opening at a position overlapping with the opening 20a.

[0049] Semiconductor layer 21 has a portion in contact with the upper surface of conductive layer 25, a portion in contact with the side surface of conductive layer 25, a portion in contact with the side surface (inner wall, side wall) of insulating layer 41 in opening 20a, a portion in contact with the side surface of conductive layer 24b in opening 20b, and a portion in contact with the upper surface of insulating layer 40 at the bottom of opening 20b. It can also be said that semiconductor layer 21 has portions provided along the side walls of opening 20a and opening 20b.

[0050] In the transistor 10, the source electrode and the drain electrode are located at different heights, and therefore, a current flows in the height direction through the semiconductor. That is, it can be said that the channel length direction has a component in the height direction (vertical direction). Therefore, the transistor of one embodiment of the present invention can also be called a VFET, a vertical transistor, a vertical channel transistor, or the like. Since the transistor 10 can have two or more of the source electrode, the semiconductor, and the drain electrode stacked, the occupied area can be significantly reduced compared to a so-called planar transistor (which can also be called a lateral transistor, LFET (lateral FET), or the like) in which the semiconductor is arranged on a plane.

[0051] Furthermore, the channel length of the transistor 10 can be precisely controlled by the thickness of the insulating layer 41, which functions as a spacer. This significantly reduces the variation in channel length compared to planar transistors. Furthermore, by thinning the insulating layer 41, transistors with extremely short channel lengths can be fabricated. For example, transistors with channel lengths of 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 200 nm or less, 100 nm or less, 50 nm or less, 30 nm or less, or 20 nm or less, and 5 nm or more, 7 nm or more, or 10 nm or more, can be fabricated. Therefore, transistors with extremely short channel lengths that could not be achieved using mass-production exposure equipment can be realized. Furthermore, transistors with channel lengths of less than 10 nm can be fabricated without using the extremely expensive exposure equipment used in cutting-edge LSI technology.

[0052] Although various semiconductor materials can be used for the semiconductor layer 21, it is particularly preferable to use an oxide semiconductor containing a metal oxide. By using an oxide semiconductor formed under appropriate conditions, a transistor having both a high on-state current and an extremely low off-state current can be realized at low cost. Unless otherwise specified, the following describes a preferred configuration example in which an oxide semiconductor is used for the semiconductor layer 21.

[0053] Here, the conductive layer 24 and the conductive layer 25 each have a stacked structure. The conductive layer 24b and the conductive layer 25b are configured to be in contact with the semiconductor layer 21. Therefore, if an oxide semiconductor is used for the semiconductor layer 21, the surfaces of the conductive layer 24b and the conductive layer 25b may be oxidized due to the influence of heat applied during or after the film formation process of the semiconductor film that becomes the semiconductor layer 21, forming an insulating oxide film between the conductive layer 24b and the semiconductor layer 21, which may increase the contact resistance. Therefore, it is preferable to use an oxide conductor containing a conductive oxide for the conductive layer 24b and the conductive layer 25b. This can prevent an increase in contact resistance due to oxidation of the surfaces of the conductive layer 24b and the conductive layer 25b. The conductive layer 24b and the conductive layer 25b may also be called an oxide layer, a metal oxide layer, an oxide conductor layer, or the like.

[0054] The conductive layer 24 can be used as one of the source wiring and the drain wiring. The conductive layer 25 can be used as the other of the source wiring and the drain wiring. Therefore, it is preferable that the conductive layer 24a and the conductive layer 25a have low electrical resistance. It is preferable to use a material having higher conductivity than an oxide conductor, such as a metal, an alloy, or a nitride thereof, for the conductive layer 24a and the conductive layer 25a. As described above, it is preferable that the conductive layer 24 has a stacked structure of a low-resistance conductive layer 24a and a conductive layer 24b containing a metal oxide, and that the conductive layer 25 has a stacked structure of a low-resistance conductive layer 25a and a conductive layer 25b containing a metal oxide.

[0055] The insulating layer 40 is provided in a region overlapping with the opening 20a and the opening 20b. The upper surface of the insulating layer 40 corresponds to the bottom of the opening 20b. By providing the insulating layer 40 between the conductive layer 23 and the conductive layer 24a, the parasitic capacitance therebetween can be reduced. This enables the transistor 10 to be driven at high speed. For example, when the transistor 10 is applied to a memory device, high speeds can be achieved for write and read operations. Furthermore, when the transistor 10 is applied to a display device, effects such as high speed frame frequency and high resolution can be achieved.

[0056] Here, an example is shown in which the insulating layer 40 has a two-layer structure of insulating layers 40a and 40b. The insulating layer 40b has a portion in contact with the semiconductor layer 21. The insulating layer 40b is preferably an oxide insulating film that releases oxygen when heated. For example, an oxide insulating film such as silicon oxide or silicon oxynitride is preferably used. This allows oxygen to be supplied from the insulating layer 40b to the semiconductor layer 21 by heat or the like applied during the process, reducing oxygen vacancies in the semiconductor layer 21 and providing a highly reliable transistor 10. On the other hand, if the insulating layer 40b releases oxygen when heated, contact between the insulating layer 40b and the conductive layer 24a may oxidize a portion of the conductive layer 24a and reduce its conductivity. Therefore, it is preferable to provide the insulating layer 40a, which is less susceptible to oxygen diffusion than the insulating layer 40b, between the insulating layer 40b and the conductive layer 24a, so that the insulating layer 40b and the conductive layer 24a are not in contact with each other. The insulating layer 40a may be made of an insulating material that diffuses oxygen less easily than silicon oxide, such as silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium aluminate, or hafnium silicate.

[0057] In this specification and the like, an oxynitride refers to a material containing more oxygen than nitrogen, and a nitride oxide refers to a material containing more nitrogen than oxygen.

[0058] The insulating layer 22 is provided to cover the insulating layer 41, the conductive layer 25, the semiconductor layer 21, the conductive layer 24b, and the insulating layer 40. The portions of the insulating layer 22 located inside the openings 20a and 20b are provided along the surface of the semiconductor layer 21 (the surface on the conductive layer 23 side).

[0059] An insulating layer 42 is provided on the insulating layer 22. The insulating layer 42 functions as an interlayer insulating layer. The insulating layer 42 has an opening 20c that overlaps with the opening 20a.

[0060] The conductive layer 23 is provided so as to fill the openings 20a and 20c. The conductive layer 23 is also provided so as to cover the insulating layer 22 within the openings 20a and 20c. Here, the upper surface of the conductive layer 23 is flattened so that the height of the upper surface is approximately the same as the upper surface of the insulating layer 42. The conductive layer 31 is also provided on the insulating layer 42, and the conductive layer 31 is in contact with the upper surface of the conductive layer 23. The conductive layer 31 functions as a gate wiring.

[0061] By providing an insulating layer 42, which functions as an interlayer insulating layer, between the conductive layer 31, which functions as a gate wiring, and the conductive layer 25 and the semiconductor layer 21 on the conductive layer 25, it is possible to reduce the parasitic capacitance therebetween. This makes it possible to realize a transistor 10 that can be driven at even higher speeds. Furthermore, by providing the insulating layer 42, it is possible to significantly reduce the parasitic capacitance between the conductive layer 24 and the conductive layer 31. Therefore, it is possible to extend the conductive layer 24 and the conductive layer 31 in the same direction, thereby increasing the degree of freedom in circuit design.

[0062] Here, an example is shown in which the conductive layer 23 has a stacked structure of conductive layers 23a and 23b. Since the conductive layer 23 is in contact with the insulating layer 22, the insulating layer 42, and the like, if an insulating film that diffuses oxygen, such as silicon oxide, is used for these layers, the conductive layer 23 may be oxidized due to the influence of heat during processing, resulting in a decrease in conductivity. Therefore, the conductive layer 23a in contact with the insulating layer 22 and the insulating layer 42 is preferably made of a conductive material that is less susceptible to oxidation than the conductive layer 23b. For example, a metal nitride film such as tantalum nitride or titanium nitride is preferably used for the conductive layer 23a. On the other hand, the conductive layer 23b can be made of a conductive material containing a low-resistance metal or alloy. This can improve the reliability of the transistor 10.

[0063] The insulating layer 41 functions as an interlayer insulating layer (spacer) that insulates the conductive layer 24 from the conductive layer 25. Here, the insulating layer 41 is shown to be a stacked film of insulating layers 41a, 41b, and 41c.

[0064] The semiconductor layer 21 is provided in contact with the inner wall of the opening 20a of the insulating layer 41b. It is preferable to use an oxide insulating film for the insulating layer 41b. In particular, it is preferable to use an oxide insulating film that releases oxygen when heated. It is also preferable to have a structure in which the insulating layer 41b is sandwiched between insulating layers 41a and 41c that have a barrier property against oxygen. This makes it possible to confine oxygen contained in the insulating layer 41b in a region surrounded by the insulating layers 41a, 41c, and the semiconductor layer 21. Furthermore, it is possible to prevent oxygen from being released and reduced in the insulating layer 41b during the process. This allows oxygen to be supplied to the semiconductor layer 21 more efficiently.

[0065] The portion of the semiconductor layer 21 that is in contact with the insulating layer 41b is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion that is not in contact with the insulating layer 41b is preferably an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 that is in contact with the insulating layer 41b can be called a channel formation region, and the region outside that can be called a low-resistance region (also called a source region or a drain region).

[0066] The insulating layer 41b is preferably a film containing as little hydrogen as possible because it is in contact with the semiconductor layer 21. Carriers are generated when oxygen vacancies in the semiconductor layer 21 combine with hydrogen, which may affect the threshold voltage of the transistor 10, for example. Therefore, an insulating film other than an oxide insulating film through which hydrogen is less likely to diffuse may be used as the insulating layer 41b. For example, a single layer of an insulating film having a barrier property against hydrogen and oxygen may be used as the insulating layer 41.

[0067] Because the semiconductor layer 21 and the insulating layer 22 are formed along the inner wall of the opening 20a in the insulating layer 41b, the thickness of this portion may be thin depending on the film formation method. For example, with film formation methods such as sputtering or plasma CVD, films formed on surfaces inclined or perpendicular to the substrate surface tend to be thinner than films formed on surfaces parallel to the substrate surface. On the other hand, with film formation methods such as atomic layer deposition (ALD) or thermal CVD, films of uniform thickness can be formed regardless of the angle of the surface on which they are formed. For example, when the angle of the sidewall of the opening 20a in the insulating layer 41b is 75 degrees or more, 80 degrees or more, or 85 degrees or more, it is preferable to form the semiconductor layer 21 and the insulating layer 22 using the ALD method.

[0068] [Regarding Components] <Substrate> The substrate on which a transistor is formed may be, for example, an insulating substrate, a semiconductor substrate, or a conductive substrate. Examples of insulating substrates include glass substrates, quartz substrates, sapphire substrates, stabilized zirconia substrates (e.g., yttria-stabilized zirconia substrates), and resin substrates. Examples of semiconductor substrates include semiconductor substrates made of silicon or germanium, or compound semiconductor substrates made of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, and gallium nitride. Examples of semiconductor substrates include those having an insulating region within the aforementioned semiconductor substrate, such as an SOI (Silicon-On-Insulator) substrate. Examples of conductive substrates include graphite substrates, metal substrates, alloy substrates, and conductive resin substrates. Alternatively, substrates containing metal nitrides or metal oxides may also be used. Further, there are substrates in which a conductive layer or a semiconductor layer is provided on an insulating substrate, substrates in which a conductive layer or an insulating layer is provided on a semiconductor substrate, and substrates in which a semiconductor layer or an insulating layer is provided on a conductive substrate. Alternatively, any of these substrates may be provided with elements. The elements provided on the substrate include capacitor elements, resistor elements, switch elements (including transistors), light-emitting elements, memory elements, and the like.

[0069] <Semiconductor Layer> The semiconductor layer 21 preferably contains a metal oxide (oxide semiconductor).

[0070] Examples of metal oxides that can be used for the semiconductor layer 21 include In oxide, Ga oxide, and Zn oxide. The metal oxide preferably contains at least In or Zn. The metal oxide preferably contains two or three elements selected from In, element M, and Zn. The element M is a metal element or semimetal element with a high bond energy with oxygen, such as a metal element or semimetal element with a bond energy with oxygen higher than that of indium. Specific examples of the element M include Al, Ga, Sn, Y, Ti, V, Cr, Mn, Fe, Co, Ni, Zr, Mo, Hf, Ta, W, La, Ce, Nd, Mg, Ca, Sr, Ba, B, Si, Ge, and Sb. The element M contained in the metal oxide is preferably one or more of the above elements, and is particularly preferably one or more selected from Al, Ga, Y, and Sn, with Ga being more preferred. Hereinafter, a metal oxide having In, M, and Zn may be referred to as an In-M-Zn oxide. In this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal elements" described in this specification and the like may include metalloid elements.

[0071] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. For example, the atomic ratios of metal elements in such an In-M-Zn oxide may be In:M:Zn = 1:1:1, In:M:Zn = 1:1:1.2, In:M:Zn = 2:1:3, In:M:Zn = 3:1:2, In:M:Zn = 4:2:3, In:M:Zn = 4:2:4.1, In:M:Zn = 5:1:3, In:M:Zn = 5:1:6, In:M:Zn = 5:1:7, In:M:Zn = 5:1:8, In:M:Zn = 6:1:6, In:M:Zn = 5:2:5, or compositions in the vicinity thereof. Note that the term "composition in the vicinity" refers to a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of a transistor can be increased.

[0072] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. For example, the atomic ratio of metal elements in such an In-M-Zn oxide may be In:M:Zn=1:3:2, In:M:Zn=1:3:3, In:M:Zn=1:3:4, or a composition close to these. By increasing the atomic ratio of M in the metal oxide, the generation of oxygen vacancies can be suppressed.

[0073] The semiconductor layer 21 can be made of, for example, In oxide, In—Zn oxide, In—Ga oxide, In—Sn oxide, In—Ti oxide, In—Ga—Al oxide, In—Ga—Sn oxide, In—Ga—Zn oxide, In—Sn—Zn oxide, In—Al—Zn oxide, In—Ti—Zn oxide, In—Ga—Sn—Zn oxide, In—Ga—Al—Zn oxide, or the like. Ga—Zn oxide may also be used. A material that does not contain Zn, such as indium oxide, is preferred because it enhances compatibility with the LSI manufacturing process. On the other hand, a material that contains Zn is preferred because it facilitates high crystallinity.

[0074] Note that the metal oxide may contain one or more metal elements with higher period numbers in the periodic table instead of or in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element with a higher period number may improve the field-effect mobility of a transistor. Examples of metal elements with higher period numbers include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include Y, Zr, Ag, Cd, Sn, Sb, Ba, Pb, Bi, La, Ce, Pr, Nd, Pm, Sm, and Eu. Note that La, Ce, Pr, Nd, Pm, Sm, and Eu are called light rare earth elements.

[0075] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0076] The metal oxide can be preferably formed by sputtering or atomic layer deposition (ALD). In particular, it is preferable to form the metal oxide film by the ALD method, which has excellent coating properties. When forming the metal oxide by the sputtering method, the composition of the metal oxide film may differ from that of the target. In particular, the zinc content in the metal oxide film may decrease to about 50% of that of the target.

[0077] In this specification, the content of a metal element in a metal oxide refers to the ratio of the number of atoms of that element to the total number of atoms of the metal element contained in the metal oxide. For example, if a metal oxide contains metal elements X, Y, and Z, and the number of atoms of each of metal elements X, Y, and Z contained in the metal oxide is A, then Ｘ , A Ｙ , A Ｚ When the content of the metal element X is Ｘ / (A Ｘ +A Ｙ +A Ｚ ) In addition, the ratio of the number of atoms of the metal element X, the metal element Y, and the metal element Z in the metal oxide (atomic number ratio) can be expressed as follows: Ｘ : B Ｙ : B Ｚ When the content of the metal element X is expressed as B Ｘ / (B Ｘ +B Ｙ +B Ｚ ) can be shown as

[0078] For example, in the case of a metal oxide containing In, a transistor with a large on-current can be realized by increasing the In content.

[0079] By using a metal oxide that does not contain Ga or has a low Ga content in the semiconductor layer 21, a transistor with high reliability against positive bias application can be obtained. That is, a transistor with a small amount of threshold voltage fluctuation in a PBTS (Positive Bias Temperature Stress) test can be obtained. Furthermore, when using a metal oxide that contains Ga, it is preferable to make the Ga content lower than the In content. This makes it possible to realize a transistor with high mobility and high reliability.

[0080] On the other hand, by increasing the Ga content, a transistor with high reliability against light can be obtained. That is, a transistor with a small amount of variation in threshold voltage in a Negative Bias Temperature Illumination Stress (NBTIS) test can be obtained. Specifically, a metal oxide in which the atomic ratio of Ga is equal to or greater than the atomic ratio of In has a larger band gap, and the amount of variation in threshold voltage of the transistor in the NBTIS test can be reduced.

[0081] Furthermore, by increasing the zinc content, the metal oxide becomes highly crystalline, which can suppress the diffusion of impurities in the metal oxide, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0082] The semiconductor layer 21 may have a stacked structure including two or more metal oxide layers. The two or more metal oxide layers included in the semiconductor layer 21 may have the same or substantially the same composition. By using a stacked structure of metal oxide layers with the same composition, for example, the same sputtering target can be used for formation, thereby reducing manufacturing costs. Note that a stacked structure in which two or more oxide semiconductor layers with different compositions are stacked may also be used. Furthermore, by using the ALD method, it is also possible to form a metal oxide layer whose composition continuously varies in the thickness direction. This not only broadens the range of design options compared to when a film with a fixed composition is used, but also makes it possible to prevent the generation of interface states and the like between two layers with different compositions, thereby improving electrical characteristics and reliability.

[0083] When the semiconductor layer 21 has a two-layer structure, it is preferable to use a material with higher mobility (higher conductivity) in the second layer, i.e., the side closer to the gate electrode, than in the first layer. This allows for a transistor that is normally off and has a large on-current. This makes it possible to achieve both low power consumption and high performance. Alternatively, a material with higher mobility than in the second layer may be used in the first layer, i.e., the side in contact with the source electrode and drain electrode. This reduces the contact resistance between the semiconductor layer 21 and the source electrode or drain electrode, thereby reducing parasitic resistance and enabling a transistor with a large on-current.

[0084] Furthermore, when the semiconductor layer 21 has a three-layer structure, it is preferable to use a material for the second layer that has a higher mobility than the first and third layers, thereby realizing a transistor with a high on-current and high reliability.

[0085] The difference in the mobility and conductivity described above can be expressed, for example, by the indium content. In addition, whether or not an element other than indium that contributes to improving conductivity is contained, or the content of that element, also affects the mobility and conductivity. Examples of high-mobility materials include In:Ga:Zn=4:3:2 [atomic ratio] and materials in the vicinity thereof, In:Zn=1:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=2:1 [atomic ratio] and materials in the vicinity thereof, In:Zn=4:1 [atomic ratio] and materials in the vicinity thereof, and In:Sn:Zn=40:X:10 [atomic ratio] (X is 0.1 or more and 5 or less, typically X=1) and materials in the vicinity thereof. On the other hand, examples of materials having lower mobility or conductivity than the above-mentioned materials include In:Ga:Zn=1:3:2 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:3:4 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=2:2:1 [atomic ratio] and materials in the vicinity thereof, In:Ga:Zn=1:1:1 [atomic ratio] and materials in the vicinity thereof, and In:Ga:Zn=1:1:2 [atomic ratio] and materials in the vicinity thereof.

[0086] It is preferable to use a crystalline metal oxide layer for the semiconductor layer 21. For example, a metal oxide layer having a c-axis aligned crystal (CAAC) structure, a polycrystalline structure, a nanocrystalline (nc) structure, or the like can be used. By using a crystalline metal oxide layer for the semiconductor layer 21, the defect level density in the semiconductor layer 21 can be reduced, and a highly reliable semiconductor device can be realized.

[0087] The higher the crystallinity of the metal oxide layer used in the semiconductor layer 21, the more the density of defect states in the semiconductor layer 21 can be reduced. On the other hand, by using a metal oxide layer with low crystallinity, a transistor capable of passing a large current can be realized.

[0088] A transistor using an oxide semiconductor (hereinafter referred to as an OS transistor) has significantly higher field-effect mobility than a transistor using amorphous silicon. Furthermore, an OS transistor has significantly lower source-drain leakage current in an off state (hereinafter also referred to as an off-state current) and can hold charge accumulated in a capacitor connected in series with the transistor for a long period of time. Furthermore, the use of an OS transistor can reduce the power consumption of a semiconductor device.

[0089] The semiconductor device according to one embodiment of the present invention can be applied to, for example, a processor, a memory device, or various ICs. The transistor according to one embodiment of the present invention is capable of passing a large current and has an extremely low off-state current, and therefore, high-speed operation of a circuit and low power consumption can be achieved at the same time.

[0090] A semiconductor device according to one embodiment of the present invention can be applied to, for example, a display device. To increase the emission luminance of a light-emitting device included in a pixel circuit of a display device, it is necessary to increase the amount of current flowing through the light-emitting device. To achieve this, it is necessary to increase the source-drain voltage of a driving transistor included in the pixel circuit. Because an OS transistor has a higher source-drain breakdown voltage than a transistor using silicon (hereinafter referred to as a Si transistor), a high voltage can be applied between the source and drain of the OS transistor. Therefore, by using an OS transistor as the driving transistor included in the pixel circuit, it is possible to increase the amount of current flowing through the light-emitting device and increase the emission luminance of the light-emitting device.

[0091] When a transistor operates in the saturation region, an OS transistor can reduce the change in source-drain current with respect to a change in gate-source voltage compared to a Si transistor. Therefore, by using an OS transistor as a driving transistor included in a pixel circuit, the amount of current flowing through the light-emitting device can be precisely controlled. This allows for a larger number of gray levels in the pixel circuit. Furthermore, even if the electrical characteristics (e.g., resistance) of the light-emitting device fluctuate or vary, a stable current can flow.

[0092] As described above, by using an OS transistor for a driving transistor included in a pixel circuit, it is possible to achieve "suppression of black floating," "increase in light emission luminance," "multiple gradations," "suppression of the influence of manufacturing variations in light-emitting devices," and the like.

[0093] OS transistors exhibit little change in electrical characteristics due to radiation exposure, i.e., have high radiation resistance, and therefore can be suitably used in environments where radiation may be incident. It can also be said that OS transistors have high reliability against radiation. For example, OS transistors can be suitably used in pixel circuits of X-ray flat panel detectors. Furthermore, OS transistors can be suitably used in semiconductor devices used in outer space. Examples of radiation include electromagnetic radiation (e.g., X-rays and gamma rays) and particle radiation (e.g., alpha rays, beta rays, proton rays, and neutron rays).

[0094] The semiconductor material that can be used for the semiconductor layer 21 is not limited to oxide semiconductors. For example, semiconductors made of simple elements or compound semiconductors can be used. Examples of semiconductors made of simple elements include silicon (including single crystal silicon, polycrystalline silicon, microcrystalline silicon, and amorphous silicon) and germanium. Examples of compound semiconductors include gallium arsenide and silicon germanium. Examples of compound semiconductors include organic semiconductors, nitride semiconductors, and oxide semiconductors. These semiconductor materials may contain impurities as dopants.

[0095] Alternatively, the semiconductor layer 21 may have a layered material that functions as a semiconductor. A layered material is a general term for a group of materials that have a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent or ionic bonds are stacked via bonds weaker than covalent or ionic bonds, such as van der Waals bonds. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-current can be provided.

[0096] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0097] The crystallinity of the semiconductor material used for the semiconductor layer 21 is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a polycrystalline semiconductor, a microcrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. Use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0098] <Gate Insulating Layer> The insulating layer 22 functions as a gate insulating layer of a transistor. When an oxide semiconductor is used for the semiconductor layer 21, it is preferable to use an oxide insulating film for at least the film of the insulating layer 22 that is in contact with the semiconductor layer 21. For example, one or more of silicon oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, hafnium oxide, hafnium oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, and Ga—Zn oxide can be used. Alternatively, a nitride insulating film such as silicon nitride, silicon nitride oxide, aluminum nitride, or aluminum nitride oxide can also be used for the insulating layer 22. Furthermore, the insulating layer 22 may have a stacked structure, for example, a stacked structure including one or more oxide insulating films and one or more nitride insulating films.

[0099] Furthermore, the insulating layer 22 is preferably formed by laminating insulating materials made of high-k materials, and preferably by using a laminate structure of a high-dielectric-constant (high-k) material and a material with a higher dielectric strength than the high-k material. For example, the insulating layer 22 can be formed by laminating an insulating film (also referred to as ZAZ) in which zirconium oxide, aluminum oxide, and zirconium oxide are stacked in this order. Alternatively, the insulating film (also referred to as ZAZA) can be formed by laminating zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide in this order. Alternatively, the insulating film can be formed by laminating hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide in this order. By using a laminate of insulators with a relatively high dielectric strength, such as aluminum oxide, the dielectric strength is improved, and electrostatic breakdown of the capacitor element can be suppressed.

[0100] Furthermore, a material exhibiting ferroelectricity may be used for the insulating layer 22. Examples of the material exhibiting ferroelectricity include hafnium oxide, zirconium oxide, and HfZrO. Ｘ (X is a real number greater than 0).

[0101] When the insulating layer 22 has a two-layer structure, it is preferable to use an insulating film having a function of capturing or fixing hydrogen as the film in contact with the semiconductor layer 21, and to use an insulating film having a barrier property against hydrogen as the film located on the conductive layer 23 side that functions as the gate electrode. This makes it possible to suppress diffusion of hydrogen from the conductive layer 23 side to the semiconductor layer 21, thereby realizing a highly reliable transistor.

[0102] As an insulating film that captures or fixes hydrogen, it is preferable to use a hafnium oxide film, a hafnium silicate film, an aluminum oxide film, etc. Furthermore, as an insulating film having a barrier property against hydrogen, it is preferable to use a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, a magnesium oxide film, a hafnium oxide film, a gallium oxide film, etc.

[0103] Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film having a barrier property against hydrogen may be used as a film located on the conductive layer 23 side. Alternatively, an insulating film that releases oxygen when heated may be used as a film in contact with the semiconductor layer 21, and an insulating film that has a function of capturing or fixing hydrogen may be used as a film located on the conductive layer 23 side.

[0104] When the insulating layer 22 has a three-layer structure, it is preferable to use an insulating film made of a material with a lower dielectric constant than the other films for the film in contact with the semiconductor layer 21, an insulating film having barrier properties against hydrogen and oxygen for the film located on the conductive layer 23 side, and an insulating film having the function of capturing or fixing hydrogen for the film located between them. Silicon oxide or silicon oxynitride can be used as the material with a low dielectric constant. With this configuration, oxygen can be supplied to the semiconductor layer 21 from the film in contact with the semiconductor layer 21. Furthermore, the film located on the conductive layer 23 side prevents oxygen from diffusing toward the conductive layer 23, thereby suppressing oxidation of the conductive layer 23.

[0105] As the insulating film having a barrier property against oxygen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, a hafnium silicate film, etc. As the insulating film having a barrier property against oxygen and hydrogen, it is preferable to use an aluminum oxide film, a silicon nitride film, a hafnium oxide film, etc.

[0106] When the insulating layer 22 has a four-layer structure, it is preferable to use an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, an insulating film made of a material with a lower dielectric constant than the other films for the film next closest to the semiconductor layer 21, an insulating film having the function of capturing or fixing hydrogen for the film next closest to the semiconductor layer 21, and an insulating film having a barrier property against hydrogen and oxygen for the film closest to the conductive layer 23. That is, in addition to the above-described three-layer structure, a configuration can be adopted in which a film in contact with the semiconductor layer 21 is added. By using an insulating film having a barrier property against oxygen for the film in contact with the semiconductor layer 21, oxygen desorption from the semiconductor layer 21 can be suppressed. In this case, it is preferable to use an aluminum oxide film as the film in contact with the semiconductor layer 21. Aluminum oxide not only has a barrier property against oxygen but also has the function of capturing or fixing hydrogen, thereby preventing hydrogen from diffusing into the semiconductor layer 21.

[0107] When the insulating layer 22 has a stacked structure, each insulating film is preferably a thin film. For example, the thickness of the insulating layer 22 is 1 nm to 20 nm, preferably 3 nm to 10 nm, to reduce the subthreshold swing (also referred to as the S value) of the transistor. The thickness of each insulating film is preferably 0.1 nm to 10 nm, more preferably 0.1 nm to 5 nm, more preferably 0.5 nm to 5 nm, still more preferably 1 nm to less than 5 nm, and even more preferably 1 nm to 3 nm.

[0108] As a specific example, it is preferable to use a four-layer structure in which an aluminum oxide film, a silicon oxide film, a hafnium oxide film, and a silicon nitride film are stacked in this order from the semiconductor layer 21 side, and to set the thicknesses of these films to 1 nm, 2 nm, 2 nm, and 1 nm from the semiconductor layer 21 side.

[0109] In this specification and the like, the barrier property refers to a property that makes it difficult for a corresponding substance to diffuse (also referred to as a property that makes it difficult for a corresponding substance to permeate, a property that the permeability of a corresponding substance is low, or a function that suppresses the diffusion of a corresponding substance). Note that when hydrogen is described as a corresponding substance, it can refer to, for example, a hydrogen atom, a hydrogen molecule, a water molecule, and OH. − Furthermore, unless otherwise specified, impurities when described as corresponding substances refer to impurities in the channel formation region or semiconductor layer, and include, for example, hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, and nitrogen oxide molecules (N ２ O, NO, NO ２ The term "oxygen" refers to at least one of an oxygen atom, an oxygen molecule, etc., when described as a corresponding substance.

[0110] Here, a transistor using a metal oxide film can have stable electrical characteristics by being surrounded by an insulating film that has a function of suppressing the permeation of impurities and oxygen. Examples of insulating films that have a function of suppressing the permeation of impurities and oxygen include insulating films containing one or more elements selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum, and the insulating films can be used in a single layer or a stacked layer. Specifically, examples of materials that can be used for the insulating film that has a function of suppressing the permeation of impurities and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and nitrides such as aluminum nitride, silicon nitride oxide, and silicon nitride.

[0111] Specifically, examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide. Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include oxides containing aluminum and hafnium (hafnium aluminate). Examples of insulating film materials that have the function of suppressing the permeation of impurities such as water and hydrogen and oxygen include nitrides such as aluminum nitride, aluminum titanium nitride, silicon nitride oxide, and silicon nitride.

[0112] Examples of insulating film materials capable of capturing or adhering hydrogen include metal oxides such as oxides containing hafnium, oxides containing magnesium, oxides containing aluminum, and oxides containing aluminum and hafnium (hafnium aluminate). These metal oxides may further contain zirconium, such as oxides containing hafnium and zirconium. Metal oxides with an amorphous structure have dangling bonds in some oxygen atoms, which enhance their ability to capture or adhering hydrogen. Therefore, these metal oxides preferably have an amorphous structure. For example, an amorphous structure may be achieved by including silicon in these oxides. For example, it is preferable to use an oxide containing hafnium and silicon (hafnium silicate). Metal oxides may have crystalline regions and / or grain boundaries in some regions.

[0113] <Conductive Layer> The conductive layer 24 and the conductive layer 25 are in contact with the semiconductor layer 21. When an oxide semiconductor is used as the semiconductor layer 21, if an easily oxidized metal such as aluminum is used in the portion of the conductive layer 24 or the conductive layer 25 in contact with the semiconductor layer 21, an insulating oxide (e.g., aluminum oxide) may be formed between the conductive layer 24 or the conductive layer 25 and the semiconductor layer 21, preventing electrical conduction therebetween. Therefore, it is preferable to use a conductive material that is resistant to oxidation, a conductive material that maintains low electrical resistance even when oxidized, or a conductive oxide material for at least the portion of the conductive layer 24 and the conductive layer 25 in contact with the semiconductor layer 21.

[0114] It is preferable to use, for example, titanium, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. as the conductive layers 24 and 25. These are conductive materials that are difficult to oxidize, or materials that maintain conductivity even when oxidized, and are therefore preferable.

[0115] Alternatively, conductive oxides such as indium oxide, zinc oxide, In—Sn oxide, In—Zn oxide, In—W oxide, In—W—Zn oxide, In—Ti oxide, In—Ti—Sn oxide, In—Sn—Si oxide, and Ga—Zn oxide can be used. Conductive oxides containing indium are particularly preferred because of their high conductivity. Alternatively, oxide materials such as In—Ga—Zn oxide that can be used for the semiconductor layer 21 can also be used as a conductive layer by increasing the carrier concentration.

[0116] For example, the conductive layer 24 and the conductive layer 25 can each be a single-layer structure of the above-mentioned conductive oxide film, a three-layer structure in which a titanium nitride film, a tungsten film, and a titanium nitride film are stacked in this order, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on tungsten, a two-layer structure in which a ruthenium film or a ruthenium oxide film is stacked on the above-mentioned conductive oxide film, or a two-layer structure in which the above-mentioned conductive oxide film is stacked on a ruthenium film or a ruthenium oxide film.

[0117] The conductive layer 23 functions as a gate electrode and can be made of various conductive materials. For example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, lanthanum, etc., or an alloy containing such a metal element, may be used as the conductive layer 23. Alternatively, nitrides of the above metals or alloys, or oxides of the above metals or alloys, may be used. For example, tantalum nitride, titanium nitride, nitrides containing titanium and aluminum, nitrides containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. may be used. Alternatively, semiconductors with high electrical conductivity, such as polycrystalline silicon containing impurity elements such as phosphorus, or silicides such as nickel silicide may be used.

[0118] The conductive layer 23 may be made of the nitride or oxide that can be used for the conductive layers 24 and 25 .

[0119] Since the conductive layers 23, 24, and 25 also function as wiring, it is preferable to use a laminate of low-resistance conductive materials. For example, the low-resistance conductive material that can be used for the conductive layer 23 described above can also be used for the lower layer of the conductive layers 24 and 25.

[0120] <Insulating Layer> The insulating layer 41b can be used as an interlayer insulating film. For example, it is preferably formed by a film formation method such as a sputtering method or a plasma CVD method. In particular, when a sputtering method is used, hydrogen is not required as a film formation gas, and therefore a film with an extremely low hydrogen content can be obtained. Therefore, the supply of hydrogen to the semiconductor layer 21 can be suppressed, and the electrical characteristics of the transistor 10 can be stabilized.

[0121] The insulating layer 41b is preferably an oxide insulating film because it is in contact with the channel formation region of the semiconductor layer 21. In particular, it is preferably an oxide insulating film that releases oxygen when heated. The oxide insulating film that can be used for the gate insulating layer can be used as the insulating layer 41b.

[0122] Furthermore, since the insulating layer 41b functions as an interlayer insulating layer, it is preferable to use a film formation method that allows film formation at a high film formation rate compared to other insulating layers. For example, the insulating layer 41 may be formed using TEOS (Tetra-Ethyl-Ortho-Silicate, chemical formula: Si(OC ２ H ５ ) ４ Alternatively, a silicon oxide film formed by plasma CVD using a silicon dioxide film may be used. This can improve productivity.

[0123] The insulating layers 41 a and 41 c are preferably made of films that do not easily diffuse hydrogen. By sandwiching the insulating layer 41 b between the insulating layers 41 a and 41 c, which do not easily diffuse hydrogen, it is possible to prevent external hydrogen from being mixed into the insulating layer 41 b that contacts the semiconductor layer 21.

[0124] The insulating layer 41 a and the insulating layer 41 c can be made of, for example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate. In particular, silicon nitride and silicon nitride oxide are suitable for use as the insulating layer 41 a and the insulating layer 41 c because they emit little impurities (for example, water and hydrogen) and are less permeable to oxygen and hydrogen.

[0125] The insulating layer 11 and the insulating layer 42 each function as an interlayer insulating layer. For the insulating layer 11 and the insulating layer 42, an insulating material that can be used for the insulating layer 41b or an insulating material that can be used for the insulating layer 41a and the insulating layer 41c can be used as appropriate.

[0126] This concludes the description of the components.

[0127] [Configuration Example 2] The following describes a configuration example in which some components are different from those in Configuration Example 1. Note that the same reference numerals are used for parts that overlap with those in Configuration Example 1, and descriptions thereof may be omitted.

[0128] 3A and 3B are schematic cross-sectional views of a transistor 10A. The transistor 10A differs from the transistor 10 illustrated in Configuration Example 1 above mainly in that the transistor 10A has an insulating layer 15.

[0129] FIG. 4A shows an enlarged view of the insulating layer 15 and its vicinity.

[0130] The insulating layer 15 has a portion located inside the opening 20 a. The insulating layer 15 is provided in contact with the side surfaces of the conductive layer 25 b, the side surfaces of the conductive layer 25 a, the side surfaces of the insulating layer 41 a, the side surfaces of the insulating layer 41 b, and the side surfaces of the insulating layer 41 c. Inside the opening 20 a, the semiconductor layer 21 is provided in contact with the insulating layer 15.

[0131] The insulating layer 15 preferably has a barrier property against hydrogen. This prevents hydrogen contained in the insulating layer 41b from diffusing directly into the semiconductor layer 21 or indirectly via a conductive layer. This makes it possible to realize a semiconductor device with good electrical characteristics and high reliability. For example, one or more of silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, and hafnium aluminate can be used. In particular, silicon nitride is preferably used.

[0132] Furthermore, it is preferable that the insulating layer 15 also have a barrier property against oxygen. This can suppress oxidation of the side surfaces of the conductive layer 25 (particularly the conductive layer 25a). For example, this can suppress oxidation of the side surfaces of the conductive layer 25 during processes such as the film formation process for the semiconductor layer 21, plasma processing for supplying oxygen to the semiconductor layer 21, microwave processing, and other heat treatments.

[0133] 4B shows an example in which the insulating layer 15 has a two-layer structure. The insulating layer 15 has an insulating layer 15a in contact with the insulating layer 41 and the like, and an insulating layer 15b in contact with the semiconductor layer 21.

[0134] For the insulating layer 15a, the above descriptions of the film having a barrier property against hydrogen and the film having a barrier property against oxygen can be referred to.

[0135] The insulating layer 15b is preferably an insulating film having a function of gettering (adsorbing, absorbing, capturing, or fixing) hydrogen. For example, by performing heat treatment after forming the semiconductor layer 21 in contact with the insulating layer 15b, hydrogen contained in the semiconductor layer 21 is captured and fixed by the insulating layer 15b, and the hydrogen concentration in the semiconductor layer 21 can be reduced.

[0136] Furthermore, examples of insulators having the function of gettering hydrogen include oxides containing one or both of aluminum and hafnium. Furthermore, it is more preferable that these oxides have an amorphous structure. In oxides having an amorphous structure, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. While these metal oxides preferably have an amorphous structure, they may also have crystalline regions formed in some parts.

[0137] The insulating layer 15b may be made of aluminum oxide, hafnium oxide, hafnium silicate, etc. Alternatively, for example, the insulating layer 15b may be a laminated film of aluminum oxide and silicon nitride.

[0138] 4C shows an example in which the insulating layer 15 has a three-layer structure. In FIG. 4C, the insulating layer 15 includes an insulating layer 15a, an insulating layer 15b, and an insulating layer 15c. The insulating layer 15c is in contact with the semiconductor layer 21.

[0139] The insulating layer 15c in contact with the semiconductor layer 21 is preferably an oxide insulating film. For example, an inorganic insulating film such as silicon oxide, silicon oxynitride, or aluminum oxide can be used. The insulating layer 15c is preferably an oxide insulating film containing excess oxygen to such an extent that oxygen is released by heating. By providing the insulating layer 15c containing excess oxygen and with a reduced hydrogen concentration in contact with the semiconductor layer 21, oxygen vacancies in the semiconductor layer 21 are reduced and the hydrogen concentration is reduced, thereby realizing a highly reliable transistor 10.

[0140] Furthermore, since the insulating layer 15b has the function of gettering hydrogen, the hydrogen concentration in the insulating layer 15c can be reduced by performing a heat treatment after forming the insulating layer 15c in contact with the insulating layer 15b.

[0141] The portion of the semiconductor layer 21 in contact with the insulating layer 15c is a region in which oxygen vacancies are reduced and can be said to be an i-type region. On the other hand, the portion not in contact with the insulating layer 15c is preferably an n-type region containing many carriers. That is, the portion of the semiconductor layer 21 in contact with the insulating layer 15c can be called a channel formation region, and the region outside that can be called a low-resistance region (also called a source region or a drain region).

[0142] FIG. 4D shows an example in which the insulating layer 41 has a single layer structure and the insulating layer 15 is not provided.

[0143] 4D is preferably an insulating film having barrier properties against hydrogen and oxygen. This can prevent oxygen contained in the semiconductor layer 21 from diffusing toward the insulating layer 41, thereby forming oxygen vacancies in the semiconductor layer 21, and can also prevent hydrogen from diffusing from the insulating layer 41 to the semiconductor layer 21, thereby achieving a highly reliable transistor. In this case, silicon nitride, silicon nitride oxide, silicon oxynitride, aluminum oxide, aluminum oxynitride, aluminum nitride, hafnium oxide, hafnium aluminate, or the like can be used for the insulating layer 41. In particular, it is preferable to use silicon nitride or silicon nitride oxide.

[0144] An insulating layer 15 may be further provided in the configuration shown in FIG. 4D.

[0145] Configuration Example 3 The transistor shown in FIG. 5A differs from Configuration Example 1 above mainly in that the shape of the semiconductor layer 21 is different.

[0146] A capacitance may be formed between a part of the semiconductor layer 21 located at the bottom of the opening 20b and the conductive layer 23 functioning as the gate electrode, with the insulating layer 22 as a dielectric. Therefore, it is preferable to provide a region at the bottom of the opening 20b where the conductive layer 23 and the semiconductor layer 21 do not overlap.

[0147] The semiconductor layer 21 is provided in contact with the side surfaces of the conductive layer 25, the side surfaces of the insulating layer 41 in the opening 20a, and the side surfaces of the conductive layer 24b in the opening 20b, and has a cylindrical shape that conforms to each opening. The lower end of the semiconductor layer 21 is provided in contact with the upper surface of the insulating layer 40. This allows oxygen to be supplied to the semiconductor layer 21 from the insulating layer 40b by heat during the process, etc.

[0148] Insulating layer 22 is provided at the bottom of opening 20b in contact with the upper surface of insulating layer 40b. As shown in Fig. 5A, it is preferable that semiconductor layer 21 is not provided between the lower surface of conductive layer 23 and the upper surface of insulating layer 40. Furthermore, when insulating layer 22 has a function of diffusing oxygen, contact between insulating layer 22 and insulating layer 40b allows oxygen to be supplied from insulating layer 40b to semiconductor layer 21 via insulating layer 22 due to heat during processing or the like.

[0149] By adopting such a configuration, it is possible to further reduce the parasitic capacitance, and to realize a transistor capable of operating at a higher speed.

[0150] 5B is a modified example of FIG. 5A. While FIG. 5A shows a three-layer structure of insulating layer 41, this example shows a single-layer structure of insulating layer 41. The insulating layer 41 can be made of the insulating material described above that does not easily diffuse oxygen and hydrogen. This configuration prevents hydrogen from diffusing from the insulating layer 41 to the semiconductor layer 21 and oxygen from being desorbed from the semiconductor layer 21 to the insulating layer 41, while allowing oxygen to be supplied to the semiconductor layer 21 directly from the insulating layer 40 or via the insulating layer 22. This allows for a transistor with excellent electrical characteristics and reliability.

[0151] [Configuration Example 4] A more specific configuration example of a transistor according to one embodiment of the present invention will be described below. Fig. 6A shows a schematic top view of a transistor and its periphery, and Fig. 6B shows a schematic cross-sectional view taken along the line A-B in Fig. 6A. Note that some components (such as an insulating layer 41) are omitted in Fig. 6A.

[0152] 6A and 6B show a connection electrode 35a connected to the conductive layer 24 and a connection electrode 35b connected to the conductive layer 25. In addition, an insulating layer 43 functioning as an interlayer insulating layer is provided on the insulating layer 42 and the conductive layer 31. For the insulating layer 43, the description of the insulating layer 42 can be referred to.

[0153] Also shown is an example in which the conductive layer 24 has a three-layer structure consisting of conductive layers 24a1, 24a2, and 24b. The conductive layer 24a1 can be a low-resistance conductive film similar to the conductive layer 24 described above. The conductive layer 24a2 can be made of a conductive material that is less susceptible to oxidation than the conductive layer 24a1, similar to the conductive layer 23a described above. This can suppress oxidation of the conductive layer 24a2.

[0154] An insulating layer 46 is provided to cover the insulating layer 45. An insulating film that gettering hydrogen, similar to the insulating layer 15b, can be used as the insulating layer 46. By providing such an insulating layer 46 below the transistor, the amount of hydrogen that can diffuse into the transistor can be reduced.

[0155] Furthermore, an insulating layer 47 is provided between the insulating layer 42 and the insulating layer 22, and between the insulating layer 42 and the conductive layer 23. As with the insulating layer 41a and the insulating layer 41c, the insulating layer 47 is preferably made of a film through which oxygen and hydrogen are less likely to diffuse. This can prevent hydrogen from diffusing from the insulating layer 42 to the semiconductor layer 21 via the insulating layer 22 or the conductive layer 23, and oxygen from the semiconductor layer 21 to the insulating layer 42 via the insulating layer 22.

[0156] The connection electrode 35a is provided on the insulating layer 43, the insulating layer 42, the insulating layer 47, the insulating layer 22, the insulating layer 41c, the insulating layer 41b, the insulating layer 41a, and the conductive layer 24b, and is embedded in an opening that reaches the conductive layer 24a1, and is in contact with the conductive layer 24a1. In this way, the connection electrode 35a is in contact with the low-resistance conductive layer 24a1 rather than the conductive layer 24b, thereby reducing the contact resistance therebetween.

[0157] The connection electrode 35b is provided on the insulating layer 43, the insulating layer 42, the insulating layer 47, the insulating layer 22, the semiconductor layer 21, and the conductive layer 25b, and is embedded in an opening that reaches the conductive layer 25a and is in contact with the conductive layer 25a. This reduces the contact resistance, similar to the connection electrode 35a.

[0158] An insulating layer 48 is provided between the connection electrodes 35a and 35b and the sidewalls of the openings. Similar to the insulating layer 47, the insulating layer 48 can be made of a material that is resistant to the diffusion of hydrogen and oxygen. This makes it possible to prevent the connection electrodes 35a and 35b from being oxidized by oxygen contained in the interlayer insulating layers, etc., and to prevent hydrogen contained in the connection electrodes 35a and 35b from diffusing toward the interlayer insulating layers.

[0159] The connection electrodes 35a and 35b each have a conductive layer 32 provided along the side and bottom surfaces of the opening, and a conductive layer 33 located on the conductive layer 32 and filling the opening. The conductive layer 33 can be made of a low-resistance conductive material similar to the conductive layer 23b described above. The conductive layer 32 can be made of a conductive material that is less susceptible to oxidation than the conductive layer 33, similar to the conductive layer 23a. This makes it possible to suppress oxidation of the conductive layer 33.

[0160] Insulating layer 15 is provided in contact with the side surfaces of conductive layer 25 and insulating layer 41. Here, as shown in Fig. 6B, the thickness of the portion of conductive layer 24b that contacts insulating layer 15 at the end of opening 20b is thinner. Therefore, not only the bottom surface of insulating layer 15 but also part of the side surface is in contact with conductive layer 24b.

[0161] Furthermore, the thickness of the semiconductor layer 21 in the region covering the edge portion located at the opening of the conductive layer 25 is thicker than the portion covering the upper surface of the conductive layer 25. In other words, the semiconductor layer 21 can be said to have an overhanging shape. For example, such a shape may be formed when a physical vapor deposition (PVD) method such as sputtering is used to form the semiconductor layer 21.

[0162] Since the semiconductor layer 21 has an overhanging shape, the conductive layer 23 has a partially constricted shape. Specifically, the portion of the conductive layer 23 located at the opening of the conductive layer 25 has a narrowly constricted shape. Since the conductive layer 23 needs to be formed so as to fill the opening having such a complex shape, the conductive layers 23a and 23b are preferably formed by a chemical vapor deposition (CVD) method, particularly a thermal CVD method, which has good step coverage.

[0163] The above is a description of the configuration example.

[0164] [Manufacturing Method Example] An example of a manufacturing method of a transistor according to one embodiment of the present invention will be described below, taking the transistor described in Structure Example 4 as an example.

[0165] Thin films (insulating films, semiconductor films, conductive films, etc.) constituting a semiconductor device can be formed by a sputtering method, a chemical vapor deposition method, a vacuum evaporation method, a pulsed laser deposition (PLD) method, an ALD method, or the like.

[0166] Furthermore, thin films (insulating films, semiconductor films, conductive films, etc.) constituting the semiconductor device can be formed by methods such as spin coating, dipping, spray coating, inkjet, dispensing, screen printing, offset printing, doctor knife, slit coating, roll coating, curtain coating, and knife coating.

[0167] Sputtering methods include RF sputtering, which uses a high-frequency power supply as the sputtering power source, DC sputtering, which uses a direct current power supply, and pulsed DC sputtering, which changes the voltage applied to the electrode in a pulsed manner. RF sputtering is mainly used to deposit insulating films, while DC sputtering is mainly used to deposit metal conductive films. Pulsed DC sputtering is mainly used to deposit films of compounds such as oxides, nitrides, and carbides using reactive sputtering.

[0168] CVD methods can be classified into plasma-enhanced chemical vapor deposition (PECVD), which uses plasma, thermal CVD (TCVD), which uses heat, and photo-CVD (photo-CVD), which uses light. CVD methods can also be further classified into metal CVD (MCVD) and metal organic CVD (MOCVD), depending on the source gas used.

[0169] The plasma CVD method can produce high-quality films at relatively low temperatures. Furthermore, since the thermal CVD method does not use plasma, it is possible to reduce plasma damage to the workpiece. Furthermore, since the thermal CVD method does not cause plasma damage during film formation, it can produce films with fewer defects.

[0170] As the ALD method, a thermal ALD method in which a reaction between a precursor and a reactant is carried out using only thermal energy, a PEALD method in which a plasma-excited reactant is used, or the like can be used.

[0171] Unlike sputtering, CVD and ALD are film formation methods that are less affected by the shape of the workpiece and have good step coverage. In particular, ALD has excellent step coverage and excellent thickness uniformity, making it suitable for coating the surface of an opening with a high aspect ratio. However, because ALD has a relatively slow film formation rate, it may be preferable to use it in combination with other film formation methods, such as CVD, which have a faster film formation rate.

[0172] In the CVD method, a film of any composition can be formed by adjusting the flow rate ratio of the source gases. For example, in the CVD method, a film with a continuously changing composition can be formed by changing the flow rate ratio of the source gases while forming the film. When forming a film while changing the flow rate ratio of the source gases, the time required for film formation can be shortened compared to when forming a film using multiple film formation chambers because no time is required for transportation or pressure adjustment. Therefore, the productivity of semiconductor devices can be increased in some cases.

[0173] In the ALD method, a film of any composition can be formed by simultaneously introducing multiple different precursors. Alternatively, when multiple different precursors are introduced, a film of any composition can be formed by controlling the number of cycles of each precursor. Furthermore, as with the CVD method, a film with a continuously changing composition can be formed.

[0174] The thin film constituting the semiconductor device can be processed using a photolithography method or the like. Alternatively, the thin film may be processed using a nanoimprint method, a sandblasting method, a lift-off method or the like. Alternatively, the island-shaped thin film may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0175] There are two typical photolithography methods: one is to form a resist mask on the thin film to be processed, process the thin film by etching or the like, and then remove the resist mask; the other is to form a photosensitive thin film, and then process the thin film into the desired shape by exposure and development.

[0176] In photolithography, the light used for exposure can be, for example, i-line (wavelength 365 nm), g-line (wavelength 436 nm), h-line (wavelength 405 nm), or a mixture of these. Other light sources that can be used include ultraviolet light, KrF laser light, ArF laser light, etc. Exposure can also be performed by immersion exposure technology. Extreme ultraviolet (EUV) light or X-rays can also be used as the light used for exposure. An electron beam can also be used instead of light used for exposure. Extreme ultraviolet light, X-rays, or an electron beam are preferred because they enable extremely fine processing. When exposure is performed by scanning a beam such as an electron beam, a photomask is not required.

[0177] For etching the thin film, dry etching, wet etching, sandblasting, or the like can be used.

[0178] 7A to 13B are schematic cross-sectional views corresponding to the steps in the example of the fabrication method described below.

[0179] First, a substrate (not shown) is prepared, and an insulating layer 11 is formed on the substrate.

[0180] The substrate may be a substrate having heat resistance sufficient to withstand at least a subsequent heat treatment. When an insulating substrate is used, a glass substrate, a quartz substrate, a sapphire substrate, a ceramic substrate, an organic resin substrate, or the like may be used. Alternatively, a semiconductor substrate such as a single-crystal semiconductor substrate made of silicon or silicon carbide, a polycrystalline semiconductor substrate, a compound semiconductor substrate such as silicon germanium or gallium nitride, or an SOI substrate may be used.

[0181] An inorganic insulating film such as a silicon oxide film or a silicon oxynitride film can be used as the insulating layer 11. The insulating layer 11 can be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like. If the surface on which the insulating layer 11 is to be formed is not flat, a planarization process may be performed after the insulating layer 11 is formed so that the upper surface of the insulating layer 11 becomes flat.

[0182] Subsequently, the insulating layer 45 and the insulating layer 46 are formed on the insulating layer 11. The insulating layer 45 and the insulating layer 46 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0183] Subsequently, conductive films 24a1f and 24a2f are stacked on the insulating layer 46 (FIG. 7A). The conductive films 24a1f and 24a2f can be formed by a film formation method such as sputtering, ALD, or CVD.

[0184] Subsequently, insulating films 40af and 40bf are formed on the conductive film 24a1f (FIG. 7B). The insulating films 40af and 40bf can be formed by a film formation method such as sputtering, ALD, or CVD.

[0185] Next, a resist mask is formed on the insulating film 40bf, and unnecessary portions of the insulating film 40bf and the insulating film 40af are removed by etching to form the insulating layer 40, which is a stack of the insulating layer 40b and the insulating layer 40a (FIG. 7C). Dry etching is preferably used for the etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0186] After the insulating film 40bf is formed or after it is processed into the insulating layer 40b, a process for supplying oxygen to the insulating film 40bf or the insulating layer 40b may be performed. This allows oxygen to be supplied from the insulating layer 40 to the semiconductor layer 21 later by heat or the like generated after the formation of the semiconductor film 21f.

[0187] Examples of the treatment for supplying oxygen include heat treatment in an oxygen-containing atmosphere and plasma treatment (including microwave plasma) in an oxygen-containing atmosphere. Alternatively, oxygen may be supplied to the insulating layer by forming an oxide film (preferably a metal oxide film) in an oxygen-containing atmosphere by a sputtering method. The formed oxide film may be removed immediately or may be left as it is. Note that the oxygen-containing atmosphere may be oxygen gas (O ２ ) as well as ozone (O ３), nitrous oxide (N ２ The atmosphere may include a gas containing an oxygen-containing compound such as oxygen (O).

[0188] Next, a conductive film 24bf is formed to cover the conductive film 24a1f, the insulating layer 40a, and the insulating layer 40b (FIG. 7D). The conductive film 24bf can be formed by a film formation method such as sputtering or ALD. When formed using a PVD method such as sputtering, the thickness of the portion covering the side surfaces of the insulating layer 40a and the insulating layer 40b may be thinner than the other portions.

[0189] Next, a resist mask is formed on the conductive film 24bf, and unnecessary portions of the conductive film 24bf, the conductive film 24a1f, and the conductive film 24a2f are removed by etching to form the conductive layer 24 in which the conductive layer 24a2, the conductive layer 24a1, and the conductive layer 24b are stacked (FIG. 7E). The etching can be performed by either wet etching or dry etching, or both. Dry etching is particularly preferable. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0190] Subsequently, insulating layers 41a, 41b, and 41c are formed on the conductive layer 24 and the insulating layer 46 (FIG. 8A). The insulating layers 41a, 41b, and 41c may be formed by a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or the like, as appropriate.

[0191] Here, it is preferable that the insulating layer 41a and the insulating layer 41c are made of insulating films having different compositions or constituent elements from the insulating layer 41b.

[0192] Furthermore, since the thicknesses of insulating layers 41a, 41b, and 41c affect the channel length of the transistor, it is important to prevent variations in the thicknesses of insulating layers 41a, 41b, and 41c.

[0193] The insulating layer 41b is preferably an oxide film containing a large amount of oxygen to such an extent that oxygen is released by heating and a small amount of hydrogen. The insulating layer 41b can be formed by a film formation method such as a PECVD method, a sputtering method, or an ALD method, but is particularly preferably formed by a sputtering method. In particular, by forming the insulating layer 41b using a gas containing oxygen and not using a gas containing hydrogen as a film formation gas, the insulating layer 41b can be formed with an extremely small amount of hydrogen and an excess amount of oxygen. By forming the insulating layer 41b in this manner, oxygen can be supplied from the insulating layer 41b to the channel formation region of the semiconductor layer 21, thereby reducing oxygen vacancies.

[0194] After the insulating layer 41b is formed and before the insulating layer 41c is formed, a treatment for supplying oxygen to the insulating layer 41b may be performed. For the treatment for supplying oxygen, see the above description.

[0195] Next, conductive films 25af and 25bf are formed by laminating them on the insulating layer 41c (FIG. 8B). The conductive films 25af and 25bf can be formed by a film formation method such as sputtering, ALD, or CVD.

[0196] Subsequently, a resist mask is formed on the conductive film 25bf, and an opening 20a reaching the conductive layer 24b is formed in the conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a (FIG. 8C).

[0197] The conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a can be etched by dry etching to form the fine openings 20a. However, this is not limiting, and wet etching and dry etching may be combined, or processing may be performed by wet etching. Furthermore, after dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0198] When the opening 20a is formed, as shown in FIG. 8C, a part of the upper portion of the conductive layer 24b may be etched, and the thickness of the portion overlapping the opening 20a may become thin.

[0199] When forming the opening 20a, the conductive film 25bf may be used as a hard mask. At this time, the opening is first formed in the conductive film 25bf using a resist mask. Then, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a are sequentially etched using the conductive film 25bf as a mask, thereby forming the opening 20a. Note that the resist mask may be removed after etching the conductive film 25bf, or may be removed during etching of the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a, or may be removed after forming the opening 20a.

[0200] Furthermore, when forming the opening 20a, the end of the conductive film 25bf may have a tapered shape as shown in FIG. 8C . This is not limited to the conductive film 25bf, but the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the like may also have a tapered shape. Furthermore, due to the influence of etching in the horizontal direction relative to the substrate (also referred to as side etching), the upper film may have a shape that protrudes more than the lower film (an overhang shape). For example, the side of the insulating layer 41b located in the opening 20a may be processed so that it is positioned outward relative to the side of the insulating layer 41c.

[0201] In this specification and the like, a tapered shape refers to a shape in which at least a part of the side surface of a structure is inclined with respect to the substrate surface.

[0202] The sidewalls of the opening 20a are preferably nearly perpendicular to the top surface of the conductive layer 24, since this reduces the area of ​​the opening 20a. This configuration allows a transistor with a small occupation area to be fabricated. Alternatively, the sidewalls of the opening 20a may be tapered. The tapered shape improves the coverage of a film formed inside the opening 20a.

[0203] The maximum width of the opening 20a (maximum diameter when the opening 20a is circular in plan view) is preferably as small as possible. For example, the maximum width of the opening 20a is 2 μm or less, 1 μm or less, 500 nm or less, 300 nm or less, 150 nm or less, 100 nm or less, 60 nm or less, 50 nm or less, 40 nm or less, 30 nm or less, or 20 nm or less, and is preferably 5 nm or more. In particular, to process the opening 20a extremely finely, it is preferable to use a lithography method using short-wavelength light such as EUV light or an electron beam.

[0204] Subsequently, heat treatment may be performed. The heat treatment may be performed at a temperature of 250° C. or higher and 650° C. or lower, preferably 300° C. or higher and 500° C. or lower, more preferably 320° C. or higher and 450° C. or lower. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration can be approximately 20%. The heat treatment may be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or higher, 1% or higher, or 10% or higher to compensate for desorbed oxygen. By performing the above heat treatment, impurities such as water and hydrogen contained in the insulating layer 41 or the like can be reduced before the formation of an oxide semiconductor film to be a semiconductor layer.

[0205] Furthermore, it is preferable that the gas used in the heat treatment be highly purified. For example, it is preferable that the moisture content of the gas used in the heat treatment be 1 ppb (0.001 ppm) or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being taken into the insulating layer 41 and the like as much as possible.

[0206] Subsequently, an insulating film 15f is formed on the conductive film 25bf and in the opening 20a (FIG. 9A). The insulating film 15f can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. In particular, it is preferable to form the insulating film 15f by using the ALD method.

[0207] Next, the insulating film 15f is etched by anisotropic dry etching without using a resist mask, thereby forming a ring-shaped (cylindrical) insulating layer 15 that contacts the side surfaces of the conductive film 25bf, the conductive film 25af, the insulating layer 41c, the insulating layer 41b, and the insulating layer 41a. After etching the insulating film 15f, the exposed portion of the conductive layer 24b is subsequently etched, thereby forming an opening 20b in the conductive layer 24b that reaches the insulating layer 40b (FIG. 9B).

[0208] When etching the insulating layer 15, the portion of the insulating film 15f along the sidewall of the opening 20a may also be exposed to the etching and thinned. Therefore, it is preferable to form the insulating film 15f thick in advance so that it will have a desired thickness after etching. In particular, when the opening 20a has a tapered shape, it is easy to thin the insulating film 15f, so forming it thick in this way is effective.

[0209] Furthermore, when etching the conductive layer 24b, the upper surface of the conductive film 25bf is exposed. Therefore, if the same conductive film is used for the conductive layer 24b and the conductive film 25bf, the conductive film 25bf may disappear in the worst case scenario. Therefore, it is preferable to form the conductive film 25bf in advance to be sufficiently thicker than the conductive layer 24b. Alternatively, a protective layer may be formed on the conductive film 25bf and then removed after the formation of the opening 20b. The protective layer may be a film that will not disappear during the formation of the openings 20a and 20b, and may be an insulating film, a conductive film, or a semiconductor film. The protective layer can be removed by dry etching or wet etching, or both.

[0210] Subsequently, a semiconductor film 21f is formed to cover the conductive film 25bf, the opening 20a, and the opening 20b (FIG. 9C).

[0211] The semiconductor film may be a metal oxide (oxide semiconductor) film having semiconductor properties. The metal oxide film may be formed by a suitable method such as sputtering, CVD, MBE, PLD, or ALD. The metal oxide film is preferably formed in contact with the sidewalls of the opening 20a and the bottom and sidewalls of the opening 20b, which have a large aspect ratio. Therefore, the metal oxide film is preferably formed by a method with good coverage, and more preferably by ALD.

[0212] The metal oxide film preferably has crystallinity. In particular, the metal oxide film of one embodiment of the present invention preferably contains a metal oxide having a CAAC structure.

[0213] It is preferable to perform a treatment to enhance the crystallinity of the metal oxide film during or after the formation of the metal oxide film. Examples of treatments to enhance the crystallinity of the metal oxide film include heat treatment, plasma treatment, microwave (typically 2.45 GHz) treatment, microwave plasma treatment, and light (e.g., ultraviolet light) irradiation treatment. A plurality of these treatments may be performed simultaneously or sequentially. For example, heat treatment and microwave plasma treatment may be performed simultaneously. Alternatively, microwave plasma treatment may be performed after heat treatment.

[0214] Furthermore, it is more preferable to perform the treatment for increasing the crystallinity of the metal oxide film multiple times during the formation of the metal oxide film. For example, when forming a metal oxide film by the ALD method, it is preferable to perform a microwave plasma treatment every time an atomic layer is formed. Alternatively, it is preferable to perform a treatment for increasing the crystallinity every time a metal oxide film having a thickness within a predetermined range is formed, which can improve productivity. Specifically, it is preferable to form a first metal oxide film having a thickness of 1 nm to 10 nm, perform the first microwave plasma treatment, and then form a second metal oxide film having a thickness of 1 nm to 10 nm, and perform the second microwave plasma treatment.

[0215] The deposition method for the first metal oxide film and the second metal oxide film is not particularly limited, and ALD or sputtering may be used for each. In particular, depositing the first metal oxide film by ALD is preferable because it can prevent elements from the layer constituting the surface to be formed from being mixed into the first metal oxide film and the second metal oxide film (also known as mixing). This is particularly suitable when the elements contained in the layer constituting the surface to be formed inhibit the crystallization of the metal oxide (e.g., when the layer contains silicon, carbon, or the like). The first metal oxide film and the second metal oxide film may have different compositions. Although a stacked structure of the first metal oxide film and the second metal oxide film is illustrated here, the present invention is not limited thereto. Similar processes can be applied to a single-layer or a stacked structure of three or more layers of metal oxide films.

[0216] Furthermore, a treatment for increasing the crystallinity of a metal oxide film may be performed after the metal oxide film is formed. Specifically, the treatment may be performed directly on the formed metal oxide film, or may be performed through another film, such as an insulating film, formed on the metal oxide film. For example, a microwave plasma treatment may be performed after the metal oxide film is formed, or an insulating film (e.g., a silicon nitride film, a silicon oxide film, an aluminum oxide film, etc.) may be formed after the metal oxide film is formed, and then a heat treatment or a microwave plasma treatment may be performed on the metal oxide film through the insulating film.

[0217] The above-described treatment for increasing the crystallinity of a metal oxide film can also serve as a treatment for removing impurities contained in the metal oxide film. For example, carbon, hydrogen, nitrogen, and the like contained in the metal oxide film can be preferably removed. Alternatively, by performing the treatment for increasing the crystallinity of a metal oxide film in an oxygen gas atmosphere, oxygen vacancies in the metal oxide film can be reduced.

[0218] When performing a treatment to increase the crystallinity of a metal oxide film, it is preferable to set the temperature of the heat treatment (or the temperature of the substrate) to room temperature (e.g., 25°C) or higher, 100°C or higher and 700°C or lower, 100°C or higher and 600°C or lower, or 300°C or higher and 450°C or lower.

[0219] By increasing the crystallinity of the metal oxide film, a highly reliable transistor can be realized.

[0220] The metal oxide film can be formed by, for example, a sputtering method using a metal oxide target.

[0221] The metal oxide film is preferably a dense film with as few defects as possible. Furthermore, the metal oxide film is preferably a high-purity film with as few impurities as possible, such as hydrogen and water, as reduced as possible. In particular, it is preferable to use a crystalline metal oxide film as the metal oxide film.

[0222] Furthermore, when forming a metal oxide film, oxygen gas may be mixed with an inert gas (e.g., helium gas, argon gas, xenon gas, etc.). Note that the higher the ratio of oxygen gas to the total deposition gas when forming the metal oxide film (hereinafter also referred to as the oxygen flow ratio), the higher the crystallinity of the metal oxide film can be, and a highly reliable transistor can be realized. On the other hand, the lower the oxygen flow ratio, the lower the crystallinity of the metal oxide film can be, and a transistor with a higher on-state current can be obtained.

[0223] When forming a metal oxide film, the higher the substrate temperature, the higher the crystallinity and density of the metal oxide film, whereas the lower the substrate temperature, the lower the crystallinity and electrical conductivity of the metal oxide film.

[0224] The metal oxide film can be formed under the conditions of a substrate temperature of from room temperature to 250° C., preferably from room temperature to 200° C., and more preferably from room temperature to 140° C. For example, a substrate temperature of from room temperature to less than 140° C. is preferable because productivity is increased. Furthermore, by forming a metal oxide film at room temperature or without intentional heating, the crystallinity can be reduced.

[0225] When the ALD method is used, it is preferable to use a film formation method such as thermal ALD (Atomic Layer Deposition) or PEALD (Plasma Enhanced ALD). The thermal ALD method is preferable because it exhibits extremely high step coverage. The PEALD method is also preferable because it exhibits high step coverage and allows low-temperature film formation.

[0226] For example, when a metal oxide is used for the semiconductor layer 21, the semiconductor layer 21 can be formed by the ALD method using a precursor containing the constituent metal element and an oxidizing agent.

[0227] For example, when forming an In—Ga—Zn oxide film, three precursors, i.e., a precursor containing indium, a precursor containing gallium, and a precursor containing zinc, can be used, or two precursors, i.e., a precursor containing indium and a precursor containing gallium and zinc, can be used.

[0228] Examples of precursors that can be used that contain indium include triethylindium, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)indium, cyclopentadienylindium, indium(III) chloride, and (3-(dimethylamino)propyl)dimethylindium.

[0229] Furthermore, examples of precursors that can be used that contain gallium include trimethylgallium, triethylgallium, tris(dimethylamido)gallium(III), gallium(III) acetylacetonate, tris(2,2,6,6-tetramethyl-3,5-heptanedionate)gallium, dimethylchlorogallium, diethylchlorogallium, and gallium(III) chloride.

[0230] Furthermore, as a precursor containing zinc, dimethyl zinc, diethyl zinc, zinc bis(2,2,6,6-tetramethyl-3,5-heptanedionate), zinc chloride, etc. can be used.

[0231] As the oxidizing agent, for example, ozone, oxygen, water, etc. can be used.

[0232] Methods for controlling the composition of the resulting film include adjusting the flow rate ratio of the source gases, the time for which the source gases are flowed, the order in which the source gases are flowed, etc. By adjusting these, it is also possible to form a film whose composition changes continuously. It is also possible to form two or more films with different compositions continuously.

[0233] After the metal oxide film is formed, it is preferable to perform heat treatment. The heat treatment may be performed within a temperature range in which the metal oxide film does not polycrystallize, such as 250°C to 650°C, preferably 400°C to 600°C. The heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, when the heat treatment is performed in a mixed atmosphere of nitrogen gas and oxygen gas, the oxygen gas concentration can be about 20%. The heat treatment may also be performed under reduced pressure. Alternatively, after the heat treatment in the nitrogen gas or inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more to compensate for the desorbed oxygen.

[0234] The gas used in the heat treatment is preferably highly purified. For example, the amount of moisture contained in the gas used in the heat treatment can be reduced to 1 ppb or less, preferably 0.1 ppb or less, and more preferably 0.05 ppb or less. By performing the heat treatment using a highly purified gas, it is possible to prevent moisture and the like from being incorporated into the metal oxide film and the like as much as possible.

[0235] 9C shows an example in which the thickness of the portion of the semiconductor film 21f covering the end of the conductive film 25bf is formed thicker than the other portion. Here, an example of the cross-sectional shape of the semiconductor film 21f is shown, which is formed by stacking three layers: a metal oxide film formed by the ALD method, a metal oxide film formed by the sputtering method, and another metal oxide film formed by the ALD method.

[0236] Next, a resist mask is formed on the semiconductor film 21f, and unnecessary portions of the semiconductor film 21f, the conductive film 25bf, and the conductive film 25af are etched to form the semiconductor layer 21, the conductive layer 25b, and the conductive layer 25a (FIG. 10A). The etching can be performed by either wet etching or dry etching, or both. Dry etching is particularly preferable. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0237] Subsequently, an insulating layer 22 is formed to cover the insulating layer 41c, the conductive layer 25a, the conductive layer 25b, and the semiconductor layer 21 (FIG. 10B). The insulating layer 22 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method.

[0238] It is preferable that the insulating layer 22 be provided with as uniform a thickness as possible on the surface of the semiconductor layer 21 in the openings 20a and 20b. Therefore, it is particularly preferable to form the insulating layer 22 by the ALD method, which is a film formation method with extremely excellent coverage. Note that, when the sidewalls of the openings 20a and 20b are tapered, the insulating layer 22 can be formed by a film formation method such as a sputtering method or a CVD method.

[0239] Subsequently, a dummy layer 17 is formed so as to fill the openings 20a and 20b and to protrude above the upper surface of the insulating layer 22 (FIG. 11A).

[0240] The dummy layer 17 can be made of an organic resin or an inorganic insulating material. For example, using a coating-type insulating film such as an SOC (spin on carbon) film or an SOG (spin on glass) film is preferable because it can flatten the upper surface and eliminate the need for a planarization process. For example, a configuration in which an SOG film is stacked on an SOC film is preferable. Alternatively, the dummy layer 17 can be formed by a film formation method such as a sputtering method or a CVD method. The material used for the dummy layer 17 preferably satisfies the following conditions: it can be formed thick, it can be formed or processed vertically, and it is easy to remove (leaving no residue and causing minimal damage to the surface on which it is formed).

[0241] The dummy layer 17 can be formed by forming an insulating film, forming a resist mask, and etching away unnecessary portions. When a photosensitive organic resin is used as the dummy layer 17, the dummy layer 17 can also be formed by forming an insulating film, then performing exposure and development processes to remove unnecessary portions.

[0242] Subsequently, insulating layer 47 and insulating layer 42 are formed by laminating them. The insulating layer 47 and insulating layer 42 can be formed by a method such as sputtering, CVD, MBE, PLD, or ALD, respectively. For example, insulating layer 47 can be formed by a film formation method with high step coverage such as ALD, and insulating layer 42 can be formed by a film formation method that can easily increase the film formation rate such as sputtering.

[0243] Next, a planarization process is performed, and the upper portions of the insulating layer 42 and the insulating layer 47 are etched until the upper surfaces of the dummy layer 17 are exposed ( FIG. 11B ). The planarization process may be performed by, for example, chemical mechanical polishing (CMP), dry etching, or the like. Note that the planarization process may also remove a portion of the dummy layer 17. For example, if the dummy layer 17 is configured by stacking an SOG film on an SOC film, the planarization process may be completed with the SOG film removed and the upper surface of the SOC film exposed.

[0244] Next, the dummy layer 17 is removed to form an opening 20c in the insulating layer 47 (FIG. 12A). The dummy layer 17 can be removed by wet etching or dry etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0245] Next, a conductive film to become conductive layer 23a and a conductive film to become conductive layer 23b are formed in this order on insulating layer 42 and in openings 20c, 20a, and 20b. The conductive film to become conductive layer 23a and the conductive film to become conductive layer 23b can be formed by CVD, ALD, sputtering, or the like. Formation by CVD is particularly preferable. The conductive film to become conductive layer 23b is formed thick so as to fill each opening.

[0246] Subsequently, a planarization process is performed, and the upper portions of the conductive films are etched until the upper surface of the insulating layer 47 is exposed (FIG. 12B), thereby forming the conductive layers 23a and 23b embedded in the openings 20a, 20b, and 20c.

[0247] At this stage, the transistor is fabricated.

[0248] Next, a conductive film is formed on the insulating layer 42 and the conductive layer 23, and unnecessary portions are removed by etching to form the conductive layer 31 (FIG. 13A). The conductive film that becomes the conductive layer 31 can be formed by sputtering, CVD, ALD, or the like.

[0249] Subsequently, an insulating layer 43 is formed to cover the insulating layer 42 and the conductive layer 31. The insulating layer 43 can be formed by the same method as the insulating layer 42.

[0250] Next, a resist mask is formed on the insulating layer 43, and the insulating layer 43 and the like are etched to form openings reaching the conductive layer 24a1 and the conductive layer 25a. The openings are preferably formed by dry etching. After the dry etching, dry cleaning using plasma or wet cleaning using a chemical solution (including acid or alkali) or water (including carbonated water) may be performed.

[0251] The two openings may be formed in the same process using the same resist mask, or may be formed in order using different resist masks.

[0252] Next, an insulating film is formed on the insulating layer 43, along the side walls of the openings that reach the conductive layer 24a1, and along the side walls of the openings that reach the conductive layer 25a, and then anisotropic dry etching is performed to form a ring-shaped (cylindrical) insulating layer 48 that contacts the side walls of each opening.

[0253] The insulating film that becomes the insulating layer 48 can be formed by a film formation method such as a sputtering method, an ALD method, or a CVD method. In particular, it is preferable to form the insulating film by using the ALD method.

[0254] Next, a conductive film that will become conductive layer 32 is formed along the sidewalls of each opening, and then a conductive film that will become conductive layer 33 is formed so as to fill each opening. Thereafter, the upper portions of the two conductive films are etched until the upper surface of insulating layer 43 is exposed, thereby forming connection electrodes 35a and 35b (FIG. 13B).

[0255] Thereafter, a wiring in contact with the connection electrode 35a and a wiring in contact with the connection electrode 35b may be formed on the insulating layer 43. For the wiring, the description of the conductive layer 31 can be referred to.

[0256] Through the above steps, a semiconductor device including the transistor exemplified in Structure Example 4 can be manufactured.

[0257] The above is a description of an example of the manufacturing method.

[0258] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0259] Embodiment 2 A structure of a memory device including a transistor and a capacitor according to one embodiment of the present invention will be described below.

[0260] 14A shows a circuit diagram of a memory cell 30. The memory cell 30 is configured with one transistor Tr1 and one capacitor C, and can also be represented as 1Tr1C. The transistor Tr1 has a gate connected to a wiring WL, one of a source and a drain connected to a wiring BL, and the other connected to one electrode of the capacitor C. The other electrode of the capacitor C is connected to a wiring PL.

[0261] The memory cell 30 can store data by holding, in the capacitor C, a data potential input from the wiring BL via the transistor Tr1. Furthermore, data can be held by turning the transistor Tr1 off. Furthermore, by turning the transistor Tr1 on, a potential corresponding to the held data is output to the wiring BL, allowing the data to be read. A signal that controls the conduction and non-conduction of the transistor Tr1 is applied to the wiring WL. Furthermore, a predetermined potential (e.g., a fixed potential) is applied to the wiring PL.

[0262] 14B and 14C show cross-sectional views of the memory cell 30. Fig. 14B is a cross-sectional view taken along the direction in which the conductive layers 25 and 34 extend, and Fig. 14C is a cross-sectional view taken along the direction in which the conductive layer 31 extends. The memory cell 30 has a configuration in which a transistor 10 is stacked on a capacitance element 50. The transistor 10 corresponds to the transistor Tr1, and the capacitance element 50 corresponds to the capacitance element C.

[0263] The configuration of the transistor 10 will not be described here because the description in Embodiment 1 can be referred to. Note that although an example using the transistor 10 is shown here, the transistor is not limited to the transistor 10 and can be replaced with various transistors described in Embodiment 1.

[0264] The capacitance element 50 includes a conductive layer 51, a conductive layer 52, and an insulating layer 53 sandwiched therebetween. The capacitance element 50 constitutes a so-called MIM (Metal-Insulator-Metal) capacitor.

[0265] The capacitance element 50 is provided on the insulating layer 11. A conductive layer 34 is provided on the insulating layer 11, and an insulating layer 55 is provided on the conductive layer 34. An opening 20d is provided in the insulating layer 55, reaching the conductive layer 34. A conductive layer 51 is provided inside the opening 20d, in contact with the side surface of the insulating layer 55 and the upper surface of the conductive layer 34. An insulating layer 53 is provided covering the insulating layer 55 and the conductive layer 51. An insulating layer 56 is provided on the insulating layer 53. The conductive layer 52 is provided so as to be embedded in the insulating layer 56 and the opening 20d.

[0266] The conductive layer 52 and the insulating layer 56 have flattened upper surfaces and are at approximately the same height. A conductive layer 24a is provided on the conductive layer 52 and the insulating layer 56. A conductive layer 31 is provided in contact with the upper surface of the conductive layer 24a.

[0267] 14B and 14C, the conductive layer 32 corresponds to the wiring BL, the conductive layer 23 corresponds to the wiring WL, and the conductive layer 34 corresponds to the wiring PL.

[0268] A low-resistance conductive material can be used for the conductive layer 34, the conductive layer 51, and the conductive layer 52. For example, the material that can be used for the conductive layer 23b can be used.

[0269] The insulating layer 53 functions as a dielectric layer of the capacitance element 50. The thinner the insulating layer 53 is and the higher the relative dielectric constant thereof is, the larger the capacitance of the capacitance element 50 can be. For example, it is preferable to use a material that can be used for the insulating layer 22.

[0270] 15A shows a circuit diagram of a memory cell 30a. The memory cell 30a has a configuration in which the capacitor C of the memory cell 30 is replaced with a transistor Tr2. The gate of the transistor Tr2 is connected to the other of the source and drain of the transistor Tr1, one of the source and drain is connected to a wiring SL, and the other is connected to a wiring RL.

[0271] The memory cell 30a can store data by holding a data potential input from the wiring BL via the transistor Tr1 at a node connected to the gate of the transistor Tr2. Furthermore, data can be held by turning off the transistor Tr1. Furthermore, the conduction state between the wiring SL and the wiring RL of the transistor Tr2 changes depending on the potential held at the gate. For example, data can be read by applying a signal to one of the wirings SL and RL and determining the magnitude of the potential or current output to the other. Therefore, the memory cell 30a can be used as a memory capable of nondestructive readout.

[0272] 15A may be provided with a capacitance element C. More specifically, one electrode of the capacitance element C may be connected to a node where the other of the source and drain of the transistor Tr1 and the gate of the transistor Tr2 are connected. In this case, the wiring PL may be connected to the other electrode of the capacitance element C. The capacitance element C may have a configuration similar to that of the capacitance element 50 described above, or various MIM capacitances such as a parallel plate type, a cylinder type, or a pillar type may be used.

[0273] 15B and 15C are cross-sectional views of the memory cell 30a. The memory cell 30a has a structure in which a transistor 10 is stacked on a transistor 70. The structure of the transistor 10 is similar to that of the memory cell 30 described above.

[0274] The transistor 70 includes a conductive layer 74a, a conductive layer 74b, an insulating layer 40c, an insulating layer 40d, a semiconductor layer 71, an insulating layer 72, a conductive layer 73, a conductive layer 75a, and a conductive layer 75b. The transistor 70 is a vertical transistor provided in a region overlapping with an opening 20e provided in the conductive layer 75b, the conductive layer 75a, the insulating layer 55a, the insulating layer 55b, and the insulating layer 55c. For the transistor 70, the description of the transistor 10 can be referred to.

[0275] A conductive layer 74a is provided on the insulating layer 11, insulating layers 40c and 40d are provided on the conductive layer 74a, a conductive layer 74b is provided covering the conductive layer 74a, the insulating layer 40c, and the insulating layer 40d, and insulating layers 55a, 55b, and 55c are stacked on the conductive layer 74b. The conductive layer 75a and the conductive layer 75b are provided on the insulating layer 55c. A semiconductor layer 71 and an insulating layer 72 are provided along the inner walls of openings 20e provided in the conductive layer 75a, the conductive layer 75b, the insulating layer 55a, the insulating layer 55b, and the insulating layer 55c. The semiconductor layer 71 is provided in contact with the top and side surfaces of the conductive layer 75b, the side surfaces of the conductive layer 75a, the insulating layer 55a, the insulating layer 55b, the insulating layer 55c, and the insulating layer 40d, and the top surface of the insulating layer 40d. The conductive layer 73 is provided so as to fill the insulating layer 56 and the opening 20e.

[0276] 15B and 15C, the conductive layer 73 corresponds to the gate of the transistor Tr2, the conductive layers 75a and 75b correspond to one of the wirings SL and RL, and the conductive layers 74a and 74b correspond to the other of the wirings SL and RL.

[0277] 16A and 16B show an example of a memory device in which two memory cells 30 are connected to a common wiring. Fig. 16A is a schematic top view of the memory device, and Fig. 16B is a schematic cross-sectional view taken along line A3-A4 in Fig. 16A.

[0278] The conductive layer 31 functioning as the wiring WL is provided for each of the two memory cells 30. The conductive layer 25a functioning as the wiring BL is provided in common to the two memory cells 30.

[0279] The conductive layer 25a functioning as the wiring BL is embedded in each interlayer insulating layer and is electrically connected to the conductive layers 61 and 62 functioning as plugs (also referred to as connection electrodes). The conductive layer 61 may be electrically connected to a sense amplifier (not shown) provided below the insulating layer 11. The conductive layer 61 may also be electrically connected to the conductive layer 32 of the memory cell stacked above the insulating layer 65.

[0280] The insulating layer 65 functions as a barrier layer and has a function of preventing impurities such as water and hydrogen from diffusing into the memory device from the outside.

[0281] Furthermore, a memory cell array can be configured by arranging the memory cells 30 in a three-dimensional matrix. As an example of a memory cell array, Figures 17A and 17B show an example of a memory device in which 4 x 2 x 4 memory cells 30 are arranged in the X, Y, and Z directions. Figure 17A is a plan view of the memory device, and Figure 17B is a cross-sectional view taken along the cutting line A3-A4 in Figure 17A.

[0282] A group of four memory cells 30 can be called a memory unit 60. 17A and 17B show eight memory units (memory unit 60[1,1] to memory unit 60[2,4]). In memory unit 60[a,b] (a and b are positive integers), a indicates an address in the Y direction, and b indicates an address in the Z direction.

[0283] In the memory unit 60, two memory cells 30 are arranged symmetrically around the conductive layer 61 or the conductive layer 62. The conductive layers 32 of the memory units 60 stacked in the Z direction are electrically connected to each other by the conductive layer 62. By stacking a plurality of memory units 60 in this way, it is possible to increase the storage capacity per unit area, and to provide a memory device that can be miniaturized or highly integrated.

[0284] 18A and 18B show an example in which the connection portion is arranged at the end of the memory unit. FIG. 18A is a plan view of the memory device, and FIG. 18B is a cross-sectional view. Here, as an example of a memory cell array, an example of a memory device in which 3 x 3 x m (m is an integer of 2 or more) memory cells 30 are arranged is shown. Of the layers having memory cells 30, the first layer is denoted as layer 80[1], and the mth layer (top) is denoted as layer 80[m].

[0285] The conductive layer 63 is provided outside the memory unit. The conductive layer 63 may be connected to wiring in a layer above the layer 80 including the conductive layer 63. For example, the conductive layer 63 provided in the layer 80[1] is electrically connected to wiring in the layer 80[2]. However, this is not limiting, and the conductive layer 63 may be configured to be electrically connected to wiring in the layer 80 located below the layer 80 including the conductive layer 63.

[0286] FIG. 19 shows an example of a cross-sectional configuration of a memory device in which a layer having memory cells 30 is stacked on a layer in which a driver circuit including a sense amplifier is provided.

[0287] 19 shows an example in which a capacitor 50 is stacked above a transistor 90, and the transistor 10 is stacked thereon. The transistor 90 is one of the transistors included in the sense amplifier.

[0288] By configuring the sense amplifier so that it overlaps with the memory cell 30, the bit line can be shortened. This reduces the load on the bit line, improving the read sensitivity of the sense amplifier. This allows the memory device to be driven at high speed.

[0289] The transistor 90 is provided over a substrate 91 and includes a conductive layer 94 functioning as a gate, an insulating layer 93 functioning as a gate insulating layer, a semiconductor region 92 formed of part of the substrate 91, and low-resistance regions 95 a and 95 b functioning as source and drain regions. The transistor 90 can be either a p-channel type or an n-channel type.

[0290] 19, a semiconductor region 92 (part of a substrate 91) where a channel is formed has a convex shape. A conductive layer 94 is provided to cover the side and top surfaces of the semiconductor region 92 with an insulating layer 93 interposed therebetween. Such a transistor 90 is also called a FIN transistor because it utilizes the convex portion of the semiconductor substrate.

[0291] A structure in which interlayer insulating layers and wiring layers are alternately stacked (also referred to as a multilayer wiring layer) is preferably provided between a layer in which the transistor 90 is provided and a layer in which the memory cell 30 is provided. In the example shown in Figure 19, the low-resistance region 95b of the transistor 90 is electrically connected to the conductive layer 32 functioning as a bit line of the memory cell 30 via a wiring and a plug.

[0292] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0293] Embodiment 3 In this embodiment, an oxide semiconductor layer that can be used as a semiconductor layer of a transistor will be described.

[0294] [Oxide Semiconductor Layer] The oxide semiconductor layer of one embodiment of the present invention preferably includes a crystalline metal oxide. Examples of the structure of a crystalline metal oxide include a c-axis aligned crystal (CAAC) structure, a polycrystalline (poly-crystal) structure, and a nanocrystalline (nc) structure. By using a crystalline metal oxide for the oxide semiconductor layer, the density of defect states in the oxide semiconductor layer can be reduced. Therefore, the reliability of a transistor including the oxide semiconductor layer of one embodiment of the present invention can be improved, and the reliability of a semiconductor device including the transistor can be improved.

[0295] The oxide semiconductor layer of one embodiment of the present invention preferably includes a metal oxide having a CAAC structure. The CAAC structure is a crystal structure in which a plurality of microcrystals (typically, a plurality of microcrystals having a hexagonal crystal structure) have c-axis orientation and are connected without being oriented in the a-b plane. Furthermore, when a cross section of an oxide semiconductor layer having a CAAC structure is observed using a high-resolution transmission electron microscope (TEM) image (also referred to as a multi-beam interference image), it can be confirmed that metal atoms are arranged in a layered manner in the crystal parts. Therefore, the oxide semiconductor layer having a CAAC structure can also be said to have a structure having layered crystal parts. When metal atoms are arranged in a layered manner in the crystal parts, a group of bright spots (specifically, bright spots arranged in a layered manner) reflecting the layered arrangement of the metal atoms is observed in a cross section of the oxide semiconductor layer observed using a TEM image.

[0296] For example, the CAAC structure is formed so that the c-axis is perpendicular or approximately perpendicular to the surface on which the metal is formed. In the CAAC structure, metal atoms are arranged in layers parallel or approximately parallel to the surface on which the metal is formed. In the region having the CAAC structure, the c-axis is preferably within 90°±20° (70° or more and 110° or less), more preferably within 90°±15° (75° or more and 105° or less), more preferably within 90°±10° (80° or more and 100° or less), and even more preferably within 90°±5° (85° or more and 95° or less) relative to the surface on which the metal is formed.

[0297] The crystallinity of the oxide semiconductor layer can be analyzed by, for example, X-ray diffraction (XRD), TEM, or electron diffraction (ED). Alternatively, a combination of these methods may be used for analysis.

[0298] When an oxide semiconductor layer having a CAAC structure is subjected to electron diffraction, spots (bright points) indicating c-axis orientation are observed in the electron diffraction pattern. The c-axis of the CAAC structure is preferably aligned in a direction parallel to a normal vector of a surface on which the oxide semiconductor layer is formed or a normal vector of the surface of the oxide semiconductor layer.

[0299] Furthermore, an FFT pattern obtained by subjecting a TEM image to a fast Fourier transform (FFT) process reflects reciprocal lattice space information similar to an electron diffraction pattern.

[0300] A cross-sectional TEM image of an oxide semiconductor layer having a CAAC structure is acquired, and an FFT process is performed on each region in the cross-sectional TEM image to create an FFT pattern. The crystal axis direction of each region can be calculated from the created FFT pattern. Specifically, the direction of a line segment connecting two spots that have high brightness and are approximately equidistant from the center among the spots observed in the created FFT pattern is defined as the crystal axis direction. Regions in which the crystal axis direction of each region calculated from the FFT pattern is preferably 70° to 110° (within 90°±20°) relative to the surface to be formed, more preferably 75° to 105° (within 90°±15°), more preferably 80° to 100° (within 90°±10°), and even more preferably 85° to 95° (within 90°±5°) can be considered to have a CAAC structure.

[0301] When an oxide semiconductor layer having a CAAC structure is viewed in a direction perpendicular to the surface on which it is formed using a TEM image, a triangular or hexagonal atomic arrangement is observed in the a-b plane, and the layer has crystallinity. Furthermore, in a Voronoi diagram created by image analysis of a TEM image obtained by observing an oxide semiconductor layer having a CAAC structure in a direction perpendicular to the surface on which it is formed, pentagonal, hexagonal, and heptagonal Voronoi regions are mainly observed, and hexagonal Voronoi regions are typically observed. For example, the proportion of hexagonal Voronoi regions among the Voronoi regions observed in the Voronoi diagram is 30% or more and less than 100%.

[0302] A method for creating a Voronoi diagram will now be described. First, image analysis of a TEM image involves performing FFT processing, filtering to leave only a certain range of information, and then performing an inverse fast Fourier transform to create an FFT-filtered image. Lattice points are extracted from the created FFT-filtered image, and perpendicular bisectors of line segments connecting adjacent lattice points are created. The points where three perpendicular bisectors intersect are defined as Voronoi points, and the polygonal regions enclosed by the lines connecting the Voronoi points are defined as Voronoi regions. In this way, a Voronoi diagram can be created.

[0303] As an example of the observation range of the TEM in creating a Voronoi diagram, a rectangular region of 50 nm in length and 50 nm in width can be observed, but the observation range is not limited to this.

[0304] Furthermore, when the distribution of the orientation of the hexagonal lattice is analyzed using lattice points extracted by image analysis of a planar TEM image, the difference in the orientation of the hexagonal lattice at the boundary between two structures with different hexagonal lattice orientations is small, and the boundary is observed to be blurred, and it appears that the two structures are connected in a manner that makes them intertwine. In other words, no clear boundary is observed in the CAAC structure.

[0305] The orientation of the hexagonal lattice can be calculated by calculating the orientation of a hexagon formed by the six lattice points closest to each lattice point.

[0306] Note that the crystallinity of the semiconductor material included in the oxide semiconductor layer is not particularly limited. For example, the oxide semiconductor layer may include one or more of an amorphous semiconductor (a semiconductor having an amorphous structure), a single-crystal semiconductor (a semiconductor having a single-crystal structure), or a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part). When the oxide semiconductor layer has crystallinity, deterioration of transistor characteristics can be suppressed in some cases.

[0307] The metal oxide according to one embodiment of the present invention preferably contains at least indium (In) or zinc (Zn), and particularly preferably contains indium as a main component. Here, the metal oxide contains indium as a main component and can further contain element M. Furthermore, the metal oxide preferably contains two or three elements selected from indium, element M, and zinc, and particularly preferably contains indium and zinc as main components. Here, the metal oxide contains indium and zinc as main components and can further contain element M. Note that element M is a metal element or a metalloid element having a high bond energy with oxygen, for example, a metal element or a metalloid element having a bond energy with oxygen higher than that of indium. Specific examples of the element M include aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium, and antimony. The element M contained in the metal oxide is preferably one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin, and yttrium, and even more preferably one or more selected from gallium and tin. When the element M contained in the metal oxide is gallium, the metal oxide according to one embodiment of the present invention preferably contains one or more selected from indium, gallium, and zinc. Note that in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements," and the "metal element" described in this specification and the like may also include metalloid elements.

[0308] In a cross section of the oxide semiconductor layer observed using a TEM image, it is confirmed that metal atoms are arranged in layers parallel or substantially parallel to the surface on which the oxide semiconductor layer is formed. For example, in a metal oxide containing indium, it is confirmed that indium is arranged in layers. Furthermore, for example, in a metal oxide containing indium and zinc, it is confirmed that indium and zinc are arranged in layers.

[0309] Examples of metal oxides according to one embodiment of the present invention include indium oxide, gallium oxide, zinc oxide, indium zinc oxide (In—Zn oxide), indium tin oxide (In—Sn oxide), indium titanium oxide (In—Ti oxide), indium gallium oxide (In—Ga oxide), indium gallium aluminum oxide (In—Ga—Al oxide), indium gallium tin oxide (In—Ga—Sn oxide, also referred to as IGTO), gallium zinc oxide (Ga—Zn oxide, also referred to as GZO), aluminum zinc oxide (Al—Zn oxide, Examples of usable oxides include indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), and indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO). Other examples include indium tin oxide containing silicon (also referred to as ITSO), gallium tin oxide (Ga-Sn oxide), and aluminum tin oxide (Al-Sn oxide).

[0310] By increasing the ratio of the number of indium atoms to the total number of atoms of all metal elements contained in the metal oxide, the transistor can have a large on-state current and high frequency characteristics.

[0311] Note that the metal oxide may contain one or more metal elements having a higher period number in the periodic table instead of indium. Alternatively, the metal oxide may contain one or more metal elements having a higher period number in the periodic table in addition to indium. The greater the overlap of the orbitals of metal elements, the greater the carrier conduction in the metal oxide tends to be. Therefore, including a metal element having a higher period number in the periodic table may improve the field-effect mobility of a transistor. Examples of metal elements having a higher period number in the periodic table include metal elements belonging to the fifth period and the sixth period. Specific examples of such metal elements include yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium. Note that lanthanum, cerium, praseodymium, neodymium, promethium, samarium, and europium are called light rare earth elements.

[0312] The metal oxide may also contain one or more nonmetallic elements, which may increase the field-effect mobility of the transistor. Examples of nonmetallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0313] Furthermore, by increasing the ratio of the number of zinc atoms to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the metal oxide can be made highly crystalline, and the diffusion of impurities in the metal oxide can be suppressed, thereby suppressing fluctuations in the electrical characteristics of the transistor and improving its reliability.

[0314] Furthermore, by increasing the ratio of the number of atoms of element M to the sum of the numbers of atoms of all metal elements contained in the metal oxide, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, carrier generation due to oxygen vacancies can be suppressed, and a transistor with a small off-state current can be obtained. Furthermore, fluctuations in the electrical characteristics of the transistor can be suppressed, thereby improving reliability.

[0315] The oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide using two types of film formation methods.

[0316] In the formation of an oxide semiconductor layer according to one embodiment of the present invention, a crystalline metal oxide is deposited by the first deposition method. The deposited metal oxide preferably has a CAAC structure. For example, a metal oxide deposited by a sputtering method is likely to have crystallinity.

[0317] When sputtering is used as the first film formation method, a mixed layer may be formed at the interface between the metal oxide and the layer on which the metal oxide is to be formed due to particles (also referred to as sputtering particles) emitted from a target or the like, or energy imparted to the substrate by the sputtering particles, etc. There is a concern that the mixed layer may inhibit the crystallization of the metal oxide.

[0318] For example, when silicon oxide is used as the surface to be formed, there is a risk that silicon may be mixed into the metal oxide when a metal oxide is formed on the silicon oxide by sputtering, which may hinder the crystallization of the metal oxide.

[0319] Therefore, in one embodiment of the present invention, a metal oxide is formed by a second film formation method before a metal oxide is formed by a first film formation method. That is, a metal oxide is formed as a first layer by the second film formation method, and then a metal oxide is formed as a second layer on the first layer by the first film formation method. In this case, it is preferable to use a film formation method that causes less damage to a surface on which the oxide semiconductor layer is to be formed than the first film formation method. This can suppress the formation of a mixed layer at the interface between the oxide semiconductor layer and the layer on which the oxide semiconductor layer is to be formed, thereby increasing the crystallinity. For example, an ALD method and a CVD method are suitable as the second film formation method because they can suppress damage to a surface on which the oxide semiconductor layer is to be formed compared to a sputtering method.

[0320] In addition, for example, a metal oxide having a microcrystalline structure or an amorphous structure with lower crystallinity than a CAAC structure may be formed as the first layer. By forming a second layer with high crystallinity on the first layer with low crystallinity or by performing heat treatment after the formation of the second layer, the crystallinity of the first layer may be increased using the second layer as a nucleus. This may increase the crystallinity of the entire oxide semiconductor layer, including the vicinity of the interface with the surface on which it is formed.

[0321] The first film formation method may be, for example, a sputtering method or a PLD method.

[0322] Examples of the second film formation method include an ALD method, a plasma enhanced CVD (PECVD) method, a thermal CVD method, a photo-assisted CVD method, a metal organic CVD (MOCVD) method, and a molecular beam epitaxy (MBE) method. A wet method can also be used as the second film formation method. Examples of the wet method include a spray coating method.

[0323] For example, the oxide semiconductor layer of one embodiment of the present invention can be formed by forming a metal oxide as a first layer by an ALD method and then forming a metal oxide as a second layer by a sputtering method. The metal oxide formed by a sputtering method preferably has a CAAC structure.

[0324] Furthermore, a third layer can be further formed on the second layer. Because the second layer has high crystallinity, the third layer can grow crystals using the crystals of the second layer as nuclei or seeds. Therefore, even if a film formation method that easily imparts crystallinity is not used as a film formation method for the third layer, the third layer can be crystallized. Here, for example, by forming the third layer using a film formation method that has higher coverage than the second layer, the oxide semiconductor layer can have both high crystallinity and high coverage throughout the layer.

[0325] Furthermore, the second layer has excellent crystallinity because the influence of the surface on which it is formed is reduced by providing the first layer, and therefore the third layer, which is crystallized using the second layer as a nucleus or seed, is also expected to have excellent crystallinity.

[0326] The third layer is an uppermost layer of the oxide semiconductor layer, and is in contact with, for example, a gate insulating film when the oxide semiconductor layer is used as a semiconductor layer of a transistor. By increasing the crystallinity of the layer in contact with the gate insulating film, carrier mobility can be increased when the transistor is in an on state.

[0327] For example, the oxide semiconductor layer of one embodiment of the present invention can be manufactured by forming metal oxides for the first and third layers by the same second deposition method and forming metal oxide for the second layer by the first deposition method. Specifically, an ALD method can be used as the second deposition method, and a sputtering method can be used as the first deposition method.

[0328] [Method for Forming Oxide Semiconductor Layer] An example of a method for forming the oxide semiconductor layer 230 will be described with reference to FIGS. 20A to 21D.

[0329] The oxide semiconductor layer 230 can be manufactured, for example, by forming an oxide semiconductor 230a over a layer 229 that is a surface to be formed by an ALD method, forming an oxide semiconductor 230b on the oxide semiconductor 230a by a sputtering method, and forming an oxide semiconductor 230c on the oxide semiconductor 230b by an ALD method. After the oxide semiconductor layer 230 is formed, heat treatment is preferably performed. The heat treatment can improve the crystallinity of the oxide semiconductor layer 230. The heat treatment here is not limited to heat treatment. For example, heat applied during the manufacturing process may be used. The layer 229 is an insulating film, such as a silicon oxide film, a silicon oxynitride film, a silicon nitride film, a silicon nitride oxide film, an aluminum oxide film, or a hafnium oxide film.

[0330] The oxide semiconductor layer 230 can be used for the semiconductor layer 21 included in each transistor described in Embodiment 1. The layer 229 corresponds to one or more of the insulating layer 40b, the conductive layer 24b, the insulating layer 41a, the insulating layer 41b, the insulating layer 41c, the conductive layer 25a, and the conductive layer 25b, which are described in Embodiment 1.

[0331] The layer 229 does not need to be crystalline. When the layer 229 is crystalline, it may have a crystal structure with low lattice matching with a metal oxide contained in the oxide semiconductor layer 230.

[0332] First, an oxide semiconductor 230a is formed on the layer 229 (FIG. 20A). Then, an oxide semiconductor 230b is formed on the oxide semiconductor 230a (FIG. 20B).

[0333] The oxide semiconductor 230b is preferably formed by a sputtering method and has a composition suitable for forming a CAAC structure.

[0334] The oxide semiconductor 230a is preferably formed by a deposition method that causes less damage to a surface on which the oxide semiconductor 230a is formed than the deposition method for the oxide semiconductor 230b. Here, the oxide semiconductor 230a is formed by an ALD method.

[0335] When a metal oxide film is formed by sputtering, a region where a component contained in the metal oxide film and a component contained in the layer on which the film is formed are alloyed may be formed as a mixed layer. In this case, it is difficult to improve the crystallinity of the alloyed region even if a heat treatment is performed later. Furthermore, an oxide semiconductor layer having a mixed layer may adversely affect the initial characteristics or reliability of a transistor. Therefore, it is preferable to suppress the formation of the mixed layer.

[0336] With this structure, the thickness of the mixed layer can be thinned or thinned to the extent that the mixed layer cannot be observed. For example, the thickness of the mixed layer can be set to 0 nm or more and 3 nm or less, preferably 0 nm or more and 2 nm or less, more preferably 0 nm or more and 1 nm or less, and further preferably 0 nm or more and less than 0.3 nm. Note that FIGS. 20A and 20B show an example in which a mixed layer is not formed between the layer 229 and the oxide semiconductor 230a.

[0337] The thickness of the mixed layer may be calculated by performing a line analysis of the composition by energy dispersive X-ray spectroscopy (EDX) or SIMS on the region and its surroundings.

[0338] For example, EDX line analysis is performed on the region and its periphery, with the direction perpendicular to the surface of the oxide semiconductor 230a being the depth direction. Next, in the profile of the quantitative values ​​of each element in the depth direction obtained by this analysis, the depth at which the quantitative value of a metal (e.g., In if the oxide semiconductor 230a contains In) that is the main component of the oxide semiconductor 230a but is not the main component of the layer that will become the surface (here, layer 229) becomes half-maximum is defined as the depth (position) of the interface between the region and the oxide semiconductor 230a. Furthermore, the depth at which the quantitative value of an element (e.g., Si) that is the main component of the layer that will become the surface but is not the main component of the oxide semiconductor 230a becomes half-maximum is defined as the depth (position) of the interface between the region and the layer that will become the surface. From the above, the thickness of the mixed layer can be calculated.

[0339] In the oxide semiconductor layer of one embodiment of the present invention, when the thickness of the mixed layer is observed by EDX analysis, the thickness is, for example, 0 nm to 3 nm, preferably 0 nm to 2 nm, more preferably 0 nm to 1 nm, and still more preferably 0 nm to less than 0.3 nm.

[0340] For example, when a silicon oxide layer is used as the layer 229 and SIMS analysis is performed on the oxide semiconductor layer 230 formed on the layer 229, the depth at which the silicon concentration is 50% of the maximum concentration of the layer 229 is defined as the interface, and the silicon concentration is 1.0×10 ２１ atoms / cm ３ , preferably 5.0 × 10 ２０ atoms / cm ３ , more preferably 1.0 × 10 ２０ atoms / cm ３ The distance between the interface and the depth at which the surface is reduced to the depth at which the surface is reduced can be measured. This distance is preferably 3 nm or less, and more preferably 2 nm or less.

[0341] Note that by reducing the thickness of the mixed layer, it is possible to form the CAAC structure near the formation surface. Here, the vicinity of the formation surface refers to, for example, a region of the oxide semiconductor layer 230 that is approximately perpendicular to the formation surface and is located at a distance of more than 0 nm and not more than 3 nm, preferably more than 0 nm and not more than 2 nm, more preferably 1 nm or more and not more than 2 nm.

[0342] When the oxide semiconductor 230a is formed by an ALD method, an oxide semiconductor layer having a microcrystalline structure or an amorphous structure, which has lower crystallinity than the CAAC structure, may be formed. That is, at the manufacturing stage shown in FIG. 20A , the oxide semiconductor 230a may have a region having lower crystallinity than the oxide semiconductor 230b.

[0343] After the oxide semiconductor 230a is formed, microwave plasma treatment is preferably performed.

[0344] In this specification, microwaves refer to electromagnetic waves having a frequency of 300 MHz to 300 GHz. Microwave plasma treatment refers to treatment using a device with a power source that generates high-density plasma using microwaves. Microwave plasma treatment can also be called microwave-excited high-density plasma treatment.

[0345] It is preferable to perform microwave plasma treatment in an atmosphere containing oxygen to reduce the impurity concentration in the oxide semiconductor layer 230. Examples of impurities include hydrogen and carbon. Although the above example illustrates a structure in which microwave plasma treatment is performed on a metal oxide in an atmosphere containing oxygen, the present invention is not limited to this. For example, microwave plasma treatment may be performed on an insulating film, more specifically, a silicon oxide film, provided near the metal oxide in an atmosphere containing oxygen. Furthermore, the heat generated by the microwave plasma treatment may increase the crystallinity of the oxide semiconductor layer.

[0346] The microwave plasma treatment is preferably carried out under reduced pressure, with the pressure preferably being 10 Pa to 1000 Pa, and more preferably being 300 Pa to 700 Pa. The microwave plasma treatment is preferably carried out in a heated state, with the temperature being room temperature (e.g., 25°C) to 500°C, preferably 100°C to 500°C, more preferably 200°C to 500°C, even more preferably 300°C to 500°C, and even more preferably 400°C to 500°C. For example, the temperature can be 400°C to 450°C.

[0347] Alternatively, after the microwave plasma treatment, a heat treatment may be performed successively without exposure to the outside air. The heat treatment temperature is, for example, preferably 100° C. or higher and 750° C. or lower, more preferably 300° C. or higher and 500° C. or lower, and even more preferably 400° C. or higher and 450° C. or lower.

[0348] The microwave plasma treatment can be performed using, for example, oxygen gas and argon gas. By performing the microwave plasma treatment in an atmosphere containing oxygen, the oxygen gas can be converted into plasma using high frequency waves, and the generated oxygen radicals can act on the oxide semiconductor layer. Due to the action of the plasma, microwaves, oxygen radicals, and the like, defects in which hydrogen has entered oxygen vacancies in the oxide semiconductor layer (hereinafter referred to as V Ｏ In this way, V contained in the oxide semiconductor layer can be separated into oxygen vacancies and hydrogen, and the hydrogen can be removed from the oxide semiconductor layer. ＯIn addition, carbon bonded to oxygen or hydrogen can be removed in some cases. Thus, impurities such as carbon or hydrogen can be reduced by performing microwave plasma treatment. Furthermore, oxygen vacancies in the oxide semiconductor layer can be reduced by supplying the oxygen radicals to the oxide semiconductor layer.

[0349] Furthermore, microwave plasma treatment is expected to improve the crystallinity of the oxide semiconductor 230a through the following mechanism. First, active species such as oxygen radicals excited by microwaves arrive at the surface of the oxide semiconductor, and a substitution reaction occurs between the active species and oxygen in the oxide semiconductor. At this time, nuclei or seeds are formed. Furthermore, lateral growth of the nuclei or seeds is induced. Note that it is preferable that the active species excited by microwaves contain oxygen (typically, oxygen ions), which is easily adsorbed to the side surfaces of the nuclei or seeds, because this lateral growth is promoted. Microwave plasma treatment causes the formation of nuclei or seeds and the lateral growth of the nuclei or seeds, improving the crystallinity of the oxide semiconductor.

[0350] On the other hand, a reaction occurs between part of the oxygen in the oxide semiconductor that exists before the microwave plasma treatment and hydrogen in the oxide semiconductor, in other words, the reaction proceeds as follows: 2H + O → H ２ O↑” reaction occurs, converting the hydrogen to H ２ O (also called dehydration or dehydrogenation). ２ Since O is one of the factors that hinder improvement of crystallinity, it is preferable to remove O from the oxide semiconductor. ２ The hydrogen concentration in the oxide semiconductor can be reduced by removing the hydrogen as O, which can also promote improvement in crystallinity. Note that the hydrogen concentration in the oxide semiconductor can be further reduced by increasing the temperature during the microwave plasma treatment.

[0351] Instead of the microwave plasma treatment, the crystallinity can also be improved by plasma treatment containing oxygen gas.

[0352] The increased crystallinity of the oxide semiconductor 230a can further increase the crystallinity of the oxide semiconductor 230b formed over the oxide semiconductor 230a, thereby increasing the crystallinity of the entire oxide semiconductor layer.

[0353] Oxygen supplied to the oxide semiconductor layer can be in various forms, such as oxygen atoms, oxygen molecules, oxygen ions (charged oxygen atoms or oxygen molecules), and oxygen radicals (oxygen atoms, oxygen molecules, or oxygen ions having an unpaired electron). Note that the oxygen injected into the oxide semiconductor layer may be one or more of the above forms, and oxygen radicals are particularly preferred.

[0354] After the oxide semiconductor 230a is formed by an ALD method, an In-M-Zn oxide is formed as the oxide semiconductor 230b over the oxide semiconductor 230a by a sputtering method.

[0355] Here, when the oxide semiconductor 230b is formed by sputtering, the mixed layer 231 is formed on or near the surface of the oxide semiconductor 230a. Furthermore, when the oxide semiconductor 230b is formed, sputtering particles or energy imparted to the substrate by the sputtering particles or the like may form minute crystalline regions in the mixed layer 231. In a subsequent heat treatment step, the mixed layer 231 or the minute crystalline regions formed in the mixed layer 231 may act as nuclei, causing at least a part of the oxide semiconductor 230a to crystallize.

[0356] In-M-Zn oxide can be used as a target for sputtering. When forming a metal oxide by sputtering, oxygen or a mixed gas of oxygen and a noble gas can be used as the sputtering gas. In addition, by increasing the proportion of oxygen contained in the sputtering gas, the excess oxygen in the oxide film to be formed can be increased. In addition, a metal oxide with high crystallinity can be formed.

[0357] When a metal oxide is formed by a sputtering method, an oxygen-excess metal oxide may be formed when the percentage of oxygen contained in the sputtering gas is set to more than 30% and less than or equal to 100%, preferably 70% to 100%. A transistor using an oxygen-excess oxide semiconductor layer for a channel formation region can have relatively high reliability. However, one embodiment of the present invention is not limited thereto. An oxygen-deficient metal oxide is formed when the percentage of oxygen contained in the sputtering gas is set to 1% to 30%, preferably 5% to 20%. A transistor using an oxygen-deficient metal oxide for a channel formation region can have relatively high field-effect mobility.

[0358] In the formation of the oxide semiconductor 230b by a sputtering method, it is preferable to heat the substrate. In the formation of the metal oxide, a metal oxide with high crystallinity can be formed by increasing the substrate temperature (stage temperature) during the formation of the metal oxide. In the formation of the oxide semiconductor 230b by a sputtering method, the substrate heating temperature is preferably, for example, 100°C or higher and 400°C or lower, and more preferably 200°C or higher and 300°C or lower.

[0359] Through the above steps, as shown in FIG. 20B, an oxide semiconductor 230a and an oxide semiconductor 230b can be formed over the layer 229.

[0360] Next, the oxide semiconductor 230c is formed on the oxide semiconductor 230b (FIG. 20C). Here, the oxide semiconductor 230c is formed by an ALD method. For the formation of the oxide semiconductor 230c by the ALD method, the method for forming the oxide semiconductor 230a can be referred to.

[0361] When the oxide semiconductor 230c is formed on the oxide semiconductor 230b having the CAAC structure by the ALD method, the oxide semiconductor 230c may grow epitaxially around the oxide semiconductor 230b as a nucleus. Therefore, when the oxide semiconductor 230c is formed, the oxide semiconductor 230c may have a region having the CAAC structure. In addition, the region having the CAAC structure is preferably formed over the entire oxide semiconductor 230c.

[0362] Next, a heat treatment step may be carried out.

[0363] The heat treatment temperature may be, for example, 100° C. to 800° C., preferably 250° C. to 650° C., and more preferably 350° C. to 550° C. Typically, the heat treatment temperature can be 400° C.±25° C. (375° C. to 425° C.). The treatment time can be 10 hours or less, or 1 minute to 5 hours, or 1 minute to 2 hours. When an RTA apparatus is used, the treatment time can be, for example, 1 second to 5 minutes. It is expected that the heat treatment can repair atomic-level gaps in the crystal portions of the CAAC structure of the oxide semiconductor 230b with the oxide semiconductor 230c (in other words, crystal molecules formed by the ALD method).

[0364] The heating device used for the heat treatment is not particularly limited, and may be a device that heats the workpiece by thermal conduction or thermal radiation from a heating element such as a resistance heating element. For example, an electric furnace or an RTA (Rapid Thermal Anneal) device such as an LRTA (Lamp Rapid Thermal Anneal) device or a GRTA (Gas Rapid Thermal Anneal) device can be used. An LRTA device is a device that heats the workpiece by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, metal halide lamp, xenon arc lamp, carbon arc lamp, high-pressure sodium lamp, or high-pressure mercury lamp. A GRTA device is a device that performs heat treatment using high-temperature gas.

[0365] The heat treatment may increase the crystallinity of the region having the CAAC structure in the oxide semiconductor 230c. Furthermore, if the region is formed only below the oxide semiconductor 230c after deposition by the ALD method, the heat treatment may cause the region to expand upward ( FIG. 20D ). That is, the heat treatment may cause the region having the CAAC structure to be formed throughout the entire layer of the oxide semiconductor 230c.

[0366] Furthermore, it is preferable that at least a portion of the oxide semiconductor 230a is converted into CAAC by the heat treatment ( FIG. 20D ). It is expected that the CAAC conversion is facilitated by the mixed layer 231 formed in the oxide semiconductor 230a during the deposition of the oxide semiconductor 230b, which acts as a nucleus or seed. It is preferable that the region in the oxide semiconductor 230a that is converted into CAAC is wide, and it is preferable that the CAAC conversion extend to the vicinity of the layer 229.

[0367] Furthermore, because the CAAC is formed from the top to the bottom of the oxide semiconductor 230a, the CAAC can be formed up to the vicinity of the layer 229 regardless of the material or crystallinity of the layer 229. For example, even if the layer 229 has an amorphous structure, the oxide semiconductor 230a can have high crystallinity. Therefore, the method for forming an oxide semiconductor layer according to one embodiment of the present invention is particularly suitable for the case where a layer on which the oxide semiconductor layer is formed has an amorphous structure.

[0368] After the oxide semiconductor layer 230c is formed, microwave plasma treatment may be performed. By performing one or both of the heat treatment and the microwave plasma treatment, the crystallinity of the entire oxide semiconductor layer can be increased.

[0369] In this manner, the impurities in the oxide semiconductor layer can be reduced. When crystal growth is performed in a state where the impurity concentration in the oxide semiconductor layer is reduced, the crystallinity can be further improved.

[0370] Note that one or both of the heat treatment and the microwave plasma treatment may be performed directly on the oxide semiconductor layer or may be performed after an insulating film or the like is formed over the oxide semiconductor layer.

[0371] As described above, in the method for forming a metal oxide film according to one embodiment of the present invention, the crystallinity of the upper and lower oxide semiconductors (the oxide semiconductor 230a and the oxide semiconductor 230c here) can be increased by using the oxide semiconductor 230b (i.e., CAAC) with high crystallinity as a nucleus or seed. This increases the crystallinity of the entire oxide semiconductor. In other words, the upper and lower oxide semiconductors can be grown by solid-phase growth using the oxide semiconductor 230b as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed by such a film formation method, that is, a CAAC film here, can be referred to as an axial growth CAAC (AG CAAC).

[0372] In the oxide semiconductor layer 230, it is preferable that a region having a CAAC structure is widely present throughout the layer. FIG. 21A shows the crystallization of the oxide semiconductors 230a, 230b, and 230c. The region having the CAAC structure of the oxide semiconductor 230a is crystalline and connected to the region having the CAAC structure of the oxide semiconductor 230b. The region having the CAAC structure of the oxide semiconductor 230c is crystalline and connected to the region having the CAAC structure of the oxide semiconductor 230b. As a result, the boundary between the oxide semiconductors 230a and 230b and the boundary between the oxide semiconductors 230b and 230c may not be observed. The oxide semiconductor layer 230 may be expressed as a single layer or a layer whose interface is not clearly observed. The interface between the two stacked films may be observed using, for example, a cross-sectional TEM, a cross-sectional scanning transmission electron microscope (STEM), or the like.

[0373] In each of the oxide semiconductors 230a, 230b, and 230c, bright spots aligned parallel or approximately parallel to the surface on which the oxide semiconductor layer 230 is formed are confirmed in cross-sectional observation using a high-resolution TEM. Furthermore, the c-axis of the CAAC structure of each of the oxide semiconductors 230a, 230b, and 230c is preferably approximately parallel to the normal direction of the surface on which the oxide semiconductor layer 230 is formed.

[0374] Furthermore, there are cases where a portion of the oxide semiconductor 230a or the oxide semiconductor 230c is not crystallized. The example shown in Fig. 21B illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a is not crystallized. Fig. 21C illustrates a state in which the vicinity of the surface in the oxide semiconductor 230c is not crystallized. Fig. 21D illustrates a state in which the vicinity of the interface with the layer 229 in the oxide semiconductor 230a and the vicinity of the surface of the oxide semiconductor 230c are not crystallized.

[0375] By increasing the crystallinity of the oxide semiconductor layer, it is expected that an increase in the electrical resistance of the semiconductor layer of a transistor using the oxide semiconductor layer can be suppressed or the initial characteristics (particularly, on-state current) of the transistor can be improved, thereby making the transistor suitable for high-speed operation.In addition, the reliability of the transistor can be improved and the on-state current can be increased.

[0376] As described above, the use of a metal oxide with a high In content in a transistor can increase the field-effect mobility of the transistor. On the other hand, an oxide semiconductor with a high In content tends to become polycrystalline. The use of a metal oxide with a polycrystalline structure in a transistor adversely affects the initial characteristics or reliability of the transistor. Therefore, by using an oxide semiconductor with a high In content in one or both of the oxide semiconductors 230a and 230c, crystals that reflect the crystal orientation of the oxide semiconductor 230b are formed, thereby suppressing polycrystallization.

[0377] Furthermore, it is preferable that the lattice mismatch between the crystals of the oxide semiconductor 230b and the crystals of the oxide semiconductor 230a or the oxide semiconductor 230c is small. This allows the oxide semiconductor 230a or the oxide semiconductor 230c to form crystals that reflect the orientation of the crystals of the oxide semiconductor 230b. In this case, for example, in cross-sectional observation of the oxide semiconductor layer 230 using a high-resolution TEM, bright spots arranged in layers in a direction parallel to the formation surface are observed in the oxide semiconductor 230a or the oxide semiconductor 230c.

[0378] The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c is not particularly limited as long as the lattice mismatch between the crystal of the oxide semiconductor 230b and the crystal of the oxide semiconductor 230a or the oxide semiconductor 230c is small. The crystal structure of the oxide semiconductor 230a or the oxide semiconductor 230c may be any of cubic, tetragonal, orthorhombic, hexagonal, monoclinic, and trigonal.

[0379] Note that when one or both of microwave plasma treatment and heat treatment are performed in the step of forming the oxide semiconductor layer 230, it may not be necessary to form the oxide semiconductor 230b. For example, as described above, by performing one or both of microwave plasma treatment and heat treatment after forming the oxide semiconductor 230a, the crystallinity of the oxide semiconductor 230a can be increased, and the crystallinity of the oxide semiconductor 230c can be increased using the oxide semiconductor 230a as a nucleus or seed. Furthermore, by performing one or both of microwave plasma treatment and heat treatment after forming the oxide semiconductor 230c, the crystallinity of the oxide semiconductor layer 230 can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer 230.

[0380] For example, by providing the metal oxide layer as the layer 229, the crystallinity of the oxide semiconductor 230a can be increased by using the metal oxide layer as a nucleus or a seed. Furthermore, by performing microwave plasma treatment or heat treatment or both after forming the oxide semiconductor 230a and after forming the oxide semiconductor 230c, the crystallinity of the oxide semiconductor layer 230 can be increased. Therefore, a CAAC structure can be formed in the oxide semiconductor layer 230.

[0381] As described above, even in a structure in which the oxide semiconductor 230b is not provided, the oxide semiconductor above can be grown by solid-phase growth using the layer 229 or the oxide semiconductor 230a as a nucleus or seed, thereby forming an oxide semiconductor with high crystallinity. An oxide semiconductor formed using such a deposition method can also be called an AG CAAC. That is, the AG CAAC can be formed without using the first deposition method. In other words, the AG CAAC can also be formed using the second deposition method (e.g., an ALD method or a CVD method) and one or both of microwave plasma treatment and heat treatment.

[0382] [Composition of Oxide Semiconductor Layer] The oxide semiconductor 230a preferably has a different composition from the oxide semiconductor 230b. The oxide semiconductor 230c preferably has a different composition from the oxide semiconductor 230b. The oxide semiconductor 230a may have the same composition as the oxide semiconductor 230c. Alternatively, the oxide semiconductor 230a and the oxide semiconductor 230c may have different compositions.

[0383] As described above, the oxide semiconductor 230b preferably has a composition suitable for forming a CAAC structure. The oxide semiconductor 230b can be formed by, for example, a sputtering method. The oxide semiconductor 230b preferably contains, for example, zinc. By containing zinc, the oxide semiconductor 230b becomes a metal oxide with high crystallinity. Furthermore, the oxide semiconductor 230b preferably contains the element M in addition to zinc. By containing the element M in the oxide semiconductor 230b, for example, oxygen vacancies can be suppressed from being formed in the metal oxide. Therefore, the reliability of a transistor using an oxide semiconductor layer can be improved. Specifically, the oxide semiconductor 230b may be a metal oxide having an atomic ratio of In:M:Zn = 1:1:1 or a similar composition, an atomic ratio of In:M:Zn = 1:1:1.2 or a similar composition, an atomic ratio of In:M:Zn = 1:1:0.5 or a similar composition, an atomic ratio of In:M:Zn = 1:1:2 or a similar composition, an atomic ratio of In:M:Zn = 4:2:3 or a similar composition, an atomic ratio of In:M:Zn = 1:3:2 or a similar composition, or an atomic ratio of In:M:Zn = 1:3:4 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Furthermore, it is preferable to use one or more of gallium, aluminum, and tin as the element M.

[0384] The oxide semiconductor 230b may not contain the element M. For example, it may be an In—Zn oxide. Specifically, it may have a composition with an atomic ratio of In:Zn=1:1 or a composition thereabout, an atomic ratio of In:Zn=2:1 or a composition thereabout, or an atomic ratio of In:Zn=4:1 or a composition thereabout. Alternatively, indium oxide may be used. Furthermore, it may have a composition containing a trace amount of the element M. For example, it may have a composition with an atomic ratio of In:Ga:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Ga:Zn=2:0.1:1 or a composition thereabout. Furthermore, it may have a composition with an atomic ratio of In:Sn:Zn=4:0.1:1 or a composition thereabout, or an atomic ratio of In:Sn:Zn=2:0.1:1 or a composition thereabout.

[0385] The oxide semiconductor 230a and the oxide semiconductor 230c can be a metal oxide having a high proportion of In. The oxide semiconductor 230a and the oxide semiconductor 230c can be formed by, for example, an ALD method. In particular, it is preferable to use a metal oxide having a higher proportion of In than the element M. By using a metal oxide having a high proportion of In, when the oxide semiconductor layer is used in a transistor, the on-state current and frequency characteristics can be increased.

[0386] Alternatively, the oxide semiconductors 230a and 230c may not contain the element M. For example, they may be In-Zn oxides. Specifically, they may have a composition of In:Zn=1:1 (atomic ratio) or a composition therearound, a composition of In:Zn=2:1 (atomic ratio) or a composition therearound, or a composition of In:Zn=4:1 (atomic ratio) or a composition therearound. Alternatively, indium oxide may be used. The oxide semiconductors 230a and 230c may contain a trace amount of the element M. Specifically, the composition may be In:Ga:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, In:Ga:Zn=2:0.1:1 (atomic ratio) or a composition close thereto, In:Sn:Zn=4:0.1:1 (atomic ratio) or a composition close thereto, or In:Sn:Zn=2:0.1:1 (atomic ratio) or a composition close thereto.

[0387] The oxide semiconductors 230a and 230c can be metal oxides containing a higher proportion of In than the oxide semiconductor 230b.

[0388] For example, metal oxides having a higher Ga content than the oxide semiconductor 230b can be used for the oxide semiconductors 230a and 230c. For example, the oxide semiconductors 230a and 230c are preferably made of metal oxides having an atomic ratio of In:Ga:Zn=1:1:1 or a composition thereabout, metal oxides having an atomic ratio of In:Ga:Zn=1:3:2 or a composition thereabout, or metal oxides having an atomic ratio of In:Ga:Zn=1:3:4 or a composition thereabout. Increasing the Ga content can sometimes make the band gaps of the oxide semiconductors 230a and 230c larger than those of the oxide semiconductor 230b. As a result, the oxide semiconductor 230b is sandwiched between the oxide semiconductors 230a and 230c, which have larger band gaps, and the oxide semiconductor 230b mainly functions as a current path (channel). The oxide semiconductor 230b is sandwiched between the oxide semiconductor 230a and the oxide semiconductor 230c, which reduces trap states at the interface of the oxide semiconductor 230b and in the vicinity thereof. This makes it possible to realize a buried-channel transistor in which the channel is located away from the insulating layer interface, thereby increasing the field-effect mobility. Furthermore, the influence of interface states that may be formed on the back channel side is reduced, which suppresses light degradation of the transistor (e.g., negative-bias light degradation) and improves the reliability of the transistor.

[0389] Alternatively, one of the oxide semiconductors 230a and 230c may be a metal oxide having a higher In content than the oxide semiconductor 230b, and the other may be a metal oxide having a higher Ga content than the oxide semiconductor 230b.

[0390] Each of the oxide semiconductors 230a, 230b, and 230c may have a stack of layers having the above-described compositions. For example, the oxide semiconductor 230c may have a structure in which a metal oxide having a high Ga content is stacked on a metal oxide having a high In content.

[0391] In the oxide semiconductor layer of one embodiment of the present invention, even when the oxide semiconductors 230a and 230c have compositions that make it difficult to form a CAAC structure when a single layer is formed, crystal growth occurs using the oxide semiconductor 230b as a nucleus, so that the entire oxide semiconductor layer including the oxide semiconductors 230a and 230c can have the CAAC structure. Alternatively, the CAAC structure can be formed in a region including at least a part of the oxide semiconductor 230a and the oxide semiconductor 230c and the oxide semiconductor 230b.

[0392] In particular, even when the oxide semiconductor 230 a and the oxide semiconductor 230 c have a high In content, the oxide semiconductor layer can have suitable crystallinity for a transistor. In the oxide semiconductor layer of one embodiment of the present invention, the increase in the In content can improve the on-state characteristics of the transistor, and the improvement in reliability can be achieved by using a CAAC structure with high crystallinity.

[0393] The oxide semiconductors 230a and 230c may be made of a metal oxide having the same composition as the oxide semiconductor 230b. Using the same composition may make it easier for CAAC to occur after heat treatment.

[0394] Furthermore, an oxide semiconductor layer having a CAAC structure formed using the above-described two types of film formation methods may have higher relative dielectric constant, film density, and film hardness or both than an oxide semiconductor layer having a CAAC structure formed using one type of film formation method.

[0395] By using an oxide semiconductor layer having a CAAC structure formed by using the above two types of film formation methods for a channel formation region of a transistor, a transistor with excellent characteristics (e.g., a transistor with high on-state current, a transistor with high field-effect mobility, a transistor with a small S value, a transistor with high frequency characteristics (also referred to as f characteristics), a highly reliable transistor, etc.) can be realized.

[0396] The composition of the metal oxide used in the oxide semiconductor layer 230 can be analyzed by, for example, EDX, XPS, inductively coupled plasma-mass spectrometry (ICP-MS), or inductively coupled plasma-atomic emission spectrometry (ICP-AES). Alternatively, the analysis may be performed by combining a plurality of these techniques. Note that for elements with low content, the actual content and the content obtained by analysis may differ due to the influence of analytical accuracy. For example, when the content of element M is low, the content of element M obtained by analysis may be lower than the actual content.

[0397] [Oxide Semiconductor Layer of Transistor] The oxide semiconductor layer of one embodiment of the present invention can be used as a semiconductor layer of a transistor.

[0398] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure, in which metal atoms are arranged in a layered manner in a direction parallel to or substantially parallel to a surface on which the oxide semiconductor layer is formed.

[0399] In the semiconductor device of one embodiment of the present invention, the oxide semiconductor layer 230 has metal atoms arranged in layers parallel to or substantially parallel to the formation surface. It can also be expressed as the a-b plane of the CAAC structure being provided in a direction parallel to or substantially parallel to the formation surface. Here, even when the formation surface is substantially perpendicular to the substrate surface, the oxide semiconductor layer 230 has metal atoms arranged in layers in a direction substantially parallel to the formation surface. With this structure, the a-b plane of the CAAC structure can be provided along the direction of current flow in the channel of the transistor. This can increase the on-state current of the transistor.

[0400] When the oxide semiconductor layer 230 is used as a semiconductor layer of a transistor, the thickness of the oxide semiconductor layer 230 is, for example, preferably 3 nm to 200 nm, more preferably 3 nm to 100 nm, further preferably 5 nm to 100 nm, further preferably 10 nm to 100 nm, further preferably 10 nm to 70 nm, further preferably 15 nm to 70 nm, further preferably 15 nm to 50 nm, and further preferably 20 nm to 50 nm. Furthermore, in a transistor used in a smaller semiconductor device, the thickness of the oxide semiconductor layer 230 is preferably 1 nm to 3 nm, or 5 nm, and is preferably 20 nm to 15 nm, 12 nm to 10 nm, or 10 nm to 1 nm. Furthermore, the average thickness of the oxide semiconductor layer 230 in a channel formation region of the transistor is particularly preferably, for example, 2 nm to 15 nm.

[0401] The oxide semiconductor 230b preferably has a thickness of, for example, 200 nm or less. When the oxide semiconductor 230b has a layer shape, the thickness is preferably, for example, 1 nm to 200 nm, more preferably 1 nm to 100 nm, and even more preferably 2 nm to 100 nm.

[0402] Alternatively, if the oxide semiconductor 230b can function as a crystal nucleus, the oxide semiconductor 230b may not exist as a layer but may be an aggregate of island-like regions. In such a case, for example, the island-like regions of the oxide semiconductor 230b exist discretely.

[0403] The oxide semiconductor 230a and the oxide semiconductor 230c each have a thickness of, for example, preferably 0.5 nm to 50 nm, more preferably 0.5 nm to 30 nm, more preferably 0.5 nm to 20 nm, more preferably 1 nm to 50 nm, more preferably 1 nm to 30 nm, more preferably 1 nm to 20 nm, and more preferably 2 nm to 20 nm. The oxide semiconductor 230a is further preferably 0.5 nm to 3 nm.

[0404] [Impurities in Oxide Semiconductor] Here, the influence of each impurity in an oxide semiconductor will be described.

[0405] It is preferable that the channel formation region of a transistor using an oxide semiconductor for a semiconductor layer have fewer oxygen vacancies or a lower concentration of impurities such as hydrogen, nitrogen, or metal elements than the source and drain regions. Ｏ ) and impurities, the electrical characteristics are likely to fluctuate and reliability may be reduced. Ｏ H may be formed, and electrons that serve as carriers may be generated. Therefore, when oxygen vacancies are present in the channel formation region of the oxide semiconductor, the transistor tends to have normally-on characteristics. Ｏ It is preferable that H is also reduced. In this way, the channel formation region of the transistor is a high-resistance region with a low carrier concentration. Therefore, the channel formation region of the transistor can be said to be i-type (intrinsic) or substantially i-type.

[0406] Therefore, reducing the impurity concentration in the oxide semiconductor is effective for stabilizing the electrical characteristics of a transistor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, carbon, and nitrogen. Note that the impurity in the oxide semiconductor refers to, for example, any element other than the main component constituting the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be considered an impurity.

[0407] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the carbon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10１９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The silicon concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ Less than or equal to 3×10, more preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 3×10, more preferably １８ atoms / cm ３ More preferably, 1×10 １８ atoms / cm ３ The following applies.

[0408] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. Therefore, the nitrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Below 5 × 10, preferably １９ atoms / cm ３ or less, more preferably 1 × 10 １９ atoms / cm ３ Less than or equal to 5 × 10, more preferably １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ The following applies.

[0409] Furthermore, hydrogen contained in an oxide semiconductor reacts with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. Hydrogen entering the oxygen vacancy may generate electrons as carriers. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen as much as possible in the channel formation region of the oxide semiconductor. Specifically, the hydrogen concentration in the channel formation region of the oxide semiconductor obtained by SIMS is 1×10 ２０ atoms / cm ３ Less than 5×10 １９ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ less than 1×10 １７ atoms / cm ３ Less than.

[0410] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. Therefore, when the concentration of the alkali metal or the alkaline earth metal in the channel formation region of the oxide semiconductor obtained by SIMS is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0411] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0412] [C-Axis Orientation Rate] The oxide semiconductor layer of one embodiment of the present invention has a CAAC structure. The crystallinity of the oxide semiconductor layer of one embodiment of the present invention can be evaluated using, for example, crystal orientation.

[0413] The crystal orientation can be obtained from a Fast Fourier Transform (FFT) pattern obtained by performing FFT processing on a TEM image. Specifically, the direction of the crystal axis can be obtained using the FFT pattern. The FFT pattern obtained by FFT processing reflects reciprocal lattice space information similar to that of an electron diffraction pattern.

[0414] By performing FFT processing on each region in a TEM image of an oxide semiconductor layer, the crystal orientation of each region can be obtained. For example, by obtaining the crystal orientation for each region within a certain area, a map showing the crystal orientation can be formed. Specifically, two spots with high intensity are observed in the FFT pattern of a region having a layered crystalline portion. The direction of the crystal axis of the region can be obtained from the angle of the line segment connecting the two spots.

[0415] The c-axis orientation rate can be calculated by calculating the proportion of c-axis oriented regions in a map showing the crystal orientation. Here, the c-axis oriented regions are defined as regions where the orientation coincides with the c-axis, and regions where the difference from the c-axis is preferably within 20 degrees, more preferably within 15 degrees, more preferably within 10 degrees, and even more preferably within 5 degrees. Here, the angle of the c-axis is defined as the angle with respect to the surface to be formed.

[0416] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation ratio can be calculated, for example, by performing TEM observation of a cross section or a plan view of the oxide semiconductor layer and using the map showing the crystal orientation described above. The region where FFT is performed (also referred to as an FFT window) can be, for example, a circle with a diameter of 1.0 nm. Note that the region where FFT is performed is not limited to a circle.

[0417] Furthermore, when performing analysis using a cross-sectional TEM image, the observation range of the cross-sectional TEM image can be, for example, a region with a width of 100 nm in the horizontal direction, with the direction perpendicular to the surface to be formed being the vertical direction. However, the observation range is not limited to this.

[0418] In the oxide semiconductor layer of one embodiment of the present invention, the c-axis orientation rate is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and still more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of a region whose orientation angle with respect to the c-axis is within 20°, for example.

[0419] The c-axis orientation rates of the region where the oxide semiconductor 230a is formed, the region where the oxide semiconductor 230b is formed, and the region where the oxide semiconductor 230c is formed are denoted by Rc1, Rc2, and Rc3, respectively. Rc2 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Rc3 / Rc1 is preferably greater than 1. Rc2 / Rc1 is preferably greater than 1. Here, the c-axis orientation rate is preferably calculated as the percentage of a region where the difference from the c-axis is within 20°, for example.

[0420] After the oxide semiconductor layer 230 is formed, the boundaries between the oxide semiconductors 230a, 230b, and 230c may not be clearly observed.

[0421] The oxide semiconductor layer 230 of one embodiment of the present invention can be divided into three regions, a first region, a second region, and a third region, starting from the top of the layer 229. Each region has a layer shape.

[0422] The first region, the second region, and the third region each have a CAAC structure. The c-axis orientation rate of the third region is preferably higher than that of the first region. The c-axis orientation rate of the second region is preferably higher than that of the first region. The c-axis orientation rate of the third region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. The c-axis orientation rate of the second region is preferably 50% or more, more preferably 60% or more, more preferably 70% or more, more preferably 80% or more, more preferably 90% or more, and even more preferably 95% or more. Here, the c-axis orientation rate is preferably calculated as the percentage of regions within a 20° difference from the c-axis, for example.

[0423] The first region is located at a distance of 0 nm to 3 nm from the top surface of the layer 229 , and the third region is located at a distance of 0 nm to 3 nm from the top surface of the oxide semiconductor layer 230 .

[0424] Alternatively, the layer thickness in each region may be, for example, approximately the same.

[0425] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0426] 22 to 25. In this embodiment, a configuration example of a memory device in which a layer having memory cells is stacked over a layer in which a driver circuit including a sense amplifier is provided will be described.

[0427] 22 is a block diagram illustrating a configuration example of a memory device 480 according to one embodiment of the present invention. The memory device 480 illustrated in FIG. 22 includes a layer 420 and a stacked layer 470.

[0428] The layer 420 is a layer including a Si transistor. The layer 470 includes stacked element layers 430[1] to 430[m] (m is an integer of 2 or more). The element layers 430[1] to 430[m] include OS transistors. The layer 470 including stacked layers including OS transistors can be provided over the layer 420.

[0429] Elements such as OS transistors and capacitors included in the element layers 430[1] to 430[m] constitute memory cells. In FIG. 22 , the element layers 430[1] to 430[m] each include a plurality of memory cells 432 arranged in a matrix of m rows and n columns (n ​​is an integer of 2 or greater).

[0430] In FIG. 22 , the memory cell 432 in the first row and first column is indicated as memory cell 432[1,1], and the memory cell 432 in the mth row and nth column is indicated as memory cell 432[m,n]. In addition, in this embodiment and the like, an arbitrary row may be referred to as row i. In addition, an arbitrary column may be referred to as column j. Therefore, i is an integer greater than or equal to 1 and less than or equal to m, and j is an integer greater than or equal to n. In addition, in this embodiment and the like, the memory cell 432 in the ith row and jth column is indicated as memory cell 432[i,j]. In addition, in this embodiment and the like, when "i+α" (α is a positive or negative integer) is used, "i+α" is not less than 1 or more than m. Similarly, when "j+α" is used, "j+α" is not less than 1 or more than n.

[0431] 22 illustrates, as an example, m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In this embodiment and the like, the first wiring WL (first row) is referred to as wiring WL[1], and the mth wiring WL (mth row) is referred to as wiring WL[m]. Similarly, the first wiring PL (first row) is referred to as wiring PL[1], and the mth wiring PL (mth row) is referred to as wiring PL[m]. Similarly, the first wiring BL (first column) is referred to as wiring BL[1], and the nth wiring BL (nth column) is referred to as wiring BL[n]. Note that the number of element layers 430[1] to 430[m] and the number of wirings WL (and wirings PL) do not necessarily have to be the same.

[0432] The memory cells 432 in the i-th row are electrically connected to the wiring WL in the i-th row (wiring WL[i]) and the wiring PL in the i-th row (wiring PL[i]). The memory cells 432 in the j-th column are electrically connected to the wiring BL in the j-th column (wiring BL[j]).

[0433] The wiring BL functions as a bit line for writing and reading data. The wiring WL functions as a word line for controlling the on / off (conducting state or non-conducting state) of an access transistor that functions as a switch. The wiring PL functions as a constant potential line connected to a capacitor. Note that a wiring for transmitting a back gate potential can be provided separately.

[0434] The memory cells 432 included in each of the element layers 430[1] to 430[m] are connected to a sense amplifier 446 (sense amplifier) ​​via a wiring BL. The wiring BL can be arranged in a direction parallel to or perpendicular to the surface of the substrate on which the layer 420 is provided. The wiring BL extending from the memory cells 432 included in the element layers 430[1] to 430[m] can be configured as wirings arranged vertically in addition to wirings arranged horizontally on the surface of the substrate, thereby shortening the length of the wiring between the element layer 430 and the sense amplifier 446. The signal propagation distance between the memory cell and the sense amplifier can be shortened, and the resistance and parasitic capacitance of the bit line can be significantly reduced, thereby reducing power consumption and signal delay. This can reduce the power consumption and signal delay of the memory device 480. Furthermore, the memory cell 432 can operate even if the capacitance of the capacitor included in the memory cell 432 is reduced. This can reduce the size of the memory device 480.

[0435] The layer 420 includes a PSW 471 (power switch), a PSW 472, and a peripheral circuit 422. The peripheral circuit 422 includes a drive circuit 440, a control circuit 473, and a voltage generation circuit 474. Each circuit included in the layer 420 includes a Si transistor.

[0436] In the memory device 480, each circuit, signal, and voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or signals may be added. The signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are input signals from the outside, and the signal RDA is an output signal to the outside. The signal CLK is a clock signal.

[0437] Furthermore, signals BW, CE, and GW are control signals. Signal CE is a chip enable signal, signal GW is a global write enable signal, and signal BW is a byte write enable signal. Signal ADDR is an address signal. Signal WDA is write data, and signal RDA is read data. Signals PON1 and PON2 are power gating control signals. Note that signals PON1 and PON2 may be generated by the control circuit 473.

[0438] The control circuit 473 is a logic circuit having the function of controlling the overall operation of the memory device 480. For example, the control circuit performs a logical operation on the signals CE, GW, and BW to determine the operation mode (e.g., write operation, read operation) of the memory device 480. Alternatively, the control circuit 473 generates a control signal for the drive circuit 440 so that this operation mode is executed.

[0439] The voltage generation circuit 474 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generation circuit 474. For example, when an H-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 474, and the voltage generation circuit 474 generates a negative voltage.

[0440] The driver circuit 440 is a circuit for writing and reading data to and from the memory cells 432. The driver circuit 440 includes a row decoder 442, a column decoder 444, a row driver 443, a column driver 445, an input circuit 447, an output circuit 448, and the sense amplifier 446 described above.

[0441] The row decoder 442 and the column decoder 444 have a function of decoding the signal ADDR. The row decoder 442 is a circuit for specifying a row to be accessed, and the column decoder 444 is a circuit for specifying a column to be accessed. The row driver 443 has a function of selecting a wiring WL specified by the row decoder 442. The column driver 445 has a function of writing data to the memory cell 432, a function of reading data from the memory cell 432, a function of holding the read data, and the like.

[0442] The input circuit 447 has a function of holding a signal WDA. The data held by the input circuit 447 is output to the column driver 445. The output data of the input circuit 447 is data (Din) to be written to the memory cell 432. The data (Dout) read from the memory cell 432 by the column driver 445 is output to the output circuit 448. The output circuit 448 has a function of holding Dout. In addition, the output circuit 448 has a function of outputting Dout to the outside of the memory device 480. The data output from the output circuit 448 is a signal RDA.

[0443] The PSW 471 has a function of controlling the supply of VDD to the peripheral circuit 422. The PSW 472 has a function of controlling the supply of VHM to the row driver 443. In this example, the high power supply voltage of the memory device 480 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to set the word line to a high level and is higher than VDD. The on / off of the PSW 471 is controlled by a signal PON1, and the on / off of the PSW 472 is controlled by a signal PON2. In FIG. 22, the number of power domains to which VDD is supplied in the peripheral circuit 422 is one, but multiple domains may also be used. In this case, a power switch may be provided for each power domain.

[0444] The element layers 430[1] to 430[m] can be stacked on the layer 420. Figure 23A is a perspective view of a memory device 480 showing five (m = 5) element layers 430[1] to 430[5] stacked on the layer 420.

[0445] 23A, the element layer 430 provided in the first layer is shown as element layer 430[1], the element layer 430 provided in the second layer is shown as element layer 430[2], and the element layer 430 provided in the fifth layer is shown as element layer 430[5]. Also shown in FIG. 23A are wirings WL and PL extending in the X direction, and wirings BL and BLB extending in the Y direction and Z direction (directions perpendicular to the substrate surface on which the driver circuit is provided). The wiring BLB is an inverted bit line. Note that, to make the drawing easier to understand, the wirings WL and PL included in each element layer 430 are partially omitted.

[0446] 23B is a schematic diagram illustrating a configuration example of the sense amplifier 446 connected to the wiring BL and the wiring BLB shown in FIG. 23A and the memory cells 432 included in the element layers 430[1] to 430[5] connected to the wiring BL and the wiring BLB. Note that a configuration in which a plurality of memory cells (memory cells 432) are electrically connected to one wiring BL and one wiring BLB is also referred to as a "memory string."

[0447] 23B illustrates an example of a circuit configuration of the memory cell 432 connected to the wiring BLB. The memory cell 432 includes a transistor 437 and a capacitor 438. Regarding the transistor 437, the capacitor 438, and the wirings (BL, WL, etc.), for example, the wiring BL[1] and the wiring WL[1] may also be referred to as wiring BL and wiring WL. The memory cell 30 exemplified in the above embodiment can be applied to the memory cell 432, for example. That is, the transistor 10 can be used as the transistor 437, and the capacitor 50 can be used as the capacitor 438. The transistor 90 (see FIG. 18 ) can be used as the transistor included in the sense amplifier 446.

[0448] In the memory cell 432, one of the source and the drain of the transistor 437 is connected to a wiring BL. The other of the source and the drain of the transistor 437 is connected to one electrode of a capacitor 438. The other electrode of the capacitor 438 is connected to a wiring PL. The gate of the transistor 437 is connected to a wiring WL.

[0449] The wiring PL is a wiring that applies a constant potential for maintaining the potential of the capacitor 438. The number of wirings can be reduced by connecting a plurality of wirings PL to each other and using them as one wiring.

[0450] In one embodiment of the present invention, OS transistors are stacked, and a wiring functioning as a bit line is arranged perpendicular to the surface of the substrate on which the layer 420 is provided. Additionally, the transistor 437 and the capacitor 438 included in the memory cell 432 are arranged side by side in the perpendicular direction to the surface of the substrate on which the layer 420 is provided. By providing each element and each wiring perpendicular to the surface of the substrate, the length of the wiring between element layers can be shortened and the density of elements provided per unit area can be increased. Therefore, a memory device with excellent storage capacity and reduced power consumption can be obtained.

[0451] 24A and 24B show circuit diagrams corresponding to the memory cell 432 described above and circuit block diagrams corresponding to the circuit diagrams. As shown in FIGS. 24A and 24B, the memory cell 432 may be represented as a block in the drawings. Note that the wiring BL shown in FIGS. 24A and 24B can be represented in the same manner even when replaced with wiring BLB.

[0452] 24C and 24D show a circuit diagram corresponding to the sense amplifier 446 and a circuit block diagram corresponding to the circuit diagram. The sense amplifier 446 includes a switch circuit 482, a precharge circuit 483, a precharge circuit 484, and an amplifier circuit 485. In addition to the wiring BL and the wiring BLB, the wirings SA_OUT and SA_OUTB for outputting read signals are also shown.

[0453] 24C, the switch circuit 482 includes, for example, n-channel transistors 482_1 and 482_2. The transistors 482_1 and 482_2 switch the conduction state between the wiring pair of the wiring SA_OUT and the wiring SA_OUTB and the wiring pair of the wiring BL and the wiring BLB in response to the signal CSEL.

[0454] 24C, the precharge circuit 483 is formed of n-channel transistors 483_1 to 483_3. The precharge circuit 483 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQ.

[0455] 24C, the precharge circuit 484 is formed of p-channel transistors 484_1 to 484_3. The precharge circuit 484 is a circuit for precharging the wiring BL and the wiring BLB to an intermediate potential VPRE corresponding to a potential VDD / 2 in response to a signal EQB.

[0456] 24C , the amplifier circuit 485 includes p-channel transistors 485_1 and 485_2 and n-channel transistors 485_3 and 485_4 connected to a wiring SAP or a wiring SAN. The wiring SAP or the wiring SAN has a function of supplying VDD or VSS. The transistors 485_1 to 485_4 are transistors that form an inverter loop.

[0457] Moreover, Fig. 24D shows a circuit block diagram corresponding to the sense amplifier 446 described in Fig. 24C etc. As shown in Fig. 24D, the sense amplifier 446 may be represented as a block in the drawings etc.

[0458] Fig. 25 is a circuit diagram of the memory device 480 of Fig. 22. Fig. 25 illustrates the circuit blocks described in Fig. 24A to Fig. 24D.

[0459] 25, the layer 470 including the element layer 430[m] includes a memory cell 432. The memory cell 432 illustrated in FIG. 25 is connected to a pair of wirings BL[1] and BLB[1] or a pair of wirings BL[2] and BLB[2], for example. The memory cell 432 connected to the wiring BL is a memory cell to which data is written or read.

[0460] The wiring BL[1] and the wiring BLB[1] are connected to a sense amplifier 446[1], and the wiring BL[2] and the wiring BLB[2] are connected to a sense amplifier 446[2]. The sense amplifier 446[1] and the sense amplifier 446[2] can read data in response to various signals described with reference to FIG.

[0461] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0462] Embodiment 5 In this embodiment, a structural example of a display device to which a transistor of one embodiment of the present invention can be applied will be described.

[0463] Since the transistor of one embodiment of the present invention can be made extremely small, a display device using the transistor of one embodiment of the present invention can have extremely high resolution. For example, the display device of one embodiment of the present invention can be used in a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, and a head-mounted display (HMD), such as a glasses-type AR device.

[0464] 26A shows a perspective view of display module 280. Display module 280 has a display device 200A and an FPC 290. Note that the display panel of display module 280 is not limited to display device 200A, and may be a display device 200B or a display device 200C, which will be described later.

[0465] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is an area for displaying an image.

[0466] 26B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 composed of a plurality of wirings.

[0467] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 26B. The pixel 284a has a light-emitting element 110R that emits red light, a light-emitting element 110G that emits green light, and a light-emitting element 110B that emits blue light.

[0468] The pixel circuit portion 283 has a plurality of pixel circuits 283a arranged periodically. Each pixel circuit 283a is a circuit that controls the light emission of three light-emitting devices included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display panel.

[0469] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 282 may constitute a part of the pixel circuit 283a. That is, the pixel circuit 283a may be composed of a transistor included in the pixel circuit portion 283 and a transistor included in the circuit portion 282.

[0470] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0471] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0472] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays, or in glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0473] Display Device 200A The display device 200A shown in FIG. 27 includes a substrate 331, a light emitting element 110R, a light emitting element 110G, a light emitting element 110B, a capacitor 240, and a transistor 320.

[0474] Substrate 331 corresponds to substrate 291 in FIG. 26A.

[0475] The transistor 320 is a vertical channel transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed, and includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a conductive layer 325, and a conductive layer 326.

[0476] Any of the various transistors exemplified in Embodiment 1 can be used as the transistor 320 .

[0477] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0478] A conductive layer 327 is provided over the insulating layer 332, an insulating layer 329 is provided over the conductive layer 327, and a conductive layer 325 is provided over the insulating layer 329 and the conductive layer 327. An insulating layer 334 is provided over the conductive layer 325, and a conductive layer 326 is provided over the insulating layer 334. Openings reaching the insulating layer 329 are provided in the insulating layer 334 and the conductive layer 325, and a semiconductor layer 321 and an insulating layer 323 are provided in the openings. An insulating layer 263 is provided over the insulating layer 323, and a conductive layer 327 is provided in the opening provided in the insulating layer 263. A conductive layer 328 in contact with the top surface of the conductive layer 327 is provided over the insulating layer 263. An insulating layer 264 is provided to cover the conductive layer 328.

[0479] The insulating layer 264 functions as an interlayer insulating layer. A barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 264 or the like to the transistor 320 may be provided between the insulating layer 264 and the insulating layer 254. An insulating film similar to the insulating layer 332 can be used as the barrier layer.

[0480] A plug 274 electrically connected to one of the conductive layers 326 is provided so as to be embedded in the insulating layer 264 and the insulating layer 263. Here, the plug 274 preferably has a conductive layer 274a covering the side surface of the opening of the insulating layer 264 and part of the top surface of the conductive layer 326, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, it is preferable to use a conductive material through which hydrogen and oxygen do not easily diffuse as the conductive layer 274a.

[0481] Furthermore, a capacitor 240 is provided on the insulating layer 264. The capacitor 240 has a conductive layer 241, a conductive layer 245, and an insulating layer 243 located therebetween. The conductive layer 241 functions as one electrode of the capacitor 240, the conductive layer 245 functions as the other electrode of the capacitor 240, and the insulating layer 243 functions as a dielectric of the capacitor 240.

[0482] The conductive layer 241 is provided over the insulating layer 264 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to the conductive layer 326 of the transistor 320 by a plug 274. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0483] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided over the insulating layer 255a, and an insulating layer 255c is provided over the insulating layer 255b.

[0484] An inorganic insulating film can be preferably used for each of the insulating layers 255a, 255b, and 255c. For example, it is preferable to use a silicon oxide film for the insulating layer 255a and the insulating layer 255c, and a silicon nitride film for the insulating layer 255b. This allows the insulating layer 255b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 255c is etched to form a recess, but the insulating layer 255c does not necessarily have to have a recess.

[0485] The light emitting elements 110R, 110G, and 110B are provided on the insulating layer 255c.

[0486] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0487] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0488] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 112R, 112G, and 112B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0489] In the region between adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0490] The pixel electrodes 111R, 111G, and 111B of the light-emitting element are electrically connected to the conductive layer 326 of the transistor 320 via a plug 256 embedded in the insulating layers 255a, 255b, and 255c, a conductive layer 241 embedded in the insulating layer 254, and a plug 274. The height of the top surface of the insulating layer 255c and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0491] A protective layer 121 is provided on the light emitting elements 110R, 110G, and 110B. A substrate 170 is attached to the protective layer 121 with an adhesive layer 171.

[0492] There is no insulating layer covering the upper end of each pixel electrode 111 between two adjacent pixel electrodes 111. This allows the distance between adjacent light-emitting elements to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0493] [Display Device 200B] The following describes a display device that has a configuration that is partially different from that described above. Note that parts that are common to the above will be referred to, and descriptions thereof may be omitted.

[0494] 28 shows an example in which a transistor 320A, which is a planar transistor having a semiconductor layer formed on a plane, and a transistor 320B, which is a vertical channel transistor, are stacked. The transistor 320B has a similar configuration to the transistor 320 in the display device 200A.

[0495] The transistor 320A includes a semiconductor layer 351 , an insulating layer 353 , a conductive layer 354 , a pair of conductive layers 355 , an insulating layer 356 , and a conductive layer 357 .

[0496] An insulating layer 352 is provided over the substrate 331. The insulating layer 352 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 351 toward the insulating layer 352. The insulating layer 352 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0497] A conductive layer 357 is provided over the insulating layer 352, and an insulating layer 356 is provided to cover the conductive layer 357. The conductive layer 357 functions as a first gate electrode of the transistor 320A, and part of the insulating layer 356 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 356 that is in contact with the semiconductor layer 351. The top surface of the insulating layer 356 is preferably planarized.

[0498] The semiconductor layer 351 is provided over the insulating layer 356. The semiconductor layer 351 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 355 is provided over and in contact with the semiconductor layer 351 and functions as a source electrode and a drain electrode.

[0499] An insulating layer 358 and an insulating layer 350 are provided to cover top surfaces and side surfaces of the pair of conductive layers 355 and side surfaces of the semiconductor layer 351. The insulating layer 358 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the semiconductor layer 351 and prevents oxygen from being released from the semiconductor layer 351. The insulating layer 358 can be formed using an insulating film similar to the insulating layer 352.

[0500] An opening reaching the semiconductor layer 351 is provided in the insulating layer 358 and the insulating layer 350. An insulating layer 353 in contact with a top surface of the semiconductor layer 351 and a conductive layer 354 are buried in the opening. The conductive layer 354 functions as a second gate electrode, and the insulating layer 353 functions as a second gate insulating layer.

[0501] The top surfaces of the conductive layer 354, the insulating layer 353, and the insulating layer 350 are planarized so that their heights are the same or approximately the same, and an insulating layer 359 is provided to cover them. The insulating layer 359 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing into the transistor 320. The insulating layer 359 can be formed using an insulating film similar to the insulating layer 352.

[0502] The transistor 320 has a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the transistor may be driven by supplying the same signal to them. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0503] [Display Device 200C] A display device 200C shown in FIG. 29 has a stacked structure of a transistor 310 having a channel formed in a semiconductor substrate and a vertical channel transistor 320.

[0504] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as one of a source and a drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0505] An element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0506] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0507] In this embodiment, a structural example of a display device that can be used for a display device manufactured using a transistor of one embodiment of the present invention will be described. The display device exemplified below can be used for the pixel portion 284 in Embodiment 4, for example.

[0508] In one embodiment of the present invention, an EL layer is processed into a fine pattern by photolithography without using a shadow mask such as a fine metal mask (FMM). This makes it possible to realize a display device with high definition and a large aperture ratio, which have been difficult to achieve until now. Furthermore, since the EL layer can be individually fabricated, a display device with extremely vivid images, high contrast, and high display quality can be realized. Note that, for example, the EL layer may be processed into a fine pattern using both a metal mask and photolithography.

[0509] Furthermore, the EL layer can be partially or entirely separated physically. This can suppress leakage current between adjacent light-emitting elements through a layer shared between the light-emitting elements (also referred to as a common layer). This can prevent crosstalk caused by unintended light emission, thereby realizing a display device with extremely high contrast. In particular, a display device with high current efficiency at low luminance can be realized.

[0510] One embodiment of the present invention can also be a display device that combines a white-emitting light-emitting element and a color filter. In this case, light-emitting elements provided in pixels (subpixels) that emit light of different colors can have the same configuration, and all layers can be common layers. Furthermore, part or all of each EL layer can be separated by photolithography. This suppresses leakage current through the common layer, thereby achieving a display device with high contrast. In particular, in an element having a tandem structure in which multiple light-emitting layers are stacked via a highly conductive intermediate layer, leakage current through the intermediate layer can be effectively prevented, thereby achieving a display device that combines high brightness, high definition, and high contrast.

[0511] When the EL layer is processed by photolithography, a portion of the light-emitting layer may be exposed, which may cause deterioration. Therefore, it is preferable to provide an insulating layer that covers at least the side surfaces of the island-shaped light-emitting layer. The insulating layer may also be configured to cover a portion of the top surface of the island-shaped EL layer. The insulating layer is preferably made of a material that has barrier properties against water and oxygen. For example, an inorganic insulating film that is less likely to diffuse water or oxygen can be used. This suppresses deterioration of the EL layer, thereby achieving a highly reliable display device.

[0512] Furthermore, there is a region (recess) between two adjacent light-emitting elements where the EL layer of either light-emitting element is not provided. When a common electrode, or a common electrode and a common layer, is formed to cover the recess, a phenomenon in which the common electrode is separated by a step at the edge of the EL layer (also called a step discontinuity) may occur, resulting in insulation of the common electrode on the EL layer. Therefore, it is preferable to use a configuration in which the local step located between two adjacent light-emitting elements is filled with a resin layer functioning as a planarization film (also called LFP: Local Filling Planarization). The resin layer functions as a planarization film. This suppresses step discontinuity of the common layer or common electrode, thereby achieving a highly reliable display device.

[0513] A more specific example of the structure of the display device of one embodiment of the present invention will be described below with reference to the drawings.

[0514] 30A is a schematic top view of a display device 100 of one embodiment of the present invention. The display device 100 includes a plurality of light-emitting elements 110R that exhibit red light, a plurality of light-emitting elements 110G that exhibit green light, and a plurality of light-emitting elements 110B that exhibit blue light, over a substrate 101. In FIG. 30A , the symbols R, G, and B are assigned within the light-emitting regions of the light-emitting elements to easily distinguish them from one another.

[0515] The light emitting elements 110R, 110G, and 110B are arranged in a matrix. Fig. 30A shows a so-called stripe arrangement in which light emitting elements of the same color are arranged in one direction. Note that the arrangement method of the light emitting elements is not limited to this, and arrangement methods such as an S-stripe arrangement, a delta arrangement, a Bayer arrangement, or a zigzag arrangement may also be used, or a pentile arrangement, a diamond arrangement, or the like may also be used.

[0516] As the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B, for example, an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode) is preferably used. Examples of the light-emitting substance contained in the EL element include a substance that emits fluorescence (fluorescent material), a substance that emits phosphorescence (phosphorescent material), and a substance that exhibits thermally activated delayed fluorescence (thermally activated delayed fluorescence: TADF material). As the light-emitting substance contained in the EL element, not only organic compounds but also inorganic compounds (such as quantum dot materials) can be used.

[0517] 30A also shows a connection electrode 111C that is electrically connected to the common electrode 113. The connection electrode 111C is given a potential (e.g., an anode potential or a cathode potential) to be supplied to the common electrode 113. The connection electrode 111C is provided outside the display area where the light-emitting elements 110R and the like are arranged.

[0518] The connection electrode 111C can be provided along the periphery of the display area. For example, it may be provided along one side of the periphery of the display area, or it may be provided over two or more sides of the periphery of the display area. That is, when the top surface shape of the display area is rectangular, the top surface shape of the connection electrode 111C can be a strip shape (rectangle), an L-shape, a U-shape (square bracket shape), a square shape, or the like.

[0519] 30B and 30C are schematic cross-sectional views corresponding to dashed dotted lines A1-A2 and A3-A4 in Fig. 30A, respectively. Fig. 30B shows a schematic cross-sectional view of light-emitting element 110R, light-emitting element 110G, and light-emitting element 110B, and Fig. 30C shows a schematic cross-sectional view of connection portion 140 where connection electrode 111C and common electrode 113 are connected.

[0520] The light-emitting element 110R has a pixel electrode 111R, an organic layer 112R, a common layer 114, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111G, an organic layer 112G, a common layer 114, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111B, an organic layer 112B, a common layer 114, and a common electrode 113. The common layer 114 and the common electrode 113 are provided in common to the light-emitting element 110R, the light-emitting element 110G, and the light-emitting element 110B.

[0521] The organic layer 112R of the light-emitting element 110R contains a light-emitting organic compound that emits at least red light. The organic layer 112G of the light-emitting element 110G contains a light-emitting organic compound that emits at least green light. The organic layer 112B of the light-emitting element 110B contains a light-emitting organic compound that emits at least blue light. The organic layer 112R, the organic layer 112G, and the organic layer 112B can also be called EL layers, and each contains at least a layer (light-emitting layer) that contains a light-emitting organic compound.

[0522] Hereinafter, when describing matters common to light emitting element 110R, light emitting element 110G, and light emitting element 110B, they may be referred to as light emitting element 110. Similarly, when describing matters common to components distinguished by alphabets, such as organic layer 112R, organic layer 112G, and organic layer 112B, they may be described using symbols without the alphabets.

[0523] The organic layer 112 and the common layer 114 may each independently include one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer. For example, the organic layer 112 may have a stacked structure of a hole injection layer, a hole transport layer, a light-emitting layer, and an electron transport layer from the pixel electrode 111 side, and the common layer 114 may have an electron injection layer.

[0524] The pixel electrode 111R, pixel electrode 111G, and pixel electrode 111B are provided for each light-emitting element. The common electrode 113 and common layer 114 are provided as a continuous layer common to each light-emitting element. A conductive film transmissive to visible light is used for either the pixel electrode or the common electrode 113, and a conductive film reflective to visible light is used for the other. By making each pixel electrode transmissive and the common electrode 113 reflective, a bottom-emission display device can be obtained. Conversely, by making each pixel electrode reflective and the common electrode 113 transmissive, a top-emission display device can be obtained. Note that by making both the pixel electrodes and the common electrode 113 transmissive, a dual-emission display device can be obtained.

[0525] A protective layer 121 is provided on the common electrode 113 to cover the light emitting elements 110R, 110G, and 110B. The protective layer 121 has a function of preventing impurities such as water from diffusing from above into each light emitting element.

[0526] The edge of the pixel electrode 111 preferably has a tapered shape. When the edge of the pixel electrode 111 has a tapered shape, the organic layer 112 provided along the edge of the pixel electrode 111 can also have a tapered shape. By tapering the edge of the pixel electrode 111, the coverage of the organic layer 112 provided over the edge of the pixel electrode 111 can be improved. Furthermore, by tapering the side surface of the pixel electrode 111, foreign matter (for example, also referred to as dust or particles) during the manufacturing process can be easily removed by a process such as cleaning, which is preferable.

[0527] For example, it is preferable to have a region where the angle between the inclined side surface and the substrate surface (also called the taper angle) is less than 90°.

[0528] The organic layer 112 is processed into an island shape by photolithography. As a result, the angle between the top surface and the side surface of the organic layer 112 at its edge is close to 90 degrees. On the other hand, an organic film formed using a fine metal mask (FMM) or the like tends to become gradually thinner as it approaches the edge. For example, the top surface is formed in a sloped shape over a range of 1 μm to 10 μm up to the edge, making it difficult to distinguish between the top surface and the side surface.

[0529] Between two adjacent light emitting elements, an insulating layer 125, a resin layer 126, and a layer 128 are provided.

[0530] Between two adjacent light-emitting elements, the side surfaces of the organic layers 112 face each other with the resin layer 126 sandwiched therebetween. The resin layer 126 is located between the two adjacent light-emitting elements and is provided so as to fill the ends of each organic layer 112 and the region between the two organic layers 112. The resin layer 126 has a smooth, convex upper surface, and a common layer 114 and a common electrode 113 are provided to cover the upper surface of the resin layer 126.

[0531] The resin layer 126 functions as a planarization film that fills in a step between two adjacent light-emitting elements. By providing the resin layer 126, it is possible to prevent a phenomenon (also called step disconnection) in which the common electrode 113 is divided by a step at the end of the organic layer 112, resulting in insulation of the common electrode on the organic layer 112. The resin layer 126 can also be called an LFP (Local Filling Planarization) layer.

[0532] An insulating layer containing an organic material can be suitably used as the resin layer 126. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, precursors of these resins, etc. can be used as the resin layer 126. Alternatively, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral, polyvinylpyrrolidone, polyethylene glycol, polyglycerin, pullulan, water-soluble cellulose, or alcohol-soluble polyamide resin can be used as the resin layer 126.

[0533] Furthermore, a photosensitive resin can be used as the resin layer 126. A photoresist can be used as the photosensitive resin. The photosensitive resin can be a positive-type material or a negative-type material.

[0534] The resin layer 126 may contain a material that absorbs visible light. For example, the resin layer 126 itself may be made of a material that absorbs visible light, or the resin layer 126 may contain a pigment that absorbs visible light. For example, the resin layer 126 may be a resin that can be used as a color filter that transmits red, blue, or green light and absorbs other light, or a resin that contains carbon black as a pigment and functions as a black matrix.

[0535] The insulating layer 125 is provided in contact with the side surface of the organic layer 112. The insulating layer 125 is also provided to cover the upper end portion of the organic layer 112. A portion of the insulating layer 125 is provided in contact with the upper surface of the substrate 101.

[0536] The insulating layer 125 is located between the resin layer 126 and the organic layer 112, and functions as a protective film to prevent the resin layer 126 from contacting the organic layer 112. If the organic layer 112 and the resin layer 126 come into contact with each other, the organic layer 112 may be dissolved by an organic solvent or the like used when forming the resin layer 126. Therefore, by providing the insulating layer 125 between the organic layer 112 and the resin layer 126, it is possible to protect the side surfaces of the organic layer 112.

[0537] The insulating layer 125 can be an insulating layer containing an inorganic material. For example, an inorganic insulating film such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, or a nitride oxide insulating film can be used for the insulating layer 125. The insulating layer 125 may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film. In particular, by using an inorganic insulating film such as a metal oxide film, an aluminum oxide film, or a silicon oxide film formed by an ALD method as the insulating layer 125, an insulating layer 125 with few pinholes and excellent protection of the EL layer can be formed.

[0538] In this specification and elsewhere, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0539] The insulating layer 125 can be formed by a sputtering method, a CVD method, a PLD method, an ALD method, or the like. The insulating layer 125 is preferably formed by an ALD method because it has good coverage.

[0540] Furthermore, a reflective film (e.g., a metal film containing one or more selected from silver, palladium, copper, titanium, aluminum, etc.) may be provided between the insulating layer 125 and the resin layer 126, so that the light emitted from the light-emitting layer is reflected by the reflective film, thereby improving the light extraction efficiency.

[0541] The layer 128 is a remaining portion of a protective layer (also referred to as a mask layer or a sacrificial layer) for protecting the organic layer 112 during etching of the organic layer 112. The layer 128 can be made of a material that can be used for the insulating layer 125. In particular, it is preferable to use the same material for the layer 128 and the insulating layer 125 because a common processing device or the like can be used for both.

[0542] In particular, inorganic insulating films such as metal oxide films such as aluminum oxide films and hafnium oxide films, or silicon oxide films formed by the ALD method have few pinholes and therefore have an excellent function of protecting the EL layer, and can be suitably used for the insulating layer 125 and the layer 128.

[0543] The protective layer 121 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, the protective layer 121 may be made of a semiconductor material or a conductive material such as indium gallium oxide, indium zinc oxide, indium tin oxide, or indium gallium zinc oxide.

[0544] The protective layer 121 may also be a laminated film of an inorganic insulating film and an organic insulating film. For example, a configuration in which an organic insulating film is sandwiched between a pair of inorganic insulating films is preferable. Furthermore, it is preferable that the organic insulating film functions as a planarizing film. This allows the upper surface of the organic insulating film to be flat, improving the coverage of the inorganic insulating film thereon and enhancing the barrier properties. Furthermore, since the upper surface of the protective layer 121 is flat, when a structure (e.g., a color filter, a touch sensor electrode, a lens array, etc.) is provided above the protective layer 121, the influence of uneven shapes caused by the structure below can be reduced, which is preferable.

[0545] 30C shows a connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected. In the connection portion 140, an opening is provided in the insulating layer 125 and the resin layer 126 above the connection electrode 111C. The connection electrode 111C and the common electrode 113 are electrically connected in the opening.

[0546] 30C shows the connection portion 140 where the connection electrode 111C and the common electrode 113 are electrically connected, but the common electrode 113 may be provided on the connection electrode 111C via the common layer 114. In particular, when a carrier injection layer is used for the common layer 114, the electrical resistivity of the material used for the common layer 114 is sufficiently low and the common layer 114 can be formed thin, so that there is often no problem even if the common layer 114 is located at the connection portion 140. This allows the common electrode 113 and the common layer 114 to be formed using the same masking mask, thereby reducing manufacturing costs.

[0547] [Configuration Example 2] The following describes a display device that has a configuration that is partially different from that of the above-described configuration example 1. Note that parts that are common to the above-described configuration example 1 will be referred to, and descriptions thereof may be omitted.

[0548] 31A shows a schematic cross-sectional view of a display device 100a. The display device 100a differs from the display device 100 in that the light-emitting element has a different configuration and that a colored layer is provided.

[0549] The display device 100a includes a light-emitting element 110W that emits white light. The light-emitting element 110W includes a pixel electrode 111, an organic layer 112W, a common layer 114, and a common electrode 113. The organic layer 112W emits white light. For example, the organic layer 112W may be configured to include two or more light-emitting materials whose emitted light colors are complementary to each other. For example, the organic layer 112W may be configured to include a light-emitting organic compound that emits red light, a light-emitting organic compound that emits green light, and a light-emitting organic compound that emits blue light. Alternatively, the organic layer 112W may be configured to include a light-emitting organic compound that emits blue light and a light-emitting organic compound that emits yellow light.

[0550] The organic layers 112W are separated between two adjacent light-emitting elements 110W. This makes it possible to suppress leakage current flowing between adjacent light-emitting elements 110W via the organic layers 112W, thereby suppressing crosstalk caused by the leakage current. As a result, a display device with high contrast and color reproducibility can be realized.

[0551] An insulating layer 122 that functions as a planarizing film is provided on the protective layer 121, and a coloring layer 116R, a coloring layer 116G, and a coloring layer 116B are provided on the insulating layer 122.

[0552] An organic resin film or an inorganic insulating film with a planarized upper surface can be used as the insulating layer 122. The insulating layer 122 forms the surface on which the colored layers 116R, 116G, and 116B are formed, and therefore, by having a planar upper surface of the insulating layer 122, the thickness of the colored layers 116R and the like can be made uniform, thereby improving color purity. Note that if the thickness of the colored layers 116R and the like is uneven, the amount of light absorption varies depending on the location of the colored layer 116R, which may result in a decrease in color purity.

[0553] Configuration Example 3 FIG. 31B shows a schematic cross-sectional view of a display device 100b.

[0554] The light-emitting element 110R has a pixel electrode 111, a conductive layer 115R, an organic layer 112W, and a common electrode 113. The light-emitting element 110G has a pixel electrode 111, a conductive layer 115G, an organic layer 112W, and a common electrode 113. The light-emitting element 110B has a pixel electrode 111, a conductive layer 115B, an organic layer 112W, and a common electrode 113. The conductive layer 115R, the conductive layer 115G, and the conductive layer 115B each have light-transmitting properties and function as an optical adjustment layer.

[0555] A microresonator (microcavity) structure can be realized by using a film that reflects visible light for the pixel electrode 111 and a film that is both reflective and transparent to visible light for the common electrode 113. In this case, by adjusting the thicknesses of the conductive layers 115R, 115G, and 115B so as to provide optimal optical path lengths, even when the organic layer 112 that emits white light is used, light of different wavelengths that are intensified can be obtained from the light-emitting elements 110R, 110G, and 110B.

[0556] Furthermore, colored layers 116R, 116G, and 116B are provided on the optical paths of the light emitting elements 110R, 110G, and 110B, respectively, so that light with high color purity can be obtained.

[0557] An insulating layer 123 is provided to cover the edges of the pixel electrode 111 and the conductive layer 115. The edges of the insulating layer 123 preferably have a tapered shape. By providing the insulating layer 123, coverage by the organic layer 112W, the common electrode 113, the protective layer 121, and the like formed thereon can be improved.

[0558] The organic layer 112W and the common electrode 113 are each provided as a continuous film in common to each light-emitting element, which is preferable because it can greatly simplify the manufacturing process of the display device.

[0559] Here, it is preferable that the edge of the pixel electrode 111 has a shape that is nearly vertical. This allows a steeply inclined portion to be formed on the surface of the insulating layer 123, and it is possible to form a thin portion in a part of the organic layer 112W that covers this portion, or to divide a part of the organic layer 112W. Therefore, it is possible to suppress leakage current that occurs through the organic layer 112W between adjacent light-emitting elements without processing the organic layer 112W by a photolithography method or the like.

[0560] The above is a description of an example of the configuration of the display device.

[0561] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0562] Embodiment 7 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0563] The electronic devices of this embodiment include a display panel (display device) in which the transistor of one embodiment of the present invention is used in a display portion. The display device of one embodiment of the present invention can easily achieve high definition and high resolution and can also achieve high display quality. Therefore, the display device of one embodiment of the present invention can be used in the display portion of various electronic devices.

[0564] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0565] In particular, the display panel of one embodiment of the present invention can have high resolution and thus can be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and MR devices.

[0566] The display panel of one embodiment of the present invention preferably has extremely high resolution, such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display panel of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display panel having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth. Furthermore, there is no particular limitation on the screen ratio (aspect ratio) of the display panel of one embodiment of the present invention. For example, the display panel can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0567] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0568] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0569] 32A to 32D , examples of wearable devices that can be worn on the head are described. These wearable devices have one or both of a function for displaying AR content and a function for displaying VR content. Note that these wearable devices may also have a function for displaying SR or MR content in addition to AR and VR. By having an electronic device have a function for displaying at least one of AR, VR, SR, and MR content, it is possible to enhance the user's sense of immersion.

[0570] The electronic device 700A shown in FIG. 32A and the electronic device 700B shown in FIG. 32B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0571] A display panel of one embodiment of the present invention can be applied to the display panel 751. Therefore, an electronic device capable of displaying images with extremely high resolution can be provided.

[0572] The electronic device 700A and the electronic device 700B can each project an image displayed on the display panel 751 onto a display area 756 of the optical member 753. Because the optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through the optical member 753. Therefore, the electronic device 700A and the electronic device 700B are each electronic devices capable of AR display.

[0573] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0574] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0575] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0576] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation or a slide operation by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can expand the range of operations.

[0577] Various touch sensors can be used as the touch sensor module. For example, various types of touch sensors can be used, such as a capacitance type, a resistive film type, an infrared type, an electromagnetic induction type, a surface acoustic wave type, and an optical type. In particular, it is preferable to use a capacitance type or an optical type sensor in the touch sensor module.

[0578] When an optical touch sensor is used, a photoelectric conversion device (also called a photoelectric conversion element) can be used as the light receiving device (also called a light receiving element). The active layer of the photoelectric conversion device can be made of either or both of an inorganic semiconductor and an organic semiconductor.

[0579] The electronic device 800A shown in Figure 32C and the electronic device 800B shown in Figure 32D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0580] A display panel of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided, which allows a user to feel a high sense of immersion.

[0581] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0582] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0583] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0584] The mounting unit 823 allows the user to wear the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 32C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0585] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0586] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0587] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0588] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0589] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 has a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 32A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 32C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0590] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 32B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or attachment unit 723.

[0591] Similarly, the electronic device 800B shown in Fig. 32D has an earphone unit 827. For example, the earphone unit 827 and the control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting the earphone unit 827 and the control unit 824 may be disposed inside the housing 821 or the attachment unit 823. The earphone unit 827 and the attachment unit 823 may also have magnets. This allows the earphone unit 827 to be fixed to the attachment unit 823 by magnetic force, which is preferable as it makes storage easier.

[0592] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0593] As described above, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0594] The electronic device 6500 shown in FIG. 33A is a portable information terminal that can be used as a smartphone.

[0595] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, a control device 6509, and the like. The display portion 6502 has a touch panel function. Note that the control device 6509 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 6502, the control device 6509, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 6509 is preferable because power consumption can be reduced.

[0596] The display panel of one embodiment of the present invention can be applied to the display portion 6502 .

[0597] FIG. 33B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0598] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0599] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0600] In a region outside the display portion 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0601] A flexible display to which the semiconductor device of one embodiment of the present invention is applied can be applied to the display panel 6511. Therefore, an extremely lightweight electronic device can be realized. Furthermore, since the display panel 6511 is extremely thin, a large-capacity battery 6518 can be mounted while keeping the thickness of the electronic device small. Furthermore, by folding back a part of the display panel 6511 and arranging a connection portion with the FPC 6515 on the back side of the pixel portion, an electronic device with a narrow frame can be realized.

[0602] 33C shows an example of a television set. A television set 7100 has a display portion 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0603] 33C can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, the display portion 7000 may be provided with a touch sensor, and the television set 7100 may be operated by touching the display portion 7000 with a finger or the like. The remote control 7111 may have a display portion that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and an image displayed on the display portion 7000 can be controlled.

[0604] The television device 7100 is configured to include a receiver, a modem, and the like. Ordinary television broadcasts can be received using the receiver. Furthermore, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from a sender to a receiver) or two-way (between a sender and a receiver, or between receivers, etc.) information communication.

[0605] 33D shows an example of a laptop personal computer. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, an external connection port 7214, a control device 7216, and the like. A display portion 7000 is incorporated in the housing 7211. The control device 7216 includes, for example, one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be applied to the display portion 7000, the control device 7216, and the like. The use of the semiconductor device of one embodiment of the present invention for the control device 7216 is preferable because power consumption can be reduced.

[0606] 33E and 33F show an example of digital signage.

[0607] 33E includes a housing 7301, a display portion 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0608] 33F shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0609] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0610] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, the intuitive operation can improve usability.

[0611] 33E and 33F , the digital signage 7300 or the digital signage 7400 is preferably capable of wirelessly linking with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. By operating the information terminal 7311 or the information terminal 7411, the display on the display unit 7000 can be switched.

[0612] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0613] 33C to 33F, the display panel of one embodiment of the present invention can be applied to the display portion 7000.

[0614] The electronic device shown in Figures 34A to 34G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including the function of detecting, detecting, or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays), a microphone 9008, etc.

[0615] The electronic devices shown in Figures 34A to 34G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, or time, a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic devices are not limited to these, and they may have various other functions. The electronic devices may have multiple display units. Furthermore, the electronic devices may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on a display unit, etc.

[0616] Details of the electronic device shown in Figures 34A to 34G will be described below.

[0617] FIG. 34A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. Note that the mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, and the like. The mobile information terminal 9101 can display text and image information on multiple surfaces. FIG. 34A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, an icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0618] 34B is a perspective view showing the mobile information terminal 9102. The mobile information terminal 9102 has a function of displaying information on three or more surfaces of the display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different surfaces. For example, a user can check information 9053 displayed in a position that can be observed from above the mobile information terminal 9102 while the mobile information terminal 9102 is placed in a breast pocket of clothes. The user can check the display without taking the mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0619] 34C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games, for example. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0620] FIG. 34D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a wirelessly capable headset. The mobile information terminal 9200 can also perform data transmission and charging with another information terminal through a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0621] 34E to 34G are perspective views showing a foldable mobile information terminal 9201. Also, FIG. 34E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 34G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 34F is a perspective view of a state in the process of changing from one of FIG. 34E and FIG. 34G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent visibility of the display. The display portion 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display portion 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0622] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0623] Embodiment 8 In this embodiment, an application example of a semiconductor device of one embodiment of the present invention will be described. The semiconductor device of one embodiment of the present invention can be used for, for example, electronic components, electronic devices, mainframes, space equipment, and data centers (also referred to as data centers (DCs)). Electronic components, electronic devices, mainframes, space equipment, and data centers using the semiconductor device of one embodiment of the present invention are effective in achieving high performance, such as low power consumption.

[0624] An electronic component or the like to which the semiconductor device of one embodiment of the present invention is applied can be applied to the electronic devices exemplified in Embodiment 5.

[0625] [Electronic Component] FIG. 35A shows a perspective view of a substrate (mounting substrate 704) on which electronic component 700 is mounted. Electronic component 700 shown in FIG. 35A has semiconductor device 710 inside mold 711. FIG. 35A omits some parts to show the interior of electronic component 700. Electronic component 700 has lands 712 on the outside of mold 711. Lands 712 are electrically connected to electrode pads 713, and electrode pads 713 are electrically connected to semiconductor device 710 via wires 714. Electronic component 700 is mounted on, for example, a printed circuit board 702. A plurality of such electronic components are combined and electrically connected on printed circuit board 702 to complete mounting substrate 704.

[0626] The semiconductor device 710 also includes a drive circuit layer 715 and a memory layer 716. The memory layer 716 has a configuration in which multiple memory cell arrays are stacked. The stacked configuration of the drive circuit layer 715 and the memory layer 716 can be a monolithic stacked configuration. In a monolithic stacked configuration, the layers can be connected without using through-electrode technology such as a TSV (Through Silicon Via) or a bonding technology such as Cu-Cu direct bonding. By configuring the drive circuit layer 715 and the memory layer 716 as a monolithic stacked configuration, for example, a so-called on-chip memory configuration can be achieved in which the memory is formed directly on the processor. The on-chip memory configuration enables the operation of the interface between the processor and the memory to be faster.

[0627] Furthermore, by configuring an on-chip memory, the size of the connection wiring can be reduced compared to technologies that use through electrodes such as TSVs, and the number of connection pins can be increased. Increasing the number of connection pins enables parallel operation, which makes it possible to improve the memory bandwidth (also called memory bandwidth).

[0628] It is also preferable that the memory cell arrays included in the memory layer 716 are formed using OS transistors and the memory cell arrays are monolithically stacked. By forming the memory cell arrays in a monolithic stacked structure, one or both of the memory bandwidth and the memory access latency can be improved. Note that the bandwidth is the amount of data transferred per unit time, and the access latency is the time from access to the start of data exchange. Note that when Si transistors are used for the memory layer 716, it is more difficult to form a monolithic stacked structure than when OS transistors are used. Therefore, it can be said that OS transistors have a superior structure to Si transistors in a monolithic stacked structure.

[0629] The semiconductor device 710 may also be referred to as a die. In this specification, a die refers to a chip piece obtained by forming a circuit pattern on, for example, a disk-shaped substrate (also called a wafer) and dicing it into cubes during the semiconductor chip manufacturing process. Examples of semiconductor materials that can be used for the die include silicon (Si), silicon carbide (SiC), and gallium nitride (GaN). For example, a die obtained from a silicon substrate (also called a silicon wafer) may be called a silicon die.

[0630] 35B shows a perspective view of electronic component 730. Electronic component 730 is an example of a SiP (System in Package) or MCM (Multi-Chip Module). Electronic component 730 has an interposer 731 provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 provided on interposer 731.

[0631] The electronic component 730 shows an example in which the semiconductor device 710 is used as a high bandwidth memory (HBM). The semiconductor device 735 can be used in an integrated circuit such as a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate ar...

Claims

a transistor, a first insulating layer, and a second insulating layer; the transistor includes a first conductive layer, a second conductive layer, a third conductive layer, a semiconductor layer, and a third insulating layer; the first conductive layer has a portion located on the second insulating layer and has a first opening reaching the second insulating layer; the first insulating layer has a portion located on the first conductive layer and has a second opening overlapping the first opening; the second conductive layer has a portion located on the first insulating layer; the semiconductor layer has a portion in contact with the second conductive layer, a portion located along a side surface of the first insulating layer in the second opening, a portion in contact with the side surface of the first conductive layer in the first opening, and a portion in contact with an upper surface of the second insulating layer at a bottom of the first opening, the third insulating layer covers the semiconductor layer in the first opening and the second opening; the third conductive layer covers the third insulating layer in the first opening and in the second opening; Semiconductor device. 　 In claim 1, Further, a fourth conductive layer is provided, the second insulating layer overlies the fourth conductive layer; the first conductive layer is in contact with an upper surface of the fourth conductive layer on the outer side of an end of the second insulating layer; Semiconductor device. 　 In claim 2, the first conductive layer comprises a metal oxide; the fourth conductive layer comprises a metal or an alloy; Semiconductor device. 　 In claim 2 or 3, the second insulating layer has a first insulating film in contact with the fourth conductive layer and a second insulating film thereon in contact with the semiconductor layer; the first insulating film includes one or more of silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, and hafnium oxide; The second insulating film contains silicon oxide or silicon oxynitride. Semiconductor device. 　 In claim 1, further comprising a fifth conductive layer and a fourth insulating layer; the fourth insulating layer has a portion located on the third insulating layer, and has a third opening that overlaps with the first opening and reaches the third insulating layer; the fifth conductive layer has a portion located on the fourth insulating layer; the third conductive layer has a portion embedded in the third opening, and an upper surface of the third conductive layer is in contact with the fifth conductive layer; Semiconductor device. 　 In claim 1, Further, a fifth insulating layer is provided, the fifth insulating layer is provided along a side surface of the first insulating layer in the second opening and is located between the first insulating layer and the semiconductor layer; Semiconductor device. 　 In claim 6, the first insulating layer includes silicon oxide or silicon oxynitride; The fifth insulating layer includes one or more of silicon nitride, aluminum oxide, silicon oxide, and hafnium oxide. Semiconductor device. 　 In claim 1, the semiconductor layer has a cylindrical shape in the first opening and the second opening, the third insulating layer has a portion in contact with an upper surface of the second insulating layer at a bottom of the first opening; Semiconductor device. 　 In claim 8, the semiconductor layer is in contact with a side surface of the second conductive layer but is not in contact with a top surface of the second conductive layer; Semiconductor device.

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