Display device

Abstract

At a portion, in each sub-pixel, where a first conductor region (12aa) of a first TFT (9d) that uses polysilicon and a third conductor region (17aa) of a second TFT (9b) that uses an oxide semiconductor are electrically connected, the first conductor region (12aa) and the third conductor region (17aa) are electrically connected via a contact hole (C) formed in inorganic insulating films (13, 15) and a conductive layer (16a) provided so as to cover the contact hole (C). The peripheral length, in a plan view, of the contact hole (C) of the sub-pixels disposed along the periphery of the display region (50) is shorter than the peripheral length, in a plan view, of the contact hole (C) of the sub-pixels disposed inside the display region (50).

Description

display device

[0001] The present invention relates to a display device.

[0002] In recent years, self-luminous organic electroluminescence (EL) display devices using organic electroluminescence (EL) elements have been attracting attention as a display device that can replace liquid crystal display devices. In these organic EL display devices, a plurality of thin film transistors (TFTs) are provided for each subpixel, which is the smallest unit of an image. Well-known examples of semiconductor layers that constitute TFTs include a semiconductor layer made of polysilicon, which has high mobility, and a semiconductor layer made of an oxide semiconductor such as In—Ga—Zn—O, which has low leakage current.

[0003] For example, Patent Document 1 discloses a display device having a hybrid structure in which a first TFT using a polysilicon semiconductor and a second TFT using an oxide semiconductor are formed on a substrate.

[0004] Japanese Patent Application Laid-Open No. 2020-17558

[0005] In an organic EL display device having a hybrid structure in which each subpixel is provided with a polysilicon TFT and an oxide semiconductor TFT, the outer subpixels in the display region where multiple subpixels are arranged emit light more brightly than the inner subpixels, resulting in uneven light emission, and there is room for improvement. Note that, since moisture penetrates the outer subpixels more easily due to the distance between them than the inner subpixels, it is thought that moisture deteriorates the characteristics of the oxide semiconductor TFTs in the outer subpixels, resulting in uneven light emission.

[0006] The present invention has been made in view of the above points, and an object of the present invention is to suppress the occurrence of uneven light emission in the display area.

[0007] In order to achieve the above object, a display device according to the present invention includes a resin substrate and a thin film transistor layer provided on the resin substrate, in which a first inorganic insulating film, a first semiconductor film made of polysilicon, a second inorganic insulating film, a first metal film, a third inorganic insulating film, a second metal film, a second semiconductor film made of an oxide semiconductor, a fourth inorganic insulating film, and a third metal film are laminated in this order, the thin film transistor layer including at least one first thin film transistor having a first semiconductor layer formed by the first semiconductor film and one second thin film transistor having a second semiconductor layer formed by the second semiconductor film, for each sub-pixel constituting a display area, and the first thin film transistor includes: the first semiconductor layer having a first conductor region and a second conductor region defined so as to be spaced apart from each other, and a first channel region defined between the first conductor region and the second conductor region; and a first gate electrode provided by the first metal film so as to overlap the first channel region via the second inorganic insulating film. the second thin film transistor comprises the second semiconductor layer in which a third conductor region and a fourth conductor region are defined to be spaced apart from each other and a second channel region is defined between the third conductor region and the fourth conductor region, and a second gate electrode provided by the third metal film to overlap the second channel region with the fourth inorganic insulating film interposed therebetween, and in each of the sub-pixels, at a portion where the first conductor region and the third conductor region are electrically connected, the first conductor region and the third conductor region are electrically connected via contact holes formed in the second inorganic insulating film and the third inorganic insulating film and a conductive layer formed in the second metal film so as to cover the contact holes, wherein a circumferential length in a plan view of the contact holes of the sub-pixels arranged along the periphery of the display region is shorter than a circumferential length in a plan view of the contact holes of the sub-pixels arranged inside the display region.

[0008] According to the present invention, it is possible to suppress the occurrence of uneven light emission in the display area.

[0009] FIG. 1 is a block diagram showing the overall configuration of an organic EL display device according to a first embodiment of the present invention. FIG. 2 is an equivalent circuit diagram of a pixel circuit in a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 3 is a plan view showing a schematic configuration of a TFT layer constituting the organic EL display device according to the first embodiment of the present invention. FIG. 4 is a cross-sectional view of a display region of the organic EL display device according to the first embodiment of the present invention. FIG. 5 is a plan view showing threshold voltage compensation TFTs and drive TFTs constituting the TFT layer of sub-pixels arranged within the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 6 is a plan view showing threshold voltage compensation TFTs and drive TFTs constituting the TFT layer of sub-pixels arranged along the outer and inner peripheries of the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 7 is a cross-sectional view of the organic EL display device taken along line VII-VII in FIG. 5. FIG. 8 is a cross-sectional view of the organic EL display device taken along line VIII-VIII in FIG. 6. FIG. 9 is a plan view schematically showing the arrangement of contact holes of different shapes in the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 10 is a plan view schematically showing the division of contact holes of different shapes in the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 11 is a plan view schematically showing a comparison of contact hole shapes in the display region of the organic EL display device according to the first embodiment of the present invention. FIG. 12 is a plan view schematically showing a comparison of contact hole shapes in a first modification of the first embodiment of the present invention. FIG. 13 is a plan view schematically showing a comparison of contact hole shapes in a second modification of the first embodiment of the present invention. FIG. 14 is a plan view schematically showing a comparison of contact hole shapes in a third modification of the first embodiment of the present invention. FIG. 15 is a plan view schematically showing a comparison of contact hole shapes in a fourth modification of the first embodiment of the present invention. FIG. 16 is a plan view schematically showing a comparison of contact hole shapes in a fifth modification of the first embodiment of the present invention. FIG. 17 is a plan view schematically showing a comparison of contact hole shapes in a sixth modification of the first embodiment of the present invention. FIG. 18 is a cross-sectional view of an organic EL layer constituting the organic EL display device according to the first embodiment of the present invention.Fig. 19 is a timing chart for explaining the operation of a pixel circuit of an organic EL display device according to a first embodiment of the present invention. Fig. 20 is a plan view schematically showing divisions of different shapes of contact holes in a display region of an organic EL display device according to a second embodiment of the present invention. Fig. 21 is a plan view schematically showing divisions of different shapes of contact holes in a display region in a first modification of the second embodiment of the present invention. Fig. 22 is a plan view schematically showing divisions of different shapes of contact holes in a display region in a second modification of the second embodiment of the present invention.

[0010] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention is not limited to the following embodiments.

[0011] First Embodiment FIGS. 1 to 19 show a first embodiment of a display device according to the present invention. In the following embodiments, an organic EL display device including an organic EL element layer is exemplified as a display device including a light-emitting element layer. FIG. 1 is a block diagram showing the overall configuration of an organic EL display device 100 according to this embodiment. FIG. 2 is an equivalent circuit diagram of a pixel circuit of a TFT layer 30 constituting the organic EL display device 100. FIG. 3 is a plan view showing a schematic configuration of the TFT layer 30. FIG. 4 is a cross-sectional view of a display region 50 of the organic EL display device 100. FIG. 5 is a plan view showing a threshold voltage compensation TFT 9b and a driving TFT 9d constituting the TFT layer 30 of a subpixel P arranged inside the display region 50 of the organic EL display device 100. FIG. 6 is a plan view showing a threshold voltage compensation TFT 9b and a driving TFT 9d constituting the TFT layer 30 of a subpixel P arranged along the outer and inner peripheries of the display region 50 of the organic EL display device 100. 7 and 8 are cross-sectional views of the organic EL display device 100 taken along line VII-VII in FIG. 5 and line VIII-VIII in FIG. 6 . FIG. 9 is a plan view schematically showing the arrangement of contact holes Ca and Cb of different shapes in the display region 50 of the organic EL display device 100. FIG. 10 is a plan view schematically showing the division of contact holes of different shapes in the display region 50 of the organic EL display device 100. FIG. 11 is a plan view schematically showing the comparison of the shapes of contact holes Ca and Cb in the display region 50 of the organic EL display device 100. FIG. 12 is a plan view schematically showing the comparison of the shapes of contact holes Caa and Cb in a first modified example of this embodiment. FIG. 13 is a plan view schematically showing the comparison of the shapes of contact holes Cab and Cb in a second modified example of this embodiment. 14 is a plan view schematically illustrating the comparison of the shapes of contact holes Cac and Cb in a third modified example of this embodiment, FIG. 15 is a plan view schematically illustrating the comparison of the shapes of contact holes Cad and Cb in a fourth modified example of this embodiment, and FIG. 16 is a plan view schematically illustrating the comparison of the shapes of contact holes Cae and Cb in a fifth modified example of this embodiment.Fig. 17 is a plan view schematically illustrating a comparison of the shapes of contact holes Caf and Cb in a sixth modified example of this embodiment. Fig. 18 is a cross-sectional view of an organic EL layer 33 constituting the organic EL display device 100 of this embodiment. Fig. 19 is a timing chart for explaining the operation of the pixel circuit of the organic EL display device 100 of this embodiment.

[0012] 1, the organic EL display device 100 includes a display area 50 for displaying images, and a gate driver 60, an emission driver 70, and a source driver 80 provided in a frame area around the display area 50. As shown in FIG. 1, a display control circuit 150 is provided outside the organic EL display device 100 and is electrically connected to the gate driver 60, the emission driver 70, and the source driver 80.

[0013] As shown in FIGS. 1 and 3 , a plurality of subpixels P are arranged in a matrix in the display region 50. Also, as shown in FIG. 3 , the display region 50 includes a subpixel P having a red light-emitting region Er for displaying red, a subpixel P having a green light-emitting region Eg for displaying green, and a subpixel P having a blue light-emitting region Eb for displaying blue, which are arranged adjacent to one another. Here, in the display region 50, one pixel is formed by, for example, three adjacent subpixels P each having a red light-emitting region Er, a green light-emitting region Eg, and a blue light-emitting region Eb. While FIG. 1 illustrates a rectangular display region 50, this rectangular shape also includes a substantially rectangular shape, such as one with arc-shaped corners, as shown in FIG. 9 . An island-shaped non-display region 51 is provided within the display region 50, as shown in FIG. 9 . Furthermore, the non-display region 51 includes a through-hole H penetrating the non-display region 51 in the thickness direction of the resin substrate 10, which will be described later, for installing an electronic component 55, such as a camera, a fingerprint sensor, or a face authentication sensor, on the rear surface side, as shown in FIG. 9 .

[0014] As shown in FIG. 4, the organic EL display device 100 includes a resin substrate 10, a TFT layer 30 provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30, and a sealing film 45 provided on the organic EL element layer 40.

[0015] The resin substrate 10 is made of, for example, polyimide resin.

[0016] As shown in FIG. 4, the TFT layer 30 includes a base coat film 11 provided on a resin substrate 10, an initialization TFT 9a (see FIG. 2), a threshold voltage compensation TFT 9b, a write control TFT 9c (see FIG. 2), a drive TFT 9d, a power supply control TFT 9e (see FIG. 2), a light-emitting control TFT 9f (see FIG. 2), an anode discharge TFT 9g (see FIG. 2), and a capacitor 9h (see FIG. 2) provided in each sub-pixel P on the base coat film 11, and a planarization film 22 provided on each of the TFTs 9a to 9g and the capacitor 9h. As shown in FIG. 4 , the TFT layer 30 includes a base coat film 11 provided on a resin substrate 10 as a first inorganic insulating film, a first semiconductor film made of polysilicon that will become a first semiconductor layer 12a or the like described later, a first gate insulating film 13 provided on a second inorganic insulating film, a first metal film that will become a first gate electrode 14a or the like described later, a first interlayer insulating film 15 provided on a third inorganic insulating film, a second metal film that will become a conductive layer 16a or the like described later, a second semiconductor film made of an oxide semiconductor that will become a second semiconductor layer 17a or the like described later, a second gate insulating film 18 provided on a fourth inorganic insulating film, a third metal film that will become a second gate electrode 19a or the like described later, a second interlayer insulating film 20, a fourth metal film that will become a first terminal electrode 21a or the like described later, and a planarization film 22 that are laminated in this order.

[0017] As shown in FIG. 1 , the display region 50 of the TFT layer 30 is provided with i first scanning signal lines PS(1) to PS(i), (i+1) second scanning signal lines NS(0) to NS(i), i light-emitting control lines EM(1) to EM(i), and j data signal lines D(1) to D(j). Note that i and j are integers equal to or greater than 2, n is an integer equal to or greater than 1 and equal to or less than i, and m is an integer equal to or greater than 1 and equal to or less than j. Also, in FIG. 1 , the first scanning signal lines PS, the second scanning signal lines NS, and the data signal lines D are not shown in the display region 50. Here, the first scanning signal lines PS(1) to PS(i) are signal lines for transmitting first scanning signals, which are control signals for P-channel transistors. The second scanning signal lines NS(0) to NS(i) are signal lines for transmitting second scanning signals, which are control signals for N-channel transistors. The light-emission control lines EM(1) to EM(i) are signal lines for transmitting light-emission control signals. The first scanning signal lines PS(1) to PS(i), the second scanning signal lines NS(0) to NS(i), and the light-emission control lines EM(1) to EM(i) are arranged parallel to one another. The first scanning signal lines PS(1) to PS(i) and the data signal lines D(1) to D(j) are arranged perpendicular to one another. Furthermore, in the timing chart of FIG. 19, the first scanning signals respectively given to the first scanning signal lines PS(1) to PS(i) are also given the symbols PS(1) to PS(i), the second scanning signals respectively given to the second scanning signal lines NS(0) to NS(i) are also given the symbols NS(0) to NS(i), the light emission control signals respectively given to the light emission control lines EM(1) to EM(i) are also given the symbols EM(1) to EM(i), and the data signals (data voltages) respectively given to the data signal lines D(1) to D(j) are also given the symbols D(1) to D(j).

[0018] The display region 50 of the TFT layer 30 is provided with a power supply line (hereinafter referred to as the "high-level power supply line") that supplies a high-level power supply voltage ELVDD for driving the organic EL elements 35 (described later), a power supply line (hereinafter referred to as the "low-level power supply line") that supplies a low-level power supply voltage ELVSS for driving the organic EL elements 35, and a power supply line (hereinafter referred to as the "initialization power supply line") that supplies an initialization voltage Vini. In this embodiment, as necessary, the high-level power supply line is also designated with the symbol ELVDD, the low-level power supply line is also designated with the symbol ELVSS, and the initialization power line is also designated with the symbol Vini. The high-level power supply voltage ELVDD, the low-level power supply voltage ELVSS, and the initialization voltage Vini are supplied from a power supply circuit (not shown). 3, the first scanning signal line 14g extending in the X direction is shown as the first scanning signal line PS, the light-emitting control line 14e extending in the X direction is shown as the light-emitting control line EM, the second scanning signal line 19h extending in the X direction is shown as the second scanning signal line NS, the initialization power line 14i extending in the X direction is shown as the initialization power line Vini, the data signal line 21g extending in the Y direction is shown as the data signal line D, and the high-level power line 21h extending in the Y direction is shown as the high-level power line ELVDD. The first scanning signal line 14g, the light-emitting control line 14e, and the initialization power line 14i are formed of a first metal film, the second scanning signal line 19h is formed of a third metal film, and the data signal line 21g and the high-level power line 21h are formed of a fourth metal film.

[0019] The base coat film 11, first gate insulating film 13, first interlayer insulating film 15, second gate insulating film 18, and second interlayer insulating film 20 are each composed of a single layer or a stack of inorganic insulating films such as silicon nitride, silicon oxide, or silicon oxynitride. At least the second semiconductor layer 17a side of the first interlayer insulating film 15 and the second semiconductor layer 17a side of the second gate insulating film 18 are composed of, for example, a silicon oxide film. The base coat film 11 is composed of, for example, a silicon oxide film, a silicon nitride film, and a silicon oxide film stacked in this order on the resin substrate 10.

[0020] The write control TFT 9c, the drive TFT 9d, the power supply control TFT 9e, and the light-emitting control TFT 9f are each provided as a first TFT having a first semiconductor layer 12a (see FIG. 4) formed of polysilicon such as low-temperature polysilicon (LTPS), and each include a first gate electrode 14a (see FIG. 4), a first terminal electrode 21a (see FIG. 4), and a second terminal electrode 21b (see FIG. 4). In the first TFT, the first semiconductor layer 12a includes a first conductor region 12aa and a second conductor region 12ab spaced apart from each other, and a first channel region 12ac formed between the first conductor region 12aa and the second conductor region 12ab. In the first TFT, the first gate electrode 14a is provided to overlap the first channel region 12ac via a first gate insulating film 13, as shown in FIG. 4. 4, the first terminal electrode 21a and the second terminal electrode 21b of the first TFT are electrically connected to the first conductor region 12aa and the second conductor region 12ab, respectively, via a pair of contact holes formed in the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 20. In the equivalent circuit diagram of FIG. 2, the first terminal electrode 21a and the second terminal electrode 21b of the write control TFT 9c, the drive TFT 9d, the power supply control TFT 9e, and the light-emitting control TFT 9f are indicated by circled numbers 1 and 2, and the third terminal electrode 21c and the fourth terminal electrode 21d of the initialization TFT 9a, the threshold voltage compensation TFT 9b, and the anode discharge TFT 9g, which will be described later, are indicated by circled numbers 3 and 4.

[0021] The initialization TFT 9a, the threshold voltage compensation TFT 9b, and the anode discharge TFT 9g are provided as second TFTs having a second semiconductor layer 17a (see FIG. 4) formed of an oxide semiconductor such as an In—Ga—Zn—O system, and are provided with a second gate electrode 19a (see FIG. 4), a third terminal electrode 21c (see FIG. 4), and a fourth terminal electrode 21d (see FIG. 4). In the second TFT, the second semiconductor layer 17a includes a third conductor region 17aa and a fourth conductor region 17ab spaced apart from each other, and a second channel region 17ac formed between the third conductor region 17aa and the fourth conductor region 17ab. In the second TFT, the second gate electrode 19a is provided so as to overlap the second channel region 17ac with a second gate insulating film 18 interposed therebetween, as shown in FIG. 4. In the second TFT, the third terminal electrode 21c and the fourth terminal electrode 21d are electrically connected to the third conductor region 17aa and the fourth conductor region 17ab, respectively, via a pair of contact holes and the conductive layers 16a and 16b formed in the second interlayer insulating film 20, as shown in FIG. 4. The In—Ga—Zn—O-based semiconductor is a ternary oxide of In (indium), Ga (gallium), and Zn (zinc), and the proportions (composition ratios) of In, Ga, and Zn are not particularly limited. The In—Ga—Zn—O-based semiconductor may be amorphous or crystalline. As the crystalline In—Ga—Zn—O-based semiconductor, a crystalline In—Ga—Zn—O-based semiconductor whose c-axis is oriented approximately perpendicular to the layer surface is preferred. Instead of the In—Ga—Zn—O-based semiconductor, another oxide semiconductor may be included. Examples of other oxide semiconductors include In—Sn—Zn—O-based semiconductors (e.g., In ２ O ３ -SnO ２In—ZnO; InSnZnO). Here, the In—Sn—Zn—O based semiconductor is a ternary oxide of In (indium), Sn (tin), and Zn (zinc). Other oxide semiconductors include In—Al—Zn—O based semiconductors, In—Al—Sn—Zn—O based semiconductors, Zn—O based semiconductors, In—Zn—O based semiconductors, Zn—Ti—O based semiconductors, Cd—Ge—O based semiconductors, Cd—Pb—O based semiconductors, CdO (cadmium oxide), Mg—Zn—O based semiconductors, In—Ga—Sn—O based semiconductors, In—Ga—O based semiconductors, Zr—In—Zn—O based semiconductors, Hf—In—Zn—O based semiconductors, Al—Ga—Zn—O based semiconductors, Ga—Zn—O based semiconductors, In—Ga—Zn—Sn—O based semiconductors, InGaO ３ (ZnO) ５ , magnesium zinc oxide (Mg ｘ Zn １－ｘ O), cadmium zinc oxide (Cd ｘ Zn １－ｘ The Zn—O-based semiconductor may be ZnO in an amorphous state, a polycrystalline state, a microcrystalline state in which the amorphous state and the polycrystalline state are mixed, or a semiconductor in which no impurity element is added, to which one or more impurity elements selected from the group 1 elements, the group 13 elements, the group 14 elements, the group 15 elements, the group 17 elements, etc. are added.

[0022] As shown in FIG. 2, the initialization TFT 9a has its second gate electrode 19a electrically connected to the second scanning signal line NS(n-1) in the (n-1)th row, its third terminal electrode 21c electrically connected to the fourth terminal electrode 21d of the threshold voltage compensation TFT 9b, the first gate electrode 14a of the driving TFT 9d and the capacitor 9h, and its fourth terminal electrode 21d electrically connected to the initialization power supply line Vini.

[0023] As shown in FIG. 2, the threshold voltage compensation TFT 9b has its second gate electrode 19a electrically connected to the second scanning signal line NS of the nth row, its third terminal electrode 21c electrically connected to the first terminal electrode 21a of the driving TFT 9d and the first terminal electrode 21a of the light-emitting control TFT 9f, and its fourth terminal electrode 21d electrically connected to the third terminal electrode 21c of the initialization TFT 9a, the first gate electrode 14a of the driving TFT 9d, and the capacitor 9h.

[0024] As shown in FIG. 2, the write control TFT 9c has its first gate electrode 14a electrically connected to the first scanning signal line PS(n) in the nth row, its first terminal electrode 21a electrically connected to the data signal line D(m) in the mth column, and its second terminal electrode 21b electrically connected to the second terminal electrode 21b of the drive TFT 9d and the second terminal electrode 21b of the power supply control TFT 9e.

[0025] 2, the first gate electrode 14a of the drive TFT 9d is electrically connected to the third terminal electrode 21c of the initialization TFT 9a, the fourth terminal electrode 21d of the threshold voltage compensation TFT 9b, and the capacitor 9h, the first terminal electrode 21a of the drive TFT 9d is connected to the third terminal electrode 21c of the threshold voltage compensation TFT 9b and the first terminal electrode 21a of the light-emitting control TFT 9f, and the second terminal electrode 21b of the drive TFT 9d is electrically connected to the second terminal electrode 21b of the write control TFT 9c and the second terminal electrode 21b of the power supply control TFT 9e. A high-level power supply voltage ELVDD is input to the second terminal electrode 21b of the drive TFT 9d during a period when the organic EL element 35 is caused to emit light, and a data signal D(m) is input to the second terminal electrode 21b of the drive TFT 9d during a period when data is written to the capacitor 9h.

[0026] As shown in FIG. 2, the power supply control TFT 9e has its first gate electrode 14a electrically connected to the light emission control line EM(n) of the nth row, its first terminal electrode 21a electrically connected to the high-level power supply line ELVDD and the capacitor 9h, and its second terminal electrode 21b electrically connected to the second terminal electrode 21b of the write control TFT 9c and the second terminal electrode 21b of the drive TFT 9d.

[0027] As shown in FIG. 2, the light-emitting control TFT 9f has its first gate electrode 14a electrically connected to the light-emitting control line EM(n) in the nth row, its first terminal electrode 21a electrically connected to the third terminal electrode 21c of the threshold voltage compensation TFT 9b and the first terminal electrode 21a of the drive TFT 9d, and its second terminal electrode 21b electrically connected to the fourth terminal electrode 21d of the anode-discharge TFT 9g and a first electrode 31 (described later) of the organic EL element 35.

[0028] As shown in FIG. 2, the anode-discharge TFT 9g has its third gate electrode 19a electrically connected to the light-emission control line EM(n) of the nth row, its third terminal electrode 21c electrically connected to the initialization power supply line Vini, and its fourth terminal electrode 21d electrically connected to the second terminal electrode 21b of the light-emission control TFT 9f and the first electrode 31 of the organic EL element 35.

[0029] The capacitor 9h includes, for example, a first capacitance electrode formed of a first metal film, a second capacitance electrode formed of a second metal film, and a first interlayer insulating film 15 provided between the first capacitance electrode and the second capacitance electrode. Here, the capacitor 9h has its first capacitance electrode electrically connected to the high-level power supply line ELVDD and the first terminal electrode 21a of the power supply control TFT 9e, and its second capacitance electrode electrically connected to the third terminal electrode 21c of the initialization TFT 9a, the fourth terminal electrode 21d of the threshold voltage compensation TFT 9b, and the first gate electrode 14a of the drive TFT 9d.

[0030] 4, the third conductor region 17aa (electrically connected to the third terminal electrode 21c) of the threshold voltage compensation TFT 9b and the first conductor region 12aa (electrically connected to the first terminal electrode 21a) of the drive TFT 9d are electrically connected to each other via a contact hole C formed in the first gate insulating film 13 and the first interlayer insulating film 15 and a conductive layer 16a provided so as to cover the contact hole C. The planar shape of the contact hole C differs depending on the position of the sub-pixel P within the display region 50, as shown in contact holes Ca and Cb described below.

[0031] Specifically, the contact holes Ca of the sub-pixels P arranged inside the display region 50 have a rectangular planar shape, as shown in FIG. 5 (see FIG. 9 ). The sub-pixels P arranged along the inner periphery of the through-hole H of the display region 50 and the contact holes Cb of the sub-pixels P arranged along the outer periphery of the display region 50 have a circular planar shape, as shown in FIG. 6 (see FIG. 9 ). Note that FIG. 9 also schematically illustrates the planar shapes of the contact holes C (Ca and Cb) of each sub-pixel P. Also, FIG. 10 divides the display region 50 into a first region Ra of sub-pixels in which the contact holes Ca are formed and a second region Rb of sub-pixels in which the contact holes Cb are formed. Also, FIG. 11 illustrates the contact holes Ca and Cb side by side to compare the perimeter and area of ​​the contact holes C.

[0032] As shown in Figures 5, 6, and 11, the circumferential lengths in a plan view of the subpixels P arranged along the inner periphery of the through-hole H of the display region 50 and the contact holes Cb of the subpixels P arranged along the outer periphery of the display region 50 are shorter than the circumferential lengths in a plan view of the contact holes Ca of the subpixels P arranged inside the display region 50. This allows moisture that penetrates from the interface between the resin substrate 10 and the base coat film 11 at the substrate edge surface and penetrates beyond the base coat film 11 and the first semiconductor layer 12a to be confined by the contact holes Cb, which have a relatively short circumferential length, and makes it possible to equalize the amount of moisture that reaches the second semiconductor layer 17a through the contact holes Ca and Cb. Note that in Figures 7 and 8, the width of the outline arrows indicates the amount of moisture that penetrates. Here, the wall surfaces of the stacked film of the first gate insulating film 13 and the first interlayer insulating film 15 in which the contact holes Ca and Cb are formed are inclined in a forward tapered shape as shown in FIGS. 7 and 8 , and therefore the circumferential lengths of the contact holes Ca and Cb in a planar view do not refer to the (relatively long) outer circumferential length on the upper surface side of the stacked film of the first gate insulating film 13 and the first interlayer insulating film 15, but to the (relatively short) inner circumferential length on the lower surface side thereof.

[0033] 5, 6, and 11, the area in a plan view of the contact holes Cb of the subpixels P arranged along the inner periphery of the through-hole H of the display region 50 and the subpixels P arranged along the outer periphery of the display region 50 is the same as the area in a plan view of the contact holes Ca of the subpixels P arranged inside the display region 50. This makes it possible to match the electrical resistance of (the first conductor region 12aa of) the first semiconductor layer 12a and the conductive layer 16a electrically connected via the contact holes Ca with the electrical resistance of (the first conductor region 12aa of) the first semiconductor layer 12a and the conductive layer 16a electrically connected via the contact holes Cb. Here, the wall surfaces of the stacked film of the first gate insulating film 13 and the first interlayer insulating film 15 in which the contact holes Ca and Cb are formed are inclined in a forward tapered shape as shown in FIGS. 5 and 6 , and therefore the area of ​​the contact holes Ca and Cb in a planar view does not refer to the (relatively wide) outer circumferential area on the upper surface side of the stacked film of the first gate insulating film 13 and the first interlayer insulating film 15, but rather to the (relatively narrow) inner circumferential area on the lower surface side thereof.

[0034] In this embodiment, a combination of a contact hole Ca that is provided in a square shape in a plan view and a contact hole Cb that is provided in a circular shape in a plan view is exemplified, but combinations such as those shown in Figures 12 to 17 may also be used.

[0035] Specifically, FIG. 12 shows a combination of a contact hole Caa provided in an equilateral triangular shape in a plan view and a contact hole Cb provided in a circular shape in a plan view.

[0036] FIG. 13 shows a combination of contact holes Cab formed in a four-pointed star shape in plan view and contact holes Cb formed in a circular shape in plan view.

[0037] FIG. 14 shows a combination of a contact hole Cac that is rectangular in plan view and a contact hole Cb that is circular in plan view.

[0038] 15 shows a combination of a contact hole Cad that is provided in a regular hexagonal shape in a plan view and a contact hole Cb that is provided in a circular shape in a plan view. Here, in the combinations of Figures 12, 13, 14, and 15, the circumferential length of contact hole Cb in a plan view is shorter than the circumferential lengths of contact holes Caa, Cab, Cac, and Cad in a plan view, and the area of ​​contact hole Cb in a plan view is equal to the area of ​​contact holes Caa, Cab, Cac, and Cad in a plan view.

[0039] 16 shows a combination of four contact holes Cae each having a relatively small circular shape in a plan view and a contact hole Cb each having a relatively large circular shape in a plan view, where the circumferential length of the contact hole Cb in a plan view is shorter than the sum of the circumferential lengths of the four contact holes Cae in a plan view, and the area of ​​the contact hole Cb in a plan view is equal to the sum of the areas of the four contact holes Cae in a plan view.

[0040] 17 illustrates a combination of a contact hole Caf that is provided in a relatively large circular shape in a plan view and a contact hole Cb that is provided in a relatively small circular shape in a plan view. In the combination of FIG. 17, the circumferential length of the contact hole Cb in a plan view is shorter than the circumferential length of the contact hole Caf in a plan view. The combination of FIG. 17 illustrates a configuration in which the amounts of moisture reaching the second semiconductor layer 17a through the contact holes Caf and Cb are simply made uniform, and the electrical resistance through the contact holes Caf and Cb is not particularly made uniform.

[0041] The planarization film 22 has a flat surface in the display region 50 and is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG (spin on glass) material.

[0042] As shown in FIG. 4, the organic EL element layer 40 includes a plurality of organic EL elements 35 (see FIG. 2) arranged in a matrix to serve as a plurality of light-emitting elements corresponding to a plurality of sub-pixels P, and edge covers 32 arranged in a lattice pattern common to all the sub-pixels P so as to cover the peripheral edges of the first electrodes 31 of the respective organic EL elements 35.

[0043] As shown in Figure 4, in each subpixel P, the organic EL element 35 has a first electrode 31 provided on the planarization film 22 of the TFT layer 30, an organic EL layer 33 provided on the first electrode 31, and a second electrode 34 provided on the organic EL layer 33.

[0044] The first electrode 31 is electrically connected to the second terminal electrode 21b of the light-emission control TFT 9f of each sub-pixel P through a contact hole formed in the planarization film 22. The first electrode 31 also has a function of injecting holes (positive holes) into the organic EL layer 33. In order to improve the efficiency of hole injection into the organic EL layer 33, the first electrode 31 is preferably formed of a material with a large work function. Examples of materials that can be used for the first electrode 31 include metal materials such as silver (Ag), aluminum (Al), vanadium (V), cobalt (Co), nickel (Ni), tungsten (W), gold (Au), titanium (Ti), ruthenium (Ru), manganese (Mn), indium (In), ytterbium (Yb), lithium fluoride (LiF), platinum (Pt), palladium (Pd), molybdenum (Mo), iridium (Ir), and tin (Sn). The material constituting the first electrode 31 is, for example, astatine (At) / astatine oxide (AtO ２ The first electrode 31 may be made of an alloy of tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), indium zinc oxide (IZO), or another conductive oxide. The first electrode 31 may be formed by stacking multiple layers made of the above materials. Examples of compound materials with a large work function include indium tin oxide (ITO) and indium zinc oxide (IZO).

[0045] As shown in FIG. 18, the organic EL layer 33 includes a hole injection layer 1, a hole transport layer 2, a light emitting layer 3, an electron transport layer 4, and an electron injection layer 5, which are stacked in this order on a first electrode 31.

[0046] The hole injection layer 1 is also called an anode buffer layer, and has the function of bringing the energy levels of the first electrode 31 and the organic EL layer 33 closer to each other, thereby improving the efficiency of hole injection from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole injection layer 1 include triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, phenylenediamine derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, and stilbene derivatives.

[0047] The hole transport layer 2 has a function of improving the efficiency of transporting holes from the first electrode 31 to the organic EL layer 33. Examples of materials constituting the hole transport layer 2 include porphyrin derivatives, aromatic tertiary amine compounds, styrylamine derivatives, polyvinylcarbazole, poly-p-phenylenevinylene, polysilane, triazole derivatives, oxadiazole derivatives, imidazole derivatives, polyarylalkane derivatives, pyrazoline derivatives, pyrazolone derivatives, phenylenediamine derivatives, arylamine derivatives, amine-substituted chalcone derivatives, oxazole derivatives, styrylanthracene derivatives, fluorenone derivatives, hydrazone derivatives, stilbene derivatives, hydrogenated amorphous silicon, hydrogenated amorphous silicon carbide, zinc sulfide, and zinc selenide.

[0048] The light-emitting layer 3 is a region into which holes and electrons are injected from the first electrode 31 and the second electrode 34, respectively, and where the holes and electrons recombine when a voltage is applied between the first electrode 31 and the second electrode 34. The light-emitting layer 3 is made of a material with high luminous efficiency. Examples of materials that can be used for the light-emitting layer 3 include metal oxinoid compounds (8-hydroxyquinoline metal complexes), naphthalene derivatives, anthracene derivatives, diphenylethylene derivatives, vinylacetone derivatives, triphenylamine derivatives, butadiene derivatives, coumarin derivatives, benzoxazole derivatives, oxadiazole derivatives, oxazole derivatives, benzimidazole derivatives, thiadiazole derivatives, benzothiazole derivatives, styryl derivatives, styrylamine derivatives, bisstyrylbenzene derivatives, trisstyrylbenzene derivatives, perylene derivatives, perinone derivatives, aminopyrene derivatives, pyridine derivatives, rhodamine derivatives, aquidin derivatives, phenoxazone, quinacridone derivatives, rubrene, poly-p-phenylenevinylene, and polysilane.

[0049] The electron transport layer 4 has a function of efficiently transferring electrons to the light-emitting layer 3. Examples of materials constituting the electron transport layer 4 include organic compounds such as oxadiazole derivatives, triazole derivatives, benzoquinone derivatives, naphthoquinone derivatives, anthraquinone derivatives, tetracyanoanthraquinodimethane derivatives, diphenoquinone derivatives, fluorenone derivatives, silole derivatives, and metal oxinoid compounds.

[0050] The electron injection layer 5 has a function of bringing the energy levels of the second electrode 34 and the organic EL layer 33 closer to each other and improving the efficiency of electron injection from the second electrode 34 to the organic EL layer 33, and this function can reduce the driving voltage of the organic EL element 35. The electron injection layer 5 is also called a cathode buffer layer. Here, examples of materials constituting the electron injection layer 5 include lithium fluoride (LiF), magnesium fluoride (MgF ２ ), calcium fluoride (CaF ２ ), strontium fluoride (SrF ２ ), barium fluoride (BaF ２inorganic alkali compounds such as aluminum oxide (Al ２ O ３ ), strontium oxide (SrO), etc.

[0051] As shown in FIG. 4 , the second electrode 34 is provided in common to all subpixels P so as to cover each organic EL layer 33 and the edge cover 32. The second electrode 34 has a function of injecting electrons into the organic EL layer 33. To improve the efficiency of electron injection into the organic EL layer 33, the second electrode 34 is preferably made of a material with a small work function. As shown in FIG. 2 , the second electrode 34 is electrically connected to the low-level power supply line ELVSS. Examples of materials that can be used for the second electrode 34 include silver (Ag), aluminum (Al), vanadium (V), calcium (Ca), titanium (Ti), yttrium (Y), sodium (Na), manganese (Mn), indium (In), magnesium (Mg), lithium (Li), ytterbium (Yb), and lithium fluoride (LiF). The second electrode 34 may be made of, for example, magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), or astatine (At) / astatine oxide (AtO ２ The second electrode 34 may be formed of an alloy such as lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), or lithium fluoride (LiF) / calcium (Ca) / aluminum (Al). The second electrode 34 may be formed of a conductive oxide such as tin oxide (SnO), zinc oxide (ZnO), indium tin oxide (ITO), or indium zinc oxide (IZO). The second electrode 34 may be formed by stacking multiple layers made of the above materials. Examples of materials with a low work function include magnesium (Mg), lithium (Li), lithium fluoride (LiF), magnesium (Mg) / copper (Cu), magnesium (Mg) / silver (Ag), sodium (Na) / potassium (K), lithium (Li) / aluminum (Al), lithium (Li) / calcium (Ca) / aluminum (Al), and lithium fluoride (LiF) / calcium (Ca) / aluminum (Al).

[0052] The edge cover 32 is made of, for example, an organic resin material such as polyimide resin or acrylic resin, or a polysiloxane-based SOG material.

[0053] As shown in Figure 4, the sealing film 45 is provided to cover the second electrode 34, and comprises a first inorganic sealing film 41, an organic sealing film 42, and a second inorganic sealing film 43 stacked in order on the second electrode 34, and has the function of protecting the organic EL layer 33 of the organic EL element 35 from moisture and oxygen.

[0054] The first inorganic sealing film 41 and the second inorganic sealing film 43 are made of an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film.

[0055] The organic sealing film 42 is made of an organic resin material such as an acrylic resin, an epoxy resin, a silicone resin, a polyurea resin, a parylene resin, a polyimide resin, or a polyamide resin.

[0056] The organic EL display device 100 also includes a first outer damming wall provided in a frame shape in the frame region of the display region 50 so as to surround the display region 50, and a second outer damming wall provided in a frame shape around the first outer damming wall. Here, the first outer damming wall and the second outer damming wall each include, for example, a lower resin layer formed in the same layer and made of the same material as the planarizing film 22, and an upper resin layer provided on the lower resin layer and formed in the same layer and made of the same material as the edge cover 32. The first outer damming wall is provided so as to overlap the outer peripheral edge of the organic sealing film 42 of the sealing film 45, and is configured to suppress the spreading of ink that will become the organic sealing film 42.

[0057] The organic EL display device 100 also includes, in the non-display region 51 within the display region 50, a first inner dam wall annularly provided to surround the through-hole H, and a second inner dam wall annularly provided around the first inner dam wall. Here, the first inner dam wall and the second inner dam wall each include, for example, a lower resin layer formed in the same layer and made of the same material as the planarizing film 22, and an upper resin layer formed in the same layer and made of the same material as the edge cover 32 on the lower resin layer. The first inner dam wall is provided so as to overlap the inner peripheral end of the organic sealing film 42 of the sealing film 45, and is configured to suppress the spreading of ink that becomes the organic sealing film 42.

[0058] Next, the operation of the organic EL display device 100 having the above configuration will be described.

[0059] 1, the display control circuit 150 receives an input image signal DIN and a group of timing signals (horizontal synchronization signal, vertical synchronization signal, etc.) TG sent from the outside, and outputs a digital video signal DV, a gate control signal GCTL that controls the operation of the gate driver 60, an emission driver control signal EMCTL that controls the operation of the emission driver 70, and a source control signal SCTL that controls the operation of the source driver 80. Here, the gate control signal GCTL includes a gate start pulse signal, a gate clock signal, etc. Furthermore, the emission driver control signal EMCTL includes an emission start pulse signal, an emission clock signal, etc. Furthermore, the source control signal SCTL includes a source start pulse signal, a source clock signal, a latch strobe signal, etc.

[0060] The gate driver 60 is electrically connected to the first scanning signal lines PS(1) to PS(i) and the second scanning signal lines NS(0) to NS(i). Based on the gate control signal GCTL output from the display control circuit 150, the gate driver 60 applies a first scanning signal to the first scanning signal lines PS(1) to PS(i) and a second scanning signal to the second scanning signal lines NS(0) to NS(i).

[0061] The emission driver 70 is electrically connected to the emission control lines EM(1) to EM(i). The emission driver 70 applies an emission control signal to the emission control lines EM(1) to EM(i) based on an emission driver control signal EMCTL output from the display control circuit 150.

[0062] The source driver 80 includes a j-bit shift register, a sampling circuit, a latch circuit, j D / A converters, and other components (not shown). The shift register has j registers connected in cascade. Based on a source clock signal, the shift register sequentially transfers pulses of a source start pulse signal supplied to the first register from its input terminal to its output terminal. Sampling pulses are output from the registers of each stage in response to the transfer of the pulses. The sampling circuit stores a digital video signal DV based on the sampling pulses. The latch circuit captures and holds one row's worth of digital video signal DV stored in the sampling circuit in accordance with a latch strobe signal. The D / A converters, provided corresponding to each data signal line D(1) to D(j), convert the digital video signal DV held in the latch circuit into an analog voltage and simultaneously apply the converted analog voltage to all data signal lines D(1) to D(j) as a data signal (data voltage).

[0063] In this manner, data signals are applied to the data signal lines D(1) to D(j), first scanning signals are applied to the first scanning signal lines PS(1) to PS(i), second scanning signals are applied to the second scanning signal lines NS(0) to NS(i), and light emission control signals are applied to the light emission control lines EM(1) to EM(i), whereby an image based on the input image signal DIN is displayed in the display area 50.

[0064] <Operation of Pixel Circuit> The operation of the pixel circuit of the organic EL display device 100 of this embodiment will be described below using the timing chart of Fig. 19. Note that this operation of the pixel circuit is just one example, and the present invention is not limited to this.

[0065] First, before time t01, the first scanning signal PS(n) is at a high level, and the second scanning signal NS(n-1), the second scanning signal NS(n), and the light-emission control signal EM(n) are at a low level. At this time, the power supply control TFT 9e and the light-emission control TFT 9f are in an on state, and the anode discharge TFT 9g is in an off state. Therefore, before time t01, a drive current corresponding to the charging voltage of the capacitor 9h is supplied to the organic EL element 35, and the organic EL element 35 emits light according to the magnitude of the drive current.

[0066] At time t01, the light-emission control signal EM(n) changes from low to high, turning the power supply control TFT 9e and the light-emission control TFT 9f off. As a result, the supply of drive current to the organic EL element 35 is cut off, and the organic EL element 35 is turned off. Furthermore, the light-emission control signal EM(n) changes from low to high, turning the anode discharge TFT 9g on. As a result, the voltage of the first electrode 31 of the organic EL element 35 is initialized based on the initialization voltage Vini.

[0067] At time t02, the second scanning signal NS(n-1) changes from low to high, turning on the initialization TFT 9a. As a result, the gate voltage of the drive TFT 9d is initialized. That is, the gate voltage of the drive TFT 9d becomes equal to the initialization voltage Vini.

[0068] At time t03, the second scanning signal NS(n-1) changes from high to low, turning the initialization TFT 9a off. Also at time t03, the second scanning signal NS(n) changes from low to high, turning the threshold voltage compensation TFT 9b on.

[0069] At time t04, the first scanning signal PS(n) changes from high to low, turning on the write control TFT 9c. Since the threshold voltage compensation TFT 9b was in the on state at time t03, the write control TFT 9c turns on at time t04, and the data signal D(m) is input to the second capacitance electrode of the capacitor 9h via the write control TFT 9c, the drive TFT 9d, and the threshold voltage compensation TFT 9b. This charges the capacitor 9h.

[0070] At time t05, the first scanning signal PS(n) changes from low level to high level, causing the write control TFT 9c to enter an OFF state.

[0071] At time t06, the second scanning signal NS(n) changes from high level to low level, causing the threshold voltage compensation TFT 9b to enter the OFF state.

[0072] At time t07, the light-emission control signal EM(n) changes from high to low, turning off the anode-discharge TFT 9g and turning on the power supply control TFT 9e and light-emission control TFT 9f, causing a drive current corresponding to the charging voltage of the capacitor 9h to be supplied to the organic EL element 35, causing the organic EL element 35 to emit light according to the magnitude of the drive current.

[0073] In this way, in the organic EL display device 100, the organic EL element 35 in each sub-pixel P emits light at a luminance corresponding to the drive current, thereby displaying an image.

[0074] Next, a description will be given of a method for manufacturing the organic EL display device 100 of this embodiment. The method for manufacturing the organic EL display device 100 includes a TFT layer forming step, an organic EL element layer forming step, a sealing film forming step, and a through-hole forming step.

[0075] <TFT Layer Formation Process> First, for example, a base coat film 11 is formed on a resin substrate 10 formed on a glass substrate by forming a silicon oxide film (thickness: about 500 nm), a silicon nitride film (thickness: about 60 nm), and a silicon oxide film (thickness: about 300 nm) by a plasma CVD (Chemical Vapor Deposition) method.

[0076] Next, an amorphous silicon film (about 50 nm thick) is formed on the substrate surface on which the base coat film 11 has been formed, for example, by plasma CVD, and the amorphous silicon film is crystallized by laser annealing or the like to form a first semiconductor film made of polysilicon, and then the first semiconductor film is patterned to form the first semiconductor layer 12a, etc.

[0077] Thereafter, a silicon oxide film (about 100 nm thick) is formed by, for example, plasma CVD on the substrate surface on which the first semiconductor layer 12a and the like are formed, thereby forming the first gate insulating film 13.

[0078] Furthermore, a molybdenum film (about 250 nm thick) or the like is formed on the surface of the substrate on which the first gate insulating film 13 is formed, for example, by sputtering to form a first metal film, and then the first metal film is patterned to form the first gate electrode 14 a, the first scanning signal line 14 g, the light emission control line 14 e, the initialization power supply line 14 i, etc.

[0079] Next, using the first gate electrode 14a as a mask, impurity ions are doped to make a portion of the first semiconductor layer 12a conductive, thereby forming a first conductor region 12aa, a second conductor region 12ab, and a first channel region 12ac in the first semiconductor layer 12a.

[0080] Thereafter, on the substrate surface on which the first conductor region 12aa etc. is formed, a single layer film of silicon oxide film (thickness: about 200 nm) or a laminated film in which a silicon nitride film (thickness: about 150 nm) and a silicon oxide film (thickness: about 50 nm) are sequentially laminated by, for example, a plasma CVD method to form a first interlayer insulating film 15, and then the laminated film of the first gate insulating film 13 and the first interlayer insulating film 15 is patterned to form a contact hole C.

[0081] Furthermore, a molybdenum film (approximately 250 nm thick) or the like is formed on the substrate surface on which the contact hole C is formed, for example, by sputtering, to form a second metal film, and then the second metal film is patterned to form conductive layers 16a and 16b, etc.

[0082] Next, on the surface of the substrate on which the conductive layer 16a and the like have been formed, InGaZnO ４ After forming a second semiconductor film made of an oxide semiconductor by depositing a film (thickness: about 30 nm) or the like, the second semiconductor film is patterned to form the second semiconductor layer 17a and the like.

[0083] Thereafter, a silicon oxide film (thickness: about 100 nm) is formed by, for example, plasma CVD on the surface of the substrate on which the second semiconductor layer 17a etc. are formed, and then a titanium film (thickness: about 50 nm), an aluminum film (thickness: about 400 nm), and a titanium film (thickness: about 50 nm) etc. are formed in this order by sputtering to form a third metal film, and the stacked film of the silicon oxide film and the third metal film is patterned to form the second gate insulating film 18, the second gate electrode 19a, the second scanning signal line 19h etc.

[0084] Subsequently, a silicon oxide film (with a thickness of about 500 nm) or the like is formed by, for example, plasma CVD on the substrate surface on which the second gate electrode 19a and the like are formed, thereby forming the second interlayer insulating film 20. Note that, by heat treatment after the formation of the second interlayer insulating film 20, a part of the second semiconductor layer 17a is made conductive, and a third conductor region 17aa, a fourth conductor region 17ab, and a second channel region 17ac are formed in the second semiconductor layer 17a.

[0085] Thereafter, on the substrate surface on which the second interlayer insulating film 20 has been formed, the first gate insulating film 13, the first interlayer insulating film 15, and the second interlayer insulating film 20 are appropriately patterned to form contact holes, and then, for example, by a sputtering method, a titanium film (thickness: about 50 nm), an aluminum film (thickness: about 400 nm), and a titanium film (thickness: about 50 nm) are formed in this order to form a fourth metal film, and the fourth metal film is patterned to form the first terminal electrode 21 a, the second terminal electrode 21 b, the third terminal electrode 21 c, the fourth terminal electrode 21 d, the data signal line 21 g, the high-level power supply line 21 h, etc.

[0086] Finally, a polyimide-based photosensitive resin film (about 2 μm thick) is applied to the substrate surface on which the first terminal electrodes 21 a etc. are formed, for example, by spin coating or slit coating, and then the applied film is pre-baked, exposed to light, developed, and post-baked to form a planarization film 22.

[0087] In this manner, the TFT layer 30 can be formed.

[0088] <Organic EL element layer formation process> Using a well-known method, a first electrode 31, an edge cover 32, an organic EL layer 33, and a second electrode 34 are formed on the planarization film 22 of the TFT layer 30 formed in the above-mentioned TFT layer formation process, thereby forming an organic EL element layer 40.

[0089] <Sealing film forming process> First, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is formed by plasma CVD using a mask on the surface of the substrate on which the organic EL element layer 40 formed in the organic EL element layer forming process is formed, thereby forming a first inorganic sealing film 41.

[0090] Subsequently, an organic resin material such as an acrylic resin is deposited by, for example, an inkjet method on the surface of the substrate on which the first inorganic sealing film 41 has been formed, to form an organic sealing film 42 .

[0091] Then, using a mask, an inorganic insulating film such as a silicon nitride film, a silicon oxide film, or a silicon oxynitride film is deposited by plasma CVD on the substrate surface on which the organic sealing film 42 has been formed, thereby forming a second inorganic sealing film 43, thereby forming a sealing film 45.

[0092] Finally, a protective sheet (not shown) is attached to the surface of the substrate on which the sealing film 45 is formed, and then laser light is irradiated from the glass substrate side of the resin substrate 10 to peel the glass substrate from the underside of the resin substrate 10, and a protective sheet (not shown) is attached to the underside of the resin substrate 10 from which the glass substrate has been peeled.

[0093] <Through-Hole Forming Step> In the non-display region 51 of the resin substrate 10 from which the glass substrate has been peeled off in the sealing film forming step, for example, a laser beam is irradiated while being scanned in a circular pattern to form a through-hole H. Thereafter, when the organic EL display device 100 having the through-hole H formed therein is fixed, for example, inside a housing, an electronic component 55 such as a camera or a fingerprint sensor is installed so that the electronic component 55 is located on the back side of the through-hole H.

[0094] In this manner, the organic EL display device 100 of this embodiment can be manufactured.

[0095] As described above, in the organic EL display device 100 of this embodiment, the circumferential lengths, in a plan view, of the subpixels P arranged along the inner periphery of the through-hole H of the display region 50 and the contact holes Cb of the subpixels P arranged along the outer periphery of the display region 50 are shorter than the circumferential lengths, in a plan view, of the contact holes Ca of the subpixels P arranged inside the display region 50. Therefore, moisture that penetrates from the interface between the resin substrate 10 and the base coat film 11 at the substrate edge surface and penetrates beyond the base coat film 11 and the first semiconductor layer 12a is confined by the contact holes Cb, which have a relatively short circumferential length, and therefore the amount of moisture that reaches the second semiconductor layer 17a through the contact holes Ca and Cb can be made uniform. This reduces the difference in moisture-induced performance degradation of the threshold voltage compensation TFTs 9b using oxide semiconductors in the subpixels P within the display region 50, and suppresses the occurrence of uneven light emission in the display region 50.

[0096] Furthermore, according to the organic EL display device 100 of this embodiment, the area in a plan view of the contact holes Cb of the subpixels P arranged along the inner periphery of the through holes H of the display region 50 and the subpixels P arranged along the outer periphery of the display region 50 is the same as the area in a plan view of the contact holes Ca of the subpixels P arranged inside the display region 50. This makes it possible to match the electrical resistance between the first conductor region 12aa and the conductive layer 16a of the first semiconductor layer 12a, which are electrically connected via the contact holes Ca, and the electrical resistance between the first conductor region 12aa and the conductive layer 16a of the first semiconductor layer 12a, which are electrically connected via the contact holes Cb.

[0097] Second Embodiment FIGS. 20 to 22 show a second embodiment of a display device according to the present invention. FIG. 20 is a plan view schematically showing the division of different contact hole shapes in a display region 50a of an organic EL display device according to this embodiment. FIG. 21 is a plan view schematically showing the division of different contact hole shapes in a display region 50b in a first modified example of this embodiment. FIG. 22 is a plan view schematically showing the division of different contact hole shapes in a display region 50c in a second modified example of this embodiment. In the following embodiments, the same components as those in FIGS. 1 to 19 are designated by the same reference numerals, and detailed descriptions thereof will be omitted.

[0098] In the first embodiment described above, an organic EL display device 100 was illustrated in which the circumferential length of the contact hole C of each subpixel P is different in two stages for each region within the display region 50, but in this embodiment, an organic EL display device is illustrated in which the circumferential length of the contact hole C of each subpixel P is different in three stages for each region within the display region 50a.

[0099] The organic EL display device of this embodiment includes a display area 50a for displaying images, and a gate driver 60 (see FIG. 1), an emission driver 70 (see FIG. 1), and a source driver 80 (see FIG. 1) provided in a frame area surrounding the display area 50a. Similar to the organic EL display device 100 of the first embodiment, the organic EL display device of this embodiment includes a resin substrate 10, a TFT layer 30 provided on the resin substrate 10, an organic EL element layer 40 provided as a light-emitting element layer on the TFT layer 30, and a sealing film 45 provided on the organic EL element layer 40.

[0100] In the display region 50a, a plurality of sub-pixels P are arranged in a matrix, similar to the display region 50 of the first embodiment. Also, in the display region 50a, similar to the display region 50 of the first embodiment, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are arranged adjacent to one another. Here, in the display region 50a, similar to the display region 50 of the first embodiment, one pixel is formed by, for example, three adjacent sub-pixels P having a red light-emitting region Er, a green light-emitting region Eg, and a blue light-emitting region Eb. Also, as shown in FIG. 20 , the display region 50a is formed in a substantially rectangular shape with arc-shaped corners, but the corners may be right-angled. In addition, an island-shaped non-display area 51 (see Figure 9) is provided inside the display area 50a along the edge of the display area 50a, and a through hole H is provided in the non-display area 51, penetrating through the thickness of the resin substrate 10, in order to install an electronic component 55 on the back side, as shown in Figure 20.

[0101] 20 , the display region 50a includes a first region Ra disposed therein, a second region Rb including a portion disposed along the outer periphery of the first region Ra separated from the through-hole H and a portion disposed along the opposite side (the left side in the figure) of the inner periphery of the second region Rb, and a third region Rc disposed between the outer and inner peripheries of the second region Rb and the third region Rc. In the display region 50a, moisture is less likely to penetrate in the order of the first region Ra, the second region Rb, and the third region Rc. Therefore, the circumferential length, in a plan view, of the contact hole C of the subpixel P disposed in the second region Rb is longer than the circumferential length, in a plan view, of the contact hole C of the subpixel P disposed in the third region Rc, but shorter than the circumferential length, in a plan view, of the contact hole C of the subpixel P disposed in the first region Ra. Furthermore, the planar areas of the contact holes C of the subpixels P disposed in the first region Ra, the second region Rb, and the third region Rc are all equal to one another. In the specific shapes of the contact holes C described in the first embodiment, the relationship in perimeter in plan view is Cab>Cac>Caa>Ca>Cad>Cb, and the relationship in area in plan view is Ca=Caa=Cab=Cac=Cad=Cb. Therefore, for example, one example of a combination is where the contact hole C of the sub-pixel P arranged in the first region Ra is contact hole Cab, the contact hole C of the sub-pixel P arranged in the second region Ra is contact hole Ca, and the contact hole C of the sub-pixel P arranged in the third region Rc is contact hole Cb.

[0102] The organic EL display device of this embodiment may also include a display region 50b for displaying an image, and a gate driver 60 (see FIG. 1), an emission driver 70 (see FIG. 1), and a source driver 80 (see FIG. 1) provided in a frame region around the display region 50b.

[0103] The display region 50b has a plurality of subpixels P arranged in a matrix, similar to the display region 50 of the first embodiment. Also, similar to the display region 50 of the first embodiment, the display region 50b includes adjacent subpixels P, for example, a subpixel P having a red light-emitting region Er for displaying red, a subpixel P having a green light-emitting region Eg for displaying green, and a subpixel P having a blue light-emitting region Eb for displaying blue. Here, similar to the display region 50 of the first embodiment, one pixel is formed by three adjacent subpixels P, each having a red light-emitting region Er, a green light-emitting region Eg, and a blue light-emitting region Eb. As shown in FIG. 21 , the display region 50b has a substantially rectangular shape with arc-shaped corners, but the corners may also be right-angled. Also, as shown in FIG. 21 , a notch N is provided at the edge of the display region 50b, penetrating the resin substrate 10 in the thickness direction and opening laterally in a plan view, for installing an electronic component 55 on the back side.

[0104] 21 , the display region 50b includes a first region Ra disposed therein, a second region Rb consisting of a portion disposed along the periphery of the cutout N and spaced from it and a portion disposed along the closed side (left side in the figure) of the cutout N, and a third region Rc disposed along the open side (right side in the figure) of the cutout N. In the display region 50b, moisture is less likely to penetrate in the order of the first region Ra, the second region Rb, and the third region Rc. Therefore, the circumferential length in a plan view of the contact hole C of the sub-pixel P disposed in the second region Rb is longer than the circumferential length in a plan view of the contact hole C of the sub-pixel P disposed in the third region Rc, but shorter than the circumferential length in a plan view of the contact hole C of the sub-pixel P disposed in the first region Ra, as in the display region 50a. Furthermore, the planar area of ​​the contact hole C of the sub-pixel P arranged in the first region Ra, the planar area of ​​the contact hole C of the sub-pixel P arranged in the second region Rb, and the planar area of ​​the contact hole C of the sub-pixel P arranged in the third region Rc are all equal to each other, as in the display region 50a.

[0105] The organic EL display device of this embodiment may also include a display region 50c for displaying images, and a gate driver 60 (see FIG. 1), an emission driver 70 (see FIG. 1), and a source driver 80 (see FIG. 1) provided in a frame region around the display region 50c.

[0106] In the display region 50c, a plurality of sub-pixels P are arranged in a matrix, similar to the display region 50 of the first embodiment. Also, in the display region 50c, similar to the display region 50 of the first embodiment, for example, a sub-pixel P having a red light-emitting region Er for displaying red, a sub-pixel P having a green light-emitting region Eg for displaying green, and a sub-pixel P having a blue light-emitting region Eb for displaying blue are provided adjacent to one another. Here, in the display region 50c, similar to the display region 50 of the first embodiment, one pixel is configured by, for example, three adjacent sub-pixels P having the red light-emitting region Er, the green light-emitting region Eg, and the blue light-emitting region Eb.

[0107] 22 , the outline of the display region 50c includes a linear portion L that extends linearly and a curved portion A that includes three arcs connected to both ends of the linear portion L, forming the outline of a so-called free-form display. The display region 50c includes a first region Ra disposed therein, a second region Rb that is spaced apart along the linear portion L, and a third region Rc that is disposed along the curved portion A. In the display region 50c, moisture is less likely to penetrate in the order of the first region Ra, the second region Rb, and the third region Rc. Therefore, the circumferential length in a plan view of the contact hole C of the subpixel P disposed in the second region Rb is longer than the circumferential length in a plan view of the contact hole C of the subpixel P disposed in the third region Rc, but shorter than the circumferential length in a plan view of the contact hole C of the subpixel P disposed in the first region Ra, similar to the display region 50a. Furthermore, the planar area of ​​the contact hole C of the sub-pixel P arranged in the first region Ra, the planar area of ​​the contact hole C of the sub-pixel P arranged in the second region Rb, and the planar area of ​​the contact hole C of the sub-pixel P arranged in the third region Rc are all equal to each other, as in the display region 50a.

[0108] Furthermore, in an organic EL display device having the display region 50a, 50b, or 50c configured as described above, the organic EL element 35 emits light at a luminance corresponding to the drive current in each sub-pixel P, thereby displaying an image, in the same manner as the organic EL display device 100 of the first embodiment described above.

[0109] The organic EL display device of this embodiment can be manufactured by changing the shape of the contact holes C from two types to three types in the TFT layer formation step of the manufacturing method for the organic EL display device 100 of the first embodiment described above.

[0110] As described above, in the organic EL display device including the display region 50a, 50b, or 50c of this embodiment, moisture is less likely to penetrate in the order of the first region Ra, the second region Rb, and the third region Rc. Therefore, the circumferential length, in a plan view, of the contact hole C of the subpixel P arranged in the second region Rb is longer than the circumferential length, in a plan view, of the contact hole C of the subpixel P arranged in the third region Rc, but shorter than the circumferential length, in a plan view, of the contact hole C of the subpixel P arranged in the first region Ra. Therefore, the amounts of moisture reaching the second semiconductor layer 17a through the contact hole C can be made uniform in the threshold voltage compensation TFTs 9b of the subpixels P arranged in the first region Ra, the second region Rb, and the third region Rc. This reduces the difference in moisture-induced performance degradation of the threshold voltage compensation TFTs 9b using oxide semiconductors in each subpixel P within the display region 50a, 50b, or 50c, and suppresses the occurrence of uneven light emission in the display region 50a, 50b, or 50c.

[0111] Furthermore, in the organic EL display device including the display region 50a, 50b, or 50c of this embodiment, the area in a plan view of the contact hole C of the subpixel P arranged in the first region Ra, the area in a plan view of the contact hole C of the subpixel P arranged in the second region Rb, and the area in a plan view of the contact hole C of the subpixel P arranged in the third region Rc are all equal to one another. This makes it possible to make the electrical resistance between the first conductor region 12aa and the conductive layer 16a of the first semiconductor layer 12a, which are electrically connected via the contact hole C, uniform in the first region Ra, the second region Rb, and the third region Rc.

[0112] Other Embodiments In the above-described embodiments, the organic EL layer has a five-layer laminated structure including a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. However, the organic EL layer may have a three-layer laminated structure including, for example, a hole injection layer / hole transport layer, a light-emitting layer, and an electron transport layer / electron injection layer.

[0113] In addition, in each of the above embodiments, an organic EL display device in which the first electrode is an anode and the second electrode is a cathode is exemplified. However, the present invention can also be applied to an organic EL display device in which the stacked structure of the organic EL layer is reversed, and the first electrode is a cathode and the second electrode is an anode.

[0114] Furthermore, in each of the above embodiments, an organic EL display device has been described as an example of a display device. However, the present invention can be applied to a display device including a plurality of light-emitting elements driven by current, and can be applied to, for example, a display device including QLEDs (Quantum-dot light emitting diodes), which are light-emitting elements using a quantum dot-containing layer.

[0115] As described above, the present invention is useful for flexible display devices.

[0116] A Curved portion C, Ca, Caa, Cab, Cac, Cad, Cae, Caf, Cb Contact hole H Through hole L Straight portion N Notched portion 9b Threshold voltage compensation TFT (threshold voltage compensation thin film transistor, second thin film transistor) 9d Drive TFT (drive thin film transistor, first thin film transistor) 10 Resin substrate 11 Base coat film (first inorganic insulating film) 12a First semiconductor layer 12aa First conductor region 12ab Second conductor region 12ac First channel region 13 First gate insulating film (second inorganic insulating film) 14a First gate electrode 15 First interlayer insulating film (third inorganic insulating film) 16a Conductive layer 17a Second semiconductor layer 17aa Third conductor region 17ab Fourth conductor region 17ac Second channel region 18 Second gate insulating film (fourth inorganic insulating film) 19a Second gate electrode 30 TFT layer (thin film transistor layer) 35 Organic EL element (organic electroluminescence element, light emitting element) 40 Organic EL element layer (light emitting element layer) 45 Sealing film 50 Display area 51 Non-display area 100 Organic EL display device

Claims

1. A semiconductor device comprising: a resin substrate; and a thin film transistor layer provided on the resin substrate, in which a first inorganic insulating film, a first semiconductor film made of polysilicon, a second inorganic insulating film, a first metal film, a third inorganic insulating film, a second metal film, a second semiconductor film made of an oxide semiconductor, a fourth inorganic insulating film and a third metal film are laminated in this order, the thin film transistor layer including at least one first thin film transistor having a first semiconductor layer formed by the first semiconductor film and a second thin film transistor having a second semiconductor layer formed by the second semiconductor film, for each sub-pixel constituting a display area, the first thin film transistor including: the first semiconductor layer including a first conductor region and a second conductor region defined to be spaced apart from each other and a first channel region defined between the first conductor region and the second conductor region; and a first gate electrode provided by the first metal film to overlap the first channel region via the second inorganic insulating film, the second thin film transistor comprises the second semiconductor layer in which a third conductor region and a fourth conductor region are defined so as to be spaced apart from each other and a second channel region is defined between the third conductor region and the fourth conductor region, and a second gate electrode provided by the third metal film so as to overlap the second channel region via the fourth inorganic insulating film, and in each of the sub-pixels, in a portion where the first conductor region and the third conductor region are electrically connected, the first conductor region and the third conductor region are electrically connected via contact holes formed in the second inorganic insulating film and the third inorganic insulating film and a conductive layer formed in the second metal film so as to cover the contact holes, the display device being characterized in that a circumferential length in a planar view of the contact holes of the sub-pixels arranged along the periphery of the display region is shorter than a circumferential length in a planar view of the contact holes of the sub-pixels arranged inside the display region.

2. A display device according to claim 1, characterized in that the area in a plan view of the contact hole of the sub-pixel arranged along the periphery of the display region is the same as the area in a plan view of the contact hole of the sub-pixel arranged inside the display region.

3. A display device according to claim 1 or 2, characterized in that an island-shaped non-display region is provided inside the display region, a through-hole is formed in the non-display region penetrating in the thickness direction of the resin substrate, and the perimeter in a planar view of the contact hole of the sub-pixel arranged along the inner periphery of the through-hole of the display region is shorter than the perimeter in a planar view of the contact hole of the sub-pixel arranged inside the display region and is the same as the perimeter in a planar view of the contact hole of the sub-pixel arranged along the outer periphery of the display region.

4. A display device according to claim 3, characterized in that the area in a plan view of the contact hole of the sub-pixel arranged along the inner periphery of the display region is the same as the area in a plan view of the contact hole of the sub-pixel arranged along the outer periphery of the display region, and the area in a plan view of the contact hole of the sub-pixel arranged inside the display region.

5. A display device according to claim 1 or 2, wherein an island-shaped non-display region is provided inside the display region along an edge of the display region, and a through hole is formed in the non-display region, penetrating in the thickness direction of the resin substrate, and the circumferential length in a plan view of the contact hole of the sub-pixel arranged along the opposite side to the edge of the inner periphery along the through hole of the display region, and the circumferential length in a plan view of the contact hole of the sub-pixel arranged along the outer periphery spaced from the through hole of the display region are longer than the circumferential length in a plan view of the contact hole of the sub-pixel arranged between the outer periphery and the inner periphery of the display region and shorter than the circumferential length in a plan view of the contact hole of the sub-pixel arranged inside the display region.

6. A display device according to claim 5, wherein the area in a plan view of the contact hole of the sub-pixel arranged along the side opposite to the edge of the inner circumference of the display area, the area in a plan view of the contact hole of the sub-pixel arranged along the outer circumference spaced from the through-hole of the display area, the area in a plan view of the contact hole of the sub-pixel arranged between the outer circumference and the inner circumference of the display area, and the area in a plan view of the contact hole of the sub-pixel arranged inside the display area are all the same.

7. A display device according to claim 1 or 2, wherein a cutout portion is provided at the edge of the display area, penetrating in the thickness direction of the resin substrate and opening laterally in a plan view, and the circumferential length in a plan view of the contact hole of the sub-pixel arranged along the closed side of the cutout of the display area and the circumferential length in a plan view of the contact hole of the sub-pixel arranged along the periphery of the display area spaced apart from the cutout are longer than the circumferential length in a plan view of the contact hole of the sub-pixel arranged along the open side of the cutout of the display area and shorter than the circumferential length in a plan view of the contact hole of the sub-pixel arranged inside the display area.

8. A display device according to claim 7, wherein the area in a plan view of the contact hole of the sub-pixel arranged along the closed side of the cutout of the display region and the area in a plan view of the contact hole of the sub-pixel arranged along the periphery spaced from the cutout of the display region, the area in a plan view of the contact hole of the sub-pixel arranged along the open side of the cutout of the display region, and the area in a plan view of the contact hole of the sub-pixel arranged inside the display region are all the same.

9. A display device according to claim 1 or 2, wherein the contour of the display area comprises a straight line portion extending in a straight line and a curved portion including at least one circular arc, connected to both ends of the straight line portion, and the perimeter in a planar view of the contact hole of the sub-pixel arranged along the straight line portion of the display area is longer than the perimeter in a planar view of the contact hole of the sub-pixel arranged along the curved portion of the display area, and shorter than the perimeter in a planar view of the contact hole of the sub-pixel arranged inside the display area.

10. A display device according to claim 9, wherein the area in a plan view of the contact hole of the sub-pixel arranged along the straight portion of the display area, the area in a plan view of the contact hole of the sub-pixel arranged along the curved portion of the display area, and the area in a plan view of the contact hole of the sub-pixel arranged inside the display area are all the same.

11. A display device according to claim 1 or 2, characterized in that the planar shape of the contact holes of the sub-pixels arranged along the periphery of the display area is circular, and the planar shape of the contact holes of the sub-pixels arranged inside the display area is polygonal.

12. A display device according to any one of claims 1 to 11, characterized in that the first thin film transistor having the first conductor region electrically connected via the contact hole is a driving thin film transistor, and the second thin film transistor having the third conductor region electrically connected via the contact hole is a threshold voltage compensation thin film transistor.

13. The display device according to any one of claims 1 to 12, further comprising: a light emitting element layer provided on said thin film transistor layer, in which a plurality of light emitting elements are arranged corresponding to a plurality of sub-pixels constituting said display area; and a sealing film provided on said light emitting element layer.

14. The display device according to claim 13, wherein each of the light-emitting elements is an organic electroluminescence element.

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