Semiconductor device

Abstract

This semiconductor device includes: a chip having a main surface; a semiconductor region of a first conductivity type formed on a surface layer part of the main surface; a device structure having a source structure and formed in the semiconductor region in a part inside the main surface; a peripheral source electrode part having a first outer edge, disposed on a peripheral edge part of the main surface, and electrically connected to the source structure; and a termination region of a second conductivity type having a second outer edge positioned closer to the peripheral edge side of the main surface than the first outer edge and formed in the surface layer part of the semiconductor region at the peripheral edge part of the main surface, the termination region being electrically connected to the peripheral source electrode part. A first distance between the first outer edge of the peripheral source electrode part and the second outer edge of the terminal region is 10 μm or more.

Description

Semiconductor Devices Related Applications

[0001] This application corresponds to Japanese Patent Application No. 2023-173818 filed with the Japan Patent Office on October 5, 2023, the entire disclosure of which is incorporated herein by reference.

[0002] The present disclosure relates to semiconductor devices.

[0003] Patent Document 1 discloses a semiconductor device having a termination structure in the peripheral region of a drift layer.

[0004] US Patent Application Publication No. 2008 / 0277669

[0005] [Summary] One embodiment of the present disclosure provides a semiconductor device having a novel layout, which can suppress the occurrence of defects caused by oxidation of a peripheral source electrode portion.

[0006] One embodiment of the present disclosure provides a semiconductor device including: a chip having a main surface; a semiconductor region of a first conductivity type formed in a surface layer portion of the main surface; a device structure having a source structure and formed in the semiconductor region in an inner portion of the main surface; a peripheral source electrode portion having a first outer edge and disposed on a peripheral portion of the main surface and electrically connected to the source structure; and a termination region of a second conductivity type formed in a surface layer portion of the semiconductor region in the peripheral portion of the main surface and having a second outer edge located closer to the peripheral portion of the main surface than the first outer edge, the termination region being electrically connected to the peripheral source electrode portion, wherein a first distance between the first outer edge of the peripheral source electrode portion and the second outer edge of the termination region is 10 μm or more.

[0007] FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1 . FIG. 4 is a plan view showing a layout example of a first main surface. FIG. 5 is an enlarged view of a portion surrounded by dashed line V in FIG. 4 . FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. 5 . FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 5 . FIG. 8 is an enlarged view of a portion surrounded by dashed line VIII in FIG. 4 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 8 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8 . FIG. 13 is an enlarged view of a portion surrounded by dashed line XIII in FIG. 4 . FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. 13 . FIG. 15 is an enlarged view of a portion surrounded by dashed line XV in FIG. 4 . FIG. 16 is a cross-sectional view taken along line XVI-XVI in FIG. 15 . FIG. 17 is a cross-sectional view taken along line XVII-XVII in FIG. 1 , along with a peripheral structure according to a first embodiment. FIG. 18 is a cross-sectional view taken along line XVIII-XVIII in FIG. 1 . FIG. 19 is an enlarged view of a portion surrounded by dashed line XIX in FIG. 17 . FIG. 20 is a plan view showing an example layout of main electrodes disposed on the first main surface. FIG. 21 is a plan view showing an example layout of a second inorganic film. FIG. 22 is a cross-sectional view showing a cross-sectional structure of a semiconductor device together with a peripheral structure according to a second embodiment, and corresponds to FIG. 19 . FIG. 23 is a cross-sectional view of a semiconductor device according to a reference embodiment, and corresponds to FIG. 19 . FIG. 24 is a cross-sectional view of a semiconductor device according to another embodiment of the present disclosure, and corresponds to FIG. 19 .

[0008] [Detailed Description] Specific embodiments will be described in detail below with reference to the accompanying drawings. The accompanying drawings are all schematic diagrams and are not strictly illustrative, and the relative positional relationships, scales, ratios, angles, etc. are not necessarily consistent. Corresponding structures among the accompanying drawings are given the same reference numerals, and duplicated descriptions are omitted or simplified. For structures whose descriptions are omitted or simplified, the descriptions given before the omission or simplification apply.

[0009] When the term "substantially" is used in this specification, this term includes a numerical value (form) equal to the numerical value (form) of the comparison target, as well as a numerical error (form error) within a range of ±10% based on the numerical value (form) of the comparison target. In the following description, terms such as "first," "second," and "third" are used, but these are symbols attached to the names of each structure to clarify the order of description, and are not intended to limit the names of each structure.

[0010] In the following description, the conductivity type of a semiconductor (impurity) is indicated using "p-type" or "n-type," but "n-type" may also be referred to as the "first conductivity type" and "p-type" as the "second conductivity type." "p-type" is a conductivity type resulting from a trivalent element, and "n-type" is a conductivity type resulting from a pentavalent element. The trivalent element is at least one of boron, aluminum, gallium, and indium. The pentavalent element is at least one of nitrogen, phosphorus, arsenic, antimony, and bismuth.

[0011] FIG. 1 is a plan view showing a semiconductor device 1 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1 . FIG. 3 is a cross-sectional view taken along line III-III in FIG. 1 . The semiconductor device 1 is a semiconductor switching device including an insulated gate transistor structure (device structure) Tr. The transistor structure Tr may also be referred to as a MISFET structure (Metal Insulator Semiconductor Field Effect Transistor structure). FIG. 4 is a plan view showing an example layout of a first main surface 3.

[0012] 1 to 3, semiconductor device 1 includes a single crystal of a wide bandgap semiconductor. In this embodiment, the wide bandgap semiconductor includes chip 2 formed in a hexahedral shape (specifically, a rectangular parallelepiped shape). Semiconductor device 1 is a "wide bandgap semiconductor device." Chip 2 may also be called a "semiconductor chip," a "wide bandgap semiconductor chip," or the like.

[0013] A wide bandgap semiconductor is a semiconductor having a bandgap that exceeds the bandgap of Si (silicon). Examples of wide bandgap semiconductors include GaN (gallium nitride), SiC (silicon carbide), and C (diamond). In this embodiment, the chip 2 is a "SiC chip" that includes a hexagonal SiC single crystal as an example of a wide bandgap semiconductor. The semiconductor device 1 is a "SiC semiconductor device."

[0014] The semiconductor device 1 may be referred to as a "SiC-MISFET." Hexagonal SiC single crystal has a variety of polytypes, including 2H (Hexagonal)-SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal. In this embodiment, an example is shown in which the chip 2 includes a 4H-SiC single crystal, but the chip 2 may also include other polytypes.

[0015] 1 to 3, chip 2 has a first main surface (principal surface) 3 on one side, a second main surface 4 on the other side, and first to fourth side surfaces 5A to 5D connecting first main surface 3 and second main surface 4. First main surface 3 and second main surface 4 are formed in a quadrangular shape in a plan view seen from vertical direction Z (hereinafter simply referred to as "plan view"). Vertical direction Z coincides with the thickness direction of chip 2.

[0016] The first main surface 3 and the second main surface 4 are preferably formed by the c-plane of the SiC single crystal. In this case, it is preferable that the first main surface 3 is formed by the silicon surface ((0001) surface) of the SiC single crystal, and the second main surface 4 is formed by the carbon surface ((000-1) surface) of the SiC single crystal.

[0017] The first side surface 5A and the second side surface 5B extend in a first direction X along the first main surface 3 and face a second direction Y that intersects with the first direction X along the first main surface 3. Specifically, the second direction Y is perpendicular to the first direction X. The third side surface 5C and the fourth side surface 5D extend in the second direction Y and face the first direction X.

[0018] In this embodiment, the first direction X is the a-axis direction ([11-20] direction) of the SiC single crystal, and the second direction Y is the m-axis direction ([1-100] direction) of the SiC single crystal. Of course, the first direction X may be the m-axis direction of the SiC single crystal, and the second direction Y may be the a-axis direction of the SiC single crystal. Hereinafter, the direction extending along the first main surface 3 may be referred to as the "horizontal direction." The horizontal direction is also the XY plane (horizontal plane) formed by the first direction X and the second direction Y, and is perpendicular to the vertical direction Z. The first main surface 3 and the second main surface 4 have an off-angle inclined at a predetermined angle in a predetermined off-direction with respect to the c-plane. The c-axis ((0001) axis) of the SiC single crystal is inclined by the off-angle from a vertical line along the vertical direction Z toward the off-direction. Furthermore, the c-plane of the SiC single crystal is inclined by the off-angle with respect to the horizontal plane. The off-axis direction is preferably the a-axis direction (first direction X) of the SiC single crystal. The off-axis angle may be greater than 0° and equal to or less than 10°.

[0019] 2 and 3, the semiconductor device 1 includes an n-type first semiconductor region 6 formed in a surface layer portion of the second main surface 4 of the chip 2. A drain potential is applied to the first semiconductor region 6 as a first potential (high potential). The first semiconductor region 6 extends in a layered form along the second main surface 4 and is exposed from the second main surface 4 and the first to fourth side surfaces 5A to 5D. In this embodiment, the first semiconductor region 6 is made of an n-type semiconductor layer. Specifically, the first semiconductor region 6 is made of a substrate (SiC substrate) including a SiC single crystal (semiconductor single crystal). The first semiconductor region 6 forms the second main surface 4 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The first semiconductor region 6 (substrate) has the off direction and off angle described above. The first semiconductor region 6 may have a thickness of 10 μm to 500 μm.

[0020] The semiconductor device 1 includes an n-type second semiconductor region (semiconductor region) 7 formed in a surface layer portion of the first main surface 3. The second semiconductor region 7 may also be referred to as a "semiconductor region," a "semiconductor layer," a "second semiconductor layer," a "drift region," or the like. The second semiconductor region 7 has an n-type impurity concentration lower than the n-type impurity concentration of the first semiconductor region 6. The second semiconductor region 7 is formed in a region on the first main surface 3 side of the first semiconductor region 6 in a cross-sectional view. The second semiconductor region 7 extends in a layer shape along the first main surface 3 and is electrically connected to the first semiconductor region 6. The second semiconductor region 7 is exposed from the first main surface 3 of the chip 2 and first to fourth side surfaces 5A to 5D of the chip 2.

[0021] In this embodiment, the second semiconductor region 7 is made of an n-type semiconductor layer. Specifically, the second semiconductor region 7 is made of an epitaxial layer (SiC epitaxial layer) including a SiC single crystal (semiconductor single crystal). The second semiconductor region 7 (epitaxial layer) forms the first main surface 3 of the chip 2 and the first to fourth side surfaces 5A to 5D of the chip 2. The second semiconductor region 7 (epitaxial layer) has the off direction and off angle described above. The second semiconductor region 7 has a thickness T1 (see also Figures 17 to 19) that is less than the thickness of the first semiconductor region 6. The thickness T1 of the second semiconductor region 7 may be 5 μm or more and 15 μm or less. The thickness T1 of the second semiconductor region 7 may have a value belonging to at least one of the ranges of 5 μm or more and 7.5 μm or less, 7.5 μm or more and 10 μm or less, 10 μm or more and 12.5 μm or less, and 12.5 μm or more and 15 μm or less.

[0022] 1 and 4, semiconductor device 1 includes first surface portion 8, second surface portion 9, and first to fourth connection surface portions 10A to 10D formed on first main surface 3. First surface portion 8, second surface portion 9, and first to fourth connection surface portions 10A to 10D define mesas 11 on first main surface 3.

[0023] The first surface portion 8 is formed at a distance inward from the periphery (first to fourth side surfaces 5A to 5D) of the first main surface 3. The first surface portion 8 has a flat surface extending in the horizontal direction and is formed by a c-plane (Si-plane). In this embodiment, the first surface portion 8 is formed in a polygonal shape (specifically, a quadrilateral shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view.

[0024] The second surface portion 9 is located closer to the periphery of the first main surface 3 than the first surface portion 8, and is recessed from the height of the first surface portion 8 in the thickness direction of the chip 2 (toward the second main surface 4). The second surface portion 9 extends in a strip shape along the first surface portion 8 in a plan view, and is formed in a ring shape (specifically, a quadrangular ring) surrounding the first surface portion 8. The second surface portion 9 is continuous with the first to fourth side surfaces 5A to 5D. The second surface portion 9 is formed approximately parallel to the first surface portion 8, and has a flat surface extending in the horizontal direction. In this embodiment, the second surface portion 9 is formed by the c-plane (Si-plane).

[0025] The first to fourth connection surface portions 10A to 10D extend in the vertical direction Z and are connected to the first surface portion 8 and the second surface portion 9. The first connection surface portion 10A, the second connection surface portion 10B, the third connection surface portion 10C, and the fourth connection surface portion 10D are located on the first side surface 5A side, the second side surface 5B side, the third side surface 5C side, and the fourth side surface 5D side, respectively. The first connection surface portion 10A and the second connection surface portion 10B extend in the first direction X and face the second direction Y. The third connection surface portion 10C and the fourth connection surface portion 10D extend in the second direction Y and face the first direction X.

[0026] The mesa 11 is defined in a protruding (convex) shape on the first main surface 3. The mesa 11 is formed only in the second semiconductor region 7, and not in the first semiconductor region 6. The first to fourth connecting surface portions 10A to 10D may extend substantially perpendicularly between the first surface portion 8 and the second surface portion 9, and define the mesa 11 in a quadrangular prism shape. The first to fourth connecting surface portions 10A to 10D may be inclined obliquely downward from the first surface portion 8 toward the second surface portion 9, and define the mesa 11 in a quadrangular pyramid shape.

[0027] The semiconductor device 1 has an active region 12, a first end region 13, a second end region 14, a third end region 15, a fourth end region 16, a fifth end region 17, a sixth end region 18 and a peripheral region 19 on the first main surface 3.

[0028] The active region 12 is a region including a transistor structure Tr. The active region 12 is a region where an output current (drain current) is generated. The active region 12 is provided in an inner portion of the first main surface 3, spaced apart from the periphery of the first main surface 3 (the first to fourth connecting surface portions 10A to 10D). In this embodiment, the active region 12 is provided in a polygonal shape (specifically, a rectangular shape) having four sides parallel to the first to fourth side surfaces 5A to 5D in a plan view. The ratio (area ratio) of the planar area of ​​the active region 12 to the planar area of ​​the first main surface 3 may be 0.5 or more and 0.95 or less. This area ratio may have a value belonging to any one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and 0.95 or less.

[0029] The first end region 13 is provided on one side of the active region 12 in the first direction X (the third connection surface 10C side) on the first surface 8, and faces the active region 12 in the first direction X. In this embodiment, the first end region 13 extends in a strip shape in the second direction Y in plan view. The second end region 14 is provided on the other side of the active region 12 in the first direction X (the fourth connection surface 10D side) on the first surface 8, and faces the first end region 13 across the active region 12 in the first direction X. In this embodiment, the second end region 14 extends in a strip shape in the second direction Y in plan view.

[0030] The third end region 15 is provided on one side in the second direction Y (the first connection surface portion 10A side) of the active region 12 and faces the active region 12 in the second direction Y. In this embodiment, the third end region 15 extends in the first direction X in a plan view and faces the first end region 13 and the second end region 14 in the second direction Y. The fourth end region 16 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the active region 12 and faces the third end region 15 in the second direction Y, with the active region 12 sandwiched between them. In this embodiment, the fourth end region 16 extends in the first direction X in a plan view and faces the first end region 13 and the second end region 14 in the second direction Y.

[0031] The fifth end region 17 is provided on one side in the second direction Y (the first connection surface portion 10A side) of the third end region 15 and faces the active region 12 across the third end region 15 in the second direction Y. The fifth end region 17 is provided in a region between the periphery of the first surface portion 8 and the third end region 15. In this embodiment, the fifth end region 17 extends in a strip shape in the first direction X in a plan view and faces the first end region 13 and the second end region 14 across the third end region 15. The sixth end region 18 is provided on the other side in the second direction Y (the second connection surface portion 10B side) of the fourth end region 16 and faces the active region 12 across the fourth end region 16 in the second direction Y. The sixth end region 18 is provided in a region between the periphery of the first surface portion 8 and the fourth end region 16. In this embodiment, the sixth end region 18 extends in a strip shape in the first direction X in a plan view, and faces the first end region 13 and the second end region 14 with the fourth end region 16 interposed therebetween.

[0032] The peripheral region 19 is provided as an inactive region on the second surface 9. In this embodiment, the peripheral region 19 is provided in a ring shape (specifically, a rectangular ring shape) surrounding the first surface 8 (mesa 11) in plan view. The peripheral region 19 surrounds the active region 12, the first end region 13, the second end region 14, the third end region 15, the fourth end region 16, the fifth end region 17, and the sixth end region 18 in plan view.

[0033] The configuration of the active region 12 will be described below. Fig. 5 is an enlarged view of the portion surrounded by the dashed line V in Fig. 4. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 5.

[0034] The semiconductor device 1 includes a p-type body region 20 formed in a surface layer of the first surface portion 8 (first main surface 3) in the active region 12. A source potential of a second potential (low potential) different from a first potential (high potential) is applied to the body region 20. The source potential may be a reference potential that serves as a reference for circuit operation. The reference potential may be ground potential or a potential other than ground potential.

[0035] The body region 20 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3, and faces the first semiconductor region 6 across a part of the second semiconductor region 7. The body region 20 is formed at a distance from the depth position of the second surface portion 9 toward the first main surface 3. The body region 20 extends in a layered form along the first surface portion 8. In this embodiment, the body region 20 is formed over the entire first surface portion 8, and is exposed from the first to fourth connection surface portions 10A to 10D.

[0036] The semiconductor device 1 includes an n-type source region 21 formed in a surface layer portion of the first surface portion 8 (first main surface 3) in the active region 12. A source potential is applied to the source region 21. The source region 21 has an n-type impurity concentration higher than the n-type impurity concentration of the second semiconductor region 7.

[0037] The source region 21 is formed in a surface layer portion of the body region 20. Specifically, the source region 21 is formed at a distance from the bottom of the body region 20 toward the first main surface 3. The source region 21 is formed in a region on the first main surface 3 side of the body region 20. The source region 21 forms a channel of a transistor together with the second semiconductor region 7 in the body region 20. In this embodiment, the source region 21 is formed at a distance inward from the periphery of the first surface portion 8.

[0038] The semiconductor device 1 includes a plurality of trench-type gate structures 25 formed in the first surface portion 8 (first main surface 3) in the active region 12. A gate potential is applied as a control potential to the plurality of gate structures 25. The plurality of gate structures 25 control inversion and non-inversion of a channel in the body region 20 in response to the gate potential.

[0039] The plurality of gate structures 25 are arranged on the first surface portion 8 at intervals inward from the periphery (first to fourth connection surface portions 10A to 10D) of the first surface portion 8. As shown in Fig. 5 , the plurality of gate structures 25 each extend in a band shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The plurality of gate structures 25 are arranged in stripes extending in the first direction X in a plan view.

[0040] 6 and 7 , the plurality of gate structures 25 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7. The body region 20 and the source region 21 are located on both sides of the plurality of gate structures 25. The plurality of gate structures 25 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between.

[0041] The side walls of the plurality of gate structures 25 are each formed by the m-plane ((1-100) plane) of the SiC single crystal. Of course, the side walls of the plurality of gate structures 25 may each be formed by the a-plane ((11-20) plane) of the SiC single crystal depending on the extension direction of the gate structures 25. The side walls of the plurality of gate structures 25 are formed approximately perpendicular to the first main surface 3. The bottom walls of the plurality of gate structures 25 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the plurality of gate structures 25 extend approximately flat along the horizontal direction. Of course, the bottom walls of the plurality of gate structures 25 may be curved in an arc shape toward the second main surface 4.

[0042] Each gate structure 25 includes a first trench 26, a first insulating film 27, and a first buried electrode 28. The first trench 26 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the gate structure 25. The first insulating film 27 covers the wall surfaces of the first trench 26. The first insulating film 27 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. It is particularly preferable that the first insulating film 27 include a silicon oxide film made of an oxide of the chip 2.

[0043] The first buried electrode 28 is buried in the first trench 26 with a first insulating film 27 sandwiched therebetween. The first buried electrode 28 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both. The first buried electrode 28 faces the channel with the first insulating film 27 sandwiched therebetween. The first buried electrode 28 faces the second semiconductor region 7, the body region 20, and the source region 21 with the first insulating film 27 sandwiched therebetween.

[0044] The semiconductor device 1 includes a plurality of trench-type first source structures (source structures) 30 formed in the first main surface 3 (first surface portion 8) in the active region 12. A source potential is applied to the plurality of first source structures 30.

[0045] The plurality of first source structures 30 are formed in the first surface portion 8 so as to be adjacent to the plurality of gate structures 25 in the second direction Y in the active region 12. Specifically, the plurality of first source structures 30 are respectively arranged in regions between the plurality of gate structures 25 and face the plurality of gate structures 25 in the second direction Y. The plurality of first source structures 30 are arranged alternately with the plurality of gate structures 25 in the second direction Y.

[0046] 5 , the multiple first source structures 30 each extend in a strip shape in the first direction X in a plan view. In this embodiment, the multiple first source structures 30 are drawn out from the active region 12 to either or both of the first end region 13 and the second end region 14 (in this embodiment, both). The multiple first source structures 30 face the gate structure 25 in the second direction Y in the active region 12, but do not face the gate structure 25 in the second direction Y in the first end region 13 (second end region 14).

[0047] 6 and 7 , the plurality of first source structures 30 penetrate the body region 20 and the source region 21 to reach the second semiconductor region 7. The body region 20 and the source region 21 are located on both sides of the plurality of first source structures 30, respectively.

[0048] The sidewalls of the multiple first source structures 30 are each formed by the m-plane of the SiC single crystal. Of course, the sidewalls of the multiple first source structures 30 may each be formed by the a-plane of the SiC single crystal depending on the extension direction of the first source structures 30. The sidewalls of the multiple first source structures 30 are formed approximately perpendicular to the first main surface 3. The bottom walls of the multiple first source structures 30 are formed by the c-plane (Si-plane) of the SiC single crystal. It is preferable that the bottom walls of the multiple first source structures 30 extend approximately flat in the horizontal direction. Of course, the bottom walls of the multiple first source structures 30 may be curved in an arc shape toward the second main surface 4.

[0049] The first source structure 30 preferably has a width greater than the width of the gate structure 25. The first source structure 30 preferably has a depth greater than the depth of the gate structure 25. The depth of the first source structure 30 is preferably approximately equal to the depth of the second surface portion 9.

[0050] 6 and 7 , one first source structure 30 includes a second trench 31, a second insulating film 32, and a second buried electrode 33. The second trench 31 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the first source structure 30. The sidewalls of the second trench 31 are connected to either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D. The bottom wall of the second trench 31 is connected to the second surface portion 9.

[0051] The second insulating film 32 covers the wall surface of the second trench 31. The second insulating film 32 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The second insulating film 32 preferably includes the same type of insulating material as the insulating material of the first insulating film 27.

[0052] The second buried electrode 33 is buried in the second trench 31 with the second insulating film 32 sandwiched therebetween. The second buried electrode 33 may contain either or both of p-type conductive polysilicon and n-type conductive polysilicon. The second buried electrode 33 preferably contains the same type of conductive material as the conductive material of the first buried electrode 28. The second buried electrode 33 faces the second semiconductor region 7, the body region 20, and the source region 21 with the second insulating film 32 sandwiched therebetween.

[0053] 5 to 7 , semiconductor device 1 includes a plurality of p-type first well regions 35 formed in regions along a plurality of gate structures 25 in a surface layer portion of first surface portion 8 (first main surface 3) of active region 12. The p-type impurity concentration of first well regions 35 is higher than the p-type impurity concentration of body region 20.

[0054] The plurality of first well regions 35 are formed along the sidewalls and bottom walls of the corresponding gate structures 25, and are each electrically connected to the body region 20 in a surface layer portion of the first surface portion 8. The plurality of first well regions 35 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 with a part of the second semiconductor region 7 in between. The plurality of first well regions 35 form pn junctions with the second semiconductor region 7.

[0055] 5 to 7 , the semiconductor device 1 includes a plurality of p-type second well regions 36 formed in regions along the plurality of first source structures 30 in a surface layer portion of the first surface portion 8 (first main surface 3) of the active region 12. The p-type impurity concentration of the second well regions 36 is higher than the p-type impurity concentration of the body region 20. The plurality of second well regions 36 are formed in a one-to-one correspondence with the plurality of first source structures 30. The plurality of second well regions 36 are formed in regions along the corresponding first source structures 30 at intervals from the plurality of gate structures 25.

[0056] The second well regions 36 are formed along the sidewalls and bottom walls of the corresponding first source structures 30, and are electrically connected to the body regions 20 in the surface layer portion of the first surface portion 8. The second well regions 36 extend along the wall surfaces of the corresponding first source structures 30 in the active region 12, the first end region 13, and the second end region 14, and are exposed from the third connection surface portion 10C and the fourth connection surface portion 10D.

[0057] The second well regions 36 are formed at intervals from the bottom of the second semiconductor region 7 toward the first surface portion 8, and face the first semiconductor region 6 across a portion of the second semiconductor region 7. The bottoms of the second well regions 36 are located closer to the bottom of the second semiconductor region 7 than the depth positions of the bottoms of the first well regions 35. That is, the depth DW2 (second depth, see FIGS. 6 and 7 ) of the second well region 36 is deeper than the depth DW1 (see FIGS. 6 and 7 ) of the first well region 35. The second well regions 36 form pn junctions with the second semiconductor region 7.

[0058] 5 and 6 , semiconductor device 1 includes a plurality of p-type contact regions 37 formed in regions along the plurality of second well regions 36 in a surface layer portion of first surface portion 8 (first main surface 3) of active region 12. Contact regions 37 have a p-type impurity concentration higher than the p-type impurity concentration of body region 20. The p-type impurity concentration of contact regions 37 is higher than the p-type impurity concentration of second well region 36 (first well region 35).

[0059] The plurality of contact regions 37 are formed in the plurality of second well regions 36. The plurality of contact regions 37 extend along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36. The plurality of contact regions 37 are formed in a one-to-many correspondence with the corresponding first source structures 30.

[0060] The plurality of contact regions 37 are formed at intervals in the first direction X along the corresponding first source structures 30. The plurality of contact regions 37 are drawn out to the surface layer portion of the body region 20 along the wall surfaces of the corresponding first source structures 30 in the corresponding second well regions 36, and are exposed from the first surface portion 8.

[0061] In this embodiment, the multiple contact regions 37 each extend in a strip shape in the first direction X in a plan view. The multiple contact regions 37 along one first source structure 30 face the multiple contact regions 37 along another first source structure 30 in the second direction Y.

[0062] The configuration of the first end region 13 will be described below. FIG. 8 is an enlarged view of the portion surrounded by the dashed line VIII in FIG. 4 . FIG. 9 is a cross-sectional view taken along line IX-IX in FIG. 8 . FIG. 10 is a cross-sectional view taken along line XX in FIG. 8 . FIG. 11 is a cross-sectional view taken along line XI-XI in FIG. 8 . FIG. 12 is a cross-sectional view taken along line XII-XII in FIG. 8 . Since the layout of the second end region 14 is similar to that of the first end region 13, a description of the layout of the second end region 14 will be omitted. The layout of the second end region 14 can be obtained by replacing "first end region 13" with "second end region 14" and "third connection surface portion 10C" with "fourth connection surface portion 10D" in the description of the first end region 13.

[0063] The semiconductor device 1 includes a plurality of trench-type second source structures 40 formed in the first surface 8 (first main surface 3) in the first end region 13. A source potential is applied to the plurality of second source structures 40. The plurality of second source structures 40 are respectively arranged on the periphery (third connection surface 10C) of the first surface 8 and in regions between the plurality of gate structures 25. The plurality of second source structures 40 are respectively arranged in regions between the plurality of first source structures 30 and face the plurality of first source structures 30 in the second direction Y. The plurality of second source structures 40 are arranged alternately with the plurality of first source structures 30 in the second direction Y.

[0064] Each second source structure 40 includes a third trench 41, a third insulating film 42, and a third buried electrode 43. The third trench 41 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the second source structure 40. The sidewalls of the third trench 41 are connected to the third connection surface portion 10C. The bottom wall of the third trench 41 is connected to the second surface portion 9. The third insulating film 42 covers the wall surfaces of the third trench 41. The third buried electrode 43 is buried in the third trench 41 with the third insulating film 42 sandwiched therebetween. The third buried electrode 43 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0065] 10 to 12 , semiconductor device 1 includes a plurality of p-type third well regions 44 formed in regions along the plurality of second source structures 40 in a surface layer portion of first surface portion 8 (first main surface 3) of first end region 13. Third well regions 44 have a p-type impurity concentration higher than the p-type impurity concentration of body region 20.

[0066] The plurality of third well regions 44 are formed in a one-to-one correspondence with the plurality of second source structures 40. The plurality of third well regions 44 are formed in regions along the corresponding second source structures 40, spaced apart from the plurality of first well regions 35 and the plurality of second well regions 36. The plurality of third well regions 44 are formed along the sidewalls and bottom walls of the corresponding second source structures 40, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8. The plurality of third well regions 44 form pn junctions with the second semiconductor region 7.

[0067] The configuration of the third end region 15 will be described below. Figure 13 is an enlarged view of the portion surrounded by the dashed line XIII in Figure 4. Figure 14 is a cross-sectional view taken along line XIV-XIV in Figure 13. The layout of the fourth end region 16 is similar to that of the third end region 15, so a description of the layout of the fourth end region 16 will be omitted. The layout of the fourth end region 16 can be obtained by replacing "third end region 15" with "fourth end region 16" and "first connecting surface portion 10A" with "second connecting surface portion 10B" in the description of the third end region 15.

[0068] The semiconductor device 1 includes a plurality of trench-type dummy gate structures 50 formed in the first surface portion 8 (first main surface 3) in the third end region 15. A source potential is applied to the plurality of dummy gate structures 50. The plurality of dummy gate structures 50 do not contribute to inversion or non-inversion of the channel.

[0069] The multiple dummy gate structures 50 are formed in a region on the first connection surface portion 10A side of the active region 12. The multiple dummy gate structures 50 each extend in a band shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The multiple dummy gate structures 50 are arranged in a stripe shape extending in the first direction X in a plan view. The multiple dummy gate structures 50 face the multiple gate structures 25 and the multiple first source structures 30 in the second direction Y.

[0070] Each dummy gate structure 50 includes a fourth trench 51, a fourth insulating film 52, and a fourth buried electrode 53. The fourth trench 51 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the dummy gate structure 50. The fourth insulating film 52 covers the wall surfaces of the fourth trench 51. The fourth buried electrode 53 is buried in the fourth trench 51 with the fourth insulating film 52 sandwiched therebetween. The fourth buried electrode 53 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0071] The semiconductor device 1 includes a plurality of trench-type third source structures 55 formed in the first surface portion 8 (first main surface 3) in the third end region 15. A source potential is applied to the plurality of third source structures 55.

[0072] The plurality of third source structures 55 are formed in a region on the first connection surface portion 10A side of the active region 12. The plurality of third source structures 55 are formed in the first surface portion 8 so as to be adjacent to the plurality of dummy gate structures 50 in the second direction Y in the third end region 15. Specifically, the plurality of third source structures 55 are respectively arranged in regions between the plurality of dummy gate structures 50 and face the plurality of dummy gate structures 50 in the second direction Y. The plurality of third source structures 55 are arranged alternately with the plurality of dummy gate structures 50 in the second direction Y. The plurality of third source structures 55 each extend in a strip shape in the first direction X in a plan view. The plurality of third source structures 55 face the plurality of gate structures 25 and the plurality of first source structures 30 in the second direction Y.

[0073] Each third source structure 55 includes a fifth trench 56, a fifth insulating film 57, and a fifth buried electrode 58. The fifth trench 56 is formed in the first surface 8 and defines the wall surfaces (sidewalls and bottom wall) of the third source structure 55. The sidewalls of the fifth trench 56 are connected to either or both (in this embodiment, both) of the third connection surface 10C and the fourth connection surface 10D. The bottom wall of the fifth trench 56 is connected to the second surface 9.

[0074] The fifth insulating film 57 covers the wall surface of the fifth trench 56. The fifth insulating film 57 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The fifth buried electrode 58 is buried in the fifth trench 56 with the fifth insulating film 57 sandwiched therebetween. The fifth buried electrode 58 may include either p-type conductive polysilicon or n-type conductive polysilicon, or both.

[0075] 14 , the semiconductor device 1 includes a plurality of p-type fourth well regions 59 formed in regions along the plurality of dummy gate structures 50 in the surface layer portion of the first surface portion 8 (first main surface 3) of the third end region 15. The fourth well regions 59 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0076] The plurality of fourth well regions 59 are formed in a one-to-one correspondence with the plurality of dummy gate structures 50. The plurality of fourth well regions 59 are formed in regions along the corresponding dummy gate structures 50 at intervals from the plurality of third source structures 55. The plurality of fourth well regions 59 are formed along the sidewalls and bottom walls of the corresponding dummy gate structures 50, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8. The plurality of fourth well regions 59 form pn junctions with the second semiconductor region 7.

[0077] 14 , the semiconductor device 1 includes a plurality of p-type fifth well regions 60 formed in regions along the plurality of third source structures 55 in a surface layer portion of the first surface portion 8 (first main surface 3) of the third end region 15. The fifth well regions 60 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0078] The plurality of fifth well regions 60 are formed in a one-to-one correspondence with the plurality of third source structures 55. The plurality of fifth well regions 60 are formed in regions along the corresponding third source structures 55 at intervals from the plurality of dummy gate structures 50. The plurality of fifth well regions 60 are formed along the sidewalls and bottom walls of the corresponding third source structures 55, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8. The plurality of fifth well regions 60 form pn junctions with the second semiconductor region 7.

[0079] The configuration of the fifth end region 17 will be described below. Figure 15 is an enlarged view of the portion surrounded by the dashed dotted line XV in Figure 4. Figure 16 is a cross-sectional view taken along line XVI-XVI in Figure 15. The layout of the sixth end region 18 is similar to that of the fifth end region 17, so a description of the layout of the sixth end region 18 will be omitted. The layout of the sixth end region 18 can be obtained by replacing "fifth end region 17" with "sixth end region 18," "third end region 15" with "fourth end region 16," and "first connection surface portion 10A" with "second connection surface portion 10B" in the description of the fifth end region 17.

[0080] The semiconductor device 1 includes a plurality of trench-type fourth source structures 65 formed in the first surface portion 8 (first main surface 3) in the fifth end region 17. A source potential is applied to the plurality of fourth source structures 65.

[0081] The plurality of fourth source structures 65 are formed in a region on the first connection surface portion 10A side with respect to the active region 12 (third end region 15). The plurality of fourth source structures 65 each extend in a band shape in the first direction X in a plan view, and are arranged at intervals in the second direction Y. The plurality of fourth source structures 65 are arranged in a stripe shape extending in the first direction X in a plan view. The plurality of fourth source structures 65 are adjacent to each other without any intervening trench structure.

[0082] Each fourth source structure 65 includes a sixth trench 66, a sixth insulating film 67, and a sixth buried electrode 68. The sixth trench 66 is formed in the first surface portion 8 and defines the wall surfaces (sidewalls and bottom wall) of the fourth source structure 65. The sidewalls of the sixth trench 66 are connected to either or both (in this embodiment, both) of the third connection surface portion 10C and the fourth connection surface portion 10D. The bottom wall of the sixth trench 66 is connected to the second surface portion 9. The sixth insulating film 67 covers the wall surfaces of the sixth trench 66. The sixth buried electrode 68 is buried in the sixth trench 66 with the sixth insulating film 67 sandwiched therebetween. The sixth buried electrode 68 may include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0083] 16 , the semiconductor device 1 includes a plurality of p-type sixth well regions 69 formed in regions along the plurality of fourth source structures 65 in a surface layer portion of the first surface portion 8 (first main surface 3) of the fifth end region 17. The sixth well regions 69 have a p-type impurity concentration higher than the p-type impurity concentration of the body region 20.

[0084] The plurality of sixth well regions 69 are formed in one-to-one correspondence with the plurality of fourth source structures 65. The plurality of sixth well regions 69 are formed in regions along the corresponding fourth source structures 65 with spaces between them. The plurality of sixth well regions 69 are formed along the sidewalls and bottom walls of the corresponding fourth source structures 65, and are each electrically connected to the body region 20 in the surface layer portion of the first surface portion 8. The plurality of sixth well regions 69 form pn junctions with the second semiconductor region 7.

[0085] The configuration of the outer peripheral region 19 side will be described below. Fig. 17 is a cross-sectional view showing the cross-sectional structure along line XVII-XVII shown in Fig. 1 together with the outer peripheral structure according to the first embodiment. Fig. 18 is a cross-sectional view along line XVIII-XVIII shown in Fig. 1. Fig. 19 is an enlarged view of the portion surrounded by the dashed dotted line XIX in Fig. 17.

[0086] The semiconductor device 1 includes a p-type outer well region 70 formed in the surface layer of the second surface portion 9 in the peripheral region 19. A source potential is applied to the outer well region 70.

[0087] The p-type impurity concentration of the outer well region 70 is higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the outer well region 70 is lower than the p-type impurity concentration of the contact region 37. The p-type impurity concentration of the outer well region 70 is higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the outer well region 70 may be approximately equal to the p-type impurity concentration of the first well region 35 (the p-type impurity concentration of the second well region 36). The p-type impurity concentration of the outer well region 70 may be lower than the p-type impurity concentration of the body region 20.

[0088] The outer well region 70 is formed at a distance from the periphery of the second surface portion 9 toward the first surface portion 8 in a plan view. The outer well region 70 extends in a band shape along the first surface portion 8 in a plan view. In this embodiment, the outer well region 70 is formed in a polygonal ring shape (more specifically, a quadrangular ring shape) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface portion 8. The outer well region 70 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0089] The outer well region 70 extends from a surface layer portion of the second surface portion 9 toward surface layer portions of the first to fourth connection surface portions 10A to 10D, and has a portion extending in the vertical direction Z along the first to fourth connection surface portions 10A to 10D. The outer well region 70 is electrically connected to the body region 20 in a surface layer portion of the first surface portion 8. The outer well region 70 is connected to the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, and the sixth well region 69 at the third connection surface portion 10C (fourth connection surface portion 10D).

[0090] The outer well region 70 is formed at a distance from the bottom of the second semiconductor region 7 toward the first main surface 3. The outer well region 70 faces the first semiconductor region 6 in the depth direction of the chip 2, with a part of the second semiconductor region 7 sandwiched between them. The bottom of the outer well region 70 is located on the bottom side of the second semiconductor region 7 relative to the depth position of the bottom wall of the gate structure 25. The bottom of the outer well region 70 is formed at a depth position substantially equal to the bottoms of the first well region 35 and the second well region 36.

[0091] The outer well region 70 forms a pn junction with the second semiconductor region 7. The outer well region 70 expands a depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer in the outer well region 70 expands in the horizontal and thickness directions and integrates with the depletion layer expanding from the active region 12. The outer well region 70 expands the depletion layer expanding from the active region 12 toward the periphery of the second surface 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first surface 8 (first to fourth connecting surface portions 10A to 10D).

[0092] 17 to 19 , the semiconductor device 1 includes a p-type outer contact region 71 formed in the surface layer portion of the second surface portion 9 in the peripheral region 19. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the outer contact region 71 is higher than the p-type impurity concentration of the outer well region 70. The p-type impurity concentration of the outer contact region 71 is approximately equal to the p-type impurity concentration of the contact region 37.

[0093] The outer contact region 71 is formed in a surface layer portion of the second surface portion 9 at a distance from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the outer contact region 71 is formed in a surface layer portion of the outer well region 70. The outer contact region 71 is formed at a distance from the bottom of the outer well region 70 toward the second surface portion 9, and faces the second semiconductor region 7 in the depth direction of the chip 2, with a part of the outer well region 70 in between.

[0094] The outer contact region 71 extends in a band shape along the first surface 8 in a plan view. In this embodiment, the outer contact region 71 is formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the first surface 8. The outer contact region 71 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quarter arc shape).

[0095] The outer contact region 71 is formed in a surface layer portion of the outer well region 70. The bottom of the outer contact region 71 is located closer to the second surface portion 9 (first main surface 3) than the bottom of the outer well region 70.

[0096] 17 to 19 , semiconductor device 1 includes p-type termination region 73 formed in the surface layer portion of second surface portion 9 in peripheral region 19. Termination region 73 may also be referred to as a "termination well region," a "JTE region (Junction Termination Extension region)," or the like. A source potential is applied to termination region 73.

[0097] Termination region 73 is formed in the surface layer portion of second surface portion 9 at a distance from the periphery of first surface portion 8 (first to fourth connecting surface portions 10A to 10D) and the periphery of second surface portion 9 (first to fourth side surfaces 5A to 5D) in plan view. Termination region 73 extends in a band shape along the periphery of first main surface 3 in plan view.

[0098] In this embodiment, the termination region 73 is formed in a polygonal ring shape (a square ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surrounds the inner part (active region 12) of the first main surface 3 and the outer well region 70. The termination region 73 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0099] Of course, termination region 73 may have a plurality of portions arranged at intervals along the inner portion (active region 12) of first main surface 3 and outer well region 70 so as to surround the inner portion (active region 12) of first main surface 3 and outer well region 70. In this case, the plurality of portions may each extend in a strip shape along the inner portion (active region 12) of first main surface 3 and outer well region 70.

[0100] 17 to 19 , termination region 73 has an inner edge 73b on the inner side of first main surface 3 and an outer edge 73a on the peripheral side of first main surface 3. Inner edge 73b of termination region 73 is connected to the outer edge of outer well region 70. Inner edge 73b of termination region 73 is connected to the outer edge of outer contact region 71. Termination region 73 is electrically connected to outer well region 70. Termination region 73 is electrically connected to outer contact region 71. Although not shown, inner edge 73b of termination region 73 may be formed at a distance from the outer edge of outer contact region 71 toward the peripheral edge of first main surface 3.

[0101] 19 , the width W1 of termination region 73 (the distance between outer edge 73 a and inner edge 73 b in the first direction X or the second direction Y; third width) may be greater than 0 μm and less than 30 μm. Width W1 of termination region 73 may have a value that falls within at least one of the following ranges: greater than 0 μm and less than 5 μm, 5 μm to 10 μm, 10 μm to 15 μm, 15 μm to 20 μm, 20 μm to 25 μm, and 25 μm to 30 μm. In the example of FIG. 19 , width W1 of termination region 73 is preferably greater than 10 μm and less than 20 μm.

[0102] The width ratio of the width W1 of the termination region 73 to the width of the outer well region 70 (the distance in the first direction X or the second direction Y between the outer edge and the inner edge of the outer well region 70) may be 0.5 or more and 5 or less. The width ratio may have a value belonging to any one of the ranges of 0.5 to 0.75, 0.75 to 1, 1 to 1.25, 1.25 to 1.5, 1.5 to 1.75, 1.75 to 2, 2 to 2.25, 2.25 to 2.5, 2.5 to 2.75, 2.75 to 3, 3 to 3.25, 3.25 to 3.5, 3.5 to 3.75, 3.75 to 4, 4 to 4.25, 4.25 to 4.5, 4.5 to 4.75, and 4.75 to 5. The width W1 of the termination region 73 is preferably wider than the width of the outer well region 70. Of course, the width W1 of the termination region 73 may be equal to or smaller than the width of the outer well region 70.

[0103] The termination region 73 is formed on the second surface portion 9 (first main surface 3). The termination region 73 has a bottom portion located on the bottom side of the second semiconductor region 7. The bottom portion of the termination region 73 forms a pn junction with the second semiconductor region 7.

[0104] 17 to 19 , the bottom of termination region 73 has a flat bottom surface that continues from the first main surface 3 side toward the peripheral edge of second surface 9. Depth D1 of termination region 73 is approximately constant. Of course, depth D1 (first depth) of termination region 73 may gradually increase toward the peripheral edge of second surface 9. Depth D1 of termination region 73 may gradually decrease toward the peripheral edge of second surface 9.

[0105] In this embodiment, the bottom of the termination region 73 is located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the body region 20. The bottom of the termination region 73 may also be located closer to the first main surface 3 than the depth position of the bottom of the body region 20.

[0106] The depth position of the bottom of the termination region 73 may be the same as the depth position of the bottom of the second well region 36. The depth D1 (first depth) of the termination region 73 may be the same as the depth DW2 (second depth, see FIGS. 6 and 7 ) of the second well region 36 (D1 = DW2). In this case, the depth position of the bottom of the termination region 73 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the first well region 35. The depth D1 (first depth) of the termination region 73 may be deeper than the depth DW1 (see FIGS. 6 and 7 ) of the first well region 35 (D1 > DW1). Of course, the depth D1 (first depth) of the termination region 73 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the second well region 36 (D1 > DW2). The depth D1 (first depth) of the termination region 73 may be located closer to the first main surface 3 than the depth position of the bottom of the second well region 36 (D1<DW2).

[0107] The bottom of the termination region 73 is located at a depth position substantially equal to that of the bottom of the outer well region 70. The bottom of the termination region 73 is flush with the bottom of the outer well region 70. Of course, the bottom of the termination region 73 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the outer well region 70, or may be located closer to the first main surface 3 than the depth position of the bottom of the outer well region 70.

[0108] The depth (first depth) D1 of the termination region 73 may be greater than 0 μm and equal to or less than 4 μm. The depth D1 of the termination region 73 may have a value belonging to at least one of the ranges of greater than 0 μm and less than or equal to 0.25 μm, 0.25 μm or more and less than or equal to 0.5 μm, 0.5 μm or more and less than or equal to 0.75 μm, 0.75 μm or more and less than or equal to 1 μm, 1 μm or more and less than or equal to 1.25 μm, 1.25 μm or more and less than or equal to 1.5 μm, 1.5 μm or more and less than or equal to 1.75 μm, 1.75 μm or more and less than or equal to 2 μm, 2 μm or more and less than or equal to 2.25 μm, 2.25 μm or more and less than or equal to 2.5 μm, 2.5 μm or more and less than or equal to 2.75 μm, 2.75 μm or more and less than or equal to 3 μm, 3 μm or more and less than or equal to 3.25 μm, 3.25 μm or more and less than or equal to 3.5 μm, 3.5 μm or more and less than or equal to 3.75 μm, and 3.75 μm or more and less than or equal to 4 μm. The depth D1 of the termination region 73 is preferably 0.5 μm or more and 3 μm or less. In this embodiment, the termination region 73 is formed on the first main surface 3, and therefore the depth D1 of the termination region 73 corresponds to the thickness of the termination region 73.

[0109] The p-type impurity concentration of the termination region 73 is 1.×10 １８ cm －３ Above 5.0 x 10 ２０ cm －３ or less. The p-type impurity concentration of the termination region 73 is higher than the n-type impurity concentration of the second semiconductor region 7. The p-type impurity concentration of the termination region 73 is lower than the p-type impurity concentration of the contact region 37. The p-type impurity concentration of the termination region 73 is lower than the p-type impurity concentration of the outer contact region 71. The p-type impurity concentration of the termination region 73 may be higher than the p-type impurity concentration of the body region 20, or may be lower than the p-type impurity concentration of the body region 20. The p-type impurity concentration of the termination region 73 may be the same as the p-type impurity concentration of the second well region 36 (first well region 35), or may be higher than the p-type impurity concentration of the second well region 36 (first well region 35), or may be lower than the p-type impurity concentration of the second well region 36 (first well region 35). The p-type impurity concentration of the termination region 73 may be the same as the p-type impurity concentration of the outer well region 70, may be higher than the p-type impurity concentration of the outer well region 70, or may be lower than the p-type impurity concentration of the outer well region 70.

[0110] The termination region 73 forms a pn junction with the second semiconductor region 7. The termination region 73 expands a depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layer in the termination region 73 expands in the horizontal and thickness directions and integrates with the depletion layer in the outer well region 70 and the depletion layer in the termination region 73. The termination region 73 expands the depletion layer expanding from the active region 12 toward the periphery of the second surface 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first surface 8 (first to fourth connecting surface portions 10A to 10D).

[0111] As described above, the termination region 73 is electrically connected to the body region 20 and the outer contact region 71 via the outer well region 70. The outer contact region 71 is electrically connected to the source electrode 85 and the source wiring 90, which will be described later. The termination region 73 is electrically connected to the source electrode 85 and the source wiring 90.

[0112] 17 to 19, semiconductor device 1 includes at least one p-type field region 72 formed in a surface layer portion of second surface portion 9 in peripheral region 19. Field region 72 may be formed in an electrically floating state or may be fixed to the source potential. The multiple field regions 72 reduce the electric field within chip 2 in peripheral region 19.

[0113] The number of field regions 72 is arbitrary. The number of field regions 72 may be 1 or more and 20 or less. The number of field regions 72 may be a value belonging to at least one of the ranges of 1 or more and 5 or less, 5 or more and 10 or less, 10 or more and 15 or less, and 15 or more and 20 or less. The number of field regions 72 is typically 1 or more and 8 or less. In this embodiment, the semiconductor device 1 includes a plurality of (for example, four) field regions 72.

[0114] The plurality of field regions 72 are formed in the surface layer portion of the second surface portion 9 at intervals from the periphery of the first surface portion 8 (first to fourth connection surface portions 10A to 10D) and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D) in a plan view. Specifically, the plurality of field regions 72 are formed in the region between the periphery of the second surface portion 9 and the termination region 73 at intervals from the termination region 73 toward the periphery of the second surface portion 9.

[0115] The multiple field regions 72 are formed at intervals from the bottom of the second semiconductor region 7 toward the second surface 9. The multiple field regions 72 are formed on the second surface 9. The multiple field regions 72 face the first semiconductor region 6 in the depth direction of the chip 2, sandwiching a part of the second semiconductor region 7 between them. The multiple field regions 72 each extend in a strip shape along the first surface 8 in a plan view.

[0116] In this embodiment, the plurality of field regions 72 are each formed in a polygonal ring shape (a quadrangular ring shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and surround the first surface portion 8. The plurality of field regions 72 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0117] The plurality of field regions 72 each form a pn junction with the second semiconductor region 7. The plurality of field regions 72 expand a depletion layer toward the second semiconductor region 7 when a reverse bias voltage is applied. The depletion layers in the plurality of field regions 72 expand in the horizontal and thickness directions and integrate with the depletion layers in the outer well region 70 and the termination region 73. The plurality of field regions 72 expand the depletion layer expanding from the active region 12 toward the periphery of the second surface 9, thereby mitigating the electric field intensity (electric field concentration) at the periphery of the first surface 8 (first to fourth connecting surface portions 10A to 10D).

[0118] The p-type impurity concentrations of the plurality of field regions 72 may be approximately equal to the p-type impurity concentration of the termination region 73. The p-type impurity concentrations of the plurality of field regions 72 may be higher than the p-type impurity concentration of the termination region 73, or may be lower than the p-type impurity concentration of the termination region 73.

[0119] The p-type impurity concentration of the multiple field regions 72 may be approximately equal to the p-type impurity concentration of the outer well region 70. The p-type impurity concentration of the multiple field regions 72 may be higher than the p-type impurity concentration of the outer well region 70, or may be lower than the p-type impurity concentration of the outer well region 70.

[0120] The p-type impurity concentrations of the plurality of field regions 72 may be substantially constant or may be non-uniform. The p-type impurity concentrations of the plurality of field regions 72 may gradually increase toward the periphery of the second surface 9. The p-type impurity concentrations of the plurality of field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0121] The widths of the multiple field regions 72 may be approximately constant or may be non-uniform. The widths of the multiple field regions 72 may gradually increase toward the peripheral edge of the second surface 9. The widths of the multiple field regions 72 may gradually decrease toward the peripheral edge of the second surface 9. The spacing between the multiple field regions 72 may be approximately constant or may be non-uniform. The spacing between the multiple field regions 72 may gradually increase toward the peripheral edge of the second surface 9. The spacing between the multiple field regions 72 may gradually decrease toward the peripheral edge of the second surface 9.

[0122] As shown in FIG. 19 , the total width W2 of the field regions 72 (the width between the inner edge of the innermost field region 72 and the outer edge of the outermost field region 72; second width) may be 5 μm or more and 30 μm or less. The width W2 may have a value that falls within at least one of the following ranges: 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or more and 25 μm or more and 30 μm or less. In the example of FIG. 19 , the width W2 is 15 μm. The total width W2 of the field regions 72 may be narrower than the width W1 of the termination region 73. Of course, the width W2 may be the same as the width W1, or may be wider than the width W1.

[0123] The bottoms of the plurality of field regions 72 are located at a depth substantially equal to that of the bottom of the termination region 73. The bottoms of the plurality of field regions 72 are flush with the bottom of the termination region 73. Of course, the bottoms of the plurality of field regions 72 may be located closer to the bottom of the second semiconductor region 7 than the depth position of the bottom of the termination region 73, or may be located closer to the first main surface 3 than the depth position of the bottom of the termination region 73.

[0124] The depth of the plurality of field regions 72 may be substantially uniform or may be non-uniform. The depth of the plurality of field regions 72 may gradually increase toward the periphery of the second surface 9. The depth of the plurality of field regions 72 may gradually decrease toward the periphery of the second surface 9.

[0125] 11 , 12 , and 16 to 18 , the semiconductor device 1 includes an insulating first inorganic film (first insulating film) 75 that selectively covers the first main surface 3. The first inorganic film 75 may also be referred to as a “first inorganic insulating film” or the like. The first inorganic film 75 selectively covers the first surface 8, the second surface 9, and the first to fourth connecting surface portions 10A to 10D. In this embodiment, the first inorganic film 75 is continuous with the periphery of the second surface 9 (continuous with the peripheries of the first to fourth side surfaces 5A to 5D). The first inorganic film 75 is formed flush with the second surface 9. The first inorganic film 75 has a layered structure including a lower inorganic film 76 and an upper inorganic film 77.

[0126] The lower inorganic film 76 selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connecting surface portions 10A to 10D. The lower inorganic film 76 may also be referred to as a "base insulating film," a "main surface insulating film," or the like. The lower inorganic film 76 is connected to the first insulating film 27, the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 on the first surface portion 8, and exposes the first buried electrode 28, the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0127] The lower inorganic film 76 covers the outer well region 70, the outer contact region 71, the termination region 73, and the plurality of field regions 72 in the second surface portion 9. The lower inorganic film 76 is connected to the second insulating film 32, the third insulating film 42, the fourth insulating film 52, the fifth insulating film 57, and the sixth insulating film 67 in the first to fourth connection surface portions 10A to 10D, and exposes the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68.

[0128] The lower inorganic film 76 covers the body region 20, the second well region 36, the third well region 44, the fourth well region 59, the fifth well region 60, the sixth well region 69, the outer well region 70 and the termination region 73 in the first to fourth connection surface portions 10A to 10D.

[0129] The lower inorganic film 76 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The lower inorganic film 76 preferably includes the same type of insulating material as the insulating material of the first insulating film 27, etc. In this embodiment, the lower inorganic film 76 has a single-layer structure made of a silicon oxide film. It is particularly preferable that the lower inorganic film 76 includes a silicon oxide film made of an oxide of the chip 2.

[0130] The upper inorganic film 77 is stacked on the lower inorganic film 76 and selectively covers the first surface portion 8, the second surface portion 9, and the first to fourth connection surface portions 10A to 10D with the lower inorganic film 76 sandwiched therebetween. The upper inorganic film 77 may also be referred to as an "upper insulating film," an "interlayer insulating film," an "intermediate insulating film," etc. The upper inorganic film 77 covers the plurality of gate structures 25, the plurality of first source structures 30, the plurality of second source structures 40, the plurality of dummy gate structures 50, the plurality of third source structures 55, and the plurality of fourth source structures 65 on the first surface portion 8.

[0131] The upper inorganic film 77 covers the outer well region 70, the outer contact region 71, the termination region 73, and the plurality of field regions 72, sandwiching the lower inorganic film 76 in the second surface portion 9. The upper inorganic film 77 covers the plurality of first source structures 30, the plurality of second source structures 40, the plurality of dummy gate structures 50, the plurality of third source structures 55, and the plurality of fourth source structures 65 in the first to fourth connection surface portions 10A to 10D.

[0132] The upper inorganic film 77 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film. The upper inorganic film 77 preferably includes a silicon oxide film. The upper inorganic film 77 preferably includes an insulating material having properties different from those of the insulating material of the lower inorganic film 76. For example, the upper inorganic film 77 preferably has a single-layer structure or a multilayer structure including at least one of a phosphorus-containing silicon oxide film (PSG film), a phosphorus- and boron-containing silicon oxide film (BPSG film), an undoped silicon oxide film (NSG film), and a tetraethyl orthosilicate film (TEOS film). For example, the upper inorganic film 77 may have a multilayer structure including an NSG film stacked on the lower inorganic film 76 and a PSG film (or BPSG film) stacked on the NSG film.

[0133] 8 and 9, the semiconductor device 1 includes a plurality of gate connection electrodes 78 that selectively cover a plurality of gate structures 25 in the active region 12. The plurality of gate connection electrodes 78 include either or both of p-type conductive polysilicon and n-type conductive polysilicon.

[0134] 8, 10, etc., the semiconductor device 1 includes a sidewall wiring 79 that covers at least one of the first to fourth connecting surface portions 10A to 10D on the second surface portion 9. The sidewall wiring 79 includes either p-type conductive polysilicon or n-type conductive polysilicon, or both. In this embodiment, the sidewall wiring 79 is formed integrally with the second buried electrode 33, the third buried electrode 43, the fourth buried electrode 53, the fifth buried electrode 58, and the sixth buried electrode 68. In this embodiment, the sidewall wiring 79 is formed in a polygonal ring shape (specifically, a square ring shape) that extends along the first to fourth connecting surface portions 10A to 10D in a plan view and surrounds the first surface portion 8.

[0135] The sidewall wiring 79 is electrically connected to the plurality of first source structures 30, the plurality of second source structures 40, the plurality of dummy gate structures 50, the plurality of third source structures 55, and the plurality of fourth source structures 65 on the first to fourth connection surface portions 10A to 10D. The sidewall wiring 79 has an overlapping portion 79a that extends from at least one of the first to fourth connection surface portions 10A to 10D onto the edge of the first surface portion 8. In this embodiment, the overlapping portion 79a extends from all of the first to fourth connection surface portions 10A to 10D onto the first surface portion 8 and is formed in a ring shape (specifically, a rectangular ring shape) that surrounds the inner portion of the first surface portion 8.

[0136] 6 and 7 , the semiconductor device 1 has a plurality of source openings 80 formed in the first inorganic film 75 in the active region 12. The plurality of source openings 80 penetrate the first inorganic film 75 and selectively expose the plurality of first source structures 30. Specifically, the plurality of source openings 80 are formed in a one-to-one correspondence with the plurality of source structures, respectively, and extend in a strip shape along the corresponding first source structure 30.

[0137] 2, 3, 17, and 18, the semiconductor device 1 has at least one outer opening 81 (one in this embodiment) formed in the first inorganic film 75 in the peripheral region 19. The outer opening 81 penetrates the first inorganic film 75 and exposes both the outer contact region 71 and the sidewall wiring 79.

[0138] Specifically, the outer opening 81 penetrates the upper inorganic film 77 to expose the sidewall wiring 79. The outer opening 81 also penetrates both the lower inorganic film 76 and the upper inorganic film 77 to expose the outer contact region 71. The outer opening 81 extends in a band shape along the outer contact region 71 and the sidewall wiring 79 in a plan view. In this embodiment, the outer opening 81 is formed in a polygonal ring shape (specifically, a quadrangular ring shape) surrounding the first surface portion 8 in a plan view.

[0139] The semiconductor device 1 has a plurality of gate openings 82 (see FIG. 9 ) formed in the first inorganic film 75 in the active region 12. The plurality of gate openings 82 penetrate the first inorganic film 75 and selectively expose the plurality of gate structures 25. Specifically, the plurality of gate openings 82 are formed in portions of the first inorganic film 75 that cover the plurality of gate connection electrodes 78, respectively, and expose the plurality of gate connection electrodes 78. The plurality of gate openings 82 are formed in a one-to-one correspondence with the plurality of gate connection electrodes 78, and each extends in a strip shape in the first direction X in a plan view.

[0140] 2, 3, and 17 to 19, the semiconductor device 1 has at least one anchor opening 83 (one in this embodiment) formed in the first inorganic film 75 in the peripheral region 19. The anchor opening 83 is selectively formed in a portion of the first inorganic film 75 that covers the peripheral edge of the second surface portion 9.

[0141] The anchor openings 83 are formed in the region between the first surface portion 8 and the second surface portion 9. Specifically, the anchor openings 83 are formed in the region between the periphery of the second surface portion 9 and the termination region 73. Even more specifically, the anchor openings 83 are formed in the region between the periphery of the second surface portion 9 and the plurality of field regions 72 (the outermost field region 72).

[0142] The anchor opening 83 penetrates the first inorganic film 75 and exposes the second surface portion 9. Specifically, the anchor opening 83 exposes the second semiconductor region 7. The anchor opening 83 may be formed at the same height as the second surface portion 9. Of course, the anchor opening 83 may be dug down toward the bottom of the second semiconductor region 7 with respect to the height position of the second surface portion 9. The bottom wall of the anchor opening 83 may be located on the bottom side of the second semiconductor region 7 with respect to the height position of the second surface portion 9.

[0143] The anchor opening 83 extends in a band shape along the first surface portion 8 in a plan view. In this embodiment, the anchor opening 83 is formed in a polygonal ring shape (specifically, a square ring shape) surrounding the first surface portion 8 in a plan view. Of course, the semiconductor device 1 may have a plurality of anchor openings 83. In this case, the plurality of anchor openings 83 may be formed at intervals along the first surface portion 8 so as to surround the first surface portion 8.

[0144] The plurality of anchor openings 83 may be formed in a matrix or staggered pattern at intervals in the first direction X and the second direction Y so as to surround the first surface portion 8. Of course, the plurality of anchor openings 83 may be formed in a stripe or lattice pattern so as to surround the first surface portion 8. Furthermore, the plurality of annular anchor openings 83 may be formed in a concentric pattern so as to surround the first surface portion 8.

[0145] The configuration on the first main surface 3 will be described below. Fig. 20 is a plan view showing an example layout of main electrodes (source electrode 85, source wiring 90, gate electrode 95, and gate wiring 100) arranged on the first main surface 3. The configuration of the main electrodes (source electrode 85, source wiring 90, gate electrode 95, and gate wiring 100) will be described below. In Fig. 20, the main electrodes are represented by hatching.

[0146] 6 , 7 , 17 , 20 , etc., semiconductor device 1 includes a source electrode (peripheral source electrode portion) 85 disposed on first inorganic film 75. Source electrode 85 is a terminal electrode to which a source potential is applied from the outside. Source electrode 85 may also be referred to as an "electrode," "first electrode," "first pad electrode," "first main surface electrode," "first terminal electrode," "source pad electrode," etc.

[0147] 20 , the source electrode 85 is disposed on a portion of the first inorganic film 75 that covers the first surface portion 8. The source electrode 85 covers at least the entire active region 12 in a plan view. The source electrode 85 covers the active region 12 at a distance from the first end region 13 and the second end region 14. The source electrode 85 covers the first surface portion 8 at a distance from both ends of the multiple gate structures 25. Specifically, the source electrode 85 is formed at a distance inward from the multiple gate connection electrodes 78.

[0148] 17 and 18 , the source electrode 85 may cover either or both of the third end region 15 and the fifth end region 17. The source electrode 85 may face the plurality of dummy gate structures 50 and the plurality of third source structures 55 on the third end region 15 side, with the first inorganic film 75 interposed therebetween. The source electrode 85 may also face the plurality of fourth source structures 65 on the fifth end region 17 side. Of course, the source electrode 85 may cover the active region 12 at a distance from either or both of the third end region 15 and the fifth end region 17.

[0149] 6 and 7 , the thickness of the source electrode 85 may be greater than the depth of the gate structure 25. The thickness of the source electrode 85 may be greater than the depth of the first source structure 30. The thickness of the source electrode 85 may be greater than the depth of the second surface portion 9. The thickness of the source electrode 85 may be greater than the thickness (total thickness) of the first inorganic film 75.

[0150] 20 , in this embodiment, the source electrode 85 has a first pad portion 85 a, a second pad portion 85 b, and a third pad portion 85 c. The first pad portion 85 a has a relatively large planar area and forms the main body of the source electrode 85. In this embodiment, the first pad portion 85 a is formed in a polygonal shape (a quadrangle in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view, and is located closer to the second side surface 5B (second connection surface portion 10B) than the first side surface 5A (first connection surface portion 10A).

[0151] The second pad portion 85b has a planar area smaller than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from one end of the first pad portion 85a in the first direction X (the end on the third connecting surface portion 10C side) toward the first connecting surface portion 10A. The third pad portion 85c has a planar area smaller than that of the first pad portion 85a, and is drawn out in a strip (rectangular) shape from the other end of the first pad portion 85a in the first direction X (the end on the fourth connecting surface portion 10D side) toward the first connecting surface portion 10A, and faces the second pad portion 85b in the first direction X.

[0152] The plane area of ​​the third pad portion 85c may be approximately equal to the plane area of ​​the second pad portion 85b, but may also be larger than the plane area of ​​the second pad portion 85b or smaller than the plane area of ​​the second pad portion 85b.

[0153] The ratio (area ratio) of the plane area of ​​the source electrode 85 to the plane area of ​​the first surface portion 8 is preferably 0.5 or more and less than 1.0. This area ratio may have a value belonging to any one of the ranges of 0.5 or more and 0.6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, and 0.9 or more and less than 1.0.

[0154] The source electrode 85 extends from above the first inorganic film 75 into the plurality of source openings 80 and is electrically connected to the plurality of first source structures 30 , the source regions 21 and the plurality of contact regions 37 within the plurality of source openings 80 .

[0155] 17 and 18 , the source electrode 85 has a first electrode surface 86 and a first electrode sidewall 87. The first electrode surface 86 extends along the first inorganic film 75. The first electrode surface 86 may have a plurality of recesses recessed toward the first surface portion 8 in a portion covering the plurality of source openings 80. The first electrode sidewall 87 is located on the first inorganic film 75. The first electrode sidewall 87 slopes obliquely downward from the first electrode surface 86 toward the first inorganic film 75. In this embodiment, the first electrode sidewall 87 slopes obliquely downward in a curved manner from the first electrode surface 86 toward the first inorganic film 75.

[0156] 6 and 7 , in this embodiment, the source electrode 85 has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89 laminated in this order from the side of the first inorganic film 75. The first lower electrode film 88 is laminated in a film form on the first inorganic film 75 as a base film (barrier film) of the source electrode 85, and forms a lower layer portion of a first electrode side wall 87 of the source electrode 85.

[0157] In this embodiment, the first lower electrode film 88 has a layered structure including a Ti film and a TiN film stacked in this order from the first inorganic film 75 side. The first lower electrode film 88 may have a single-layer structure made of a Ti film or a TiN film. The first lower electrode film 88 has a thickness (total thickness) that is less than the thickness (total thickness) of the first inorganic film 75.

[0158] The first lower electrode film 88 collectively covers the region of the first inorganic film 75 where the multiple source openings 80 are formed, and extends into the multiple source openings 80 from above the first inorganic film 75. The first lower electrode film 88 has a portion that covers the insulating main surface of the first inorganic film 75 in a film-like manner, a portion that covers the wall surfaces of the multiple source openings 80 in a film-like manner, and a portion that covers the first surface portions 8 within the multiple source openings 80 in a film-like manner.

[0159] Specifically, the first lower electrode film 88 directly covers the insulating principal surface of the first inorganic film 75 and faces the plurality of gate structures 25 across the first inorganic film 75. The first lower electrode film 88 extends into the plurality of source openings 80 from above the insulating principal surface of the first inorganic film 75 and coats the wall surfaces of the plurality of source openings 80 in a film-like manner. The first lower electrode film 88 coats the first surface portion 8 in the plurality of source openings 80 in a film-like manner. The first lower electrode film 88 is mechanically and electrically connected to the plurality of first source structures 30, source regions 21, and plurality of contact regions 37 in the plurality of source openings 80.

[0160] 6 and 7 , the first upper electrode film 89 is laminated in the form of a film on the first lower electrode film 88 as the main body of the source electrode 85, and forms the upper layer portions of the first electrode surface 86 and the first electrode sidewall 87 of the source electrode 85. The first upper electrode film 89 contains a conductive material different from that of the first lower electrode film 88. The first upper electrode film 89 may include at least one of an Al film, an Al alloy film, a Cu film, and a Cu alloy film. The Al alloy film may include at least one of an AlSi alloy film, an AlCu alloy film, and an AlSiCu alloy film.

[0161] The first upper electrode film 89 has a thickness greater than the thickness (total thickness) of the first lower electrode film 88. The thickness of the first upper electrode film 89 is preferably greater than the thickness of the first inorganic film 75. The thickness of the first upper electrode film 89 is preferably greater than the depth of the gate structure 25. The thickness of the first upper electrode film 89 is preferably greater than the depth of the first source structure 30. The thickness of the first upper electrode film 89 is preferably greater than the depth of the second surface portion 9.

[0162] The first upper electrode film 89 collectively covers the region of the first inorganic film 75 where the plurality of source openings 80 are formed, in the form of a film, and backfills the plurality of source openings 80. The first upper electrode film 89 has a portion that covers the insulating principal surface of the first inorganic film 75 with the first lower electrode film 88 in between, a portion that covers the wall surfaces of the plurality of source openings 80 with the first lower electrode film 88 in between, and a portion that covers the first surface portion 8 with the first lower electrode film 88 in between.

[0163] Specifically, the first upper electrode film 89 covers the insulating main surface of the first inorganic film 75 with the first lower electrode film 88 interposed therebetween, and faces the plurality of gate structures 25 with the first inorganic film 75 and the first lower electrode film 88 interposed therebetween. The first upper electrode film 89 extends into the plurality of source openings 80 from above the first inorganic film 75, and coats the wall surfaces of the plurality of source openings 80 in a film-like manner with the first lower electrode film 88 interposed therebetween.

[0164] The first upper electrode film 89 covers the first surface portion 8 in a film state within the plurality of source openings 80, sandwiching the first lower electrode film 88. The first upper electrode film 89 is electrically connected to the plurality of first source structures 30, the source regions 21, and the plurality of contact regions 37 via the first lower electrode film 88 within the plurality of source openings 80.

[0165] 2, 3, 6, 7, and 17 to 20, the semiconductor device 1 includes a source wiring (peripheral source electrode portion) 90 arranged around the source electrode 85 on the first inorganic film 75. The same potential (source potential) as the source potential applied to the source electrode 85 is applied to the source wiring 90. The source wiring 90 may also be referred to as a "wiring," a "first wiring," a "finger electrode," a "source finger," or the like.

[0166] 17 and 18 , the thickness of the source wiring 90 is greater than the depth of the gate structure 25. The thickness of the source wiring 90 is greater than the depth of the first source structure 30. The thickness of the source wiring 90 is greater than the depth of the second surface portion 9. The thickness of the source electrode 85 is preferably greater than the thickness (total thickness) of the first inorganic film 75. The thickness of the source wiring 90 is preferably approximately equal to the thickness of the source electrode 85. Of course, the thickness of the source wiring 90 may be greater than the thickness of the source electrode 85 or may be less than the thickness of the source electrode 85. The thickness of the source wiring 90 may be 0.5 μm or more and 5 μm or less.

[0167] 18 and 20 , the source wiring 90 has a wiring width smaller than the electrode width of the source electrode 85 and is selectively routed over the first inorganic film 75. The source wiring 90 extends in a strip shape along the first electrode sidewall 87 of the source electrode 85 at a distance from the first electrode sidewall 87. The source wiring 90 preferably extends in a strip shape along at least one of the third connecting surface portion 10C and the fourth connecting surface portion 10D. In this embodiment, the source wiring 90 is formed in a polygonal ring shape (specifically, a square ring shape) extending along the first to fourth connecting surface portions 10A to 10D in a plan view and surrounds the source electrode 85.

[0168] In this embodiment, the source wiring 90 is disposed on the first end region 13, the second end region 14, the third end region 15, the fourth end region 16, the fifth end region 17, and the sixth end region 18 in plan view, and surrounds the active region 12. The source wiring 90 may have an edge portion that connects the portion extending in the first direction X and the portion extending in the second direction Y in an arc shape (preferably a quadrant arc shape).

[0169] 20 , the source wiring 90 is electrically connected to the source electrode 85 on the first surface 8. Specifically, the source wiring 90 has a portion extending along the second connection surface 10B that extends in a strip shape in the second direction Y toward the source electrode 85 (first pad portion 85 a), and is connected to an end of the source electrode 85 (first pad portion 85 a). The source wiring 90 is formed as an extraction wiring that is extracted from the source electrode 85.

[0170] The source wiring 90 is drawn out from the first surface 8 across at least one (all in this embodiment) of the first to fourth connection surface portions 10A to 10D onto the second surface 9. In this embodiment, the source wiring 90 is formed as the outermost wiring on the second surface 9. The source wiring 90 does not face other electrodes in the horizontal direction along the insulating main surface of the first inorganic film 75 in the peripheral region 19. In other words, other electrodes are not interposed between the periphery of the second surface 9 and the region between the source wiring 90.

[0171] 2 and 3 , the source wiring 90 covers the sidewall wiring 79 on the first to fourth connection surface portions 10A to 10D with the first inorganic film 75 (upper inorganic film 77) interposed therebetween. The source wiring 90 enters the outer opening 81 from above the first inorganic film 75 and is connected to both the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.

[0172] As a result, the source wiring 90 is electrically connected to the outer contact region 71 and the sidewall wiring 79. The source wiring 90 transmits the source potential applied to the source electrode 85 to the first source structure 30, the second source structure 40, the dummy gate structure 50, the third source structure 55, and the fourth source structure 65 via the sidewall wiring 79. The source wiring 90 also transmits the source potential applied to the source electrode 85 to the outer well region 70 and the termination region 73 via the outer contact region 71.

[0173] 17 and 18 , the source wiring 90 is disposed at a distance from the plurality of field regions 72 on the first surface portion 8 (inside the first main surface 3) side, and faces a portion of the termination region 73 and the entire outer well region 70 across the first inorganic film 75. In this embodiment, the source wiring 90 is disposed at a distance from the outer edge of the termination region 73 on the first surface portion 8 (inside the first main surface 3) side, and covers the entire outer well region 70 and the entire outer contact region 71. The source wiring 90 covers a portion of the inner side of the termination region 73 (the source electrode 85 side). The source wiring 90 exposes the plurality of field regions 72.

[0174] As shown in FIGS. 17 and 18 , the source wiring 90 has a first wiring surface 91, a first inner wall 92 on the inner side (the source electrode 85 side), and a first outer wall 93 on the outer side (the peripheral edge side of the chip 2). The portion of the first wiring surface 91 located on the first surface 8 is located at a height position approximately equal to that of the first electrode surface 86 of the source wiring 90. The portion of the first wiring surface 91 located on the second surface 9 is recessed toward the second surface 9 relative to the portion of the first wiring surface 91 located on the first surface 8. The portion of the first wiring surface 91 located on the second surface 9 is preferably located above the height position of the first surface 8 (the side of the portion of the first wiring surface 91 located on the first surface 8). Of course, the portion of the first wiring surface 91 located on the second surface 9 may also be located below the height position of the first surface 8 (the side of the second surface 9).

[0175] 17 and 18 , the first inner side wall 92 is located on a portion of the first inorganic film 75 that covers the first surface portion 8, with a gap between the first inner side wall 92 and the first electrode side wall 87 of the source electrode 85. The first inner side wall 92 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75.

[0176] 17 to 19 , the first outer wall 93 is located on a portion of the first inorganic film 75 that covers the second surface 9. The first outer wall 93 slopes obliquely downward from the first wiring surface 91 toward the first inorganic film 75. In this embodiment, the first outer wall 93 slopes obliquely downward in a curved shape from the first wiring surface 91 toward the first inorganic film 75. In this embodiment, the lower end of the outer edge of the first outer wall 93 is the outer edge (first outer edge) 90a of the source wiring 90.

[0177] In this embodiment, the first outer wall 93 faces the outer well region 70 with the first inorganic film 75 interposed therebetween. The first outer wall 93 faces the outer contact region 71 with the first inorganic film 75 interposed therebetween. The first outer wall 93 does not face the multiple field regions 72 in the vertical direction Z.

[0178] The first outer wall 93 faces a part of the termination region 73 with the first inorganic film 75 interposed therebetween. The first outer wall 93 faces an inner edge 73b of the termination region 73 with the first inorganic film 75 interposed therebetween. The first outer wall 93 does not face an outer edge (second outer edge) 73a of the termination region 73 in the vertical direction Z.

[0179] 19 , the outer edge 90a of the source wiring 90 is located more inward (closer to the source electrode 85) than the outer edge 73a of the termination region 73. In other words, the outer edge 73a of the termination region 73 is located more outward (closer to the periphery of the chip 2) than the outer edge 90a of the source wiring 90. A first distance L1 between the outer edge 73a of the termination region 73 and the outer edge 90a of the source wiring 90 is 10 μm or more.

[0180] The first distance L1 may be 10 μm or more and 50 μm or less. The first distance L1 may have a value belonging to at least one of the following ranges: 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less. In the example of FIG. 19 , the first distance L1 is 16 μm.

[0181] The first distance L1 may be equal to or greater than the thickness T1 of the second semiconductor region 7. When the second semiconductor region 7 includes an epitaxial layer, the first distance L1 may be equal to or greater than the thickness T1 of the epitaxial layer.

[0182] A second distance L2 (see FIGS. 17 and 18 ) between the outer edge 90a of the source wiring 90 and the periphery of the first main surface 3 (first to fourth side surfaces 5A to 5D) may be 20 μm or more and 100 μm or less. The second distance L2 may have a value belonging to at least one of the following ranges: 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, and 90 μm or more and 100 μm or less. In the example shown in FIGS. 17 and 18 , the second distance L2 is 50 μm.

[0183] The ratio (L1 / L2) of the first distance L1 to the second distance L2 may be 0.1 or greater and 0.6 or less. The ratio (L1 / L2) may have a value belonging to at least one of the following ranges: 0.1 or greater and 0.15 or less, 0.15 or greater and 0.2 or less, 0.2 or greater and 0.25 or less, 0.25 or greater and 0.3 or less, 0.3 or greater and 0.35 or greater and 0.4 or less, 0.4 or greater and 0.45 or less, 0.45 or greater and 0.5 or less, 0.5 or greater and 0.55 or less, and 0.55 or greater and 0.6 or less. In the examples of FIGS. 17 to 19 , the ratio (L1 / L2) is 0.16.

[0184] The first distance L1 may be the same as the overall width (second width) W2 of the plurality of field regions 72. Of course, the first distance L1 may be greater than the overall width (second width) W2 of the plurality of field regions 72. The first distance L1 may be smaller than the overall width (second width) W2 of the plurality of field regions 72.

[0185] 19 , inner edge 73b of termination region 73 is located further inward of first main surface 3 (closer to first surface portion 8) than outer edge (first outer edge) 90a of source wiring 90. A third distance L3 (see FIGS. 17 and 18 ) between inner edge 73b of termination region 73 and outer edge 90a of source wiring 90 is 5 μm or greater.

[0186] The third distance L3 (see FIGS. 17 and 18 ) may be 3 μm or more and 20 μm or less. The third distance L3 may have a value belonging to at least one of the following ranges: 3 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, and 15 μm or more and 20 μm or less. In the example of FIGS. 17 and 18 , the third distance L3 is approximately 10 μm. It is preferable that the first distance L1 is longer than the third distance L3. Of course, the first distance L1 may be equal to or less than the third distance L3.

[0187] 10 and other drawings, the source wiring 90 has a laminated structure including a first lower electrode film 88 and a first upper electrode film 89, similar to the source electrode 85. The first lower electrode film 88 is laminated in the form of a film on the first inorganic film 75 as a base film (barrier film) of the source wiring 90, and forms a lower layer portion of a first outer wall 93 of the source wiring 90.

[0188] The first lower electrode film 88 covers the entire region of the first inorganic film 75 where the outer opening 81 is formed, and extends into the outer opening 81 from above the first inorganic film 75. The first lower electrode film 88 is mechanically and electrically connected to the outer contact region 71 and the sidewall wiring 79 within the outer opening 81.

[0189] The first upper electrode film 89 is laminated in film form on the first lower electrode film 88 as the main body of the source wiring 90, and forms the first wiring surface 91 of the source wiring 90, the upper layer portion of the first inner wall 92, and the upper layer portion of the first outer wall 93. The first upper electrode film 89 collectively covers the region of the first inorganic film 75 where the outer opening 81 is formed, and backfills the outer opening 81. The first upper electrode film 89 is electrically connected to the outer contact region 71 and the sidewall wiring 79 via the first lower electrode film 88 within the outer opening 81.

[0190] Inside the chip 2, different electric field distributions are formed on the first surface 8 side (active region 12 side) and the second surface 9 side (peripheral region 19 side). For example, on the first surface 8 side, a substantially uniform electric field distribution is formed along the first main surface 3. On the other hand, on the second surface 9 side, an end portion of the electric field distribution formed on the first surface 8 side is formed, and the electric field is more likely to concentrate there than on the first surface 8.

[0191] The source electrode 85 is disposed on the active region 12, which has a relatively low first electric field, while the source wiring 90 is disposed on the peripheral region 19, which has a second electric field higher than the first electric field.

[0192] 2, 3 and 20, semiconductor device 1 includes a gate electrode 95 disposed on first inorganic film 75. Gate electrode 95 is a terminal electrode to which a gate potential is applied from the outside.

[0193] 20 , the gate electrode 95 is disposed on the first inorganic film 75 at a distance from the source electrode 85. The gate electrode 95 is disposed on the portion of the first inorganic film 75 that covers the first surface portion 8. The gate electrode 95 is formed in a polygonal shape (a quadrangular shape in this embodiment) having four sides parallel to the periphery of the chip 2 in a plan view. The gate electrode 95 has a planar area that is smaller than the planar area of ​​the source electrode 85.

[0194] In this embodiment, the gate electrode 95 does not have direct electrical connection to the plurality of gate structures 25 (see FIGS. 6, 7, etc.). Of course, the gate electrode 95 may be electrically connected to the plurality of gate structures 25 via the plurality of gate openings 82 (see FIG. 9). Of course, the portions of the plurality of gate structures 25 located directly below the gate electrode 95 may be removed.

[0195] 2 , the gate electrode 95 has a second electrode surface 96 and a second electrode sidewall 97. The second electrode surface 96 extends along the first inorganic film 75. The second electrode sidewall 97 is located on the first inorganic film 75. The second electrode sidewall 97 slopes obliquely downward from the second electrode surface 96 toward the first inorganic film 75. In this embodiment, the gate electrode 95 has a laminated structure including a second lower electrode film and a second upper electrode film laminated in this order from the first inorganic film 75 side.

[0196] 9 and 20, the semiconductor device 1 includes a gate wiring 100 disposed on the first inorganic film 75 around the source electrode 85.

[0197] 20 , the gate wiring 100 has a wiring width smaller than the electrode width of the gate electrode 95, and is selectively routed over the first inorganic film 75. The gate wiring 100 is disposed inward from the periphery of the first surface portion 8 at a distance. The gate wiring 100 is not positioned on the second surface portion 9.

[0198] The gate wiring 100 is electrically connected to the gate electrode 95 on the first surface 8. Specifically, the gate wiring 100 is connected to the end of the gate electrode 95 on the first connection surface 10A side. The gate wiring 100 is formed as a lead-out wiring led out from the gate electrode 95. The connection portion of the gate electrode 95 and the gate wiring 100 may be regarded as part of the gate electrode 95. As shown in FIG. 9 and other figures, the gate wiring 100 has a layered structure including a second lower electrode film 98 and a second upper electrode film 99, similar to the gate electrode 95.

[0199] 9 , the gate wiring 100 enters the plurality of gate openings 82 from above the first inorganic film 75, and is electrically connected to the ends (both ends) of the plurality of gate structures 25 within the plurality of gate openings 82. Specifically, the gate wiring 100 is mechanically and electrically connected to the plurality of gate connection electrodes 78 within the plurality of gate openings 82, and is electrically connected to the plurality of gate structures 25 via the plurality of gate connection electrodes 78. As a result, the gate potential applied to the gate electrode 95 is applied to the plurality of gate structures 25 via the gate wiring 100.

[0200] Fig. 21 is a plan view showing an example layout of the second inorganic film 110. In Fig. 21, the second inorganic film 110 is shown hatched. The second inorganic film 110 will be described below with reference to Figs. 2, 3, 17 to 19, and 21.

[0201] The semiconductor device 1 includes an insulating second inorganic film (second insulating film) 110 that selectively covers the first inorganic film 75. The second inorganic film 110 may be referred to as a "second inorganic insulating film," an "upper insulating film," a "passivation film," or the like. The second inorganic film 110 may include at least one of a silicon oxide film, a silicon nitride film, and a silicon oxynitride film.

[0202] The second inorganic film 110 preferably contains an insulating material different from the insulating material of the first inorganic film 75. Specifically, the second inorganic film 110 preferably contains an insulating material different from the insulating material of the upper inorganic film 77. In this embodiment, the second inorganic film 110 has a single-layer structure made of a silicon nitride film.

[0203] The second inorganic film 110 preferably has a thickness less than the thickness of the source electrode 85 (gate electrode 95). The thickness of the second inorganic film 110 is preferably greater than the thickness of the lower inorganic film 76. The thickness of the second inorganic film 110 is preferably greater than the thickness of the upper inorganic film 77. The thickness of the second inorganic film 110 is preferably greater than the thickness (total thickness) of the first inorganic film 75. Of course, the thickness of the second inorganic film 110 may be less than the thickness (total thickness) of the first inorganic film 75. The thickness of the second inorganic film 110 may be less than the thickness of the upper inorganic film 77. The thickness of the second inorganic film 110 may be less than the thickness of the lower inorganic film 76.

[0204] The thickness of the second inorganic film 110 may be 0.01 μm or more and 5 μm or less. The thickness of the second inorganic film 110 may have a value belonging to at least one of the ranges of 0.01 μm or more and 0.1 μm or less, 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1 μm or less, 1 μm or more and 1.5 μm or less, 1.5 μm or more and 2 μm or less, 2 μm or more and 2.5 μm or less, 2.5 μm or more and 3 μm or less, 3 μm or more and 3.5 μm or less, 3.5 μm or more and 4 μm or less, 4 μm or more and 4.5 μm or less, and 4.5 μm or more and 5 μm or less. The thickness of the second inorganic film 110 is preferably 0.1 μm or more and 2 μm or less.

[0205] 2, 3, and 21, the second inorganic film 110 selectively covers the source electrode 85, the source wiring 90, the gate electrode 95, and the gate wiring 100 on the first inorganic film 75. Specifically, the second inorganic film 110 has a first inner coating portion 111, a second inner coating portion 112, and an outer coating portion 113.

[0206] In this embodiment, the first inner covering portion 111 is formed in a ring shape in plan view that surrounds the inner portion of the first electrode surface 86. Specifically, the first inner covering portion 111 is formed in a polygonal ring shape (U-ring) that matches the planar shape of the first electrode surface 86 in plan view.

[0207] The first inner covering portion 111 extends flatly over the first electrode surface 86. The first inner covering portion 111 covers the peripheral edge of the first electrode surface 86 (source electrode 85), leaving the inside of the first electrode surface 86 (source electrode 85) exposed. The first inner covering portion 111 extends in a strip shape along the peripheral edge of the first electrode surface 86 along the first electrode sidewall 87. The first inner covering portion 111 selectively covers the source electrode 85. Specifically, the first inner covering portion 111 coats the first electrode surface 86 of the source electrode 85 in a film-like manner so as to expose at least a portion of the first electrode sidewall 87 of the source electrode 85. In this embodiment, the first inner covering portion 111 exposes the entire first electrode sidewall 87.

[0208] 2 , in this embodiment, the first inner covering portion 111 has an extension 115 that extends from above the source electrode 85 to above the connection portion between the source electrode 85 and the source wiring 90. In this embodiment, the extension 115 is formed to be wider than the other portions. Of course, the extension 115 may have approximately the same width as the other portions.

[0209] 2, 3, 21, etc., the first inner covering portion 111 defines a first pad opening 116 that exposes the inner portion of the first electrode surface 86. The first pad opening 116 is defined in a polygonal shape having four sides parallel to the periphery of the chip 2 in a plan view. In this embodiment, the first pad opening 116 is defined in a polygonal shape (U-shape) that matches the planar shape of the first electrode surface 86 in a plan view.

[0210] 2 and 21 , the second inner coating portion 112 selectively covers the gate electrode 95. Specifically, the second inner coating portion 112 forms a film covering the second electrode surface 96 (see FIG. 2 ) of the gate electrode 95 so as to expose at least a portion of the second electrode sidewall 97 of the gate electrode 95. In this embodiment, the second inner coating portion 112 exposes the entire area of ​​the second electrode sidewall 97 (see FIG. 2 ).

[0211] In this embodiment, the second internal covering portion 112 is formed in a ring shape that surrounds the inner portion of the second electrode surface 96 in a plan view. The second internal covering portion 112 is formed in a polygonal ring shape (a square ring shape in this embodiment) that has four sides parallel to the periphery of the chip 2 in a plan view. Specifically, the second internal covering portion 112 is formed in a polygonal ring shape (specifically, a square ring shape) that matches the planar shape of the second electrode surface 96 in a plan view.

[0212] The second inner covering portion 112 defines a second pad opening 117 that exposes the inner portion of the second electrode surface 96. The second pad opening 117 is defined in a polygonal shape (a quadrilateral shape in this embodiment) having four sides parallel to the periphery of the chip 2 in plan view.

[0213] 17 to 19 and 21 , the outer covering portion 113 selectively covers the first inorganic film 75 at a distance from the first inner covering portion 111 and the second inner covering portion 112. Specifically, the outer covering portion 113 is formed on the covering portion of the first inorganic film 75 that corresponds to the second surface portion 9. In plan view, the outer covering portion 113 extends in a strip shape along the first surface portion 8. In plan view, the outer covering portion 113 is formed in a ring shape (a square ring shape in this embodiment) that surrounds the first surface portion 8.

[0214] The outer covering portion 113 extends in a film-like shape along the second surface portion 9 within the anchor opening 83. The outer covering portion 113 defines an anchor recess 118 that is recessed toward the anchor opening 83 in the covering portion corresponding to the anchor opening 83. When multiple anchor openings 83 are formed in the first inorganic film 75, the outer covering portion 113 defines multiple anchor recesses 118. The anchor recess 118 has a planar shape that is approximately similar to the planar shape of the anchor opening 83. The anchor recess 118 extends in a band-like shape (annular in this embodiment) along the anchor opening 83 in a plan view.

[0215] In this embodiment, the outer covering portion 113 is drawn out from the anchor opening 83 toward the periphery of the second surface portion 9 (toward the first to fourth side surfaces 5A to 5D). The outer covering portion 113 is formed at a distance inward from the periphery of the second surface portion 9, and exposes the first inorganic film 75 from the periphery of the second surface portion 9.

[0216] 19 and 21 , the outer covering portion 113 has an inner edge 113a that is positioned between the first outer wall 93 of the source wiring 90 and the periphery of the second surface portion 9 (first to fourth side surfaces 5A to 5D). The inner edge 113a of the outer covering portion 113 is positioned between the anchor opening 83 and the first outer wall 93 of the source wiring 90. The inner edge 113a of the outer covering portion 113 is positioned closer to the first surface portion 8 (closer to the first outer wall 93) than the outer edge 73a of the termination region 73. The inner edge 113a of the outer covering portion 113 extends along the second electrode sidewall 97 at a distance from the second electrode sidewall 97.

[0217] In this embodiment, the outer covering portion 113 sandwiches the first inorganic film 75 on the second surface portion 9 side, covering a part of the outer side (the peripheral edge side of the first main surface 3) of the termination region 73 and the entire areas of the plurality of field regions 72. The outer covering portion 113 exposes the outer well region 70 and the outer contact region 71.

[0218] As shown in FIG. 19 , the distance W3 between the inner edge 113a of the outer coating portion 113 and the outer edge 73a of the termination region 73 (the width of the coating target portion 73c; first width) may be 10 μm or more and 50 μm or less. The width W3 may have a value within at least one of the following ranges: 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more and 35 μm or less, 35 μm or more and 40 μm or less, 40 μm or more and 45 μm or less, and 45 μm or more and 50 μm or less. The width W3 may be less than the overall width W2 of the multiple field regions 72. The width W3 may be the same as the width W2 or, as in the first embodiment shown in FIG. 19 , may be narrower than the width W2. Of course, the width W3 may also be wider than the width W2.

[0219] 1 to 3, 17, and 18 again, the semiconductor device 1 includes an insulating organic film 120 that selectively covers the second inorganic film 110. The organic film 120 may be referred to as an "organic insulating film," a "resin film," or the like. The organic film 120 preferably includes a transparent resin or a translucent resin. The organic film 120 preferably includes a photosensitive resin. The photosensitive resin may be a negative type or a positive type. The organic film 120 may include at least one of a polyimide film, a polyamide film, and a polybenzoxazole film.

[0220] The organic film 120 may have a thickness greater than the depth of the gate structure 25. The thickness of the organic film 120 may be greater than the thickness (total thickness) of the first inorganic film 75. The thickness of the organic film 120 may be greater than the thickness of the source electrode 85 (gate electrode 95). The thickness of the organic film 120 may be greater than the thickness of the second inorganic film 110. The thickness of the organic film 120 is preferably less than the thickness of the chip 2. The thickness of the organic film 120 may be greater than the thickness of the second semiconductor region 7 or less than the thickness of the second semiconductor region 7.

[0221] The organic film 120 covers the second surface portion 9 from above the first surface portion 8, across the first to fourth connection surface portions 10A to 10D. The organic film 120 directly covers the first inner coating portion 111, the second inner coating portion 112, and the outer coating portion 113 of the second inorganic film 110.

[0222] The organic film 120 directly covers the first electrode sidewall 87 of the source electrode 85 in the region between the first inner coating portion 111 and the outer coating portion 113. The organic film 120 directly covers the second electrode sidewall 97 of the gate electrode 95 in the region between the second inner coating portion 112 and the outer coating portion 113. The organic film 120 directly covers both the first electrode sidewall 87 of the source electrode 85 and the second electrode sidewall 97 of the gate electrode 95 in the region between the first inner coating portion 111 and the second inner coating portion 112.

[0223] The organic film 120 covers the entire periphery of the first internal covering portion 111 and defines a first upper pad opening 121 that exposes the inner portion of the first electrode surface 86 (see FIGS. 1 to 3). Specifically, the organic film 120 covers the first internal covering portion 111 with a gap between the inner edge (inner wall) of the first internal covering portion 111 and the outer edge (outer wall) of the first internal covering portion 111, exposing the inner edge of the first internal covering portion 111. The wall surface of the first upper pad opening 121 is positioned closer to the first electrode sidewall 87 than the wall surface of the first pad opening 116, and faces the first electrode surface 86 across the first internal covering portion 111.

[0224] The organic film 120 covers the entire periphery of the second internal covering portion 112 and defines a second upper pad opening 122 that exposes the inner portion of the second electrode surface 96 (see FIGS. 1 to 3 ). Specifically, the organic film 120 covers the second internal covering portion 112 with a gap between the inner edge (inner wall) of the second internal covering portion 112 and the outer edge (outer wall) of the second internal covering portion 112, exposing the inner edge of the second internal covering portion 112. The wall surface of the second upper pad opening 122 is positioned closer to the second electrode sidewall 97 than the wall surface of the second pad opening 117, and faces the second electrode surface 96 with the second internal covering portion 112 in between.

[0225] The organic film 120 covers the outer well region 70, the termination region 73, and the plurality of field regions 72 on the second surface 9 side, sandwiching the first inorganic film 75 and the second inorganic film 110. The organic film 120 covers the anchor openings 83 on the periphery of the second surface 9, sandwiching the second inorganic film 110. The organic film 120 engages with the anchor recesses 118 of the second inorganic film 110 (the anchor openings 83 of the first inorganic film 75).

[0226] In this embodiment, the organic film 120 is drawn out from the anchor opening 83 toward the periphery of the second surface portion 9 (toward the first to fourth side surfaces 5A to 5D). The organic film 120 is formed at a distance inward from the periphery of the second surface portion 9, exposing the first inorganic film 75 from the periphery of the second surface portion 9. In this embodiment, the organic film 120 covers the outer covering portion 113 at a distance inward from the outer edge (outer wall) of the outer covering portion 113, exposing the outer edge of the outer covering portion 113.

[0227] 2 and 3 , the semiconductor device 1 includes a drain electrode 125 covering the second main surface 4. The drain electrode 125 is a terminal electrode to which a drain potential is applied from the outside. The drain electrode 125 may also be referred to as an "electrode," a "third electrode," a "third pad electrode," a "third main surface electrode," a "third terminal electrode," a "drain pad electrode," or the like.

[0228] The drain electrode 125 is electrically connected to the first semiconductor region 6. The drain electrode 125 may cover the entire second main surface 4 so as to be continuous with the periphery of the second main surface 4 (so as to be continuous with the first to fourth side surfaces 5A to 5D). The drain electrode 125 may also cover a portion of the second main surface 4 so as to expose the periphery of the second main surface 4.

[0229] The breakdown voltage that can be applied between the source electrode 85 and the drain electrode 125 (between the first main surface 3 and the second main surface 4) may be 500 V or more and 3000 V or less. The breakdown voltage may have a value that belongs to at least one of the ranges of 500 V or more and 1000 V or less, 1000 V or more and 1500 V or less, 1500 V or more and 2000 V or less, 2000 V or more and 2500 V or less, and 2500 V or more and 3000 V or less.

[0230] FIG. 22 is a cross-sectional view showing the cross-sectional structure of the semiconductor device 1 together with the peripheral structure according to the second embodiment, and corresponds to FIG.

[0231] 17 to 19, the first distance L1 between the outer edge 90a of the source wiring 90 and the outer edge 73a of the termination region 73 is wider in the second embodiment. In the example of FIG. 22, the first distance L1 is 20 μm or more (e.g., 30 μm). In the second embodiment, the first distance L1 is also greater than the overall width (second width) W2 of the multiple field regions 72.

[0232] From another perspective, the width W3 of the coating target portion 73c (the distance between the inner edge of the outer coating portion 113 and the termination region 73) is wider than the overall width W2 of the multiple field regions 72. From another perspective, in the second embodiment, the first distance L1 is wider than the width W2. In this case, the ratio of the first distance L1 to the second distance L2 (L1 / L2) is 0.47.

[0233] As described above, according to the first and second embodiments, the semiconductor device 1 includes a p-type termination region 73 formed in the second surface 9 (the peripheral portion of the first main surface 3) and a source wiring 90 disposed on the second surface 9. The first distance L1 between the outer edge 90a of the source wiring 90 and the outer edge 73a of the termination region 73 is 10 μm or more. From another perspective, the first distance L1 is equal to or greater than the thickness T1 of the second semiconductor region 7 (epitaxial layer). From another perspective, the ratio (L1 / L2) of the first distance L1 to the second distance L2 is 0.1 or more. From yet another perspective, the first distance L1 is longer than the third distance L3 between the inner edge 73b of the termination region 73 and the outer edge 90a of the source wiring 90.

[0234] In the outer peripheral region 19, a high electric field is generated in the terminal region 73 where the electric field tends to concentrate. Specifically, in the terminal region 73, a high electric field is locally formed in a high electric field region 74 (see FIG. 19 ) of a predetermined width extending from the outer edge 73 a of the terminal region 73 toward the first surface 8.

[0235] 23 is a cross-sectional view of a semiconductor device 151 according to the reference embodiment, and is a view corresponding to FIG. 19. If the first distance L1 is set short (for example, to about 6 μm) as in the semiconductor device 151 according to the reference embodiment shown in FIG. 23, a high electric field region 74 is formed directly below the source wiring 90, which may result in a high electric field being concentrated in the source wiring 90. In this case, the oxidation reaction of the source wiring 90 may be accelerated.

[0236] In contrast, in this embodiment, the first distance L1 is 10 μm or more. From another perspective, the first distance L1 is equal to or greater than the thickness T1 of the second semiconductor region 7 (epitaxial layer). From another perspective, the ratio (L1 / L2) of the first distance L1 to the second distance L2 is 0.1 or more. From yet another perspective, the first distance L1 is longer than the third distance L3. Therefore, the high electric field region 74 (see FIG. 19 ) is formed in a region closer to the periphery of the first main surface 3 than the outer edge 90a of the source wiring 90. That is, the electric field region 74 is not formed directly below the source wiring 90. This allows the electric field generated in the source wiring 90 to be kept low. Because a high electric field is not generated directly below the source wiring 90, oxidation of the source wiring 90 can be suppressed. This prevents defects caused by oxidation of the source wiring 90.

[0237] Furthermore, since the ratio (L1 / L2) of the first distance L1 to the second distance L2 is 0.6 or less, it is possible to prevent the proportion of the termination region 73 on the first main surface 3 from becoming high. Therefore, it is possible to improve the efficiency of forming the transistor structure Tr on the first main surface 3.

[0238] Fig. 24 is a cross-sectional view of a semiconductor device 201 according to another embodiment of the present disclosure, and is a view corresponding to Fig. 19. In Fig. 24, the same components as those described up to now are denoted by the same reference numerals, and description thereof will be omitted.

[0239] 1 to 22 in that the semiconductor device 201 according to the other embodiment does not include the plurality of field regions 72. In other respects, the semiconductor device 201 does not differ from the semiconductor device 1. The semiconductor device 201 provides the same effects as those described in relation to the embodiment shown in FIGS.

[0240] Furthermore, a semiconductor device 201 according to another embodiment may employ a configuration in which the first distance L1 is large, as in the second embodiment shown in Fig. 22. In other words, in the second embodiment shown in Fig. 22, the plurality of field regions 72 may be eliminated.

[0241] In the above-described embodiments, the source wiring 90 is the outermost electrode portion, but a configuration in which the source wiring 90 is not used may be adopted. The peripheral portion of the source electrode 85 may be the outermost electrode portion (peripheral source electrode portion). In this case, the distance between the peripheral portion (peripheral source electrode portion) of the source electrode 85 and the outer edge 73a of the termination region 73 can be considered to be the same as the first distance L1 described above. In this case, the distance between the peripheral portion (peripheral source electrode portion) of the source electrode 85 and the outer edge 73a of the termination region 73 is preferably 10 μm or more.

[0242] This makes it possible to suppress the electric field generated in the peripheral portion (peripheral source electrode portion) of the source electrode 85. This makes it possible to suppress oxidation of the peripheral portion (peripheral source electrode portion) of the source electrode 85. This makes it possible to suppress the occurrence of defects caused by oxidation of the peripheral portion (peripheral source electrode portion) of the source electrode 85.

[0243] The above-described embodiments can be implemented in other forms. For example, in the above-described embodiments, the mesa 11 (the first surface 8, the second surface 9, and the first to fourth connecting surface portions 10A to 10D) is defined on the first main surface 3. However, the first main surface 3 does not necessarily have to have the mesa 11, and may be formed flat.

[0244] In this case, the active region 12 and the peripheral region 19 are defined by the outer well region 70. Also, in this case, the first end region 13, the second end region 14, the third end region 15, the fourth end region 16, the fifth end region 17, and the sixth end region 18 may be removed.

[0245] In each of the above-described embodiments, an example has been shown in which the anchor openings 83 are formed in the first inorganic film 75. However, a first inorganic film 75 that does not have the anchor openings 83 may also be employed.

[0246] In the above-described embodiments, examples have been described in which the first conductivity type is n-type and the second conductivity type is p-type, but the first conductivity type may be p-type and the second conductivity type may be n-type. A specific configuration in this case can be obtained by replacing n-type regions with p-type regions and p-type regions with n-type regions in the above description and accompanying drawings.

[0247] In the above-described embodiments, the chip 2 includes a SiC single crystal. However, the chip 2 may include a silicon single crystal. Similarly, the first semiconductor region 6 may include a silicon single crystal. Similarly, the second semiconductor region 7 may include a silicon single crystal.

[0248] In each of the above-described embodiments, a p-type collector region may be formed in a surface layer portion of the second main surface 4 of the chip 2. In this case, the transistor structure Tr includes an IGBT (Insulated Gate Bipolar Transistor) structure instead of the MISFET structure. A specific configuration in this case can be obtained by replacing the "source" of the MISFET structure with the "emitter" of the IGBT structure and the "drain" of the MISFET structure with the "collector" of the IGBT structure in the above description. In this case, the chip 2 may have a single-layer structure made of an n-type semiconductor substrate.

[0249] In each of the above-described embodiments, the first semiconductor region 6 (second semiconductor region 7) may be formed as part or all of the cathode region of a semiconductor rectifier (diode), and the body region 20 may be formed as part or all of the anode region of the semiconductor rectifier (diode). In this case, the source electrode 85 is formed as an anode electrode, and the drain electrode 125 is formed as a cathode electrode. Of course, instead of the body region 20 (anode region) and the source electrode 85, a Schottky electrode (anode electrode) that forms a Schottky junction with the second semiconductor region 7 may be employed.

[0250] The embodiments of the present disclosure are to be considered as illustrative in all respects and not restrictive, and are intended to include modifications in all respects.

[0251] The following additional features can be extracted from the description of this specification and the drawings. Hereinafter, alphanumeric characters in parentheses represent corresponding components in the above-mentioned embodiments, but are not intended to limit the scope of each clause to the embodiments.

[0252] [Supplementary Note 1-1] A chip (2) having a main surface (3), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), a device structure (Tr) having a source structure (30) and formed in the semiconductor region (7) in an inner portion of the main surface (3), a peripheral source electrode portion (90) having a first outer edge (90a), disposed on a peripheral portion of the main surface (3) and electrically connected to the source structure (30), and a termination region (73) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in the peripheral portion of the main surface (3), the termination region (73) having a second outer edge (73a) located closer to the peripheral edge of the main surface (3) than the first outer edge (90a), the termination region (73) being electrically connected to the peripheral source electrode portion (90), A semiconductor device (1, 201), wherein a first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) is 10 μm or more.

[0253] According to this configuration, the semiconductor device (1, 201) includes a second conductivity type termination region (73) formed in the peripheral portion of the main surface (3), and a peripheral source electrode portion (90) arranged on the peripheral portion of the main surface (3). A first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) is 10 μm or more.

[0254] A high electric field is generated in the terminal region (73) at the peripheral edge of the main surface (3). In the terminal region (73), a particularly high electric field is formed in a region of a predetermined width (high electric field region (74)) extending from the second outer edge (73a) of the terminal region (73) toward the inner portion of the main surface (3). Therefore, if the first distance (L1) is set short, the high electric field region (74) is formed directly below the peripheral source electrode portion (90), which may result in a high electric field being concentrated at the peripheral source electrode portion (90). In this case, the oxidation reaction of the peripheral source electrode portion (90) may be accelerated.

[0255] In contrast, in this configuration, the first distance (L1) is 10 μm or more. Therefore, a high electric field region (74) is not formed directly below the peripheral source electrode portion (90), and a high electric field is not generated in the peripheral source electrode portion (90). Therefore, oxidation of the peripheral source electrode portion (90) can be suppressed. This makes it possible to suppress the occurrence of problems caused by oxidation of the peripheral source electrode portion (90).

[0256] [Supplementary Note 1-2] The semiconductor device (1, 201) according to Supplementary Note 1-1, wherein the first distance (L1) is equal to or greater than the thickness (T1) of the semiconductor region (7).

[0257] [Appendix 1-3] The semiconductor device (1, 201) according to appendix 1-2, wherein the semiconductor region (7) includes an epitaxial layer, and the first distance (L1) is equal to or greater than the thickness (T1) of the epitaxial layer.

[0258] [Appendix 1-4] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-3, wherein a ratio (L1 / L2) of the first distance (L1) to a second distance (L2) between a first outer edge (90a) of the peripheral source electrode portion (90) and a periphery of the main surface (3) is 0.1 or more and 0.6 or less.

[0259] [Appendix 1-5] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-4, wherein the first distance (L1) is longer than a third distance (L2) between an inner edge (73b) of the termination region (73) and a first outer edge (90a) of the peripheral source electrode portion (90).

[0260] [Appendix 1-6] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-5, further comprising: a first insulating film (75) covering the termination region (73) on the main surface (3); and a second insulating film (110) arranged on the first insulating film (75) at a distance from a first outer edge (90a) of the peripheral source electrode portion (90), wherein the termination region (73) includes a coverage target portion (73c) having the second outer edge (73a) and covered by the second insulating film (110).

[0261] [Appendix 1-7] The semiconductor device (1, 201) according to Appendix 1-6 further includes a field region (72) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in a region between the termination region (73) and the periphery of the main surface (3), and a first width (W3) of the coverage target portion (73c) in the termination region (73) is equal to or smaller than a second width (W2) of the field region.

[0262] [Appendix 1-8] The semiconductor device (1, 201) according to Appendix 1-6 or Appendix 1-7 further includes a field region (72) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in a region between the termination region (73) and the periphery of the main surface (3), wherein a first width (W3) of the coverage target portion (73c) in the termination region (73) is wider than a second width (W2) of the field region.

[0263] [Supplementary Note 1-9] The semiconductor device (1, 201) according to Supplementary Note 1-7 or Supplementary Note 1-8, wherein the second width (W2) of the field region is narrower than the third width (W1) of the termination region (73).

[0264] [Appendix 1-10] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-9, wherein the chip (2) includes SiC.

[0265] [Appendix 1-11] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-10, wherein the device structure (Tr) includes: a trench-type source structure (30) located in the semiconductor region (7); and a well region (36) of a second conductivity type formed in a region along the source structure (30) in the chip (2) and extending along the source structure (30), and wherein a first depth (D1) of the termination region (73) is the same as a second depth (DW2) of the well region (36).

[0266] [Note 1-12] The impurity concentration of the termination region (73) is 1.x10 １８ cm －３ Above 5.0 x 10 ２０ cm －３ The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-11, which is as follows:

[0267] [Supplementary Note 1-13] The semiconductor device (1, 201) according to any one of Supplementary Notes 1-1 to 1-12, wherein the termination region (73) is formed on the main surface (3).

[0268] [Appendix 1-14] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-13, further comprising a source electrode (85) disposed on the inner portion of the main surface (3) and electrically connected to the device structure (Tr), and the peripheral source electrode portion (90) includes a source wiring (90) drawn out from the source electrode (85).

[0269] [Appendix 1-15] The semiconductor device (1, 201) according to any one of Appendices 1-1 to 1-14, wherein the peripheral source electrode portion (90) is an outermost electrode portion with no other electrode interposed between it and the periphery of the main surface (3).

[0270] [Supplementary Note 2-1] A chip (2) having a main surface (3), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), a device structure (Tr) having a source structure (30) and formed in the semiconductor region (7) in an inner portion of the main surface (3), a peripheral source electrode portion (90) having a first outer edge (90a), disposed on a peripheral portion of the main surface (3) and electrically connected to the source structure (30), and a termination region (73) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in the peripheral portion of the main surface (3), having a second outer edge (73a) located closer to the peripheral edge of the main surface (3) than the first outer edge (90a), the termination region (73) being electrically connected to the peripheral source electrode portion (90), A semiconductor device (1, 201) in which a first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) is equal to or greater than a thickness (T1) of the semiconductor region (7).

[0271] According to this configuration, the semiconductor device (1, 201) includes a second conductivity type termination region (73) formed on the peripheral edge of the main surface (3), and a peripheral source electrode portion (90) disposed on the peripheral edge of the main surface (3). A first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) is equal to or greater than the thickness (T1) of the semiconductor region (7).

[0272] [Supplementary Note 2-2] The semiconductor device (1, 201) according to Supplementary Note 2-1, wherein the semiconductor region (7) includes an epitaxial layer, and the first distance (L1) is equal to or greater than the thickness (T1) of the epitaxial layer.

[0273] [Supplementary Note 3-1] A chip (2) having a main surface (3), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), a device structure (Tr) having a source structure (30) and formed in the semiconductor region (7) in an inner portion of the main surface (3), a peripheral source electrode portion (90) having a first outer edge (90a), disposed on a peripheral portion of the main surface (3) and electrically connected to the source structure (30), and a termination region (73) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in the peripheral portion of the main surface (3), having a second outer edge (73a) located closer to the peripheral edge of the main surface (3) than the first outer edge (90a), the termination region (73) being electrically connected to the peripheral source electrode portion (90), A semiconductor device (1, 201) in which a ratio (L1 / L2) of a first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) to a second distance (L2) between a first outer edge (90a) of the peripheral source electrode portion (90) and the periphery of the main surface (3) is 0.1 or more and 0.6 or less.

[0274] [Supplementary Note 4-1] A chip (2) having a main surface (3), a semiconductor region (7) of a first conductivity type formed in a surface layer portion of the main surface (3), a device structure (Tr) having a source structure (30) and formed in the semiconductor region (7) in an inner portion of the main surface (3), a peripheral source electrode portion (90) having a first outer edge (90a), disposed on a peripheral portion of the main surface (3) and electrically connected to the source structure (30), and a termination region (73) of a second conductivity type formed in a surface layer portion of the semiconductor region (7) in the peripheral portion of the main surface (3), having a second outer edge (73a) located closer to the peripheral edge of the main surface (3) than the first outer edge (90a), the termination region (73) being electrically connected to the peripheral source electrode portion (90), A semiconductor device (1, 201), wherein a first distance (L1) between a first outer edge (90a) of the peripheral source electrode portion (90) and a second outer edge (73a) of the termination region (73) is longer than a third distance (L3) between an inner edge (73b) of the termination region (73) and the first outer edge (90a) of the peripheral source electrode portion (90).

[0275] 1: Semiconductor device 2: Chip 3: First main surface 4: Second main surface 5A: First side surface 5B: Second side surface 5C: Third side surface 5D: Fourth side surface 6: First semiconductor region 7: Second semiconductor region (semiconductor region) 8: First surface portion 9: Second surface portion 10A: First connection surface portion 10B: Second connection surface portion 10C: Third connection surface portion 10D: Fourth connection surface portion 11: Mesa 12: Active region 13: First end region 14: Second end region 15: Third end region 16: Fourth end region 17: Fifth end region 18: Sixth end region 19: Peripheral region 20: Body region 21: Source region 25: Gate structure 26: First trench 27 : First insulating film 28 : First buried electrode 30 : First source structure (source structure) 31 : Second trench 32 : Second insulating film 33 : Second buried electrode 35 : First well region 36 : Second well region 37 : Contact region 40 : Second source structure 41 : Third trench 42 : Third insulating film 43 : Third buried electrode 44 : Third well region 45 : Termination region 50 : Dummy gate structure 51 : Fourth trench 52 : Fourth insulating film 53 : Fourth buried electrode 55 : Third source structure 56 : Fifth trench 57 : Fifth insulating film 58 : Fifth buried electrode 59 : Fourth well region 60 : Fifth well region 65 : Fourth source structure 66 : Sixth trench 67 : Sixth insulating film 68 : Sixth buried electrode 69 : Sixth well region 70 : Outer well region 71 : Outer contact region 72 : Field region 73 : Termination region 73 a : Outer edge (second outer edge) 73 b : Inner edge 75 : First inorganic film 76 : Lower inorganic film 77 : Upper inorganic film 78 : Gate connecting electrode 79 : Sidewall wiring 79 a : Overlap portion 80 : Source opening 81 : Outer opening 82 : Gate opening 83 : Anchor opening 85 : Source electrode (peripheral source electrode portion)85a: First pad portion 85b: Second pad portion 85c: Third pad portion 86: First electrode surface 87: First electrode side wall 88: First lower electrode film 89: First upper electrode film 90: Source wiring 90a: Outer edge (first outer edge) 91: First wiring surface 92: First inner side wall 93: First outer side wall 95: Gate electrode 96: Second electrode surface 97: Second electrode side wall 98: Second lower electrode film 99: Second upper electrode film 100: Gate wiring 101: Second wiring surface 102: Second inner side wall 103: Second outer side wall 110: Second inorganic film 111: First inner covering portion 112: Second inner covering portion 113: Outer covering portion 113a : inner edge 114b : second removed portion 115 : extension portion 116 : first pad opening 117 : second pad opening 118 : anchor recess 120 : organic film 121 : first upper pad opening 122 : second upper pad opening 125 : drain electrode D1 : depth (first depth) DW1 : depth DW2 : depth (second depth) L1 : first distance L2 : second distance L3 : third distance T1 : thickness Tr : transistor structure (device structure) W1 : width W2 : width (second width) W3 : width (first width) X : first direction Y : second direction Z : vertical direction

Claims

1. A semiconductor device comprising: a chip having a main surface; a semiconductor region of a first conductivity type formed on a surface portion of the main surface; a device structure having a source structure and formed in the semiconductor region in an inner portion of the main surface; a peripheral source electrode portion having a first outer edge, disposed on a peripheral portion of the main surface and electrically connected to the source structure; and a termination region of a second conductivity type formed on a surface portion of the semiconductor region in the peripheral portion of the main surface, the termination region having a second outer edge located closer to the peripheral portion of the main surface than the first outer edge, the termination region being electrically connected to the peripheral source electrode portion, wherein a first distance between the first outer edge of the peripheral source electrode portion and the second outer edge of the termination region is 10 μm or more.

2. The semiconductor device according to claim 1, wherein said first distance is equal to or greater than a thickness of said semiconductor region.

3. The semiconductor device according to claim 2, wherein the semiconductor region includes an epitaxial layer, and the first distance is equal to or greater than a thickness of the epitaxial layer.

4. The semiconductor device according to claim 1, wherein a ratio of the first distance to a second distance between the first outer edge of the peripheral source electrode portion and the periphery of the main surface is 0.1 or more and 0.6 or less.

5. The semiconductor device of claim 1, wherein said first distance is greater than a third distance between an inner edge of said termination region and said first outer edge of said peripheral source electrode portion.

6. A semiconductor device as claimed in any one of claims 1 to 5, further comprising: a first insulating film covering the termination region on the main surface; and a second insulating film arranged on the first insulating film and spaced from the first outer edge of the peripheral source electrode portion, wherein the termination region includes a portion to be covered having the second outer edge and covered by the second insulating film.

7. The semiconductor device according to claim 6, further comprising a field region of a second conductivity type formed in a surface layer portion of the semiconductor region in a region between the termination region and a periphery of the main surface, wherein a first width of the portion to be covered in the termination region is equal to or smaller than a second width of the field region.

8. A semiconductor device as described in claim 6 or 7, further comprising a field region of a second conductivity type formed in a surface layer portion of the semiconductor region in a region between the termination region and the periphery of the main surface, wherein a first width of the portion to be covered in the termination region is wider than a second width of the field region.

9. The semiconductor device according to claim 7 or 8, wherein said second width of said field region is narrower than a third width of said termination region.

10. The semiconductor device according to any one of claims 1 to 9, wherein the chip comprises SiC.

11. A semiconductor device according to any one of claims 1 to 10, wherein the device structure includes: a trench-type source structure located in the semiconductor region; and a well region of a second conductivity type formed in a region along the source structure within the chip and extending along the source structure; and a first depth of the termination region is the same as a second depth of the well region.

12. The impurity concentration of the termination region is 1.x10 １８ cm －３ Above 5.0 x 10 ２０ cm －３ The semiconductor device according to any one of claims 1 to 11, wherein:

13. The semiconductor device according to claim 1, wherein the termination region is formed on the main surface.

14. The semiconductor device according to any one of claims 1 to 13, further comprising a source electrode disposed on the inner portion of the main surface and electrically connected to the device structure, and the peripheral source electrode portion includes a source wiring extending from the source electrode.

15. The semiconductor device according to any one of claims 1 to 14, wherein the peripheral source electrode portion is an outermost electrode portion with no other electrodes interposed between it and the periphery of the main surface.

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