Voltage glitch detector

Abstract

A voltage glitch detection circuit is implemented with a comparator in the form of an operational amplifier (op-amp) configured to function as a latch. The comparator responds to a glitch in a voltage supply by switching its output state and maintaining the new state until the circuit is reset. The comparator can be calibrated to screen out noise associated with the voltage supply. The voltage glitch detection circuit can be used to protect a chip that relies on the voltage supply from a malicious attack.

Description

VOLTAGE GLITCH DETECTORCROSS-REFERENCE TO RELATED APPLICATION

[0001] This application claims priority to U.S. Provisional Application No. 63 / 588,383, filed on October 6, 2023, and entitled “VOLTAGE GLITCH DETECTOR,” the disclosure of which is incorporated by reference herein in its entirety.TECHNICAL FIELD

[0001] This description relates to protection against attacks on semiconductor chips. More specifically, this description relates to voltage glitch detector circuits for detecting evidence of tampering with the voltage supplied to a semiconductor chip.BACKGROUND

[0002] Semiconductor chip hackers are known to interfere with power supplies to central processing units (CPUs), microprocessor chips, and systems-on-chips (SoCs), to corrupt chip performance. One example of such a chip attack is a practice called “undervolting” in which the supply voltage to a microprocessor is decreased to induce errors, expose or corrupt sensitive data, and evade chip security. The supply voltage can be accessed by the hacker either directly or via a voltage regulator. By inducing a fault, or a glitch, in the supply voltage, the process of storing sensitive data in memory can be interrupted, thereby exposing the data, or causing the data to be stored in an unintended, insecure, location. Another example of a voltage glitch attack involves altering the power source of a passive chip in a smart card, e.g., a chip-containing credit card or bank card used in financial transactions. During a transaction, the smart card connects to a terminal that supplies power to the internal chip in the smart card, so that data can be exchanged. If the terminal is hacked to alter the supply voltage, data can be extracted from the smart card chip. Software updates and security patches are ineffective against such hardware attacks on supply voltage signals.SUMMARY

[0003] The present disclosure describes devices and methods for detecting irregularities in voltage supply lines for use in powering computer chips.

[0004] In some aspects, the techniques described herein relate to a supply voltage sensor, including: a voltage comparison circuit having a first input terminal, a second input terminal, and an output terminal; a voltage supply line configured to provide power to the voltage comparison circuit; and a filter coupled to the voltage supply line and configured to generate a filtered voltage supply signal that is provided to the first input terminal.

[0005] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the filter is a low pass filter.

[0006] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the low pass filter includes a resistor and a capacitor.

[0007] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the voltage comparison circuit is configured with a positive feedback loop that couples the output of the voltage comparison circuit to the second input terminal to create a latch.

[0008] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein a PSRR of the voltage comparison circuit is selected to increase sensitivity to noise on the voltage supply line.

[0009] In some aspects, the techniques described herein relate to a supply voltage sensor, further including a load configured to receive a signal from the voltage comparison circuit.

[0010] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the voltage comparison circuit is further configured to deliver power to the load.

[0011] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the voltage comparison circuit is implemented using an operational amplifier (op-amp).

[0012] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the op-amp is configured to detect an irregularity in the voltage supply line.

[0013] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the voltage comparison circuit is implemented using a comparator.

[0014] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the voltage comparison circuit is implemented using an operational transconductance amplifier (OTA).

[0015] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the output signal is high when a signal at the second input terminal exceeds a signal at the first input terminal.

[0016] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein the output signal switches from high to low when a signal at the first input terminal exceeds a signal at the second input terminal.

[0017] In some aspects, the techniques described herein relate to a supply voltage sensor, wherein, after the output signal switches from high to low, the output signal remains low until the voltage sensor is reset.

[0018] In some aspects, the techniques described herein relate to a system, including: a power supply configured to produce a voltage supply line signal; a filter configured to receive the voltage supply line signal and to produce a delayed voltage supply line signal therefrom; a load configured to receive power from the voltage supply line signal; and a supply voltage sensor coupled between the power supply and the load, the supply voltage sensor configured to compare the voltage supply line signal with the delayed voltage supply line signal, and to block power delivery to the load when an irregularity occurs in the power supply line signal.

[0019] In some aspects, the techniques described herein relate to a system, wherein the filter includes a single low pass filter.

[0020] In some aspects, the techniques described herein relate to a system, wherein the load includes at least one of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a system-on-chip, an accelerator, a data parallel accelerator, or a controller.

[0021] In some aspects, the techniques described herein relate to a system, wherein the supply voltage sensor is implemented as an operational amplifier (op-amp) having a positive input and a negative input.

[0022] In some aspects, the techniques described herein relate to a system, wherein the op-amp includes self-calibration to reduce a voltage offset between the positive input and the negative input.

[0023] In some aspects, the techniques described herein relate to a method of detecting an irregularity in a voltage supply signal, the method including: using the voltage supply signal to power a comparator; receiving the voltage supply signal at a positive terminal of the comparator; filtering the voltage supply signal to produce a delayed voltage supply signal; receiving the delayed voltage supply signal at a negative terminal of thecomparator; comparing the voltage supply signal with the delayed voltage supply signal to detect a voltage difference between the positive terminal and the negative terminal, indicating a voltage supply irregularity; delivering the voltage supply signal when no voltage supply irregularity is indicated; and blocking the voltage supply signal when a voltage supply irregularity is indicated.

[0024] In some aspects, the techniques described herein relate to a method, wherein blocking the voltage supply signal protects a downstream circuit from damage due to the voltage supply irregularity.

[0025] In some aspects, the techniques described herein relate to a method, wherein the downstream circuit includes a processor, and blocking the voltage supply signal when a voltage supply irregularity is detected ceases operation of the processor.BRIEF DESCRIPTION OF THE DRAWINGS

[0026] FIG. 1 is detailed circuit schematic diagram of a voltage glitch detector, according to a first implementation of the present disclosure.

[0027] FIG. 2 is a timing diagram showing signals of the voltage glitch detector shown in FIG. 1 as a function of time, according to some implementations of the present disclosure.

[0028] FIG. 3 is a circuit schematic diagram of a voltage glitch detector according to a second implementation of the present disclosure.

[0029] FIG. 4 is a block diagram of a system for shielding a load from a voltage glitch, according to some implementations of the present disclosure.

[0030] FIG. 5 is a flow diagram illustrating a method of detecting a glitch in a voltage supply signal, according to some implementations of the present disclosure.

[0031] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying figures. It is noted that, in accordance with common practice in the industry, various features are not necessarily drawn to scale. Dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion. In the drawings, like reference symbols may indicate like and / or similar components (elements, structures, etc.) in different views. The drawings illustrate generally, by way of example, but not by way of limitation, various implementations discussed in the present disclosure. Reference symbols shown in one drawing may not berepeated for the same, and / or similar elements in related views. Reference symbols that are repeated in multiple drawings may not be specifically discussed with respect to each of those drawings but are provided for context between related views. Also, not all like elements in the drawings are specifically referenced with a reference symbol when multiple instances of an element are illustrated.DETAILED DESCRIPTION

[0032] Protection of a semiconductor chip against hardware attacks, such as undervolting or other glitch attacks, begins with detecting irregularities in the supply voltage signal provided to the chip. Detection of such irregularities can be accomplished using a supply voltage sensor in the form of a voltage glitch detection circuit that compares an expected voltage level to the actual voltage level received by the chip. In some implementations, the expected voltage level can be derived from the supply voltage signal itself by applying a filter to screen out fast timescale glitches, so that the filtered signal can be compared to the raw signal that includes the fast timescale glitches. Thus, a reference voltage is not needed. A voltage glitch detection circuit therefore can include a filter and a comparator that compares the raw voltage supply signal to the filtered voltage supply signal. When a glitch occurs, the comparator will detect a difference between the actual supply voltage signal and the filtered signal.

[0033] FIG. 1 is an example circuit diagram of a voltage glitch detection circuit 100 for use as a supply voltage sensor, in accordance with some implementations of the present disclosure. The voltage glitch detection circuit 100 includes a voltage supply signal 101, a voltage comparison circuit 102, and a filter 104, coupled as described below. The voltage comparison circuit 102 can be in the form of, for example, a comparator, an operational amplifier (op-amp), or an operational transconductance amplifier (OTA).

[0034] The voltage supply signal 101 supplies a voltage VDD to the voltage comparison circuit 102. In some implementations, the value of VDD can be, for example, 5V or 12 V. The voltage supply signal 101 is also supplied to the filter 104.

[0035] The filter 104 receives, as input, the voltage supply signal 101 and provides, as output, a filtered voltage supply signal 105. In some implementations, the filter 104 is a single bandpass filter, e.g., an RC-low pass filter that includes a resistor R and a capacitor C. The filter 104 can be tuned, by selecting the R and C values, to filter out signals having frequencies outside a prescribed frequency band. The voltage VDD supplied to the filter104 is reduced by a resistor R1 coupled in a voltage divider configuration with the resistor R.

[0036] The voltage comparison circuit 102 compares the voltage supply signal 101 with the filtered voltage supply signal 105 to detect an irregularity in the voltage supply signal 101, which will not appear in the filtered voltage supply signal 105. Some existing comparators compare an input signal against a reference signal. Instead, by comparing the voltage supply signal 101 against the filtered voltage supply signal 105, the voltage comparison circuit 102 does not need a reference signal.

[0037] FIG. 1 further illustrates internal details of the voltage comparison circuit 102 within the voltage glitch detection circuit 100, in accordance with an implementation of the present disclosure. In some implementations, the voltage comparison circuit 102 includes a ground connection 112 and four terminals: a power input terminal 114, a negative input terminal 116, a positive input terminal 118, and an output terminal 120. In the voltage glitch detection circuit 100, the voltage supply signal 101 is coupled to the power input terminal 114. The filtered voltage supply signal 105 is coupled to the negative input terminal 116. An output signal 122 from the output terminal 120 of the voltage comparison circuit 102 is fed back to the positive input terminal 118 through a resistor R2. The positive input terminal 118 is grounded through a resistor R3.

[0038] The voltage comparison circuit 102, e.g., implemented with an op-amp compares signals at the negative input terminal 116 and the positive input terminal 118. When the positive input terminal 118 has a higher voltage than the negative input terminal 116, the output signal 122 is set to a high state, e.g., equal to the supply voltage at the power input terminal 114. Otherwise, the output signal 122 is set to a low state, e.g., the ground state of 0 V. A glitch in the voltage supply signal 101 can be detected by monitoring the output signal 122 for a sudden change between a high state and a low state. Additionally, or alternatively, a glitch in the voltage supply signal 101 can be detected by monitoring the output signal 122 for a sustained low state.

[0039] FIG. 2 is a timing diagram 200 showing behavior of four signals in the voltage glitch detection circuit 100: the voltage supply line signal VDD, the input to the voltage comparison circuit 102 at the positive input terminal 118, the input to the voltage comparison circuit 102 at the negative input terminal 116, and the output signal 122 of the voltage comparison circuit 102. The timing diagram 200 is a plot of voltage as a function of time, t. The voltage supply signal 101 starts at a level of VDD and experiences a glitch 210 that temporarily changes the voltage supply to a level below VDD. An irregularity inthe supply voltage, such as the glitch 210, may be characteristic of an attempt to undervolt a chip that receives power from a power supply that provides the voltage supply signal, VDD.

[0040] In the timing diagram 200, the voltage on the positive input terminal 118 tracks the voltage supply signal 101, albeit at absolute voltage values that are a fraction of the voltage supply signal 101, because of the voltage divider formed by resistors, R2 and R3. The negative input terminal 116 is tied to the filtered voltage supply signal 105, which remains substantially constant, in spite of the glitch 210. The values of the resistors R1 and R can be selected in relation to the values of the resistors R2 and R3, such that, in a steady state (i.e., before the glitch occurs) the voltage level at the negative input terminal 116 is lower than the voltage level at the positive input terminal 118. Then, when the glitch occurs and the value of VDD decreases, the RC filter maintains the value of the filtered voltage supply signal 105 that is provided to the negative input terminal 116 of the voltage comparison circuit 102 close to the original steady state value of the voltage level at the negative input terminal 116. Because of this, the slowly-varying signal provided to the negative input terminal 116 can be compared to the quickly-varying signal that is provided to positive input terminal 118 to detect a voltage glitch.

[0041] It is noted that the maximum voltage at the output terminal 120 is determined by VDD, SO that as VDD decreases, the maximum output of the voltage comparison circuit 102 in its high state decreases as well.

[0042] The output signal 122 of the voltage comparison circuit 102 remains high as long as the voltage at the positive input terminal 118 exceeds the voltage at the negative input terminal 116. When there is not a glitch 210, the output signal 122 stays high. However, at time t=to, the glitch 210, which occurs on VDD, causes the voltage level at the output terminal to drop, which is then fed back to the positive input terminal 118, causing the voltage level at the positive input terminal 118 to drop below the voltage level at the negative input terminal 116. Such a drop in the voltage level would be consistent with an undervolting attack, or with significant fluctuations in the voltage supply signal 101. When this change occurs, the output signal 122 suddenly transitions from the lowered VDD (glitch) value to zero Even when the voltage level of VDD is restored following the glitch, the output signal 122 remains low because of the feedback loop - once the output signal 122 is low, it pulls the voltage at the positive input terminal 118 down to zero, which is lower than the voltage at the negative input terminal 116. Consequently, the output signal122 will remain locked in a low state indefinitely, until the voltage glitch detection circuit 100 is reset.

[0043] The voltage glitch detection circuit 100 therefore functions as a latch circuit because it responds immediately to a change in the input voltage supply signal 101 and retains its state until a reset is initiated, e.g., by resetting the power or by applying an external reset signal. The output signal 122 can then be fed to a downstream device, e.g., a load, that is also powered by VDD, as a warning signal, or as a signal that automatically disables the downstream device, e.g., by blocking transmission of the voltage supply signal.

[0044] It is desirable for the voltage glitch detection circuit 100 to ignore minor fluctuations, or noise, in the voltage supply signal 101 that do not constitute a glitch or other irregularity caused by a rogue attack. Sensitivity of the voltage glitch detection circuit 100 to noise can be increased during a design phase of the voltage glitch detection circuit 100 by selecting an internal property of the voltage comparison circuit 102 called a power supply rejection ratio, or PSRR. The PSRR is defined as a ratio of a change in input offset voltage to a change in supply voltage. The input offset voltage is the voltage level of the output signal 122 when the two input terminals are connected, so that the input differential is 0 V. In some implementations, fluctuations in the supply voltage can be on the order of 0.1-1.0 V, while the input offset voltage is on the order of microvolts. In some implementations, the PSRR of the voltage comparison circuit 102 can be selected, e.g., calibrated, so that the output signal 1222 does not change state in the presence of noise on the voltage supply signal 101 but does change state due to a glitch. In some implementations, the voltage comparison circuit 102 can be provided with a selfcalibration capability. In some implementations, the voltage comparison circuit 102 can be custom-designed and / or manufactured to have a PSRR that is suitable for use as a glitch detector, without reacting to noise levels.

[0045] FIG. 3 is a schematic of a voltage glitch detection circuit 300 for use as a supply voltage sensor, in accordance with a second implementation of the present disclosure. The voltage glitch detection circuit 300 includes the voltage supply signal 101, the filter 104, and a voltage comparison circuit 302 having an inverted output signal 312.

[0046] The voltage glitch detection circuit 300 functions as a latch with an inverted output. Like the voltage glitch detection circuit 100, the voltage glitch detection circuit 300 responds immediately to a change in the voltage supply signal 101. The voltage glitch detection circuit 300 provides an output signal 122 and an inverted output signal 312.

[0047] As illustrated in FIG. 3, the filter 104 is coupled to the voltage supply line VDD to generate the filtered voltage supply signal 105, as in the voltage glitch detection circuit 100. The voltage glitch detection circuit 300 further resembles the voltage glitch detection circuit 100, except that the voltage comparison circuit 302 is substituted for the voltage comparison circuit 102. In the example shown in FIG. 3, the voltage comparison circuit 302 is implemented with an op-amp 304 followed by an inverter 306. Alternatively, the voltage comparison circuit 302 can be implemented with an operational transconductance amplifier followed by the inverter 306. The output signal 122 from the op-amp 304 is inverted to produce the inverted output signal 312. In the voltage comparison circuit 302, the negative input terminal 116 and the positive input terminal 118 of the op-amp 304 are reversed so that, the filtered voltage supply signal 105 is coupled to the positive input terminal 118 and the inverted output signal 312 of the comparator 302 is fed back to the negative input terminal 116. The combination of the op-amp 304 and the inverter 306, coupled as shown in FIG. 3, is functionally similar to the voltage comparison circuit 102, except that the PSRR is reduced in the voltage comparison circuit 302. The reduced PSRR can be advantageous because it allows for a faster response time so that short timescale glitches can be detected.

[0048] The timing diagram 200 in FIG. 2 shows the behavior of the voltage glitch detection circuit 300, whenthe inverted output signal 312 is substituted for the output signal 122. The inverted output signal 312 of the voltage glitch detection circuit 300 can be fed to a downstream device that is powered by VDD, as a warning signal, or as a signal that automatically disables the downstream device, e.g., by blocking transmission of the voltage supply signal.

[0049] FIG. 4 is a block diagram of a system 400 that includes a supply voltage sensor 402 configured to protect a load 404, in accordance with some implementations of the present disclosure. The supply voltage sensor 402, together with the supply voltage VDD and the filter 104, constitute a voltage glitch detection circuit, e.g. the voltage glitch detection circuit 100 or the voltage glitch detection circuit 300. In some implementations, the load 404 can include at least one microprocessor configured as, for example, a central processing unit (CPU), a graphics processing unit (GPU), a general purpose graphics processing unit (GPGPU), an accelerator, a data parallel accelerator, a system-on-chip (SOC), a controller, or other processor-based load.

[0050] The supply voltage sensor 402, implemented as e.g., the voltage comparison circuit 102 or the comparator 302, can be installed in-line with the voltage supply signal101 feeding power to the load 404, as shown in FIG. 4 to sense an irregularity, or glitch, in the voltage supply signal 101. The supply voltage sensor 402 compares the voltage supply signal 101 with the filtered voltage supply signal 105 to detect a glitch in the voltage supply signal 101. When the output signal 122 of the voltage glitch detection circuit 100, or the inverted output signal 312 of the voltage glitch detection circuit 300 responds to the glitch 210 by switching to a low value, e.g., 0 V, delivery of power to the power input of the load 404 will effectively be blocked, ceasing operation of the load 404. Alternatively, the output of the supply voltage sensor can be combined with the voltage supply signal 101 so as to gate delivery of the voltage supply signal 101 to the load 404.

[0051] FIG. 5 is a flow chart illustrating a method 500 for detecting an irregularity in a voltage supply signal using e.g., the system 400 equipped with a voltage glitch detection circuit, e.g., the voltage glitch detection circuit 100 or the voltage glitch detection circuit 300, in accordance with some implementations of the present disclosure. Operations 502- 510 of the method 500 can be carried out to detect a voltage glitch, according to some implementations as described above with reference to FIGs 1 and 2. Operations of the method 500 can be performed in a different order, or not performed, depending on specific applications. It is noted that the method 500 may not always detect an irregularity in a voltage supply signal. Accordingly, it is understood that additional processes can be provided before, during, or after method 500, and that some of these additional processes may be briefly described herein.

[0052] At 502, the method 500 includes using a voltage supply signal 101 to power a comparator, e.g., the voltage comparison circuit 102 or the comparator 302, in accordance with some implementations of the present disclosure. When the comparator is implemented as the voltage comparison circuit 102, the voltage supply signal 101 can be coupled to the power input terminal 114 of the op-amp 110, as well as to the filter 104.

[0053] At 504, the method 500 further includes receiving the voltage supply signal 101 at the positive input terminal 118 of the voltage comparison circuit 102, in accordance with some implementations of the present disclosure. In some implementations, receiving the voltage supply signal 101 at the positive input terminal 118 includes receiving the voltage supply signal 101 indirectly at the positive input terminal 118 via the output signal 122. Since the output signal 122 initially tracks the voltage supply signal 101, the positive input terminal 118 is essentially receiving VDD. However, instead of coupling the voltage supply signal 101 directly to the positive input terminal 118, the output signal 122 is fed back to the positive input terminal 118. (It is noted that in conventional implementations ofa comparator, e.g., an op-amp, the output signal 122 is fed back to the negative input terminal 116, not the positive input terminal 118.)

[0054] At 506, the method 500 further includes filtering the voltage supply signal 101 to produce a delayed voltage supply signal e.g., filtered voltage supply signal 105, in accordance with some implementations of the present disclosure. In some implementations, the filter 104 is an RC low pass filter as shown in FIG. 1 and FIG. 3. The filter 104 produces a filtered signal 105 that is also delayed with respect to the voltage supply signal 101.

[0055] At 508, the method 500 further includes receiving the delayed voltage supply signal 105 at the negative input terminal 116 of the comparator 302 or voltage comparison circuit 102, in accordance with some implementations of the present disclosure. As shown in FIG. 1, the filtered voltage supply signal 105 is supplied as input to the negative input terminal 116 of the voltage comparison circuit 102 of the comparator, e.g., the voltage comparison circuit 102 or the comparator 302.

[0056] At 510, the method 500 further includes comparing the voltage supply signal 101 with the delayed filtered voltage supply signal 105, in accordance with some implementations of the present disclosure. That is, the voltage comparison circuit 102 compares VDD with a filtered version of VDD. If a glitch occurs in VDD„ the glitch will not pass through the filter 104. Thus, there will be a difference between the two inputs of the voltage comparison circuit 102, which will cause a sudden change in the output signal 122.

[0057] Even if the filtered voltage supply signal 105 does not completely filter out the glitch, a delay inherent in the filter 104, e.g., when implemented as an RC low pass filter, will ensure that a glitch that is present in the filtered voltage supply signal 105 does not coincide with the glitch in the voltage supply signal 101, and therefore the voltage comparison circuit 102 will still sense a difference in the two signals. The glitch in the voltage supply signal 101 will occur first, and therefore the output signal 122 will still transition from high to low and remain low, consistent with the timing sequence described above with respect to FIG. 2.

[0058] The comparison can be made by the voltage comparison circuit 102 or the comparator 302, implemented using an op-amp. The op-amp outputs a high value when the voltage at the positive input terminal 118 exceeds the voltage at the negative input terminal 116. When that condition is no longer met, e.g., when a glitch occurs in the voltage supply VDD, the voltage supply signal 101 is lowered with respect to the filtered voltage supply signal 105, thus causing the output signal 122 of the voltage comparisoncircuit 102 to switch suddenly to a zero value, indicating the presence of a voltage irregularity on the power supply line. The output signal 122 then remains at the low value until the comparator is reset. When the output signal 122 drops to 0 V, the feedback connection ties the positive input terminal 118 to 0 V as well, which is below the voltage level of the negative input terminal 116. Thereafter, subsequent comparison of the two inputs can only result in the output signal 122 being low and prohibited from returning to a high state.

[0059] At 512, the method 500 further includes delivering the voltage supply signal when no irregularity is indicated, in accordance with some implementations of the present disclosure. The output signal 122 and / or the inverted output signal 312 can be used to gate delivery of the voltage supply signal 101 to a downstream device, e.g., a processor that relies on the voltage supply VDD and is sensitive to irregularities thereof. As long as the output signal 122 is high or the inverted output signal 312 is low, the voltage supply signal 101 can be delivered to the processor.

[0060] At 514, the method 500 further includes blocking the voltage supply signal 101 when an irregularity is indicated, in accordance with some implementations of the present disclosure. When an irregularity occurs in the voltage supply signal 101, the output signal 122 will suddenly switch from a high state to a low state, as described above with respect to FIG. 2, a low output signal 122 (or a high inverted output signal 312) can be used to block the voltage supply signal 101 so it is not available to power a downstream device (load), e.g., to a downstream component such as a microprocessor-based device, thereby effectively ceasing operation of the load. As shown in FIG. 4, by blocking the voltage supply signal 101, a low output signal 122 can prevent data transmission to, or through, the load 404, or a low output signal 122 can trigger a shut-down of the load 404, thus protecting the load 404 from damage, e.g., data corruption, caused by the glitch 210. In some implementations, blocking the voltage supply signal 101 can include switching to an alternate or back-up power supply that can replace the system 400 as the power input to the load 404.

[0061] As described above, various implementations of a voltage glitch detector are presented, based on a voltage comparison circuit that functions as a latch. The voltage comparison circuit may compare a supply line signal with a filtered / delayed version of the supply line signal, to trigger a sudden change in output voltage. The output of each circuit can be monitored to detect the sudden change in output voltage that responds to an irregularity in the supply voltage that does not appear in the filtered signal. The voltageglitch detector can be used to protect an external device that relies on the supply line voltage as a power source and that may be sensitive to alterations in the supply voltage signal.

[0062] It will be understood that, in the foregoing description, when an element, such as a layer, a region, or a substrate, is referred to as being on, connected to, electrically connected to, coupled to, or electrically coupled to another element, it may be directly on, connected or coupled to the other element, or one or more intervening elements may be present. In contrast, when an element is referred to as being directly on, directly connected to or directly coupled to another element or layer, there are no intervening elements or layers present. Although the terms directly on, directly connected to, or directly coupled to may not be used throughout the detailed description, elements that are shown as being directly on, directly connected or directly coupled can be referred to as such. The claims of the application may be amended to recite exemplary relationships described in the specification or shown in the figures.

[0063] As used in this specification, a singular form may, unless definitely indicating a particular case in terms of the context, include a plural form. Spatially relative terms (e.g., over, above, upper, under, beneath, below, lower, top, bottom, and so forth) are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. In some implementations, the relative terms above and below can, respectively, include vertically above and vertically below. In some implementations, the term adjacent can include laterally adjacent to or horizontally adjacent to.

[0064] Some implementations may be implemented using various semiconductor processing and / or packaging techniques. Some implementations may be implemented using various types of semiconductor device processing techniques associated with semiconductor substrates including, but not limited to, for example, silicon (Si), silicon carbide (SiC), gallium arsenide (GaAs), gallium nitride (GaN), and / or so forth.

[0065] While certain features of the described implementations have been illustrated as described herein, many modifications, substitutions, changes, and equivalents will now occur to those skilled in the art. For instance, features illustrated with respect to one implementation can, where appropriate, also be included in other implementations. It is, therefore, to be understood that the appended claims are intended to cover all such modifications and changes as fall within the scope of the implementations. It should be understood that they have been presented by way of example only, not limitation, andvarious changes in form and details may be made. Any portion of the apparatus and / or methods described herein may be combined in any combination, except mutually exclusive combinations. The implementations described herein can include various combinations and / or sub-combinations of the functions, components and / or features of the different implementations described.

Claims

CLAIMS1. A supply voltage sensor, comprising: a voltage comparison circuit having a first input terminal, a second input terminal, and an output terminal; a voltage supply line configured to provide power to the voltage comparison circuit; and a filter coupled to the voltage supply line and configured to generate a filtered voltage supply signal that is provided to the first input terminal.

2. The supply voltage sensor of claim 1, wherein the filter is a low pass filter.

3. The supply voltage sensor of claim 2, wherein the low pass filter includes a resistor and a capacitor.

4. The supply voltage sensor of any one of the preceding claims, wherein the voltage comparison circuit is configured with a positive feedback loop that couples the output terminal of the voltage comparison circuit to the second input terminal to function as a latch.

5. The supply voltage sensor of any one of the preceding claims, wherein a PSRR t of the voltage comparison circuit is selected to increase sensitivity to noise on the voltage supply line.

6. The supply voltage sensor of any one of the preceding claims, further comprising a load configured to receive a signal from the voltage comparison circuit.

7. The supply voltage sensor of claim 6, wherein the voltage comparison circuit is further configured to deliver power to the load.

8. The supply voltage sensor of any one of the preceding claims, wherein the voltage comparison circuit is implemented using an operational amplifier (op-amp).

9. The supply voltage sensor of any one of the preceding claims, wherein the voltage comparison circuit is implemented with an operational transconductance amplifier.

10. The supply voltage sensor of any one of the preceding claims, wherein the voltage comparison circuit is implemented with a comparator.

11. The supply voltage sensor of any one of the preceding claims, wherein the voltage comparison circuit is configured to detect an irregularity in the voltage supply line.

12. The supply voltage sensor of any one of the preceding claims, wherein an output signal is high when a signal at the second input terminal exceeds a signal at the first input terminal.

13. The supply voltage sensor of any one of the preceding claims, wherein an output signal switches from high to low when a signal at the first input terminal exceeds a signal at the second input terminal.

14. The supply voltage sensor of claim 13, wherein, after the output signal is configured to switch from high to low, the output signal remains low until the supply voltage sensor is reset.

15. A system, comprising: a power supply configured to produce a voltage supply line signal; a filter configured to receive the voltage supply line signal and to produce a delayed voltage supply line signal therefrom; a load configured to receive power from the voltage supply line signal; and a supply voltage sensor coupled between the power supply and the load, the supply voltage sensor configured to compare the voltage supply line signal with the delayed voltage supply line signal, and to block power delivery to the load when an irregularity occurs in the voltage supply line signal.

16. The system of claim 15, wherein the filter includes a single low pass filter.

17. The system of any one of claims 15-16, wherein the load includes at least one of a central processing unit, a graphics processing unit, a general purpose graphics processing unit, a system-on-chip, an accelerator, a data parallel accelerator, or a controller.

18. The system of any one of claims 15-17, wherein the supply voltage sensor is implemented as an operational amplifier (op-amp) having a positive input and a negative input.

19. The system of claim 18, wherein the op-amp includes self-calibration to reduce a voltage offset between the positive input and the negative input.

20. A method of detecting an irregularity in a voltage supply signal, the method comprising: using the voltage supply signal to power a comparator; receiving the voltage supply signal at a positive terminal of the comparator; filtering the voltage supply signal to produce a delayed voltage supply signal; receiving the delayed voltage supply signal at a negative terminal of the comparator; comparing the voltage supply signal with the delayed voltage supply signal to detect a voltage difference between the positive terminal and the negative terminal, indicating a voltage supply irregularity; delivering the voltage supply signal when no voltage supply irregularity is indicated; and blocking the voltage supply signal when a voltage supply irregularity is indicated.

21. The method of claim 20, wherein blocking the voltage supply signal protects a downstream circuit from damage due to the voltage supply irregularity.

22. The method of claim 21, wherein the downstream circuit includes a processor, and blocking the voltage supply signal when a voltage supply irregularity is detected ceases operation of the processor.

Images