Preparation method for flexible three-dimensional integrated circuit structure, phase inverter and integrated circuit

Abstract

The present application relates to a preparation method for a flexible three-dimensional integrated circuit structure, a phase inverter and an integrated circuit. The method comprises: forming a first substrate; forming a P-type transistor on the first substrate; depositing a second gate dielectric layer of an N-type transistor on the P-type transistor; forming a second channel region of the N-type transistor on the second gate dielectric layer; etching by means of a second wet etching method to expose a first source electrode and a first drain electrode of the P-type transistor; and forming a second source electrode and a second drain electrode of the N-type transistor on two sides of the second channel region, respectively, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below to form an output end of a phase inverter. According to the phase inverter and the integrated circuit prepared by means of the method of the present application, high flexibility of the phase inverter and the integrated circuit are kept, and the technical effects of ensuring the stability performance of the phase inverter and the integrated circuit, and reducing the time delay are achieved.

Description

Preparation method of flexible three-dimensional integrated circuit structure, inverter and integrated circuit Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a method for preparing a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit. Background Art

[0002] The rapid development of flexible electronics based on CMOS technology has accelerated the advent of the Internet of Things (IoT). Flexible CMOS electronics are widely used in health monitoring, human-computer interaction, and wearable electronics. In most flexible product applications, CMOS integrated circuits are required to possess both high integration density and high mechanical flexibility.

[0003] For the implementation of high-density integrated circuits, single-layer stacked three-dimensional structures are widely used. Compared to traditional planar circuit structures, this structure offers the advantages of high integration density and reduced parasitic effects of interconnect lines. However, traditional three-dimensional structures contain interconnecting wires connecting different layers. These interconnects are formed by opening holes in the dielectric layers of the upper and lower transistor layers and depositing metal in the holes. These interconnects cannot withstand the high mechanical stress when the flexible circuit is bent. Therefore, the mechanical flexibility of the integrated circuit formed based on this structure is greatly reduced, reducing the performance of the integrated circuit formed by this structure.

[0004] In order to solve the above problems, it is necessary to propose a new method for preparing a flexible three-dimensional integrated circuit structure, an inverter and an integrated circuit.

[0005] Summary of the Invention

[0006] In response to the technical problems existing in the prior art, the present application provides a method for preparing a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit to solve the technical problems existing in the prior art, such as the inability of interconnect lines in the integrated circuit structure to withstand high mechanical stress when the flexible circuit is bent, the low flexibility of the integrated circuit structure, and the resulting significant reduction in the performance of the integrated circuit structure.

[0007] In a first aspect, the present application provides a method for preparing a flexible three-dimensional integrated circuit structure, the method comprising:

[0008] providing a first substrate;

[0009] Spin-coating metallic carbon nanotubes as a material for forming source and drain electrodes on a first substrate to pattern-form a first source electrode and a first drain electrode of a P-type transistor, spin-coating semiconducting carbon nanotubes as a material for forming a channel region on the first substrate between the first source electrode and the first drain electrode to pattern-form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, and depositing a gate layer on the first gate dielectric layer and patterning to form a gate of the P-type transistor;

[0010] Depositing an oxide insulating layer on the P-type transistor, the oxide insulating layer serving as a second gate dielectric layer of the N-type transistor;

[0011] Depositing metal oxide a-IGZO on the second gate dielectric layer by DC magnetron sputtering to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside the second channel region by a first wet etching method to form a second channel region of the N-type transistor;

[0012] Etching the first gate dielectric layer and the second gate dielectric layer by a second wet etching method to expose the first source electrode and the first drain electrode of the P-type transistor; and

[0013] A second source electrode and a second drain electrode of the N-type transistor are formed on both sides of the second channel region, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below to form an output end of the inverter.

[0014] In some embodiments, the DC magnetron sputtering method uses a sputtering power of 120 W and a sputtering time of 200 s to achieve a metal oxide a-IGZO channel layer with a thickness of 20 nm;

[0015] The first wet etching method uses a solution of 36% dilute hydrochloric acid and deionized water in a ratio of 50:1.

[0016] In some embodiments, a flexible material solution is spin-coated on a supporting substrate comprising glass, and the flexible material solution on the supporting substrate is dried and solidified to form a thin film, thereby forming a first substrate.

[0017] In some embodiments, the first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of flexible materials.

[0018] In some embodiments, the first substrate includes flexible PEN, PET, or PI.

[0019] In some embodiments, the material forming the first channel region of the P-type transistor includes at least semiconductor carbon nanotubes, the material forming the first source electrode and the first drain electrode includes at least metallic carbon nanotubes, the material forming the gate includes at least metal ITO, and the material forming the first gate dielectric layer and the second gate dielectric layer includes at least a mixed material of Al2O3 and PI.

[0020] In some embodiments, the gate of the P-type transistor is formed by photolithography, and the patterning method includes first forming a pattern with photoresist, then depositing ITO, and then removing the photoresist to form the gate by a stripping method.

[0021] In a second aspect, the present application provides a flexible three-dimensional inverter, comprising:

[0022] a first substrate;

[0023] A P-type transistor located on a first substrate, the P-type transistor comprising a first source electrode, a first drain electrode, a first channel region, a first gate dielectric layer, and a gate, wherein the first source electrode and the first drain electrode are respectively located on either side of the first channel region, and the first gate dielectric layer and the gate are sequentially located on the first source electrode, the first channel region, and the first drain electrode; wherein the first channel region of the P-type transistor is formed of at least a semiconducting carbon nanotube, and the first source electrode and the first drain electrode are formed of at least a metallic carbon nanotube;

[0024] an oxide insulating layer located on the P-type transistor, the oxide insulating layer being a second gate dielectric layer of the N-type transistor;

[0025] a second channel region of the N-type transistor located on the second gate dielectric layer;

[0026] The second source electrode and the second drain electrode of the N-type transistor located on both sides of the second channel region, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below, form the output end of the inverter.

[0027] In some embodiments, the gate is formed of at least a material including metal ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of at least a mixed material including Al 2 O 3 and PI.

[0028] In a third aspect, the present application provides an integrated circuit comprising any flexible three-dimensional inverter as described above.

[0029] The present application provides a method for preparing a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit. The method proposes a new design structure that can simultaneously achieve high mechanical flexibility while ensuring high density of the integrated circuit. Even after bending under harsh bending conditions, the electrical characteristics of the inverter prepared by the method for preparing the flexible three-dimensional integrated circuit structure do not significantly decrease, thereby maintaining the high flexibility of the inverter and the integrated circuit, achieving the technical effect of ensuring stable performance of the inverter and the integrated circuit and reducing delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Below, the preferred embodiments of the present application will be further described in detail with reference to the accompanying drawings, wherein:

[0031] 1A-1F are schematic structural diagrams of a flexible three-dimensional integrated circuit structure according to an embodiment of the present application;

[0032] FIG2 is a flowchart of a method for preparing a flexible three-dimensional integrated circuit structure according to an embodiment of the present application;

[0033] 3A-3I are schematic diagrams of a three-dimensional structure of a flexible three-dimensional integrated circuit structure according to an embodiment of the present application;

[0034] FIG4 is a second flow chart of a method for preparing a flexible three-dimensional integrated circuit structure according to an embodiment of the present application;

[0035] FIG5 is a schematic structural diagram of a flexible three-dimensional inverter according to an embodiment of the present application; and

[0036] FIG6A is a diagram showing a bent state of a flexible inverter fabricated by a method for fabricating a flexible three-dimensional integrated circuit structure according to an embodiment of the present application; and

[0037] FIG6B is a performance diagram of a flexible inverter fabricated by a method for fabricating a flexible three-dimensional integrated circuit structure according to an embodiment of the present invention under different bending conditions. DETAILED DESCRIPTION

[0038] To make the purpose, technical solutions, and advantages of the embodiments of this application more clear, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0039] In the detailed description that follows, reference may be made to the various drawings that form part of this application and illustrate specific embodiments of the present application. In the drawings, similar reference numerals describe substantially similar components in different figures. Each specific embodiment of the present application is described below in sufficient detail to enable a person of ordinary skill in the art to implement the technical solutions of the present application. It should be understood that other embodiments may be utilized or that structural, logical, or electrical changes may be made to the embodiments of the present application.

[0040] Technologies, methods, and devices known to persons of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, such technologies, methods, and devices should be considered part of the specification. The lines between the elements in the drawings are merely for ease of explanation, indicating that at least the elements at both ends of the line are communicating with each other, and are not intended to limit the unconnected elements from being unable to communicate. Furthermore, the number of lines between two elements is intended to indicate at least the number of signals involved in the communication between the two elements or at least the number of outputs provided, and is not intended to limit the two elements to communicating only with the signals shown in the figure.

[0041] A transistor may refer to a transistor of any structure, such as a field effect transistor (FET) or a bipolar junction transistor (BJT). When the transistor is a field effect transistor, it may be hydrogenated amorphous silicon, metal oxide, low temperature polysilicon, organic transistor, etc., depending on the channel material. Depending on whether the carrier is an electron or a hole, it can be divided into an N-type transistor and a P-type transistor, wherein the control electrode refers to the gate of the field effect transistor, the first electrode may be the drain or source of the field effect transistor (also referred to as the drain electrode or source electrode, both of which refer to the same in this article), the corresponding second electrode may be the source or drain of the field effect transistor, and the control electrode or the third electrode may be the gate; when the transistor is a bipolar transistor, the control electrode refers to the base of the bipolar transistor, the first electrode may be the collector or emitter of the bipolar transistor, the corresponding second electrode may be the emitter or collector of the bipolar transistor, and the control electrode or the third electrode may be the base. The transistor may be manufactured using amorphous silicon, polycrystalline silicon, oxide semiconductor, organic semiconductor, NMOS / PMOS process or CMOS process.

[0042] The following description uses multiple embodiments with reference to the accompanying drawings as examples. The drain and source of the transistors in the embodiments of the present application may vary depending on the bias state of the transistors. However, this application is not limited to the embodiments illustrated, and various variations of the embodiments of the present application are also within the scope of protection.

[0043] To achieve high-density and high mechanical flexibility CMOS integrated circuits, excellent structural design is essential. Currently, mainstream CMOS integrated circuit structures mainly include planar and three-dimensional stacking. Planar structures are highly flexible but are limited by low circuit integration density. Three-dimensional stacking structures can help achieve high integration density circuits, but due to the presence of interlayer interconnects, this structure reduces the mechanical flexibility of the integrated circuit. Therefore, there is a trade-off between high integration density and high flexibility of the integrated circuit.

[0044] This application provides a novel integrated circuit structure that overcomes the previous incompatibility between high density and high mechanical flexibility. High-density integrated circuits based on this structure exhibit ultra-flexibility, with no significant degradation in electrical properties after bending under harsh conditions.

[0045] The following is a further detailed description of the embodiments of the present application with reference to the accompanying drawings. The method steps described herein are merely illustrative, and are illustrated using only an exemplary flexible three-dimensional integrated circuit structure. As is well known to those skilled in the art, the disclosed method is also applicable to other types of integrated circuits and those based on other material systems, such as logic gates, SRAMs, full adders, amplifiers, and the like.

[0046] FIG2 is a flow chart of a method for preparing a flexible three-dimensional integrated circuit structure according to an embodiment of the present application. As shown in FIG2 , the present application provides a method for preparing a flexible three-dimensional integrated circuit structure, the method comprising:

[0047] S201: forming a first substrate;

[0048] S202: Spin-coating metallic carbon nanotubes as a material for forming source and drain electrodes on a first substrate to pattern-form a first source electrode and a first drain electrode of a P-type transistor, spin-coating semiconducting carbon nanotubes as a material for forming a channel region on the first substrate between the first source electrode and the first drain electrode to pattern-form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, and depositing a gate layer on the first gate dielectric layer and patterning to form a gate of the P-type transistor;

[0049] S203: depositing an oxide insulating layer on the P-type transistor, where the oxide insulating layer serves as a second gate dielectric layer of the N-type transistor;

[0050] S204: depositing metal oxide a-IGZO on the second gate dielectric layer by DC magnetron sputtering to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside the second channel region by a first wet etching method to form a second channel region of the N-type transistor;

[0051] S205: etching the first gate dielectric layer and the second gate dielectric layer by a second wet etching method to expose the first source electrode and the first drain electrode of the P-type transistor; and

[0052] S206: forming a second source electrode and a second drain electrode of the N-type transistor on both sides of the second channel region, respectively, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below to form an output end of the inverter.

[0053] Specifically, a P-type transistor is formed on a first substrate, and the P-type transistor includes a first source electrode, a first drain electrode and a first channel region, a first gate dielectric layer and a gate, wherein the first source electrode and the first drain electrode are respectively located on both sides of the first channel region, and the first gate dielectric layer and the gate are sequentially located on the first source electrode, the first channel region and the first drain electrode.

[0054] The method for preparing a flexible three-dimensional integrated circuit structure in this embodiment proposes a new design structure, which can achieve high mechanical flexibility while ensuring high density of the integrated circuit. Even after bending under harsh bending conditions, the electrical characteristics of the inverter prepared by this method for preparing a flexible three-dimensional integrated circuit structure do not decrease significantly, thereby maintaining the high flexibility of the inverter and the integrated circuit, and achieving the technical effect of ensuring the stable performance of the inverter and the integrated circuit.

[0055] In some embodiments, the DC magnetron sputtering method uses a sputtering power of 120 W and a sputtering time of 200 s to achieve a metal oxide a-IGZO channel layer with a thickness of 20 nm;

[0056] The first wet etching method uses a solution of 36% dilute hydrochloric acid and deionized water in a ratio of 50:1.

[0057] In some embodiments, a flexible material solution is spin-coated on a supporting substrate comprising glass, and the flexible material solution on the supporting substrate is dried and solidified to form a thin film, thereby forming a first substrate.

[0058] In some embodiments, the first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of flexible materials.

[0059] In some embodiments, the first substrate includes flexible PEN, PET or PI; this is for illustrative purposes only, and other substrate materials known to those skilled in the art can be applied here, without limitation.

[0060] In some embodiments, the material forming the first channel region of the P-type transistor includes at least semiconductor carbon nanotubes, the material forming the first source electrode and the first drain electrode includes at least metallic carbon nanotubes, the material forming the gate includes at least metal ITO, and the material forming the first gate dielectric layer and the second gate dielectric layer includes at least a mixed material of Al2O3 and PI.

[0061] In some embodiments, the gate of the P-type transistor is formed by photolithography, and the patterning method includes first forming a pattern with photoresist, then depositing ITO, and then removing the photoresist to form the gate by a stripping method.

[0062] The following describes in detail a method for fabricating a flexible three-dimensional integrated circuit structure according to another embodiment of the present application, using another example. Figures 1A-1F are schematic diagrams of the structure of a flexible three-dimensional integrated circuit structure according to an embodiment of the present application; Figure 4 is a second flow chart of a method for fabricating a flexible three-dimensional integrated circuit structure according to an embodiment of the present application; Figure 4 corresponds one-to-one with the steps in Figures 1A-1F. Figures 3A-3I are schematic diagrams of the three-dimensional structure of a flexible three-dimensional integrated circuit structure according to an embodiment of the present application.

[0063] In the method involved in the present application, unless otherwise specified, the pre-treatment of the supporting substrate before the formation of the flexible material substrate (eg, flexible PI substrate) will not be described in detail in the steps.

[0064] In some embodiments, the support substrate needs to be pre-treated to ensure that the flexible material substrate is formed on it and the circuit can be torn off from the support substrate without damage after being fully prepared on the flexible material substrate.

[0065] As shown in FIG4 , step S401 : forming a flexible substrate; the flexible substrate refers to the aforementioned first substrate;

[0066] For example, the flexible substrate may include PEN, PET and PI films, and the formation process of the flexible substrate includes directly using purchased films or forming the films by spin coating a solution.

[0067] In some embodiments, the flexible substrate is obtained by spin-coating a flexible PI solution on a support substrate including glass and silicon, and drying and curing the flexible PI solution spin-coated on the support substrate into a PI film to obtain a flexible substrate 101 as shown in FIG1A .

[0068] Step S402: forming a P-type transistor on the flexible substrate.

[0069] Exemplarily, the P-type transistor may include a carbon nanotube thin film transistor.

[0070] In some embodiments, as shown in FIG1B and FIG3B-FIG3E, metallic carbon nanotubes can be used as the forming material of the first source electrode and the first drain electrode (or referred to as the source-drain electrode, the first definition here is a distinguishing function, used to indicate that it is the source-drain electrode of the P-type transistor) and spin-coated on the flexible substrate 101, and patterned by photolithography and plasma etching. Subsequently, the semiconductor carbon nanotubes are spin-coated and patterned in the same way as the source-drain electrode of the P-type transistor to form the channel region of the P-type transistor, or the first channel region. The gate dielectric layer of the P-type transistor (for example, Al2O3 / PI mixed material) is deposited on the channel layer (or the first channel region) of the formed P-type transistor by ALD and patterned by photolithography and phosphoric acid 70°C wet etching. Subsequently, it is deposited by magnetron sputtering and patterned by lift-off to form the gate or gate electrode of the P-type transistor. For example, the magnetron sputtering power is 100 W, the time is 6.5 minutes, and the thickness of the deposited ITO is 80 nm. Afterwards, the device is placed in acetone for ultrasonic treatment to remove the photoresist and the ITO above the photoresist to form the gate electrode of the transistor, thereby forming a P-type transistor 102.

[0071] In some embodiments, other methods such as inkjet printing or other material systems may be used to form P-type transistors. As long as the patterning method and material selection are compatible with the flexible substrate, they can be applied here without specific limitation.

[0072] Step S403: Depositing a gate dielectric layer of the N-type transistor; wherein the P-type transistor and the N-type transistor share a gate, as shown in FIG1C and FIG3F , a layer of oxide insulating layer is deposited on the gate electrode of the P-type transistor as the gate dielectric layer 103 of the N-type transistor (to distinguish the gate dielectric layer of the P-type transistor, it can be referred to as a second gate dielectric layer).

[0073] In some embodiments, the gate dielectric layer may be formed of a mixed Al2O3 / PI material. In this embodiment, the deposition and etching methods of the material layer are consistent with the formation method of the gate dielectric layer in the P-type transistor described above, and are not further described here.

[0074] Step S404: forming the channel region 104 of the N-type transistor. Exemplarily, the second channel region of the N-type transistor (or the channel layer of the N-type transistor) may include a-IGZO metal oxide.

[0075] In some embodiments, as shown in FIG1D and FIG3G, a metal oxide a-IGZO channel layer is deposited on the second gate dielectric layer Al2O3 / PI mixed material by DC magnetron sputtering, with a sputtering power of 120W and a sputtering time of 200s to achieve a metal oxide a-IGZO channel layer with a thickness of 20nm. Thereafter, the metal oxide a-IGZO channel layer is etched by wet etching with a solution of 36% dilute hydrochloric acid and deionized water in a ratio of 50:1 to remove a-IGZO outside the channel area to achieve patterning. In some embodiments, other semiconductor materials well known to those skilled in the art can also be used as the channel layer of the N-type transistor, as long as the deposition and patterning process are compatible with the existing materials below and do not reduce the performance of the formed P-type transistor. There is no limitation on this.

[0076] Step S405: Patterning the gate dielectric layer of the N-type transistor to expose the source and drain electrodes of the underlying P-type transistor. Exemplarily, the patterning method may include wet etching.

[0077] In some embodiments, as shown in FIG1E and FIG3H , after forming the a-IGZO channel layer of the N-type transistor, the Al2O3 / PI mixed material of the gate dielectric layer is patterned and etched. This can reduce the formation of interface states between the channel layer of the N-type transistor and its gate dielectric layer. This etching method is consistent with the gate dielectric layer etching method in the P-type transistor described above.

[0078] Step S406: forming the source and drain electrodes 106 of the N-type transistor. For example, the source and drain electrodes of the N-type transistor may comprise metal ITO. In some embodiments, the drain electrode of the N-type transistor needs to be connected to the drain electrode of the underlying P-type transistor to form the output terminal of the inverter.

[0079] In some embodiments, as shown in FIG1D and FIG3I , the ITO source and drain electrodes are formed in the same manner as the gate electrode of the P-type transistor in step 402 and will not be further described here. Of course, other metal materials, such as molybdenum, titanium, and platinum, can also be used as the source and drain electrodes, provided that the work function of the material matches that of the channel layer. These materials are not limited to any other material known to those skilled in the art.

[0080] The integrated circuit manufactured by the method for manufacturing a flexible three-dimensional integrated circuit structure provided in this embodiment has excellent mechanical flexibility and stable performance.

[0081] An embodiment of the present application further provides a flexible three-dimensional inverter, comprising:

[0082] a first substrate;

[0083] A P-type transistor located on a first substrate, the P-type transistor comprising a first source electrode, a first drain electrode, a first channel region, a first gate dielectric layer, and a gate, wherein the first source electrode and the first drain electrode are respectively located on either side of the first channel region, and the first gate dielectric layer and the gate are sequentially located on the first source electrode, the first channel region, and the first drain electrode; wherein the first channel region of the P-type transistor is formed of at least a semiconducting carbon nanotube, and the first source electrode and the first drain electrode are formed of at least a metallic carbon nanotube;

[0084] an oxide insulating layer located on the P-type transistor, the oxide insulating layer being a second gate dielectric layer of the N-type transistor;

[0085] a second channel region of the N-type transistor located on the second gate dielectric layer;

[0086] The second source electrode and the second drain electrode of the N-type transistor located on both sides of the second channel region, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below, form the output end of the inverter.

[0087] In some embodiments, the gate is formed of at least a material including metal ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of at least a mixed material including Al 2 O 3 and PI.

[0088] In some embodiments, the first substrate is formed of a flexible film; and the thickness of the first substrate is 10-15 μm.

[0089] In some embodiments, the first substrate is a PI film.

[0090] In some embodiments, the flexible PI solution is first spin-coated on a supporting substrate comprising glass, and then the formed PI film is dried and solidified. The thickness of the PI film is controlled by controlling the rotation speed of the spin coating.

[0091] In some embodiments, the material forming the second channel region of the N-type transistor includes at least a-IGZO, and the second source electrode, the second drain electrode, and the gate electrode include at least metal ITO.

[0092] Figure 5 is a schematic diagram of the structure of a flexible three-dimensional inverter according to one embodiment of the present application; the schematic diagram also includes a cross-sectional SEM image of the stacked structure and a partial magnified image. As shown in Figure 5, the prepared inverter uses a common gate and drain structure for two types of transistors. The materials of each layer in the structure disclosed in this application include, but are not limited to, those shown in Figure 5.

[0093] An embodiment of the present application provides an integrated circuit, which includes any of the above flexible three-dimensional inverters.

[0094] The above-mentioned flexible three-dimensional inverter and integrated circuit can achieve the technical effects achieved by the method for preparing a flexible three-dimensional integrated circuit structure, which will not be described in detail here.

[0095] Figure 6A is a bending state diagram of a flexible inverter prepared by a method for preparing a flexible three-dimensional integrated circuit structure according to an embodiment of the present application; Figure 6B is a performance diagram of a flexible inverter under different bending conditions prepared by a method for preparing a flexible three-dimensional integrated circuit structure according to an embodiment of the present invention.

[0096] The integrated circuit fabricated using the method described herein exhibits excellent mechanical flexibility. Under the bending conditions shown in FIG6A , the integrated circuit's electrical characteristics show no significant degradation when bent a varying number of times. As shown in FIG6B , curve 601 is a graph of the electrical characteristics of the inverter after fabrication, while curves 602 and 603 are graphs of the inverter's electrical characteristics after 3,000 and 6,000 bends, respectively, at a bending radius of 500 μm. The curves in the figure clearly show that the variation between the curves is minimal when the number of bends varies.

[0097] The integrated circuit structure and preparation method described in this application integrate P-type carbon nanotube transistors and N-type a-IGZO transistors in a vertical stacking manner to form a flexible three-dimensional inverter. Wet etching of the gate dielectric layer is proposed to achieve a common gate and common drain structure. By adopting this structure, the flexible three-dimensional integrated circuit is characterized by high mechanical flexibility while ensuring high circuit integration density. The flexible three-dimensional inverter prepared by the method described in this application maintains its excellent electrical performance after 6000 bends with a bending radius of 500μm.

[0098] The preparation method, inverter and integrated circuit of the flexible three-dimensional integrated circuit structure in this application have higher mechanical flexibility than integrated circuits with traditional three-dimensional structure design (such as traditional inverters), and their performance does not decrease significantly after bending under harsh bending conditions; and they have lower delay time; and the manufacturing method of the integrated circuit in this application is simple, and has strong adaptability and convenience for the future large-scale production of flexible integrated circuits.

[0099] The present application provides a method for preparing a flexible three-dimensional integrated circuit structure, an inverter, and an integrated circuit. The method proposes a new design structure that can simultaneously achieve high mechanical flexibility while ensuring high density of the integrated circuit. Even after bending under harsh bending conditions, the electrical characteristics of the inverter prepared by the method for preparing the flexible three-dimensional integrated circuit structure do not significantly decrease, thereby maintaining the high flexibility of the inverter and the integrated circuit, achieving the technical effect of ensuring stable performance of the inverter and the integrated circuit and reducing delay.

[0100] The present application also provides a memory, comprising a memory array and a control circuit, wherein the memory cell circuits in the memory array and the control circuit comprise any of the above-described integrated circuits.

[0101] The above embodiments are only used to illustrate the present application and are not intended to limit the present application. Ordinary technicians in the relevant technical field can make various changes and modifications without departing from the scope of the present application. Therefore, all equivalent technical solutions should also fall within the scope disclosed in the present application.

Claims

1. A method for preparing a flexible three-dimensional integrated circuit structure, characterized in that: The method comprises: providing a first substrate; Spin-coating metallic carbon nanotubes as a material for forming source and drain electrodes on the first substrate, patterning to form a first source electrode and a first drain electrode of a P-type transistor, spin-coating semiconductor carbon nanotubes as a material for forming a channel region on the first substrate between the first source electrode and the first drain electrode, patterning to form a first channel region of the P-type transistor, depositing a first gate dielectric layer of the P-type transistor on the first channel region, and depositing a gate layer on the first gate dielectric layer and patterning to form a gate of the P-type transistor; Depositing an oxide insulating layer on the P-type transistor, wherein the oxide insulating layer is a second gate dielectric layer of the N-type transistor; Depositing metal oxide a-IGZO on the second gate dielectric layer by DC magnetron sputtering to form a metal oxide a-IGZO channel layer, and removing the metal oxide a-IGZO channel layer outside the second channel region by a first wet etching method to form the second channel region of the N-type transistor; Etching the first gate dielectric layer and the second gate dielectric layer by a second wet etching method to expose the first source electrode and the first drain electrode of the P-type transistor; and A second source electrode and a second drain electrode of the N-type transistor are respectively formed on both sides of the second channel region, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below to form an output end of the inverter.

2. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1, characterized in that: The DC magnetron sputtering method uses a sputtering power of 120 W and a sputtering time of 200 s to achieve a metal oxide a-IGZO channel layer with a thickness of 20 nm; The first wet etching method uses a solution of 36% dilute hydrochloric acid and deionized water in a ratio of 50:

1.

3. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1, characterized in that: The flexible material solution is spin-coated on a supporting substrate comprising glass, and the flexible material solution on the supporting substrate is dried and solidified to form a thin film, thereby forming the first substrate.

4. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1, characterized in that: The first substrate, the first gate dielectric layer, the second gate dielectric layer, the first channel region, the second channel region, the first source electrode, and the first drain electrode are all formed of flexible materials.

5. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1 or 4, characterized in that: The first substrate includes flexible PEN, PET or PI.

6. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1, characterized in that: The gate is formed of at least metal ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of at least Al2O3 and PI mixed materials.

7. The method for preparing a flexible three-dimensional integrated circuit structure according to claim 1, characterized in that: The gate of the P-type transistor is formed by photolithography, including: setting the power of magnetron sputtering to 100W and the time to 6.5 minutes to deposit an ITO layer with a thickness of 80nm, and performing ultrasonic treatment in acetone to remove the photoresist and the ITO layer above the photoresist to form the gate.

8. A flexible three-dimensional inverter, characterized in that: The flexible three-dimensional inverter comprises: a first substrate; A P-type transistor located on the first substrate, the P-type transistor comprising a first source electrode, a first drain electrode and a first channel region, a first gate dielectric layer and a gate, wherein the first source electrode and the first drain electrode are respectively located on both sides of the first channel region, and the first gate dielectric layer and the gate are sequentially located on the first source electrode, the first channel region and the first drain electrode; wherein the first channel region of the P-type transistor is formed of a material comprising at least a semiconductor carbon nanotube, and the first source electrode and the first drain electrode are formed of a material comprising at least a metallic carbon nanotube; an oxide insulating layer located on the P-type transistor, wherein the oxide insulating layer is a second gate dielectric layer of the N-type transistor; a second channel region of the N-type transistor located on the second gate dielectric layer; a second source electrode and a second drain electrode of the N-type transistor located on both sides of the second channel region, wherein the second drain electrode is connected to the first drain electrode of the P-type transistor below, forms the output of the inverter.

9. The flexible three-dimensional inverter according to claim 8, characterized in that: The gate is formed of at least metal ITO, and the first gate dielectric layer and the second gate dielectric layer are formed of at least Al2O3 and PI mixed materials.

10. An integrated circuit, characterized in that: The integrated circuit comprises the flexible three-dimensional inverter as described in any one of claims 8-9.

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