RFID tag rectifier with active bias ladders

Abstract

A rectifier comprises a main rectifying chain having sequentially coupled NMOS and PMOS rectifying elements, a first active bias ladder and a second active bias ladder. The first active bias ladder may be coupled to a first charge pump and include first and second bias voltage tracking circuits. The first and second bias voltage tracking circuits may bias the first and last NMOS rectifying elements of the main rectifying chain. The first active bias ladder may act as a voltage divider, providing a bias to intermediate NMOS rectifying elements. Similarly, the second active bias ladder may be coupled to a second charge pump and include third and fourth voltage tracking circuits that bias the first and last PMOS rectifying elements. The second active bias ladder may also act as a voltage divider and provide a bias to intermediate PMOS rectifying elements.

Description

RFID TAG RECTIFIER WITH ACTIVE BIAS LADDERSCROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application claims priority to U.S. Provisional Patent Application Ser. No. 63 / 590,040 filed on October 13, 2023. The disclosures of the Provisional Application are hereby incorporated by reference in their entirety.BACKGROUND

[0002] Radio-Frequency Identification (RFID) systems typically include RFID readers, also know n as RFID reader / writers or RFID interrogators, and RFID tags. RFID systems can be used in many ways for locating and identifying objects to which the tags are attached. RFID systems are useful in product-related and service-related industries for tracking objects being processed, inventoried, or handled. In such cases, an RFID tag is usually attached to an individual item, or to its package.

[0003] In principle, RFID techniques entail using an RFID reader to inventory one or more RFID tags, where inventorying involves at least singulating a tag and receiving an identifier from the singulated tag. “Singulated’' is defined as a reader singling-out one tag, potentially from among multiple tags, for a reader-tag dialog. "‘Identifier’ is defined as a number identifying the tag or the item to which the tag is attached, such as a tag identifier (TID), electronic product code (EPC), etc. The reader transmitting a Radio-Frequency (RF) wave performs the interrogation. The RF wave is ty pically electromagnetic, at least in the far field. The RF wave can also be predominantly electric or magnetic in the near or transitional near field. The RF wave may encode one or more commands that instruct the tags to perform one or more actions.

[0004] In typical RFID systems, an RFID reader transmits a modulated RF inventory signal (a command), receives a tag reply, and transmits an RF acknowledgement signal responsive to the tag reply. A tag that senses the interrogating RF wave may respond by transmitting back another RF wave. The tag either generates the transmitted back RF wave originally, or by reflecting back a portion of the interrogating RF w ave in a process known as backscatter. Backscatter may take place in a number of ways.

[0005] The reflected-back RF wave may encode data stored in the tag, such as a number. The response is demodulated and decoded by the reader, which thereby identifies, counts, or otherwise interacts with the associated item. The decoded data can denote a serial number, a price, a date, a time, a destination, an encrypted message, an electronic signature, other attribute(s), any combination of attributes, and so on. Accordingly, when a reader receives tag data it can leam about the item that hosts the tag and / or about the tag itself.

[0006] An RFID tag typically includes an antenna section, a radio section, a powermanagement section, and frequently a logical section, a memory, or both. In some RFID tags the power-management section included an energy storage device such as a battery. RFID tags with an energy storage device are known as battery-assisted, semiactive, or active tags. Other RFID tags can be pow ered solely by the RF signal they receive. Such RFID tags do not include an energy storage device and are called passive tags. Of course, even passive tags typically include temporary energy- and data / flag-storage elements such as capacitors or inductors.BRIEF SUMMARY

[0007] This summary is provided to introduce a selection of concepts in a simplified form that are further described below in the Detailed Description. This summary is not intended to identity' key features or essential features of the claimed subject matter, nor is it intended as an aid in determining the scope of the claimed subject matter.

[0008] Examples are directed to a rectifier for a Radio Frequency Identification (RFID) integrated circuit (IC). The rectifier may include a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled n-channel metal oxide semiconductor (NMOS) and p- channel metal oxide semiconductor (PMOS) rectifying elements. The rectifier may also include a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain. A first bias generator may be coupled to the first active bias ladder and the main rectifying chain. The first bias generator may be configured to provide a first bias to the first active bias ladder. The first bias generator may comprise: a first charge pump coupled to a first point of the main rectifying chain; and a first bias voltage tracking circuit coupled to a first point of the first activebias ladder, and a first NMOS rectifying element in the main rectifying chain. The rectifier may also include a second bias generator coupled to the first active bias ladder and the main rectifying chain. The second bias generator may be configured to provide a second bias to the first active bias ladder. The second bias generator may include a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectifying chain.

[0009] According to further examples, a Radio Frequency Identification (RFID) integrated circuit (IC) may comprise an antenna port and a rectifier coupled to the antenna port. The rectifier may include a main rectifying chain comprising three or more rectify ing stages, wherein each rectifying stage includes a pair of sequentially coupled NMOS and PMOS rectifying elements. The rectifier may also include a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain. A first bias generator may be coupled to the first active bias ladder and the main rectifying chain. The first bias generator may be configured to provide a first bias to the first active bias ladder. The first bias generator may comprise: a first charge pump coupled to a first point of the main rectifying chain; and a first bias voltage tracking circuit coupled to a first point of the first active bias ladder, and the first NMOS rectifying element in the main rectifying chain. The rectifier may also include a second bias generator coupled to the first active bias ladder and the main rectifying chain. The second bias generator may be configured to provide a second bias to the first active bias ladder. The second bias generator may include a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectifying chain.

[0010] These and other features and advantages will be apparent from a reading of the following detailed description and a review of the associated drawings. It is to be understood that both the foregoing general description and the following detailed description are explanatory' only and are not restrictive of aspects as claimed.BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The following Detailed Description proceeds with reference to the accompanying drawings, in which:

[0012] FIG. 1 is a block diagram of components of an RFID system.

[0013] FIG. 2 is a diagram showing components of a passive RFID tag, such as a tag that can be used in the system of FIG. 1.

[0014] FIG. 3 is a conceptual diagram for explaining a half-duplex mode of communication between the components of the RFID system of FIG. 1.

[0015] FIG. 4 is a block diagram showing a detail of an RFID tag, such as the one shown in FIG. 2.

[0016] FIGS. 5A and 5B illustrate signal paths during tag-to-reader and reader-to-tag communications in the block diagram of FIG. 4.

[0017] FIGS. 6A and 6B illustrate examples of dual-path and single-path rectifiers.

[0018] FIG. 7 illustrates the biasing of rectifier stages.

[0019] FIG. 8 illustrates an example rectifier using active bias ladders, according to some embodiments.DETAILED DESCRIPTION

[0020] In the following detailed description, references are made to the accompanying drawings that form a part hereof, and in which are shown by way of illustration specific embodiments or examples. These embodiments or examples may be combined, other aspects may be utilized, and structural changes may be made without departing from the spirit or scope of the present disclosure. The following detailed description is therefore not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims and their equivalents.

[0021] As used herein, “memory ” is one of ROM, RAM, SRAM, DRAM, NVM, EEPROM, FLASH, Fuse, MRAM, FRAM, and other similar information-storage technologies as will be know n to those skilled in the art. Some portions of memory may be writeable and some not. “Command” refers to a reader request for one or more tags to perform one or more actions, and includes one or more tag instructions preceded by a command identifier or command code that identifies the command and / or the tag instructions. “Instruction” refers to a request to a tag to perform a single explicit action (e g., write data into memory). “Program” refers to a request to a tag to perform a set or sequence of instructions (e.g., read a value from memory' and, if the read value is less than a threshold then lock a memory w ord). “Protocol” refers to an industry standard for communications between a reader and a tag (and vice versa),such as the Class- 1 Generation-2 UHF RFID Protocol for Communications at 860MHz - 960 MHz by GS1 EPCglobal, Inc. ("Gen2 Protocol’7), versions 1.2.0 and 2.0 of which are hereby incorporated by reference.

[0022] Technical advantages of example implementations may include using two active bias ladders for biasing, as opposed to using local charge pump techniques which require N or 2N local charge pumps, resulting in reductions in power consumption and die area. RF-driven biasing may provide a relatively quick startup time. Yet another advantage includes shared coupling gate capacitors with the main rectifier, resulting in additional area savings. Example implementations may also use bias voltage tracking circuits to track the voltage between rectifying elements and the rectifier final output.

[0023] FIG. 1 is a diagram of the components of a typical RFID system 100, incorporating embodiments. An RFID reader 110 transmits an interrogating RF signal 112. RFID tag 120 in the vicinity of RFID reader 110 senses interrogating RF signal 112 and generate signal 126 in response. RFID reader 110 senses and interprets signal 126. The signals 112 and 126 may include RF w aves and / or non-propagating RF signals (e.g., reactive near-field signals).

[0024] Reader 110 and tag 120 communicate via signals 112 and 126. When communicating, each encodes, modulates, and transmits data to the other, and each receives, demodulates, and decodes data from the other. The data can be modulated onto, and demodulated from, RF waveforms. The RF waveforms are typically in a suitable range of frequencies, such as those near 900 MHz, 13.56 MHz, and so on.

[0025] The communication betw een reader and tag uses symbols, also called RFID symbols. A symbol can be a delimiter, a calibration value, and so on. Symbols can be implemented for exchanging binary data, such as “0” and “1”, if that is desired. When symbols are processed by reader 110 and tag 120 they can be treated as values, numbers, and so on.

[0026] Tag 120 can be a passive tag, or an active or battery-assisted tag (i. e.. a tag having its own power source). When tag 120 is a passive tag, it is powered from signal 112.

[0027] FIG. 2 is a diagram of an RFID tag 220, which may function as tag 120 of FIG. 1. Tag 220 is drawn as a passive tag, meaning it does not have its own powersource. Much of what is described in this document, however, applies also to active and battery-assisted tags.

[0028] Tag 220 is typically (although not necessarily) formed on a substantially planar inlay 222. which can be made in many ways known in the art. Tag 220 includes a circuit which may be implemented as an IC 224. In some embodiments IC 224 is implemented in complementary' metal-oxide semiconductor (CMOS) technology. In other embodiments IC 224 may be implemented in other technologies such as bipolar junction transistor (BJT) technology, metal-semiconductor field-effect transistor (MESFET) technology’, and others as will be well known to those skilled in the art. IC 224 is arranged on inlay 222.

[0029] Tag 220 also includes an antenna for exchanging wireless signals with its environment. The antenna is often flat and attached to inlay 222. IC 224 is electrically coupled to the antenna via suitable IC contacts (not shown in FIG. 2). The term “electrically coupled" as used herein may mean a direct electrical connection, or it may mean a connection that includes one or more intervening circuit blocks, elements, or devices. The “electrical” part of the term “electrically coupled” as used in this document shall mean a coupling that is one or more of ohmic / galvanic, capacitive, and / or inductive. Similarly, the term “electrically isolated” as used herein means that electrical coupling of one or more types (e.g., galvanic, capacitive, and / or inductive) is not present, at least to the extent possible. For example, elements that are electrically isolated from each other are galvanically isolated from each other, capacitively isolated from each other, and / or inductively isolated from each other. Of course, electrically isolated components will generally have some unavoidable stray capacitive or inductive coupling between them, but the intent of the isolation is to minimize this stray coupling to a negligible level when compared with an electrically coupled path.

[0030] IC 224 is shown with a single antenna port, comprising tw o IC contacts electrically coupled to tw o antenna segments 226 and 228 which are shown here forming a dipole. Many other embodiments are possible using any number of ports, contacts, antennas, and / or antenna segments.

[0031] Diagram 250 depicts top and side view s of tag 252, formed using a strap. Tag 252 differs from tag 220 in that it includes a substantially planar strap substrate 254having strap contacts 256 and 258. IC 224 is mounted on strap substrate 254 such that the IC contacts on IC 224 electrically couple to strap contacts 256 and 258 via suitable connections (not shown). Strap substrate 254 is then placed on inlay 222 such that strap contacts 256 and 258 electrically couple to antenna segments 226 and 228. Strap substrate 254 may be affixed to inlay 222 via pressing, an interface layer, one or more adhesives, or any other suitable means.

[0032] Diagram 260 depicts a side view of an alternative way to place strap substrate 254 onto inlay 222. Instead of strap substrate 254’s surface, including strap contacts 256 / 258, facing the surface of inlay 222, strap substrate 254 is placed with its strap contacts 256 / 258 facing away from the surface of inlay 222. Strap contacts 256 / 258 can then be either capacitively coupled to antenna segments 226 / 228 through strap substrate 254, or conductively coupled using a through-via which may be formed by crimping strap contacts 256 / 258 to antenna segments 226 / 228. In some embodiments the positions of strap substrate 254 and inlay 222 may be reversed, with strap substrate 254 mounted beneath inlay 222 and strap contacts 256 / 258 electrically coupled to antenna segments 226 / 228 through inlay 222. Of course, in yet other embodiments strap contacts 256 / 258 may electrically couple to antenna segments 226 / 228 through both inlay 222 and strap substrate 254.

[0033] In operation, the antenna receives a signal and communicates it to IC 224, which may both harvest pow er and respond if appropriate, based on the incoming signal and the IC’s internal state. If IC 224 uses backscatter modulation then it responds by modulating the antenna’s reflectance, which generates response signal 126 from signal 112 transmitted by the reader. Electrically coupling and uncoupling the IC contacts of IC 224 can modulate the antenna’s reflectance, as can varying the admittance of a shunt-connected circuit element which is coupled to the IC contacts. Varying the impedance of a series-connected circuit element is another means of modulating the antenna's reflectance. If IC 224 is capable of transmitting signals (e.g., has its own power source, is coupled to an external power source, and / or is able to harvest sufficient power to transmit signals), then IC 224 may respond by transmitting response signal 126.

[0034] In the embodiments of FIG. 2, antenna segments 226 and 228 are separate from IC 224. In other embodiments the antenna segments may alternatively be formed on IC 224. Tag antennas according to embodiments may be designed in any form andare not limited to dipoles. For example, the tag antenna may be a patch, a slot, a loop, a coil, a hom, a spiral, a monopole, microstrip, stripline, or any other suitable antenna.

[0035] An RFID tag such as tag 220 is often attached to or associated with an individual item or the item packaging. An RFID tag may be fabricated and then attached to the item or packaging, or may be partly fabricated before attachment to the item or packaging and then completely fabricated upon attachment to the item or packaging. In some embodiments, the manufacturing process of the item or packaging may include the fabrication of an RFID tag. In these embodiments, the resulting RFID tag may be integrated into the item or packaging, and portions of the item or packaging may serve as tag components. For example, conductive item or packaging portions may serve as tag antenna segments or contacts. Nonconductive item or packaging portions may serve as tag substrates or inlays. If the item or packaging includes integrated circuits or other circuitry, some portion of the circuitry may be configured to operate as part or all of an RFID tag IC.

[0036] The components of the RFID system of FIG. 1 may communicate with each other in any number of modes. One such mode is called full duplex, where both reader 110 and tag 120 can transmit at the same time. In some embodiments, RFID system 100 may be capable of full duplex communication if tag 120 is configured to transmit signals as described above. Another such mode, suitable for passive tags, is called half-duplex, and is described below.

[0037] FIG. 3 is a conceptual diagram 300 for explaining half-duplex communications between the components of the RFID system of FIG. 1, in this case with tag 120 implemented as passive tag 220 of FIG. 2. The explanation is made with reference to a TIME axis, and also to a human metaphor of “talking” and “listening”. The actual technical implementations for “talking” and “listening” are now described.

[0038] RFID reader 110 and RFID tag 120 talk and listen to each other by taking turns. As seen on axis TIME, when reader 110 talks to tag 120 the communication session is designated as “R->T”, and when tag 120 talks to reader 110 the communication session is designated as “T- R”. Along the TIME axis, a sample R->T communication session occurs during a time interval 312, and a following sample T->R communication session occurs during a time interval 326. Interval 312may typically be of a different duration than interval 326 - here the durations are shown approximately equal only for purposes of illustration.

[0039] According to blocks 332 and 336, RFID reader 110 talks during interval 312, and listens during interval 326. According to blocks 342 and 346. RFID tag 120 listens while reader 110 talks (during interval 312), and talks while reader 110 listens (during interval 326).

[0040] In terms of actual behavior, during interval 312 reader 110 talks to tag 120 as follows. According to block 352, reader 110 transmits signal 112, which was first described in FIG. 1. At the same time, according to block 362, tag 120 receives signal 112 and processes it to extract data and so on. Meanwhile, according to block 372, tag 120 does not backscatter with its antenna, and according to block 382, reader 110 has no signal to receive from tag 120.

[0041] During interval 326, tag 120 talks to reader 110 as follows. According to block 356, reader 110 transmits a Continuous Wave (CW) signal, which can be thought of as a carrier that typically encodes no information. This CW signal serves both to transfer energy to tag 120 for its own internal power needs, and also as a carrier that tag 120 can modulate with its backscatter. Indeed, during interval 326, according to block 366, tag 120 does not receive a signal for processing. Instead, according to block 376, tag 120 modulates the CW emitted according to block 356 so as to generate backscatter signal 126. Concurrently, according to block 386, reader 110 receives backscatter signal 126 and processes it.

[0042] FIG. 4 is a block diagram showing a detail of an RFID IC, such as IC 224 in FIG. 2. Electrical circuit 424 in FIG. 4 may be formed in an IC of an RFID tag, such as tag 220 of FIG. 2. Circuit 424 has a number of main components that are described in this document. Circuit 424 may have a number of additional components from what is shown and described, or different components, depending on the exact implementation.

[0043] Circuit 424 shows two IC contacts 432, 433. suitable for coupling to antenna segments such as antenna segments 226 / 228 of RFID tag 220 of FIG. 2. When two IC contacts form the signal input from and signal return to an antenna they are often referred-to as an antenna port. IC contacts 432, 433 may be made in any suitable way, such as from metallic pads and so on. In some embodiments circuit 424 uses morethan two IC contacts, especially when tag 220 has more than one antenna port and / or more than one antenna.

[0044] Circuit 424 includes signal-routing section 435 which may include signal wiring, signal-routing busses, receive / transmit switches, and so on that can route a signal to the components of circuit 424. In some embodiments IC contacts 432 / 433 couple galvanically and / or inductively to signal-routing section 435. In other embodiments (such as is shown in FIG. 4) circuit 424 includes optional capacitors 436 and / or 438 which, if present, capacitively couple IC contacts 432 / 433 to signalrouting section 435. This capacitive coupling causes IC contacts 432 / 433 to be galvanically decoupled from signal-routing section 435 and other circuit components.

[0045] Capacitive coupling (and resultant galvanic decoupling) between IC contacts 432 and / or 433 and components of circuit 424 is desirable in certain situations. For example, in some RFID tag embodiments IC contacts 432 and 433 may galvanically connect to terminals of a tuning loop on the tag. In this situation, capacitors 436 and / or 438 galvanically decouple IC contact 432 from IC contact 433, thereby preventing the formation of a short circuit between the IC contacts through the tuning loop.

[0046] Capacitors 436 / 438 may be implemented within circuit 424 and / or partly or completely external to circuit 424. For example, a dielectric or insulating layer on the surface of the IC containing circuit 424 may serve as the dielectric in capacitor 436 and / or capacitor 438. As another example, a dielectric or insulating layer on the surface of a tag substrate (e.g., inlay 222 or strap substrate 254) may serve as the dielectric in capacitors 436 / 438. Metallic or conductive layers positioned on both sides of the dielectric layer (i.e., between the dielectric layer and the IC and between the dielectric layer and the tag substrate) may then serve as terminals of the capacitors 436 / 438. The conductive layers may include IC contacts (e.g., IC contacts 432 / 433), antenna segments (e.g., antenna segments 226 / 228), or any other suitable conductive layers.

[0047] Circuit 424 also includes a rectifier and PMU (Power Management Unit) 441 that harvests energy from the RF signal received by antenna segments 226 / 228 to power the circuits of IC 424 during either or both reader-to-tag (R- T) and tag-to-reader (T->R) sessions. Rectifier and PMU 441 may be implemented in any way known in the art.

[0048] Circuit 424 additionally includes a demodulator 442 that demodulates the RF signal received via IC contacts 432, 433. Demodulator 442 may be implemented in any way known in the art, for example including a slicer, an amplifier, and so on.

[0049] Circuit 424 further includes a processing block 444 that receives the output from demodulator 442 and performs operations such as command decoding, memory interfacing, and so on. In addition, processing block 444 may generate an output signal for transmission. Processing block 444 may be implemented in any way known in the art. for example by combinations of one or more of a processor, memory, decoder, encoder, and so on.

[0050] Circuit 424 additionally includes a modulator 446 that modulates an output signal generated by processing block 444. The modulated signal is transmitted by driving IC contacts 432, 433, and therefore driving the load presented by the coupled antenna segment or segments. Modulator 446 may be implemented in any way known in the art. for example including a switch, driver, amplifier, and so on.

[0051] In one embodiment, demodulator 442 and modulator 446 may be combined in a single transceiver circuit. In another embodiment modulator 446 may modulate a signal using backscatter. In another embodiment modulator 446 may include an active transmitter. In yet other embodiments demodulator 442 and modulator 446 may be part of processing block 444.

[0052] Circuit 424 additionally includes a memory' 450 to store data 452. At least a portion of memory 450 is preferably implemented as a Nonvolatile Memory (NVM). which means that data 452 is retained even when circuit 424 does not have power, as is frequently the case for a passive RFID tag.

[0053] In some embodiments, particularly^ in those with more than one antenna port, circuit 424 may contain multiple demodulators, rectifiers, PMUs, modulators, processing blocks, and / or memories.

[0054] In terms of processing a signal, circuit 424 operates differently during a R->T session and a T- R session. The different operations are described below, in this case with circuit 424 representing an IC of an RFID tag.

[0055] FIG. 5 A shows version 524-A of components of circuit 424 of FIG. 4, further modified to emphasize a signal operation during a R->T session during time interval 312 of FIG. 3. Demodulator 442 demodulates an RF signal received from IC contacts 432, 433. The demodulated signal is provided to processing block 444 as C_IN. In one embodiment, C_IN may include a received stream of symbols.

[0056] Version 524-A shows as relatively obscured those components that do not play a part in processing a signal during a R->T session. Rectifier and PMU 441 may be active, such as for converting RF power. Modulator 446 generally does not transmit during a R->T session, and typically does not interact with the received RF signal significantly, either because switching action in section 435 of FIG. 4 decouples modulator 446 from the RF signal, or by designing modulator 446 to have a suitable impedance, and so on.

[0057] Although modulator 446 is typically inactive during a R->T session, it need not be so. For example, during a R->T session modulator 446 could be adjusting its own parameters for operation in a future session, and so on.

[0058] FIG. 5B shows version 524-B of components of circuit 424 of FIG. 4, further modified to emphasize a signal operation during a T- R session during time interval 326 of FIG. 3. Processing block 444 outputs a signal C_OUT. In one embodiment, C_OUT may include a stream of symbols for transmission. Modulator 446 then modulates C_OUT and provides it to antenna segments such as segments 226 / 228 of RFID tag 220 via IC contacts 432, 433.

[0059] Version 524-B shows as relatively obscured those components that do not play a part in processing a signal during a T- R session. Rectifier and PMU 441 may be active, such as for converting RF power. Demodulator 442 generally does not receive during a T->R session, and typically does not interact with the transmitted RF signal significantly, either because switching action in section 435 of FIG. 4 decouples demodulator 442 from the RF signal, or by designing demodulator 442 to have a suitable impedance, and so on.

[0060] Although demodulator 442 is typically inactive during a T4R session, it need not be so. For example, during a T- R session demodulator 442 could be adjusting its own parameters for operation in a future session, and so on.

[0061] In typical embodiments, demodulator 442 and modulator 446 are operable to demodulate and modulate signals according to a protocol, such as the Gen2 Protocol mentioned above. In embodiments where circuit 424 includes multiple demodulators and / or modulators, each may be configured to support different protocols or different sets of protocols. A protocol specifies, in part, symbol encodings, and may include a set of modulations, rates, timings, or any other parameter associated with data communications. In addition, a protocol can be a vanant of a stated protocol such as the Gen2 Protocol, for example including fewer or additional commands than the stated protocol calls for, and so on. In such instances, additional commands are sometimes called custom commands.

[0062] In some embodiments, the performance of a rectifier or charge pump may be improved by biasing one or more rectifying elements in the rectifier / charge pump. "‘Biasing’7refers to the application of a voltage or current (the “bias”) at one or more points in a circuit to place one or more components in that circuit into a desired operating state. Bias may be in the form of a direct current (DC) or non-time-varying voltage or current. For example, if transistors are used as rectifying elements. DC or non-time-varying biases may be applied to the gates of transistors. In other examples, a bias may be applied to a part of a circuit in order to set, or raise, the voltage experienced by components of the circuits.

[0063] A rectifier, especially in the context of RFID, is configured to harvest energy from an RF signal, as mentioned above in relation to FIG. 4. For a passive RFID tag, the rectifier may serve as the primary', if not the only, source of power. A rectifier operates by using rectifying elements (e.g., diodes or transistors) to convert a timevariant signal (often referred to as an “AC” or “alternating current” signal) to a mostly time-invariant signal (often referred to as a “DC” or “direct current” signal), by accumulating charge on storage elements such as capacitors. In many RFID applications, the AC signal seen by a tag IC’s rectifier results from the RF signal incident on the tag’s antenna, and may have relatively low voltage amplitudes. Accordingly, a rectifier for RFID applications often includes multiple sets of rectifying elements, each configured to derive a small DC signal from the incident RF signal, and is configured to add the derived DC signals from each set of rectifying elements together to form an output DC signal with a voltage and current suitable topower a tag IC. These sets of rectifying elements may be arbitrarily organized into "stages" such that a given rectifier can be subdivided into one or more stages.

[0064] A rectifier with transistor rectifying elements that are directly controlled by an AC signal (e.g., via gates of the transistors) may be referred to as a "synchronous" rectifier. A rectifier coupled to only one phase of an AC signal may be referred to as a “single-ended” rectifier, versus a rectifier coupled to opposing phases of the AC signal (a “differential” rectifier). A single-ended rectifier typically has as its inputs a single RF signal and ground. On the other hand, a “differential” rectifier typically has a differential pair of RF signals as its inputs. This differential pair comprises two complementary RF signals with the same magnitude but out of phase by 180 degrees or having opposite polarities.

[0065] A rectifier may have two main current pathways for accumulating charge (a “dual-path” rectifier) or a single main current pathway for accumulating charge (a “single-path” rectifier). Dual-path rectifiers are also commonly known as a “fullwave” or “H-bridge” rectifiers, while single-path rectifiers are also referred to as a “half-wave” rectifiers.

[0066] FIG.6A shows a 4-stage dual -path rectifier 600. Each rectifier stage receives input through an anode node (“An”) and delivers output through a cathode node (“Cath”). The cathode of a given stage interconnects with the anode of the subsequent stage, establishing a sequential linkage. Within each individual stage, there are 4 rectifying transistors (for example, 602, 604, 606, and 608), coupled to inputs RFN 610 and RFP 620 via coupling capacitors (for example, 622, 624, 626, and 628), configured to allow AC signals through while blocking DC signals. The rectifying transistors are configured to pump charge, generating a positive DC voltage between the anode and the cathode of the stage. For example, during one half of an RF cycle when RFP 620 is positive and RFN 610 is negative, the NMOS rectifying transistor 602 becomes conductive, pumping charge from the anode An2 to the capacitor 616 through current path 612. Capacitor 616 is a charge-accumulating capacitor configured to accumulate charge, different from the coupling capacitors described above. Meanwhile, the PMOS rectifying transistor 604 is also conductive, forming the other current path 614 from charge-accumulating capacitor 618 to the cathode Cath2. Similarly , during the other half of an RF cycle when RFN 610 is positive and RFP 620 is negative, it is the NMOS rectifying transistor 606 and the PMOS rectifyingtransistor 608 that pump charge and form the conductive paths. Circuit modules 632, 634, 636. and 638, also referred to as "‘threshold voltage compensation’7circuits, are used to bias the rectifying transistors 602, 604, 606, and 608 appropriately. A transistor is biased, usually by the application of a DC voltage between its gate and source, to allow the transistor to switch on (thereby allowing current to flow through its channel) and off (preventing current from flowing through its channel) with relatively small changes in its gate voltage. In some examples, this is done byapplying a DC bias voltage near or at a transistor’s threshold voltage between its gate and source. A small additional change in the voltage at the transistor’s gate will then cause the transistor to switch on or off. Therefore, biasing, for example by circuit modules 632. 634, 636, and 638. may ensure efficient power conversion of AC signals into DC signals.

[0067] FIG. 6B illustrates a single-path rectifier 640, which can be viewed as a half part of a dual-path rectifier. Specifically, the single-path rectifier 640 includes one half from the odd stages of a dual-path rectifier and another half from the even stages of the dual-path rectifier. In other words, a dual-path rectifier may be considered as two single-path rectifiers interleaved with each other. In contrast to a dual-path rectifier, where a single stage has two conductive paths in a given half RF cycle, a stage in a single-path rectifier only has one conductive path in a given half RF cycle.

[0068] As mentioned above, the performance of a rectifier or charge pump may be improved by biasing one or more rectifying elements in the rectifier / charge pump. “Biasing’’ refers to the application of a voltage or current (the “bias”) at one or more points in a circuit to place one or more components in that circuit into a desired operating state. Bias may be in the form of a direct current (DC) or non-time-varying voltage or current. For example, if transistors are used as rectify ing elements, DC or non-time-varying biases may be applied to the gates of transistors. In other examples, a bias may be applied to a part of a circuit in order to set, or raise, the voltage experienced by components of the circuits.

[0069] FIG. 7 illustrates the biasing of rectifier stages 700 and 750. In rectifier stage 700, biasing is provided via a DC voltage bias, which may be referred to as “voltagebiasing”. Rectifier stage 700, which may be one of several stages in a rectifier, includes an NMOS transistor 702 and a PMOS transistor 706, arranged to serve as rectifying elements along a main current path 716. The main current path 716 forrectifier stage 700 begins at anode 730, which is also the drain of transistor 702. The main current path 716 then passes through the source of transistor 702, which is coupled to an RF+ input 720 via a charge-accumulating capacitor and to the drain of transistor 706. The main current path 716 then passes through the source of transistor 706, which serves as cathode 732.

[0070] The gate of transistor 702 is coupled, via a coupling capacitor, to an RF- input 710, which has a different phase than RF+ input 720. The gate of transistor 702 is also coupled to DC bias 704 via RF block 712. which serves to isolate the RF signal originating from RF- input 710 and the DC signal provided by DC bias 704. The DC bias 704 is then coupled to the source of transistor 702. As a result, transistor 702 is voltage-biased, where the bias value is based on the voltage provided by DC bias 704.

[0071] The gate of transistor 706, like the gate of transistor 702, is also coupled to the RF- input 710 via a coupling capacitor. The gate of transistor 706 is further coupled to DC bias 708 via RF block 714, which serves to isolate the RF signal originating from RF- input 710 and the DC signal provided by DC bias 708. The DC bias 708 is then coupled to the source of transistor 706, thereby voltage-biasing transistor 706.

[0072] In rectifier stage 750, biasing is provided via current flowing through biasing transistors, which may be referred to as “current-biasing”. Rectifier stage 750, which may be one of several stages in a rectifier, includes NMOS transistor 752 and PMOS transistor 756, arranged to serve as rectifying elements along a main current path 762. The main current path 762 begins at anode 780, which is also the drain of transistor 752. The main current path 762 then passes through the source of transistor 752, which is coupled to the drain of transistor 756 and also to the RF+ input 720 via a charge-accumulating capacitor. The main current path 762 then passes through the source of transistor 756, which serves as cathode 782.

[0073] The gate of transistor 752 is coupled, via a coupling capacitor, to RF- input 710. A biasing NMOS transistor 754 is disposed between the gate and source of transistor 752, where the gate and source of biasing transistor 754 are coupled to the gate and source, respectively, of transistor 752. The gate of biasing transistor 754 is coupled to its drain and to the output of current source 760. This configuration causes biasing transistor 754 to provide a voltage bias between the gate and source of transistor 752, where the voltage bias value is based on the current provided by thecurrent source 760. The current source 760 may include or be implemented using one or more charge pumps or current mirrors.

[0074] Transistor 756 is configured similarly to transistor 752. The gate of transistor 756 is coupled, via a coupling capacitor, to RF- input 710. A biasing PMOS transistor 758 is disposed between the gate and source of transistor 756, where the gate and source of biasing transistor 758 are coupled to the gate and source, respectively, of transistor 756. The gate of biasing transistor 758 is coupled to its drain and to the input of current source 760. This configuration causes biasing transistor 758 to provide a voltage bias between the gate and source of transistor 756, where the voltage bias value is based on the current associated with the current source 760.

[0075] One way to provide the voltage for biasing rectifying elements is to use charge pumps. A charge pump is similar to a rectifier in that it can generate a DC signal from an AC signal. In one example, each rectifying element in a rectifier may be biased with a separate local charge pump. For example, referring to FIG. 7, each of the DC biases 704 and 708 may be a separate local charge pump. For rectifiers with multiple rectifying elements, this local charge pump biasing technique may require many biasing charge pumps, resulting in excessive power consumption and increased area consumption (on the integrated circuit). An alternative biasing method involves the use of passive resistive ladders, combined with multiple current mirrors to establish precise voltage levels at the initial and end nodes. This technique enables the simultaneous and accurate biasing of multiple rectifying elements. Current flowing through an appropriately designed passive resistive ladder generates multiple biasing voltages, each suitable for a particular rectifying element. This reduces power and area consumption as compared to local charge pump biasing. However, this resistive ladder technique works best when ultra-high resistance elements (on the order of 100+ megaohms) can be implemented with relatively little die area, which may not be the case for more advanced semiconductor technology’ nodes. Also, with high resistance, internal circuit nodes may be associated with relatively large time constants, leading to a slow start-up behavior.

[0076] One approach that may be suitable for advanced semiconductor technology nodes is to use active bias ladders. Active bias ladders, like passive resistive ladders, generate multiple biasing voltages, each suitable for a particular rectifying element. However, in contrast to passive resistive ladders, active bias ladders may have activeelements (e.g., transistors) that are coupled to inputs such as RF inputs. For example, active bias ladders may be implemented as charge pumps with diode-connected transistors coupled to RF inputs as well as rectifying elements (for biasing), resulting in current flow opposite that of passive resistive ladders when the RF input amplitude is large enough for the charge transfer current caused by RF pumping to exceed the DC reverse leakage of the transistors. Compared to passive resistive ladder biasing, active bias ladders may provide faster start-up behavior while occupying less circuit area.

[0077] FIG. 8 illustrates an example rectifier 800 using active bias ladders, according to some embodiments. The rectifier 800 includes a main rectifying chain 802 which may alternatively be referred to as a main current path, first and second active bias ladders 804 and 806, first and second charge pumps 808 and 810. The rectifier 800 also includes first, second, third, and fourth bias voltage tracking circuits 812, 814. 816, and 818. The rectifier 800 is configured to generate a DC voltage from opposing phases of an RF signal. Accordingly, the rectifier 800 is coupled to the two opposing phases, denoted as RFN and RFP. The main rectifying chain 802 includes a series of rectifying elements, configured to rectify the RF signal phases to generate several relatively small DC voltage components. The main rectifying chain 802 may be configured such that all generated DC components are added together, resulting in a DC voltage component output VDD FINAL at its end point. The input, or starting point, of the main rectifying chain 802 is connected to a reference potential GND, which in some cases may be a virtual ground.

[0078] The main rectifying chain 802 includes a series of rectifying stages. In FIG. 8, there are 8 rectifying stages, each of which include one NMOS transistor and one PMOS transistor. The gate of each consecutive NMOS transistor in the main rectifying chain 802 is alternately coupled through a coupling capacitor (labeled as Cl) to either RFN or RFP. Similarly, the gate of each consecutive PMOS transistor in the main rectifying chain 802 is alternately coupled through a coupling capacitor to either RFN or RFP. As mentioned above, coupling capacitors are configured to allow AC signals through while blocking DC signals. In each rectifying stage, the gate of the NMOS and PMOS transistors are coupled to the same RF phase, while the shared node of the NMOS and PMOS transistors is coupled to the opposite RF phase through a capacitor configured to accumulate charge. For example, the shared node between apair of NMOS and PMOS transistors whose gates are coupled to RFN is coupled to RFP through a charge-accumulating capacitor (labeled as CO). Likewise, the node between a pair of NMOS and PMOS transistors whose gates are coupled to RFP is coupled to RFN through a charge-accumulating capacitor.

[0079] As described above, rectifying elements in single-path, synchronous rectifiers such as the rectifier 800 may need to be biased appropriately to efficiently convert AC signals into DC signals. In the rectifier 800, the first active bias ladder 804 is configured to bias each of the NMOS transistor rectifying elements in the main rectifying chain 802, while the second active bias ladder 806 is configured to bias each of the PMOS transistor rectifying elements in the main rectifying chain 802. The first and second active bias ladders 804 and 806 may each include a series of low- threshold or native NMOS biasing transistors arranged in a charge pump configuration. Each NMOS biasing transistor has its gate coupled to its drain as well as to either RF phase RFN or RFP (hence, “active”) through a coupling capacitor (labeled as Cl). The drain of each NMOS biasing transistor in the first active bias ladder 804 is coupled to the gate of a corresponding NMOS rectifying element in the main rectifying chain 802, biasing the respective NMOS rectifying element. The drain of each NMOS biasing transistor in the second active bias ladder 806 is coupled to the gate of a corresponding PMOS rectifying element in the main rectifying chain 802, biasing the respective PMOS rectifying element. Similar to passive resistive ladder biasing, an active bias ladder uses the same bias current to generate multiple voltages to bias all of the NMOS or PMOS rectifying elements in the main rectifying chain 802 simultaneously, in conjunction with additional circuitry to set appropriate starting and ending biasing voltages, described below.

[0080] The use of active bias ladders to bias rectifying elements in a rectifier reduces area and power consumption as compared to using local charge pumps, as described above, because (a) only two charge pumps are needed for all of the NMOS and PMOS rectifying elements in the rectifier as compared to one or more charge pumps per pair of rectifying elements and (b) the biasing elements in each active bias ladder can use / reuse the same bias current. Compared to passive resistive ladders, active bias ladders do not require high resistance elements and can be quicker to start up, because they are powered and driven by the RF signal. In addition, active bias ladders can sharecoupling capacitors with the main rectifying path (e.g., the coupling capacitors Cl), further reducing the required die area.

[0081] In the rectifier 800, additional circuitry is present to set the appropriate starting and ending biasing voltages for the main rectifying chain 802. For the NMOS rectifying elements, an appropriate first biasing voltage for a first NMOS rectifying element (e.g., the leftmost NMOS rectifying element) is set by a first bias generator formed by the combination of the first charge pump 808 and the first bias voltage tracking circuit 812. The first charge pump 808 is coupled to and pumps from the starting point of the main rectifying chain 802 to the starting point of the first active bias ladder 804. The first bias voltage tracking circuit 812 is disposed between the starting point of the first active bias ladder 804 and the drain of the first NMOS rectifying element in the main rectifying chain 802, which, in the rectifier 800, is also the starting point of the main rectifying chain 802. An appropriate second bias voltage for the last NMOS rectifying element (e.g., the rightmost NMOS rectifying element) is set by a second bias generator including the second bias voltage tracking circuit 814, which is coupled between an end point of the first active bias ladder 804 and the drain of the rightmost NMOS rectifying element in the main rectifying chain 802. For the PMOS rectifying elements, an appropriate third bias voltage for a first PMOS rectifying element (e.g., the leftmost PMOS rectifying element) is set by a third bias generator including the third bias voltage tracking circuit 816, which is coupled between the starting point of the second active bias ladder 806 and the drain of the first PMOS rectifying element in the main rectifying chain 802. An appropriate fourth bias voltage for the last PMOS rectifying element (e.g., the rightmost PMOS rectifying element) is set by an fourth bias generator formed by the combination of the second charge pump 810 and the fourth bias voltage tracking circuit 818. The second charge pump 810 is coupled to and pumps from the end point of the second active bias ladder 806 to the output or end point of the main rectifying chain 802, while the fourth bias voltage tracking circuit 818 is disposed between the end point of the second active bias ladder 806 and the drain of the last PMOS rectifying element in the main rectifying chain 802, which is also the end point of the main rectifying chain 802.

[0082] In the rectifier 800. the bias voltage tracking circuits 812 - 818 are diode- connected NMOS and PMOS transistors. In this situation, coupling resistive elements(e.g., first, second, third, and fourth resistors 822, 824, 826, and 828) serve as RF blocks to isolate AC signals from the drain terminals of the diode-connected transistors, thereby ensuring that the signals at those drain terminals are primarily DC and reducing AC signal loss at those transistors. However, bias voltage tracking circuits may be implemented in any other suitable way. In some examples, the bias voltage tracking circuits 812 - 818 are implemented as transistors similar to the rectifying transistors at the beginning and ending of the main rectifying chain 802 in order to track their threshold voltages and any variations due to temperature and manufacturing. The bias voltage tracking circuits 812 - 818 may directly bias the beginning and ending NMOS and PMOS rectifying transistors of the main rectify ing chain 802.

[0083] In some examples, the bias voltage tracking circuits 812 - 818 may be positioned at any other appropriate locations. For example, the source nodes of the bias voltage tracking circuits 812 - 818 can be located externally to the main rectifier chain 802, or at any intermediate rectifier stage. Accordingly, the drain nodes of the bias voltage tracking circuits 812 - 818 can be located externally to the active bias ladders 804 - 806, or at any intermediate active bias ladder stage, with or without coupling resistive elements (such the resistors 822 - 828). The resistance or impedance of the coupling resistive element can be flexible and optimized to increase, or decrease, rectifier performance.

[0084] In FIG.8, the first and second active bias ladders 804 and 806 act as voltage dividers between the bias voltage tracking circuits 812 - 818 to appropriately bias the intermediate NMOS / PMOS rectifying transistors of the main rectifying chain 802. For example, the voltage divider formed by the first active bias ladder 804 may apply a different intermediate bias, e.g. with a value between the first bias voltage and the second bias voltage, to each of the NMOS rectifying transistors of the main rectifying chain 802. Similarly, the voltage divider formed by the second active bias ladder 806 may apply a different intermediate bias, e.g. with a value between the third bias voltage and the fourth bias voltage, to each of the PMOS rectify ing transistors of the main rectifying chain 802. When the amplitude of the RF input is sufficient, there is a current pumping up, flowing upwards from the low potential node to the high potential node, along either of the active bias ladders. In cases where the incident RF amplitude is insufficient, the leakage of the biasing transistors in the active biasladders may surpass the pumping current. This can lead to a current flow from the high potential node to the low potential node along the active bias ladder. In this scenario, the first and second active bias ladders 804 and 806 continue to function as voltage dividers, supplying similar biasing voltage segments for the intermediate rectifying stages of the main rectifying chain 802. This operation can be aided by the inclusion of additional charge pumps or elements that provide current injection (e.g., current mirrors), which serve to charge the drain nodes of the transistors within the bias voltage tracking circuits 812-818.

[0085] In some examples, rectifier biasing may be adjusted by controlling the diode- connected NMOS and PMOS transistors inside the bias voltage tracking circuits 812 — 818. For example, the transistors inside the bias voltage tracking circuits 812 - 818 may contain multiple transistor segments connected in series and / or parallel. Digitally controlled switch transistors, including such connected transistor segments, may allow adjustment of the bias voltages (e g., adjusting a digitally controlled switch transistor in the first bias voltage tracking circuit 812 may adjust the first bias voltage). Rectifier biasing may also be adjusted by changing the number of the stages in the charge pumps 808 and 810, for example by using appropriately coupled digitally controlled switch transistors. For instance, in cases where the incident RF power is elevated, each stage within charge pumps 808 and 810 produces a greater DC voltage increment compared to situations where the incident RF power remains at a lower level. Therefore, under high incident RF power scenarios, the number of stages within charge pumps 808 and 810 may be decreased to maintain an optimal bias state for the main rectifier chain 802.

[0086] Rectifier biasing may be adjusted for any reason. In some embodiments, rectifier biasing may be adjusted to increase or decrease rectifying efficiency. Increasing a rectifier’s rectifying efficiency may address situations where power delivery from the rectifier is undesirably low, preventing other components from operating. Decreasing the rectifier’s rectifying efficiency may address situations where powder delivery from the rectifier is undesirably high, potentially causing undesirable effects and damage to other components. In some embodiments, rectifier biasing may be adjusted to change the input impedance presented by the rectifier. The rectifier input impedance in turn affects the input impedance of an RFID IC containing the rectifier, which then affects how the IC couples with an antenna andinteracts with RF waves. For example, rectifier biasing and input impedance may be adjusted to control impedance matching between the IC and a coupled antenna, or to control impedance differences between different backscatter states, as described in copending and commonly assigned U.S. Patent Application No. 15 / 888,916 (Atty’. Docket No. 5088.0373USI1 / IMPJ-0585), herein incorporated by reference in its entirety.

[0087] While FIG. 8 depicts a synchronous rectifier with eight pairs of NMOS / PMOS rectifying elements, the concepts described herein are applicable to synchronous rectifiers with more or fewer rectifying element pairs. For example, bias current reuse may enable the implementation of a synchronous rectifier with any desired number of rectify ing element pairs, where the number of pairs exceeds the number of bias current paths in the rectifier.

[0088] Optimizations may lead to modifications of the structure of rectifiers. For example, the rectifier 800 depicts the various bias voltage tracking circuits being coupled to the outer (i.e., first and last) rectifying stages. However, in other examples one or more bias voltage tracking circuits may be coupled to one or more intermediate rectifying stages. If so, the bias voltage tracking circuit may not be coupled to a corresponding charge pump. Similarly, while FIG. 8 depicts only the first and fourth bias generators as including a charge pump, any of the four bias generators may or may not include a bias voltage tracking circuit, an RF block or resistive element, and a charge pump. In addition, the connections of various components of the rectifier 800 may be modified to modify performance. For example, the fourth resistive element 828 may instead connect the fourth bias voltage tracking circuit 818 to the gate of the rightmost PMOS element. In other examples, additional circuit components may be added to the rectifier 800. Such examples may include adding a diode-connected transistor to the start (left side) of the second charge pump 810, such that it has a similar structure to the first charge pump 810. Another such example may include adding a diode-connected transistor to the start (left side) of the first active bias ladder 804, similarly to how the diode-connected transistor of the second active bias ladder 806 is depicted.

[0089] For the various transistors described herein, the drain and source nodes of the transistors may be switched based on the applied voltage potentials. This allows for designation of the terminals to be reversed: for example, the terminal acting as the“drain’" and the terminal acting as the “source"’ can be switched, depending on which terminal has a higher voltage. Accordingly, implementations of rectifiers, active bias ladders, charge pumps, and bias voltage tracking circuits described herein with certain elements coupled to a transistor’s drain may also equivalently function with the elements coupled to the transistor’s source, and vice-versa.

[0090] According to some examples, a rectifier for a Radio Frequency Identification (RFID) integrated circuit (IC) may include a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled NMOS and PMOS rectifying elements. The rectifier may additionally include a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain. The rectifier may further include a first bias generator coupled to the first active bias ladder and the main rectifying chain. The first bias generator may be configured to provide a first bias to the first active bias ladder. The first bias generator may include: a first charge pump coupled to a first point of the main rectify ing chain; and a first bias voltage tracking circuit coupled to a first point of the first active bias ladder, and a first NMOS rectifying element in the main rectifying chain. The rectifier may also include a second bias generator coupled to the first active bias ladder and the main rectifying chain. The second bias generator may be configured to provide a second bias to the first active bias ladder. The second bias generator may include a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectifying chain.

[0091] According to other examples, the rectifier may further include a second active bias ladder configured to bias the PMOS rectifying elements in the main rectifying chain. The rectifier may also include a third bias generator coupled to the second active bias ladder and the main rectifying chain. The third bias generator may be configured to provide a third bias to the second active bias ladder. The third bias generator may comprise a third bias voltage tracking circuit coupled to a first point of the second active bias ladder and a first PMOS rectifying element in the main rectifying chain. The rectifier may additionally include a fourth bias generator coupled to the second active bias ladder and the main rectify ing chain, wherein the fourth bias generator is configured to provide a fourth bias to the second active bias ladder. The fourth bias generator may comprise a second charge pump coupled to a second point of the main rectifying chain and a fourth bias voltage tracking circuitcoupled to a second point of the second active bias ladder and a second PMOS rectifying element in the main rectifying chain. Each of the first bias voltage tracking circuit and the second bias voltage tracking circuit may comprise a diode-connected NMOS transistor. Similarly, each of the third bias voltage tracking circuit and the fourth bias voltage tracking circuit may comprise a diode-connected PMOS transistor.

[0092] According to yet other examples, the rectifier may further include first and second resistive elements. The first bias voltage tracking circuit may be coupled to the first NMOS rectifying element in the main rectifying chain at: a drain of the first NMOS rectifying element; and a gate of the first NMOS rectifying element through the first resistive element. The second bias voltage tracking circuit may be coupled to the second NMOS rectifying element in the main rectifying chain at: a drain of the second NMOS rectifying element; and a gate of the second NMOS rectifying element through the second resistive element. In some examples, such as when the rectifier includes a second active bias ladder, a third bias voltage tracking circuit, and a fourth bias voltage tracking circuit, the rectifier may further comprise third and fourth resistive elements. The third bias voltage tracking circuit may be coupled to the first PMOS rectifying element of the main rectifying chain at: a drain of the first PMOS rectifying element; and a gate of the first PMOS rectifying element through the third resistive element. The fourth bias voltage tracking circuit may be coupled to the second PMOS rectifying element of the main rectify ing chain at a drain of the second PMOS rectifying element. The fourth bias voltage tracking circuit may also be coupled to a gate of the second PMOS rectifying element, or the second charge pump, through the fourth resistive element.

[0093] According to further examples, each rectifying element in the main rectifying chain may be coupled to one of two opposing phases of a radio frequency signal. The rectifier may be a synchronous rectifier. In some examples, each transistor of the first active ladder and the second active ladder that is coupled to a rectifying element of the main rectifying chain may be coupled to one or two opposing phases of a radio frequency signal. The first charge pump and the first voltage tracking circuit may be configurable to adjust the first bias based on an output voltage generated by the rectifier. In some examples, the first charge pump may be configurable to adjust the first bias by limiting a number of operational stages within the first charge pump. Similarly, the second charge pump may be configurable to adjust the fourth bias bylimiting a number of operational stages within the second charge pump. In other examples, the first bias voltage tracking circuit may include a plurality of connectable transistor segments and may be configurable to adjust the first bias by connecting or disconnecting at least one of the connectable transistor segments. In some examples, the second bias voltage tracking circuit may be configurable to adjust the second bias based on the output voltage by connecting or disconnecting at least one of a plurality of connectable transistor segments of the second bias voltage tracking circuit. Examples described can be extended to the third bias voltage tracking circuit and the fourth bias voltage tracking circuit, each including a plurality of connectable transistor segments that can be configured to, respectively, adjust the third and fourth bias based on the output voltage generated by the rectifier. In other examples, the second bias generator may further include a third charge pump, and the third bias generator may also further include a fourth charge pump. Only some and not all of the rectifying stages of the main rectifying chain may be directly coupled to any of the first, second, third, or fourth bias generators.

[0094] According to some examples, a Radio Frequency Identification (RFID) integrated circuit (IC) may comprise an antenna port and a rectifier coupled to the antenna port. The rectifier may include a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled NMOS and PMOS rectifying elements. The rectifier may additionally include a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain. The rectifier may further include a first bias generator coupled to the first active bias ladder and the main rectifying chain. The first bias generator may be configured to provide a first bias to the first active bias ladder. The first bias generator may include: a first charge pump coupled to a starting point of the main rectifying chain; and a first bias voltage tracking circuit coupled to a first point of the first active bias ladder and a first NMOS rectifying element in the main rectifying chain. The rectifier of the RFID IC may also include a second bias generator coupled to the first active bias ladder and the main rectifying chain. The second bias generator may be configured to provide a second bias to the first active bias ladder. The second bias generator may include a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectify ing chain.

[0095] According to other examples, the rectifier of the RFID IC may may further include a second active bias ladder configured to bias the PMOS rectifying elements in the main rectifying chain. The rectifier may also include a third bias generator coupled to the second active bias ladder and the main rectifying chain. The third bias generator may be configured to provide a third bias to the second active bias ladder. The third bias generator may comprise a third bias voltage tracking circuit coupled to a first point of the second active bias ladder and a first PMOS rectifying element in the main rectifying chain. The rectifier may additionally include a fourth bias generator coupled to the second active bias ladder and the main rectifying chain, wherein the fourth bias generator is configured to provide a fourth bias to the second active bias ladder. The fourth bias generator may comprise a second charge pump coupled to a second point of the main rectifying chain; and a fourth bias voltage tracking circuit coupled to a second point of the second active bias ladder, and a second PMOS rectifying element in the main rectifying chain. Each of the first bias voltage tracking circuit and the second bias voltage tracking circuit may comprise a diode-connected NMOS transistor. Similarly, each of the third bias voltage tracking circuit and the fourth bias voltage tracking circuit comprise a diode-connected PMOS transistor.

[0096] According to yet other examples, the rectifier of the RFID IC may further include first and second resistive elements. The first bias voltage tracking circuit may be coupled to the first NMOS rectifying element in the main rectifying chain at: a drain of the first NMOS rectifying element; and a gate of the first NMOS rectifying element through the first resistive element. The second bias voltage tracking circuit may be coupled to the second NMOS rectify ing element in the main rectifying chain at: a drain of the second NMOS rectifying element; and a gate of the second NMOS rectifying element through the second resistive element. In some examples, such as when the rectifier of the RFID IC includes a second active bias ladder, a third bias voltage tracking circuit, and a fourth bias voltage tracking circuit, the rectifier may further comprise third and fourth resistive elements. The third bias voltage tracking circuit may be coupled to the first PMOS rectifying element of the main rectifying chain at: a drain of the first PMOS rectifying element; and a gate of the first PMOS rectifying element through the third resistive element. The fourth bias voltage tracking circuit may be coupled to the second PMOS rectifying element of the main rectifyingchain at a drain of the second PMOS rectifying element. The fourth bias voltage tracking circuit may also be coupled to a gate of the second PMOS rectifying element, or the second charge pump, through the fourth resistive element.

[0097] According to further examples, each rectifying element in the main rectifying chain may be coupled to one of two opposing phases of a radio frequency signal. The rectifier of the RFID IC may be a synchronous rectifier. In some examples, each transistor of the first active ladder and the second active ladder that is coupled to a rectifying element of the main rectifying chain may be coupled to one or two opposing phases of a radio frequency signal. The first charge pump and the first voltage tracking circuit may be configurable to adjust the first bias based on an output voltage generated by the rectifier. In some examples, the first charge pump may be configurable to adjust the first bias by limiting a number of operational stages within the first charge pump. Similarly, the second charge pump may be configurable to adjust the end bias by limiting a number of operational stages within the second charge pump. In other examples, the first bias voltage tracking circuit may include a plurality of connectable transistor segments and may be configurable to adjust the first bias by connecting or disconnecting at least one of the connectable transistor segments. In some examples, the second bias voltage tracking circuit may be configurable to adjust the second bias based on the output voltage by connecting or disconnecting at least one of a plurality of connectable transistor segments of the second bias voltage tracking circuit. Examples described can be extended to the third bias voltage tracking circuit and the fourth bias voltage tracking circuit, each including a plurality of connectable transistor segments that can be configured to, respectively, adjust the third and fourth bias based on the output voltage generated by the rectifier. In other examples, the second bias generator may further include a third charge pump, and the third bias generator may also further include a fourth charge pump. Only some and not all of the rectify ing stages of the main rectify ing chain may be directly coupled to any of the first, second, third, or fourth bias generators.

[0098] The foregoing detailed description has set forth various embodiments of the devices and / or processes via the use of block diagrams and / or examples. Insofar as such block diagrams and / or examples contain one or more functions and / or aspects, it will be understood by those within the art that each function and / or aspect within such block diagrams or examples may be implemented individually and / or collectively, bya wide range of hardware, software, firmware, or virtually any combination thereof. Those skilled in the art will recognize that some aspects of the RFID embodiments disclosed herein, in whole or in part, may be equivalently implemented employing integrated circuits, as one or more computer programs running on one or more computers (e.g., as one or more programs running on one or more computer systems), as one or more programs running on one or more processors (e.g. as one or more programs running on one or more microprocessors), as firmware, or as virtually any combination thereof, and that designing the circuitry and / or writing the code for the software and / or firmware would be well within the skill of one of skill in the art in light of this disclosure.

[0099] The present disclosure is not to be limited in terms of the particular embodiments described in this application, which are intended as illustrations of various aspects. Many modifications and variations can be made without departing from its spirit and scope, as will be apparent to those skilled in the art. Functionally equivalent methods and apparatuses within the scope of the disclosure, in addition to those enumerated herein, will be apparent to those skilled in the art from the foregoing descriptions. Such modifications and variations are intended to fall within the scope of the appended claims. The present disclosure is to be limited only by the terms of the appended claims, along with the full scope of equivalents to which such claims are entitled. It is to be understood that this disclosure is not limited to particular methods, configurations, antennas, transmission lines, and the like, which can, of course, vary. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to be limiting.

[0100] With respect to the use of substantially any plural and / or singular terms herein, those having skill in the art can translate from the plural to the singular and / or from the singular to the plural as is appropriate to the context and / or application. The various singular / plural permutations may be expressly set forth herein for sake of clarity.

[0101] It will be understood by those within the art that, in general, terms used herein, and especially in the appended claims (e.g., bodies of the appended claims) are generally intended as “open” terms (e.g., the term “including” should be interpreted as “including but not limited to,” the term “having” should be interpreted as “having atleast,” the term “includes” should be interpreted as “includes but is not limited to,” etc.). It will be further understood by those within the art that if a specific number of an introduced claim recitation is intended, such an intent will be explicitly recited in the claim, and in the absence of such recitation no such intent is present. For example, as an aid to understanding, the following appended claims may contain usage of the introductory phrases "at least one" and "one or more" to introduce claim recitations. However, the use of such phrases should not be construed to imply that the introduction of a claim recitation by the indefinite articles "a" or "an" limits any particular claim containing such introduced claim recitation to embodiments containing only one such recitation, even when the same claim includes the introductory phrases "one or more" or "at least one" and indefinite articles such as "a" or "an" (e.g., “a” and / or “an” should be interpreted to mean “at least one” or “one or more”); the same holds true for the use of definite articles used to introduce claim recitations. In addition, even if a specific number of an introduced claim recitation is explicitly recited, those skilled in the art will recognize that such recitation should be interpreted to mean at least the recited number (e.g.. the bare recitation of "two recitations," without other modifiers, means at least two recitations, or two or more recitations).

[0102] Furthermore, in those instances where a convention analogous to “at least one of A, B, and C, etc.” is used, in general such a construction is intended in the sense one having skill in the art would understand the convention (e.g., “ a system having at least one of A, B, and C” would include but not be limited to systems that have A alone, B alone, C alone, A and B together, A and C together, B and C together, and / or A, B, and C together, etc.). It will be further understood by those within the art that virtually any disjunctive word and / or phrase presenting two or more alternative terms, whether in the description, claims, or drawings, should be understood to contemplate the possibilities of including one of the terms, either of the terms, or both terms. For example, the phrase “A or B” will be understood to include the possibilities of “A” or “B” or “A and B.”

[0103] As will be understood by one skilled in the art, for any and all purposes, such as in terms of providing a written description, all ranges disclosed herein also encompass any and all possible subranges and combinations of subranges thereof. Any listed range can be easily recognized as sufficiently describing and enabling thesame range being broken down into at least equal halves, thirds, quarters, fifths, tenths, etc. As a non-limiting example, each range discussed herein can be readily broken down into a lower third, middle third and upper third, etc. As will also be understood by one skilled in the art all language such as “up to,” “at least,” “greater than,” “less than,” and the like include the number recited and refer to ranges which can be subsequently broken down into subranges as discussed above. Finally, as will be understood by one skilled in the art, a range includes each individual member. Thus, for example, a group having 1-3 cells refers to groups having 1, 2, or 3 cells. Similarly, a group having 1-5 cells refers to groups having 1, 2, 3, 4, or 5 cells, and so forth.

Claims

CLAIMSWE CLAIM:

1. A rectifier for a Radio Frequency Identification (RFID) integrated circuit (IC), the rectifier comprising: a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled NMOS and PMOS rectifying elements; a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain; a first bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the first bias generator is configured to provide a first bias to the first active bias ladder and comprises: a first charge pump coupled to a first point of the main rectifying chain; and a first bias voltage tracking circuit coupled to the first charge pump, a first point of the first active bias ladder, and a first NMOS rectifying element in the main rectifying chain; and a second bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the second bias generator is configured to provide a second bias to the first active bias ladder and comprises: a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectifying chain.

2. The rectifier of claim 1, further comprising: a second active bias ladder configured to bias the PMOS rectifying elements in the main rectifying chain; a third bias generator coupled to the second active bias ladder and the main rectifying chain, wherein the third bias generator is configured to provide a third bias to the second active bias ladder and comprises: a third bias voltage tracking circuit coupled to a first point of the second active bias ladder and a first PMOS rectifying element in the main rectifying chain; anda fourth bias generator coupled to the second active bias ladder and the main rectifying chain, wherein the fourth bias generator is configured to provide a fourth bias to the second active bias ladder and comprises: a second charge pump coupled to a second point of the main rectifying chain; and a fourth bias voltage tracking circuit coupled to the second charge pump, a second point of the second active bias ladder, and a second PMOS rectifying element in the main rectifying chain.

3. The rectifier of claim 2, wherein: each of the first bias voltage tracking circuit and the second bias voltage tracking circuit comprise a diode-connected NMOS transistor; and each of the third bias voltage tracking circuit and the fourth bias voltage tracking circuit comprise a diode-connected PMOS transistor.

4. The rectifier of claim 1, further comprising first and second resistive elements, wherein: the first bias voltage tracking circuit is coupled to the first NMOS rectifying element in the main rectifying chain at: a drain of the first NMOS rectifying element; and a gate of the first NMOS rectifying element through the first resistive element; and the second bias voltage tracking circuit is coupled to the second NMOS rectifying element in the main rectifying chain at: a drain of the second NMOS rectifying element; and a gate of the second NMOS rectifying element through the second resistive element.

5. The rectifier of claim 2, further comprising third and fourth resistive elements, wherein: the third bias voltage tracking circuit is coupled to the first PMOS rectifying element of the main rectifying chain at: a drain of the first PMOS rectifying element: anda gate of the first PMOS rectifying element through the third resistive element; and the fourth bias voltage tracking circuit is coupled to a second PMOS rectifying element of the main rectify ing chain at: a drain of the second PMOS rectify ing element; and a gate of the second PMOS rectifying element, or the second charge pump, through the fourth resistive element.

6. The rectifier of claim 1, wherein each transistor of the first active ladder and the second active ladder that is coupled to a rectify ing element of the main rectify ing chain is coupled to one of two opposing phases of a radio frequency signal.

7. The rectifier of claim 1, wherein at least one of the first charge pump and the first bias voltage tracking circuit is configurable to adjust the first bias based on an output voltage generated by the rectifier.

8. The rectifier of claim 7, wherein: the first charge pump is configurable to adjust the first bias by limiting a number of operational stages within the first charge pump; the first bias voltage tracking circuit includes a plurality of connectable transistor segments; and the first bias voltage tracking circuit is configurable to adjust the first bias by connecting or disconnecting at least one of the connectable transistor segments.

9. The rectifier of claim 1, wherein only some and not all of the rectify ing stages of the main rectifying chain are directly coupled to any of the first, second, third, or fourth bias generators.

10. A Radio Frequency Identification (RFID) integrated circuit (IC) comprising: an antenna port; and a rectifier coupled to the antenna port, the rectifier comprising: a main rectifying chain comprising three or more rectifying stages, wherein each rectifying stage includes a pair of sequentially coupled NMOS and PMOS rectifying elements;a first active bias ladder configured to bias the NMOS rectifying elements in the main rectifying chain; a first bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the first bias generator is configured to provide a first bias to the first active bias ladder and comprises: a first charge pump coupled to a first point of the main rectifying chain; and a first bias voltage tracking circuit coupled to the first charge pump, a first point of the first active bias ladder, and a first NMOS rectifying element in the main rectifying chain; and a second bias generator coupled to the first active bias ladder and the main rectifying chain, wherein the second bias generator is configured to provide a second bias to the first active bias ladder and comprises: a second bias voltage tracking circuit coupled to a second point of the first active bias ladder and a second NMOS rectifying element in the main rectifying chain.

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