Bit capacitor and quantum chip

Abstract

The present application relates to the field of quantum computing, and discloses a bit capacitor and a quantum chip. The bit capacitor comprises a first metal plate, a second metal plate, and a Josephson junction; a first end of the Josephson junction is connected to the first metal plate, and a second end of the Josephson junction is connected to the second metal plate; sub-metal sheets are arranged on the first metal plate and / or the second metal plate; and the lengths of the sub-metal sheets are smaller than those of the first metal plate and the second metal plate. According to the present application, the first metal plate and the second metal plate are connected by means of the Josephson junction to form a bit capacitor of a double-island structure, thereby providing a larger line layout space to prevent mutual interference between different signal lines. The sub-metal sheets are arranged on the first metal plate and the second metal plate, thereby increasing the parallel capacitance of the first metal plate and the second metal plate, and increasing the equivalent capacitance value of the bit capacitor of the double-island structure. The overall capacitance value of the bit capacitor can be changed by adjusting the capacitance values of the sub-metal sheets, so that the overall size of the bit capacitor does not need to be adjusted, and the design cost is reduced.

Description

A bit capacitor and quantum chip Technical Field

[0001] The present application relates to the field of quantum computing, and in particular to a bit capacitor and a quantum chip. Background Art

[0002] The quantum chip is the core component of a quantum computer. It integrates quantum bits and related circuits on a substrate, thereby carrying the function of quantum information processing. Typically, a quantum chip includes multiple quantum devices such as bit capacitors and resonant cavities. Among them, the bit capacitor is generally composed of a single independent metal sheet and the chip ground to form a coplanar waveguide (CPW) structure. Currently, the metal sheet of the bit capacitor usually uses a cross-shaped metal sheet or a cross-shaped metal sheet to increase the facing area of ​​the bit capacitor, thereby increasing the capacitance of the bit capacitor.

[0003] Figure 1 is a structural diagram of a cross-shaped bit capacitor provided by an embodiment of the present application. As shown in Figure 1, the size of the bit capacitor in the form of a cross-shaped metal sheet is comparable to the size in the case of a 1 / 4 wavelength resonator meandering layout. In the quantum chip array, the bit capacitor expands in two dimensions. As the number of bits increases, the layout space reserved for the pulse control signal line (XY control line), the frequency control signal line (Z control line), and the quantum bit reading line is relatively small. In order to meet the wiring requirements, it is necessary to sacrifice the isolation index between different signal lines, which may cause mutual interference between different signal lines and affect the normal operation of the system. At the same time, when the capacitance requirements of each bit capacitor in the quantum chip array change, the size of the bit capacitor also changes, causing the quantum chip to need to be redesigned, increasing the design cost of the chip.

[0004] Therefore, it can be seen that how to provide a new bit capacitor to prevent mutual interference between different signal lines due to a small wiring space is a problem that needs to be solved urgently by those skilled in the art.

[0005] Summary of the Invention

[0006] The purpose of this application is to solve the problem in the prior art that the layout space reserved for bit capacitors in the form of cross-shaped metal sheets is small, which may cause mutual interference between different signal lines, and the problem of increased chip design costs caused by the need to redesign all bit capacitors in the array when the capacitance requirements of the bit capacitors change during the design process. A bit capacitor and quantum chip are provided to provide a larger circuit layout space to prevent mutual interference between different signal lines.

[0007] In order to solve the above technical problems, the present application provides a bit capacitor, comprising:

[0008] a first metal plate, a second metal plate, and a Josephson junction;

[0009] The first end of the Josephson junction is connected to the first metal plate, and the second end of the Josephson junction is connected to the second metal plate;

[0010] A sub-metal sheet is provided on the first metal plate and / or the second metal plate; and the sub-metal sheet is shorter than the first metal plate and the second metal plate.

[0011] Preferably, the first metal plate and the second metal plate each include a first metal arm and a second metal arm;

[0012] The included angle between the first metal arm and the second metal arm is 90 degrees.

[0013] Preferably, the first metal plate and the second metal plate have the same shape and the same area.

[0014] Preferably, the sub-metal sheet includes a first I-shaped metal sheet and a second I-shaped metal sheet;

[0015] The first I-shaped metal sheet and the second I-shaped metal sheet each include a third metal arm, a fourth metal arm, and a fifth metal arm, and the third metal arm, the fourth metal arm, and the fifth metal arm are all linear metal arms;

[0016] The third metal arm is parallel to the fifth metal arm, and the third metal arm and the fifth metal arm are both perpendicular to the fourth metal arm;

[0017] The first end of the fourth metal arm is connected to the midpoint of the third metal arm, and the second end of the fourth metal arm is connected to the midpoint of the fifth metal arm;

[0018] The center point of the fourth metal arm of the first I-shaped metal sheet is arranged on the first metal arm of the first metal plate and / or the second metal plate;

[0019] The center point of the fourth metal arm of the second I-shaped metal sheet is arranged on the second metal arm of the first metal plate and / or the second metal plate.

[0020] Preferably, the sub-metal sheet is a snowflake-shaped metal sheet;

[0021] The snowflake-shaped metal sheet includes a straight metal arm and at least one angular metal arm;

[0022] The right-angled vertex of each of the angled metal arms is arranged on the straight metal arm, and one end of the straight metal arm is connected to the intersection of the first metal arm and the second metal arm of the first metal plate and / or the second metal plate;

[0023] The opening direction of each of the angled metal arms is the same as the opening direction of the metal plate to which the straight metal arm is connected.

[0024] Preferably, the sub-metal sheet includes a first dumbbell-shaped metal sheet and a second dumbbell-shaped metal sheet;

[0025] The first dumbbell-shaped metal sheet and the second dumbbell-shaped metal sheet each include: a first U-shaped metal arm, a second U-shaped metal arm and a straight metal arm;

[0026] The first end of the straight metal arm is connected to the midpoint of the bottom edge of the first U-shaped metal arm, and the second end of the straight metal arm is connected to the midpoint of the bottom edge of the second U-shaped metal arm;

[0027] The midpoint of the straight metal arm of the first dumbbell-shaped metal sheet is fixed to the first metal arm and / or the second metal arm of the first metal plate, and the midpoint of the straight metal arm of the second dumbbell-shaped metal sheet is fixed to the first metal arm and / or the second metal arm of the second metal plate.

[0028] Preferably, it further comprises: a pulse control signal line and a frequency control signal line;

[0029] The pulse control signal line is connected to the control electrode of the bit capacitor to control the excitation state of the bit capacitor;

[0030] The frequency control signal line is connected to the Josephson junction to control the frequency of the bit capacitor.

[0031] Preferably, the substrates of the first metal plate, the second metal plate and the sub-metal sheet are silicon or sapphire connected to the metal plates through bonding technology.

[0032] In order to solve the above technical problems, the present application also provides a quantum chip, including the bit capacitor.

[0033] Preferably, the bit capacitors are connected in a fixed coupling manner.

[0034] The present application provides a bit capacitor, comprising: a first metal plate, a second metal plate and a Josephson junction; the first end of the Josephson junction is connected to the first metal plate, and the second end of the Josephson junction is connected to the second metal plate; a sub-metal sheet is provided on the first metal plate and / or the second metal plate; the length of the sub-metal sheet is less than that of the first metal plate and the second metal plate. It can be seen that in the technical solution provided by the present application, the first metal plate and the second metal plate are connected through the Josephson junction to form a bit capacitor of a double-island structure, thereby providing a larger circuit layout space to prevent mutual interference between different signal lines. At the same time, a sub-metal sheet is provided on the first metal plate and the second metal plate to achieve the purpose of increasing the parallel capacitance of the first metal plate and the second metal plate, thereby increasing the equivalent capacitance value of the two parts of the double-island structure bit capacitor. In addition, in the bit capacitor design stage, the overall capacitance of the bit capacitor can be changed by adjusting the capacitance of the sub-metal sheet, without adjusting the size of the bit capacitor, thereby reducing the design cost.

[0035] In addition, the present application also provides a quantum chip, including the above-mentioned bit capacitor, with the same effect as above. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0037] FIG1 is a structural diagram of a cross-shaped bit capacitor provided in an embodiment of the present application;

[0038] FIG2 is an equivalent circuit diagram of a cross-shaped bit capacitor provided in an embodiment of the present application;

[0039] FIG3 is a structural diagram of a dual-island structure bit capacitor provided in an embodiment of the present application;

[0040] FIG4 is an equivalent circuit diagram of a dual-island structure bit capacitor provided in an embodiment of the present application;

[0041] FIG5 is a structural diagram of a bit capacitor provided in an embodiment of the present application;

[0042] FIG6 is an equivalent circuit diagram of a bit capacitor provided in an embodiment of the present application;

[0043] FIG7 is a structural diagram of another I-shaped bit capacitor provided in an embodiment of the present application;

[0044] FIG8 is a schematic diagram of a bit capacitor structure of a quantum chip provided in an embodiment of the present application;

[0045] FIG9 is a structural diagram of a snowflake-shaped bit capacitor provided in an embodiment of the present application;

[0046] FIG10 is a structural diagram of another snowflake-shaped bit capacitor provided in an embodiment of the present application;

[0047] FIG11 is a schematic diagram of a bit capacitor structure of another quantum chip provided in an embodiment of the present application;

[0048] FIG12 is a structural diagram of a dumbbell-shaped bit capacitor provided in an embodiment of the present application;

[0049] The figure numbers are as follows: 1 is the first metal plate, 2 is the second metal plate, 3 is the Josephson junction, 4 is the first metal arm, 5 is the second metal arm, 6 is the first I-shaped metal plate, 7 is the second I-shaped metal plate, 8 is the third metal arm, 9 is the fourth metal arm, 10 is the fifth metal arm, 11 is the straight metal arm of the snowflake-shaped bit capacitor, 12 is the angular metal arm, 13 is the first dumbbell-shaped metal plate, 14 is the second dumbbell-shaped metal plate, 15 is the first U-shaped metal arm, 16 is the second U-shaped metal arm, 101 is the bit capacitor, 102 is the cross-shaped bit capacitor, 103 is the chip ground, 104 is the resonator, 105 is the Z control line, 106 is the XY control line, and 107 is the read line. DETAILED DESCRIPTION

[0050] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0051] The core of this application is to provide a bit capacitor and quantum chip, thereby providing a larger circuit layout space to prevent mutual interference between different signal lines and improve the reliability of the bit capacitor.

[0052] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0053] The quantum chip is the core component of a quantum computer. A quantum chip includes multiple quantum devices such as bit capacitors and resonant cavities. Among them, the bit capacitor usually includes a metal sheet and a chip ground 103. The metal sheets commonly used at present are mostly cross-shaped metal sheets to improve the coherence time of the bit capacitor and achieve better control accuracy and lower energy consumption. In addition, the design of the cross-shaped metal sheet can also improve the control accuracy of the quantum bit and reduce the energy consumption of the bit capacitor. This improves the performance and reliability of the bit capacitor, thereby achieving more stable and accurate quantum computing operations. The size of this type of bit capacitor is comparable to the size of the 1 / 4 wavelength resonator 104 in the case of a serpentine layout. For example, on a sapphire substrate with a thickness of 500um, when the capacitance value of the bit capacitor is 84fF, the size of the cross-shaped bit capacitor is approximately 550um*550um, and the size of the 1 / 4 wavelength resonator 104 in the case of a serpentine layout is approximately 420um*420um. As the number of bits increases, the quantum bits expand in two dimensions. At this time, the layout space reserved for the XY control line 106, the Z control line 105, and the read line 107 is small. It is usually necessary to sacrifice the isolation index between the signal lines to meet the wiring requirements, resulting in the normal operation of the quantum chip being affected. Figure 2 is an equivalent circuit diagram of a cross-shaped bit capacitor provided in an embodiment of the present application. As shown in Figures 1 and 2, in the cross-shaped bit capacitor 102, the Josephson junction 3 is connected across the metal plate 102 of the cross-shaped bit capacitor and the chip ground 103, and the equivalent inductance is L j A bit capacitor C is formed between the metal plate of the cross-shaped bit capacitor 102 and the chip ground 103 q The resonator 104, the Z control line 105, the XY control line 106 and the read line 107 are coupled to the "cross" bit capacitor 102 in different planes. A coupling capacitor C is formed between the cross bit capacitor 102 and the resonator 104. g The Z control line 105 applies magnetic flux to the Josephson junction 3 through mutual inductance. As the number of bits increases, the qubits expand in two dimensions. At this point, the layout space reserved for the XY control line 106, the Z control line 105, and the readout line 107 is small, and the isolation between signal lines usually needs to be sacrificed to meet wiring requirements. Based on the equivalent circuit model and series-parallel relationship in Error! Reference source not found, the impedance in the dashed box can be calculated as:

[0054] Assume that the numerator of the above formula = 0, considering C g <<C q , we can get the series resonant frequency ω 01 for:

[0055] Assuming the denominator of the above equation = 0, the parallel resonant frequency ω can be obtained 02 for:

[0056] It can be seen that the actual capacitance of the bit capacitor of the "cross-shaped" structure is C q .

[0057] In order to solve this problem, the present application provides a bit capacitor, comprising: a first metal plate 1, a second metal plate 2 and a Josephson junction 3; the first end of the Josephson junction 3 is connected to the first metal plate 1, and the second end of the Josephson junction 3 is connected to the second metal plate 2; a sub-metal sheet is provided on the first metal plate 1 and / or the second metal plate 2; the length of the sub-metal sheet is less than the first metal plate 1 and the second metal plate 2. It can be seen that the technical solution provided by the present application is that the first metal plate 1 and the second metal plate 2 are connected through the Josephson junction 3 to form a bit capacitor with a double-island structure, thereby providing a larger circuit layout space to prevent mutual interference between different signal lines. At the same time, a sub-metal sheet is provided on the first metal plate 1 and the second metal plate 2, so as to achieve the purpose of increasing the parallel capacitance of the first metal plate 1 and the second metal plate 2, thereby increasing the equivalent capacitance value of the two parts of the double-island structure bit capacitor. In addition, in the bit capacitor design stage, the overall capacitance of the bit capacitor can be changed by adjusting the capacitance of the sub-metal sheet, without adjusting the size of the bit capacitor, thereby reducing the design cost.

[0058] FIG3 is a structural diagram of a dual-island structure bit capacitor provided by an embodiment of the present application. As shown in FIG3 , the dual-island structure includes two separate island-shaped metal sheets, which are connected by a Josephson junction 3. The Josephson junction 3 is connected between a first metal plate 1 and a second metal plate 2 of similar size. The equivalent inductance is L j The first metal plate 1 and the second metal plate 2 are both bent into a 90° shape, and self-capacitance C is formed between the first metal plate 1 and the second metal plate 2 and the chip ground 103. q1 and C q2 , a coupling capacitor C is formed between the first metal plate 1 and the second metal plate 2 12 The resonator 104, the Z control line 105, the XY control line 106 and the read line 107 are coupled to the first metal plate 1 and the second metal plate 2 of the double-island structure bit capacitor in different planes. The resonator 104 and the first metal plate 1 and the second metal plate 2 form coupling capacitors C g1 and C g2 FIG4 is an equivalent circuit diagram of a dual-island structure bit capacitor provided by an embodiment of the present application. As shown in FIG4 , based on Hough's law, the following equations can be listed:

[0059] Among them, i1, i2, i3, i4, and i5 are the current values ​​of each circuit in Figure 4, and I is the current value in the main circuit.

[0060] In loop ①, we can get:

[0061] In loop ②, we can get:

[0062] Among them, jω is a complex unit,

[0063] After i2, i3, i4, and i5 are represented by i1, the impedance in the dotted box can be obtained as:

[0064] From the numerator = 0, consider C g1 、C g2 and C 12 Much smaller than C q1 and C q2 , the series resonant frequency can be obtained as:

[0065] in is the approximate equivalent bit capacitance.

[0066] Similarly, from the denominator = 0, consider C g1 、C g2 and C 12 Much smaller than C q1 and C q2 , the parallel resonant frequency can be obtained:

[0067] in

[0068] Since the bit capacitor of the double-island structure is composed of two metal pieces of similar size, under the same size, there are C q1 ≈C q2 ≈2C q Compared to the traditional "M-shaped" structure, the dual-island structure has a larger overall size, leaving more space for signal lines and readout lines 107, making it more convenient for on-chip layout. However, in the dual-island structure, the Josephson junction 3 must be connected across the first metal plate and the second metal plate. That is, the Z control line 105 must extend to the center of the bit capacitor to apply magnetic flux to the Josephson junction 3. This requires the resonator 104 wiring to bypass the center of the bit capacitor (the dotted box area) and the Z control line 105 wiring area (the lower left corner), as shown in Figure 3.

[0069] For a given design capacitance value C q (Capacitor C q1 and C q2 The sum of the capacitance values ​​after parallel connection). When the designed capacitance value is determined, C q1 Indicates C q2 ,have:

[0070] Since the capacitor size is positively correlated with the capacitance value, considering the simplest case, the size (side length) l of the bit capacitor is:

[0071] Where k is a constant.

[0072] C q1 Seek the derivation, There is C q1 ≥2C q , that is, C q1 =2C q When , the bit capacitor has a minimum size.

[0073] It can be seen that its minimum size is four times that of the "M-shaped" structure (without considering the size of the gap with the ground and the width of the bit capacitor). This means that the dual-island structure can indeed increase the space for the resonant cavity, XY control line 106, Z control line 105 and reading line 107, but the increased size is too much and cannot be reduced (because of the existence of a minimum size). This will result in a larger overall chip size, which is different from the chip size of other solutions, and the packaging box and printed circuit board (PCB) must be customized. At the same time, the increase in chip size will also lead to a decrease in integration, which will inevitably have an impact on various aspects of design.

[0074] FIG5 is a structural diagram of a bit capacitor provided in an embodiment of the present application. As shown in FIG5 , the bit capacitor includes: a first metal plate 1, a second metal plate 2, and a Josephson junction 3; the first end of the Josephson junction 3 is connected to the first metal plate 1, and the second end of the Josephson junction 3 is connected to the second metal plate 2; a sub-metal plate is provided on the first metal plate 1 and / or the second metal plate 2; the length of the sub-metal plate is shorter than that of the first metal plate 1 and the second metal plate 2. In a specific implementation, the first end of the Josephson junction 3 is connected to the first metal plate 1, and the second end of the Josephson junction 3 is connected to the second metal plate 2 to form a double-island bit capacitor, thereby expanding the size of the bit capacitor and reserving sufficient wiring space for the XY control line 106, the Z control line 105, etc., to prevent the problem of signal interference caused by the small distance between different control lines. However, as can be seen from the above, the size of the double-island bit capacitor with the same capacitance is much larger than the cross-shaped bit capacitor 102. Therefore, when a large number of double-island bit capacitors are used to form a quantum chip, the size of the quantum chip may be too large, which is not conducive to the normal application of the quantum chip. Therefore. The bit capacitor provided by the present application also includes a sub-metal plate arranged on the first metal plate 1 and / or the second metal plate 2. In a specific implementation, a corresponding capacitance is generated between the sub-metal plate and the chip ground 103. This capacitance can be regarded as being connected in parallel with the capacitance value between the first metal plate 1 (or the second metal plate 2) and the chip ground 103. In this case, the capacitance value generated by the part of the double-island bit capacitor provided with the sub-metal plate is increased.

[0075] In a specific implementation, a sub-metal sheet can be provided on both the first metal plate 1 and the second metal plate 2, or a sub-metal sheet can be provided only on the first metal plate 1 or only on the second metal plate 2. The shape of the sub-metal sheet can be the I-shaped, snowflake-shaped, etc. mentioned in the scheme of this application, or it can be other structures, which are not limited here. Figure 5 is a structural diagram of a bit capacitor with an I-shaped sub-metal sheet, and Figure 6 is an equivalent circuit diagram of a bit capacitor provided in an embodiment of this application. The circuit diagram shown in Figure 6 corresponds to Figure 5. As shown in Figure 6, the bit capacitor provided in this embodiment includes a Josephson junction 3, a first metal plate 1, a second metal plate 2, a chip ground 103, a resonator 104, a Z control line 105, an XY control line 106, a read line 107, and four I-shaped sub-metal sheets. The Josephson junction 3 is connected across the first metal plate 1 and the second metal plate 2, and the equivalent inductance is L j ; Self-capacitance C is formed between the first metal plate 1, the second metal plate 2 and the chip ground 103 q1 and C q2 Each sub-metal sheet and the chip ground 103 form a capacitor C q11 、C q12 、C q21 、C q22The first metal plate 1 and the second metal plate 2 are provided with a first I-shaped metal sheet 6 and a second I-shaped metal sheet 7; a coupling capacitor C is formed between the first metal plate 1 and the second metal plate 2 12 The resonator 104, the Z control line 105, the XY control line 106, and the read line 107 are coupled to the novel bit capacitor (the first metal plate 1, the second metal plate 2, and the corresponding sub-metal plate) in different planes. The resonator 104 forms coupling capacitors C with the first metal plate 1 (after connecting the sub-metal plate in parallel) and the second metal plate 2 (after connecting the sub-metal plate in parallel). g1 and C g2 Based on Hough's law, the equations can be listed as follows:

[0076] ① The circuits are:

[0077] ②The circuits are:

[0078] Among them, C Q1 is the equivalent capacitance formed by the first metal plate 1 and the sub-metal sheet, and C Q1 =C q1 +C q11 +C q12 ; C Q2 is the equivalent capacitance formed by the second metal plate 2 and the sub-metal sheet, and C Q2 =C q2 +C q21 +C q22 ;

[0079] After i2, i3, i4, and i5 are represented by i1, the impedance in the dotted box can be obtained as:

[0080] From the numerator = 0, consider C g1 、C g2 and C 12 Much smaller than C q1 and C q2 , the series resonant frequency can be obtained as:

[0081] in is the approximate equivalent bit capacitance.

[0082] Similarly, from the denominator = 0, consider C g1 、C g2 and C 12 Much smaller than C q1 and C q2 , the parallel resonant frequency can be obtained:

[0083] in

[0084] Among them, C Q Can be approximately regarded as C Q1 and C Q2 The capacitance value after series connection is C because the two metal pieces are of similar size. Q1 ≈C Q2 ≈2C Q Because the traditional double-island structure bit capacitor is composed of two metal plates of similar size, under the same size, there are:

[0085] Therefore, the bit capacitance formed by the classic dual-island structure is approximately one-fourth that of the bit capacitance formed by the "cross" structure. That is, for the same capacitance value, the dual-island structure is approximately four times the size of the "cross" bit capacitor. This increased bit capacitor size leaves more space for the layout of the XY control lines 106, Z control lines 105, and read lines 107, meeting wiring requirements without sacrificing isolation between signal lines.

[0086] In a specific implementation, the capacitance of the bit capacitor provided in this application is the sum of the first metal plate 1, the second metal plate 2, and their respective sub-metal plates. Therefore, by adding branches, which is equivalent to a parallel capacitor, the size of the single-arm capacitor structure is reduced. On the basis of ensuring the capacitance value, the size of the dual-island bit capacitor is reduced. During the quantum chip design process, if the capacitance of the required bit capacitor changes, it is only necessary to adjust the size of the sub-metal plate, without adjusting the size of the first metal plate 1 and the second metal plate 2, thereby reducing the design cost.

[0087] The present embodiment provides a bit capacitor, comprising: a first metal plate, a second metal plate and a Josephson junction; the first end of the Josephson junction is connected to the first metal plate, and the second end of the Josephson junction is connected to the second metal plate; a sub-metal sheet is provided on the first metal plate and / or the second metal plate; the length of the sub-metal sheet is less than that of the first metal plate and the second metal plate. It can be seen that in the technical solution provided by the present application, the first metal plate and the second metal plate are connected through the Josephson junction to form a bit capacitor of a double-island structure, thereby providing a larger circuit layout space to prevent mutual interference between different signal lines. At the same time, a sub-metal sheet is provided on the first metal plate and the second metal plate, so as to achieve the purpose of increasing the parallel capacitance of the first metal plate and the second metal plate, thereby increasing the equivalent capacitance value of the two parts of the double-island structure bit capacitor. In addition, in the bit capacitor design stage, the overall capacitance of the bit capacitor can be changed by adjusting the capacitance of the sub-metal sheet, without adjusting the size of the bit capacitor, thereby reducing the design cost.

[0088] It is understandable that the first metal plate 1 and the second metal plate 2 can be metal plates of any shape, as long as the first metal plate 1 and the second metal plate 2 are connected via the Josephson junction 3. At the same time, the sizes of the first metal plate 1 and the second metal plate 2 can be the same or different. However, in a specific quantum chip array, multiple bit capacitors are required for connection. When the size or shape of the bit capacitors differs too much, it is not conducive to the connection between different bit capacitors.

[0089] To address this technical issue, based on the above embodiment, the first metal plate 1 and the second metal plate 2 each include a first metal arm 4 and a second metal arm 5; the angle between the first metal arm 4 and the second metal arm 5 is 90 degrees. Furthermore, the first metal plate 1 and the second metal plate 2 have the same shape and equal area.

[0090] In this embodiment, the size and shape of the first metal plate 1 and the second metal plate 2 are limited, making the bit capacitor formed by the first metal plate 1 and the second metal plate 2 easy to use. At the same time, the angle between the metal arms of the first metal plate 1 and the second metal plate 2 is 90 degrees, which increases the area of ​​contact between the first metal plate 1, the second metal plate 2 and the chip ground 103, thereby increasing the capacitance of the bit capacitor.

[0091] As shown in Figure 5, the sub-metal sheet includes a first I-shaped metal sheet 6 and a second I-shaped metal sheet 7; the first I-shaped metal sheet 6 and the second I-shaped metal sheet 7 both include a third metal arm 8, a fourth metal arm 9 and a fifth metal arm 10, and the third metal arm 8, the fourth metal arm 9 and the fifth metal arm 10 are all linear metal arms; the third metal arm 8 is parallel to the fifth metal arm 10, and the third metal arm 8 and the fifth metal arm 10 are both perpendicular to the fourth metal arm 9; the first end of the fourth metal arm 9 is connected to the midpoint of the third metal arm 8, and the second end of the fourth metal arm 9 is connected to the midpoint of the fifth metal arm 10; the center point of the fourth metal arm 9 of the first I-shaped metal sheet 6 is set on the first metal arm 4 of the first metal plate 1 and / or the second metal plate 2; the center point of the fourth metal arm 9 of the second I-shaped metal sheet 7 is set on the second metal arm 5 of the first metal plate 1 and / or the second metal plate 2.

[0092] FIG7 is a structural diagram of another I-shaped bit capacitor provided in an embodiment of the present application. As shown in FIG7 , by merely providing a sub-metal sheet on the first metal plate 1, the capacitance value of the bit capacitor can also be changed. The new asymmetric dual-island model of the "I-shaped" branch circuit used in FIG7 has been adjusted based on the original symmetrical structure. The two parts of the double island are no longer symmetrical structures. Only two of them are needed to flexibly design the other half of the bit capacitor of the double island model, such as the newly added "I-shaped" branch circuit in this embodiment. The other half continues to use the previous two long arms to form a "boomerang"-like shape. The advantage of this design is that it can increase the flexibility and adjustability of the structure, making it convenient to change parameter indicators during subsequent layout iterations and updates. Only one end of the branch circuit needs to be changed, which can achieve efficient chip version iteration. At the same time, the other "boomerang"-shaped bit capacitor arm can have a longer length to increase the spacing between bits. After the center spacing between bits increases, the overall space increases, and the space occupied by the resonator 104 remains unchanged, so there will be more and larger space left for signal lines (XY lines and Z lines) to route and layout, and the spacing between each signal line can also be increased, and the isolation can be greatly improved.

[0093] FIG8 is a schematic diagram of a bit capacitor structure of a quantum chip provided in an embodiment of the present application. As shown in FIG8 , a plurality of bit capacitors with I-shaped sub-metal sheets are interconnected to form a bit capacitor array.

[0094] Figure 9 is a structural diagram of a snowflake-shaped bit capacitor provided in an embodiment of the present application. As shown in Figure 9, the sub-metal sheet is a snowflake-shaped metal sheet; the snowflake-shaped metal sheet includes a straight metal arm 11 and at least one angular metal arm 12; the right-angle vertex of each angular metal arm 12 is set on the straight metal arm 11, and one end of the straight metal arm 11 is connected to the intersection of the first metal arm 4 and the second metal arm 5 of the first metal plate 1 and / or the second metal plate 2; the opening direction of each angular metal arm 12 is the same as the opening direction of the metal plate to which the straight metal arm 11 is connected.

[0095] FIG9 shows a situation where sub-metal sheets are provided on both the first metal plate 1 and the second metal plate 2, and FIG10 is a structural diagram of another snowflake-shaped bit capacitor provided in an embodiment of the present application; only by providing a sub-metal sheet on the first metal plate 1, the purpose of changing the capacitance of the bit capacitor can also be achieved. The new asymmetric dual-island model of the "snowflake-shaped" branch circuit used in FIG10 has been adjusted on the basis of the original symmetrical structure, combining the characteristics of the asymmetric bit dual-island model and the "snowflake-shaped" branch circuit model. The advantage of this design is that the idle space between the two arms can be effectively utilized, and the newly added multiple branches can flexibly adjust the self-capacitance value. When the parameter indicators are changed during subsequent layout iterations and updates, it is only necessary to change one end of the branch circuit, and efficient chip version iteration can be performed. Because the "snowflake-shaped" branch circuit has more branches, the adjustment flexibility is higher, and the structural integration and spatial reuse rate are also higher. At the same time, the "boomerang" design of the other double-island structure also ensures that its single-arm length is greater than the classic "M-shaped" and "cross-shaped" structures, which can fully meet the wiring space requirements. Whether it is an out-of-plane layout or a co-plane layout, there will be sufficient space for the resonant cavity, XY signal lines and Z signal lines, which is convenient for internal chip design.

[0096] Figure 11 is a schematic diagram of the bit capacitor structure of another quantum chip provided in an embodiment of the present application; as shown in Figure 11, a plurality of bit capacitors with snowflake-shaped sub-metal sheets are interconnected to form a bit capacitor array.

[0097] The new dual-island model of the "snowflake-shaped" branch circuit used in this embodiment can effectively utilize the idle space between the two arms. At the same time, the newly added multiple branches can flexibly adjust the self-capacitance value. On this basis, due to the increase in multiple branches, the coupling capacitance value between adjacent bit capacitors will be larger, which is more conducive to adjusting to the required parameter indicators. Since the "snowflake-shaped" branch circuit has more branches, the adjustment flexibility is higher, and the structural integration and spatial reuse rate are also higher.

[0098] Figure 12 is a structural diagram of a dumbbell-shaped bit capacitor provided in an embodiment of the present application. As shown in Figure 12, the sub-metal sheet includes a first dumbbell-shaped metal sheet 13 and a second dumbbell-shaped metal sheet 14; the first dumbbell-shaped metal sheet 13 and the second dumbbell-shaped metal sheet 14 both include: a first U-shaped metal arm 15, a second U-shaped metal arm 16 and a straight metal arm; the first end of the straight metal arm is connected to the midpoint of the bottom edge of the first U-shaped metal arm 15, and the second end of the straight metal arm is connected to the midpoint of the bottom edge of the second U-shaped metal arm 16; the midpoint of the straight metal arm of the first dumbbell-shaped metal sheet 13 is fixed on the first metal arm 4 and / or the second metal arm 5 of the first metal plate 1, and the midpoint of the straight metal arm of the second dumbbell-shaped metal sheet 14 is fixed on the first metal arm 4 and / or the second metal arm 5 of the second metal plate 2.

[0099] In a specific implementation, in order to control the working state of the bit capacitor, the technical solution provided in this embodiment also includes: a pulse control signal line and a frequency control signal line; the pulse control signal line is connected to the control electrode of the bit capacitor to control the excitation state of the bit capacitor; the frequency control signal line is connected to the Josephson junction 3 to control the frequency of the bit capacitor.

[0100] The pulse control signal lines are used to generate control pulses. They are typically located on the top surface of the chip and connected to control electrodes on the chip surface. These control electrodes, typically thin metal films or metallized semiconductor films, interact directly with the qubits within the chip. The pulse control signal lines are primarily used to generate control pulses for precise control of the qubits. The amplitude, frequency, and phase of these control pulses can be adjusted to achieve different control effects. For example, by varying the pulse frequency, the speed of the qubit can be controlled; by varying the pulse amplitude and phase, the rotation angle and direction of the qubit can be controlled. This control method enables operations such as acceleration, deceleration, and stopping of the qubit.

[0101] Frequency-modulated signal lines are primarily used to generate frequency-modulated signals to control the frequency of qubits. The frequency of these signals can be altered by adjusting the amplitude and phase of the signal lines. For example, by varying the frequency of the signal lines, the frequency of the qubit can be adjusted; by varying the amplitude and phase of the signal lines, the amplitude and phase difference of the qubit can be controlled. This control method enables operations such as frequency matching, filtering, and signal separation of qubits.

[0102] In quantum chips, the metal plate substrate in the bit capacitor plays a major role in building the qubit structure. The metal plate provides stable electrical properties, enabling higher repeatability and consistency in the qubit. Furthermore, the metal plate acts as a medium between the qubit and the signal transmission line, directing signal energy from the transmission line to the qubit and vice versa.

[0103] The metal plate's substrate is typically made of high-resistivity semiconductor materials, such as silicon and gallium arsenide. These materials offer high conductivity and low noise, reducing resistance and thermal noise in the circuit, thereby minimizing specific heat errors in the qubit. Furthermore, the metal plate's surface is typically polished to reduce surface roughness and surface defect density, thereby improving coupling efficiency between the plate and the qubit.

[0104] When manufacturing quantum chips, metal plates are typically bonded to substrate materials to achieve good thermal conductivity and electrical connections. Common bonding techniques include direct bonding, metal thermocompression bonding, and eutectic bonding. These techniques tightly bond the metal plates to the substrate, ensuring the stability and reliability of the quantum bit structure.

[0105] In this embodiment, the substrates of the first metal plate 1, the second metal plate 2 and the sub-metal sheet are silicon or sapphire connected to the metal plates through bonding technology, thereby providing stable electrical properties and efficient signal transmission for the quantum bit, while also ensuring the reliability and stability of the quantum bit structure.

[0106] In addition, the present application also provides a quantum chip comprising an array of multiple bit capacitors. In a specific implementation, different bit capacitors can be connected using fixed coupling or adjustable coupling. Fixed coupling refers to the connection relationship between the bit capacitor and the adjacent circuit element or qubit being determined during the manufacturing process and cannot be adjusted during operation. Typically, fixed coupling is achieved using metal connecting wires or shared electrodes. The advantages of this coupling method are simple design and ease of manufacturing, and it is suitable for fixed connection relationships between circuit elements or qubits. However, since it cannot be adjusted during operation, fixed coupling may not be suitable for scenarios requiring flexible connection. Adjustable coupling refers to the connection relationship between the bit capacitor and the adjacent circuit element or qubit being adjustable during operation to achieve flexible connection and optimize performance. Adjustable coupling is usually achieved using a programmable switch or regulator, which can open or close the connection between the bit capacitor and the adjacent circuit element or qubit when needed. The advantage of this coupling method is its high flexibility, and the connection relationship can be dynamically adjusted as needed during operation, making it suitable for scenarios requiring flexible connection and optimized performance. In this embodiment, fixed coupling is used to connect different bit capacitors.

[0107] This embodiment provides a quantum chip, including the above-mentioned bit capacitor, which includes: a first metal plate, a second metal plate and a Josephson junction; the first end of the Josephson junction is connected to the first metal plate, and the second end of the Josephson junction is connected to the second metal plate; a sub-metal plate is provided on the first metal plate and / or the second metal plate; the length of the sub-metal plate is less than that of the first metal plate and the second metal plate. It can be seen that in the technical solution provided by the present application, the first metal plate and the second metal plate are connected through the Josephson junction to form a bit capacitor with a double-island structure, thereby providing a larger circuit layout space to prevent mutual interference between different signal lines. At the same time, a sub-metal plate is provided on the first metal plate and the second metal plate to achieve the purpose of increasing the parallel capacitance of the first metal plate and the second metal plate, thereby increasing the equivalent capacitance value of the two parts of the double-island structure bit capacitor. In addition, in the bit capacitor design stage, the overall capacitance of the bit capacitor can be changed by adjusting the capacitance of the sub-metal plate, without adjusting the size of the bit capacitor, thereby reducing the design cost.

[0108] The above is a detailed introduction to a bit capacitor and quantum chip provided by the present application. The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same and similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part description. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of this application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of this application.

[0109] It should also be noted that, in this specification, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variants thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus comprising the element.

Claims

1. A bit capacitor, characterized in that: include: A first metal plate (1), a second metal plate (2) and a Josephson junction (3); The first end of the Josephson junction (3) is connected to the first metal plate (1), and the second end of the Josephson junction (3) is connected to the second metal plate (2); A sub-metal sheet is arranged on the first metal plate (1) and / or the second metal plate (2); the sub-metal sheet is shorter than the first metal plate (1) and the second metal plate (2).

2. The bit capacitor according to claim 1, characterized in that: The first metal plate (1) and the second metal plate (2) both comprise a first metal arm (4) and a second metal arm (5); The included angle between the first metal arm (4) and the second metal arm (5) is 90 degrees.

3. The bit capacitor according to claim 1, characterized in that: The first metal plate (1) and the second metal plate (2) have the same shape and the same area.

4. The bit capacitor according to claim 2, characterized in that: The sub-metal sheets include a first I-shaped metal sheet (6) and a second I-shaped metal sheet (7); The first I-shaped metal sheet (6) and the second I-shaped metal sheet (7) both comprise a third metal arm (8), a fourth metal arm (9) and a fifth metal arm (10), and the third metal arm (8), the fourth metal arm (9) and the fifth metal arm (10) are all straight metal arms; The third metal arm (8) is parallel to the fifth metal arm (10), and the third metal arm (8) and the fifth metal arm (10) are both perpendicular to the fourth metal arm (9); The first end of the fourth metal arm (9) is connected to the midpoint of the third metal arm (8), and the second end of the fourth metal arm (9) is connected to the midpoint of the fifth metal arm (10); The center point of the fourth metal arm (9) of the first I-shaped metal sheet (6) is arranged on the first metal arm (4) of the first metal plate (1) and / or the second metal plate (2); The center point of the fourth metal arm (9) of the second I-shaped metal sheet (7) is arranged on the second metal arm (5) of the first metal plate (1) and / or the second metal plate (2).

5. The bit capacitor according to claim 2, characterized in that: The sub-metal sheet is a snowflake-shaped metal sheet; The snowflake-shaped metal sheet comprises a straight metal arm (11) and at least one angular metal arm (12); The right-angled vertex of each of the angular metal arms (12) is arranged on the straight metal arm (11), and one end of the straight metal arm (11) is connected to the intersection of the first metal arm (4) and the second metal arm (5) of the first metal plate (1) and / or the second metal plate (2); The opening direction of each of the angled metal arms (12) is the same as the opening direction of the metal plate to which the linear metal arm (11) is connected.

6. The bit capacitor according to claim 2, characterized in that: The sub-metal sheet comprises a first dumbbell-shaped metal sheet (13) and a second dumbbell-shaped metal sheet (14); The first dumbbell-shaped metal sheet (13) and the second dumbbell-shaped metal sheet (14) both comprise: a first U-shaped metal arm (15), a second U-shaped metal arm (16) and a straight metal arm; The first end of the straight metal arm is connected to the midpoint of the bottom edge of the first U-shaped metal arm (15), and the second end of the straight metal arm is connected to the midpoint of the bottom edge of the second U-shaped metal arm (16); The midpoint of the straight metal arm of the first dumbbell-shaped metal sheet (13) is fixed to the first metal arm (4) and / or the second metal arm (5) of the first metal plate (1), and the midpoint of the straight metal arm of the second dumbbell-shaped metal sheet (14) is fixed to the first metal arm (4) and / or the second metal arm (5) of the second metal plate (2).

7. The bit capacitor according to any one of claims 1 to 6, characterized in that: Also includes: Pulse control signal line and frequency control signal line; The pulse control signal line is connected to the control electrode of the bit capacitor to control the excitation state of the bit capacitor; The frequency control signal line is connected to the Josephson junction (3) to control the frequency of the bit capacitor.

8. The bit capacitor according to claim 1, characterized in that: The substrates of the first metal plate (1), the second metal plate (2) and the sub-metal sheet are silicon or sapphire connected to the metal plates by bonding technology.

9. A quantum chip, characterized in that: The invention comprises the bit capacitor as described in any one of claims 1 to 8.

10. The quantum chip according to claim 9, characterized in that: The bit capacitors are connected in a fixed coupling manner.

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