Display driving circuit and display driving method for display panel, and display apparatus

Abstract

A display driving circuit (00) and a display driving method for a display panel (10), and a display apparatus. In the display driving circuit (00), a plurality of scan driving units (Gate GOA) cascaded in a scan driving circuit (01) are coupled to a clock signal line (CK) and a start signal line (STV) respectively, and on the basis of signals provided by the coupled signal lines, transmit scan driving signals to pixels; a plurality of light-emitting driving units (EM GOA) cascaded in a light-emitting driving circuit (02) are coupled to the clock signal line (CK) and the start signal line (STV) respectively, and on the basis of signals provided by the coupled signal lines, transmit light-emitting control signals to the pixels; a plurality of reset driving units (Reset GOA) cascaded in a reset driving circuit (03) are coupled to the clock signal line (CK) and the start signal line (STV) respectively, and on the basis of signals provided by the coupled signal lines, transmit reset control signals to the pixels, so as to drive the pixels to emit light. Moreover, the scan driving circuit (01), the light-emitting driving circuit (02) and the reset driving circuit (03) that provide different signals to the pixels share one clock signal line (CK), thereby facilitating narrow bezel design.

Description

Display driving circuit and display driving method for display panel, and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display driving circuit and a display driving method of a display panel, and a display device. Background Art

[0002] A display device generally includes a display panel and a display driving circuit. The display panel includes a substrate and a plurality of pixels located on the substrate. The display driving circuit is coupled to the plurality of pixels and is used to drive the plurality of pixels to emit light.

[0003] In the related art, gate drive on array (GOA) technology is usually used to set the display driver circuit on the substrate of the display panel. Accordingly, the display driver circuit is also called a GOA circuit. In addition, based on the current pixel structure, the display device usually includes multiple GOA circuits for providing different signals (such as a scan driver circuit and a light control circuit). Each GOA circuit is respectively coupled to multiple drive signal lines and multiple pixels, and is used to transmit the required signals to the multiple pixels based on the drive signals provided by the multiple drive signal lines, so as to drive the multiple pixels to emit light.

[0004] As a result, the GOA circuit occupies a larger area of ​​the display panel, which is not conducive to a narrow frame design.

[0005] Summary of the Invention

[0006] The present disclosure provides a display driving circuit and display driving method for a display panel, and a display device. The technical solution is as follows:

[0007] In one aspect, a display driving circuit is provided, which is applied to a display panel, wherein the display panel includes a plurality of pixels; the display driving circuit includes:

[0008] a scan driving circuit comprising a plurality of cascaded scan driving units, each coupled to a clock signal line and an enable signal line, and further coupled to the plurality of pixels, and configured to transmit a scan driving signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and an enable signal provided by the coupled enable signal line;

[0009] a light-emitting driving circuit comprising a plurality of cascaded light-emitting driving units, each coupled to a clock signal line and an on-signal line, and further coupled to the plurality of pixels, and configured to transmit a light-emitting control signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and an on-signal provided by the coupled on-signal line;

[0010] a reset driving circuit comprising a plurality of cascaded reset driving units, each coupled to the clock signal line and the start signal line, and further coupled to the plurality of pixels, and configured to transmit a reset control signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and a start signal provided by the coupled start signal line;

[0011] Among them, the clock signal lines coupled to the multiple scan driving units, the clock signal lines coupled to the multiple light-emitting driving units, and the clock signal lines coupled to the multiple reset driving units are shared; and the start signal lines coupled to the multiple scan driving units, the start signal lines coupled to the multiple light-emitting driving units, and the start signal lines coupled to the multiple reset driving units are independent of each other.

[0012] Optionally, at least one of the scan driving unit, the light emitting driving unit, and the reset driving unit includes:

[0013] a first gate circuit, coupled to the enable signal line, the clock signal line, the first power line, the second power line, and the output node, respectively, and configured to control the connection and disconnection between the first power line and the output node, and control the connection and disconnection between the second power line and the output node, in response to the clock signal and the enable signal;

[0014] a second gate circuit, coupled to the output node, the first power line, the second power line, and the output terminal, respectively, and configured to control the connection and disconnection between the first power line and the output terminal, and the connection and disconnection between the second power line and the output terminal, in response to the potential of the output node;

[0015] Among them, the output ends of the multiple scan driving units are coupled to the multiple pixels through multiple scan lines, the output ends of the multiple light-emitting driving units are coupled to the multiple pixels through multiple light-emitting control lines, and the output ends of the multiple reset driving units are coupled to the multiple pixels through multiple reset control lines.

[0016] Optionally, the output node includes: a first output node and a second output node; the first gate circuit includes:

[0017] The first part is coupled to the start signal line, the first power line, the second power line and the input node respectively, and is used to control the connection and disconnection between the first power line and the input node, and control the connection and disconnection between the second power line and the input node in response to the start signal, so as to invert the start signal into an inverted start signal and transmit it to the input node;

[0018] The second part is coupled to the start signal line, the clock signal line, the first power line, the second power line, the input node, the first output node and the second output node, respectively, and is used to control the on-off of the first power line and the first output node, and control the on-off of the second power line and the first output node in response to the start signal and the clock signal; and to control the on-off of the first power line and the second output node, and control the on-off of the second power line and the second output node in response to the inverted start signal and the clock signal.

[0019] Optionally, the at least one driving unit further includes:

[0020] a third gate circuit, connected in series between the target signal line and the second portion, and further coupled to the first power line and the second power line, respectively, and configured to control the connection and disconnection between the first power line and the second portion, and to control the connection and disconnection between the second power line and the second portion, in response to a target signal provided by the target signal line;

[0021] The target signal line includes at least one of the clock signal line and the start signal line.

[0022] Optionally, the target signal line includes: the clock signal line and the start signal line.

[0023] Optionally, the third gate circuit includes: at least one first logic gate;

[0024] Wherein, the control end of the at least one first logic gate is coupled to the target signal line, the input end of the at least one first logic gate is coupled to the first power line and the second power line respectively, and the output end of the at least one first logic gate is coupled to the second part.

[0025] Optionally, the at least one first logic gate includes: a transmission gate.

[0026] Optionally, the at least one first logic gate includes: an even number of first NOT gates connected in series.

[0027] Optionally, the at least one first logic gate includes: two first NOT gates connected in series.

[0028] Optionally, the first part of the first gate circuit includes: a second logic gate; the second part of the first gate circuit includes: a third logic gate and a fourth logic gate; the second gate circuit includes: a fifth logic gate and a sixth logic gate;

[0029] A control terminal of the second logic gate is coupled to the start signal line, an input terminal of the second logic gate is coupled to the first power line and the second power line respectively, and an output terminal of the second logic gate is coupled to the input node;

[0030] The control end of the third logic gate is coupled to the start signal line and the clock signal line respectively, the input end of the third logic gate is coupled to the first power line and the second power line respectively, and the output end of the third logic gate is coupled to the first output node;

[0031] The control terminal of the fourth logic gate is coupled to the clock signal line and the input node respectively, the input terminal of the fourth logic gate is coupled to the first power line and the second power line respectively, and the output terminal of the fourth logic gate is coupled to the second output node;

[0032] The control terminal of the fifth logic gate is coupled to the first output node and the output terminal of the sixth logic gate respectively, and the input terminal of the fifth logic gate is coupled to the first power line and the second power line respectively;

[0033] The control end of the sixth logic gate is coupled to the second output node and the output end of the fifth logic gate respectively, the input end of the sixth logic gate is coupled to the first power line and the second power line respectively, and the output end of the fifth logic gate is also coupled to the pixel as the output end of the second gate circuit.

[0034] Optionally, the second logic gate includes a second NOT gate; the third logic gate, the fourth logic gate, the fifth logic gate, and the sixth logic gate all include a NAND gate.

[0035] Optionally, among the first gate circuit, the second gate circuit and the third gate circuit, at least one gate circuit includes a logic gate comprising: at least one P-type transistor and at least one N-type transistor.

[0036] Optionally, the material of the P-type transistor includes: low-temperature polysilicon material; the material of the N-type transistor includes: oxide material.

[0037] Optionally, the display panel further comprises: a substrate having a display area and a non-display area at least partially surrounding the display area, the plurality of pixels being located in the display area and arranged in an array;

[0038] The scan driving circuit includes: a first scan driving circuit and a second scan driving circuit; the reset driving circuit includes: a first reset driving circuit and a second reset driving circuit;

[0039] The start signal line coupled to the first scan driving circuit and the start signal line coupled to the second scan driving circuit are independent of each other; the start signal line coupled to the first reset driving circuit and the start signal line coupled to the second reset driving circuit are independent of each other;

[0040] Furthermore, the potential of the effective level of the scan driving signal transmitted by the scan driving unit in the first scan driving circuit is opposite to the potential of the effective level of the scan driving signal transmitted by the scan driving unit in the second scan driving circuit; the potential of the effective level of the reset control signal transmitted by the reset driving unit in the first reset driving circuit is opposite to the potential of the effective level of the reset control signal transmitted by the reset driving unit in the second reset driving circuit;

[0041] The display driving circuit is located in the non-display area; and the first scanning driving circuit, the second scanning driving circuit, the first reset driving circuit, the second reset driving circuit and the light emitting driving circuit included in the display driving circuit are distributed on both sides of multiple rows of pixels in the first direction.

[0042] Optionally, the potential of the scan driving signal transmitted by the scan driving unit in the first scan driving circuit is lower than the potential of the scan driving signal transmitted by the scan driving unit in the second scan driving circuit; the scan driving circuit includes: two first scan driving circuits;

[0043] Furthermore, the two first scan driving circuits, the second scan driving circuit, the first reset driving circuit, the second reset driving circuit and the light emitting driving circuit are evenly distributed on both sides in the first direction in groups of three.

[0044] Optionally, among the two first scan driving circuits, the multiple cascaded scan driving units included in one first scan driving circuit are located on a first side of the two sides; and the multiple cascaded scan driving units included in the other first scan driving circuit are located on a second side of the two sides;

[0045] The plurality of cascaded scan driving units included in the second scan driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides;

[0046] The plurality of cascaded reset driving units included in the first reset driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides;

[0047] The plurality of cascaded reset driving units included in the second reset driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides;

[0048] The plurality of cascaded light emitting driving units included in the light emitting driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides.

[0049] Optionally, the plurality of cascaded scan driving units included in the second scan driving circuit are located on the same side of the two sides, the plurality of cascaded reset driving units included in the first reset driving circuit are located on the same side of the two sides, the plurality of cascaded reset driving units included in the second reset driving circuit are located on the same side of the two sides, and the plurality of cascaded light-emitting driving units included in the light-emitting driving circuit are located on the same side of the two sides;

[0050] The plurality of cascaded reset driving units included in the first reset driving circuit and the plurality of cascaded reset driving units included in the second reset driving circuit are both located on the first side of the two sides;

[0051] The plurality of cascaded scan driving units included in the second scan driving circuit and the plurality of cascaded light emitting driving units included in the light emitting driving circuit are both located on the second side of the two sides;

[0052] Moreover, in the first direction and along the direction close to the display area, on the first side, the second reset drive circuit, the first reset drive circuit and a first scan drive circuit are arranged in order; on the second side, the second scan drive circuit, the light-emitting drive circuit and another first scan drive circuit are arranged in order.

[0053] Optionally, the second scan driving circuit includes a plurality of cascaded scan driving units respectively located on a first side and a second side of the two sides; the first reset driving circuit includes a plurality of cascaded reset driving units respectively located on the first side and the second side of the two sides; the second reset driving circuit includes a plurality of cascaded reset driving units respectively located on the first side and the second side of the two sides; the light driving circuit includes a plurality of cascaded light driving units respectively located on the first side and the second side of the two sides;

[0054] Wherein, among the plurality of cascaded scan driving units included in the second scan driving circuit, every two adjacent scan driving units are located on the first side and the second side respectively;

[0055] Among the plurality of cascaded reset driving units included in the first reset driving circuit, every two adjacent reset driving units are located on the first side and the second side respectively;

[0056] Among the plurality of cascaded reset driving units included in the second reset driving circuit, every two adjacent reset driving units are located on the first side and the second side respectively;

[0057] Among the plurality of cascaded light-emitting driving units included in the light-emitting driving circuit, every two adjacent light-emitting driving units are located on the first side and the second side respectively;

[0058] Moreover, along the second direction of the multiple columns of pixels, on the first side and the second side, the reset driving units included in the second reset driving circuit and the scan driving units included in the second scan driving circuit are alternately arranged; the reset driving units included in the first reset driving circuit and the light-emitting driving units included in the light-emitting driving circuit are alternately arranged, and the second direction intersects with the first direction.

[0059] In another aspect, a display driving method is provided, which is applied to the display driving circuit as described in the above aspect and is used to drive a display panel to display, wherein the display panel includes a plurality of pixels; the method includes:

[0060] providing an enable signal to the enable signal line and providing a clock signal to the clock signal line;

[0061] The scan driving circuit transmits a scan driving signal to the plurality of pixels based on the received start signal and the clock signal;

[0062] The light driving circuit transmits a light emitting control signal to the plurality of pixels based on the received start signal and the clock signal;

[0063] The reset driving circuit transmits a reset control signal to the plurality of pixels based on the received start signal and the clock signal;

[0064] The scan drive signal, the light emitting control signal and the reset control signal are used to drive the plurality of pixels to emit light, so that the display panel performs display.

[0065] In another aspect, a display device is provided, comprising: a display panel, and the display driving circuit according to the above aspect;

[0066] The display driving circuit is coupled to a plurality of pixels in the display panel and is used to drive the plurality of pixels to emit light. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0068] FIG1 is a schematic structural diagram of a display driving circuit provided by an embodiment of the present disclosure;

[0069] FIG2 is a schematic structural diagram of a driving unit in a display driving circuit provided by an embodiment of the present disclosure;

[0070] FIG3 is a schematic structural diagram of a driving unit in another display driving circuit provided by an embodiment of the present disclosure;

[0071] FIG4 is a schematic structural diagram of a driving unit in another display driving circuit provided by an embodiment of the present disclosure;

[0072] FIG5 is a circuit structure diagram of a driving unit in a display driving circuit provided by an embodiment of the present disclosure;

[0073] FIG6 is a circuit structure diagram of a driving unit in another display driving circuit provided by an embodiment of the present disclosure;

[0074] FIG7 is a circuit structure diagram of a driving unit in another display driving circuit provided by an embodiment of the present disclosure;

[0075] FIG8 is a schematic diagram of a signal simulation of the driving unit shown in FIG5 provided by an embodiment of the present disclosure;

[0076] FIG9 is a schematic diagram of a signal simulation of the driving unit shown in FIG6 provided by an embodiment of the present disclosure;

[0077] FIG10 is a schematic diagram of another signal simulation of the driving unit shown in FIG6 provided by an embodiment of the present disclosure;

[0078] FIG11 is a schematic diagram of the layout of various parts of a display driving circuit provided in an embodiment of the present disclosure;

[0079] FIG12 is a schematic diagram showing the layout of various parts of another display driving circuit provided in an embodiment of the present disclosure;

[0080] FIG13 is a flow chart of a display driving method provided by an embodiment of the present disclosure;

[0081] FIG14 is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0082] In order to make the objectives, technical solutions and advantages of the present disclosure more clear, the embodiments of the present disclosure will be further described in detail below with reference to the accompanying drawings.

[0083] In a display device, a GOA circuit typically includes multiple cascaded GOA units, which are coupled to multiple rows of pixels (e.g., in a one-to-one correspondence) to drive the multiple rows of pixels to emit light. However, as described in the background art, the configuration of a GOA circuit is not conducive to the narrow bezel design of the display device. Furthermore, the presence of capacitor C and resistor R in the circuit, as well as the coupling between capacitors (coupled), changes the RC loading (i.e., the load), which in turn changes the output environment of the GOA unit, affecting the output of the GOA unit and making it impossible to reliably drive the pixels to emit light.

[0084] The embodiments of the present disclosure provide a display driving circuit (ie, a GOA circuit), which not only facilitates the design of a narrow frame, but also ensures good output stability, thereby reliably driving pixels to emit light.

[0085] FIG1 is a schematic diagram of a display driver circuit according to an embodiment of the present disclosure. The display driver circuit can be applied to a display panel 10, which includes a plurality of pixels (not shown). The display driver circuit 00 includes a scan driver circuit 01, a light-emitting driver circuit 02, and a reset driver circuit 03.

[0086] The scan drive circuit 01 includes multiple cascaded scan drive units (Gate GOAs). The cascaded Gate GOAs are coupled to a clock signal line CK and a turn-on signal line STV, respectively, and are also coupled to multiple pixels. The cascaded Gate GOAs are used to transmit scan drive signals to the multiple pixels in response to a clock signal provided by the coupled clock signal line CK and a turn-on signal provided by the coupled turn-on signal line STV.

[0087] The light-emitting driver circuit 02 includes multiple cascaded light-emitting driver units (EM GOAs). The cascaded EM GOAs are coupled to a clock signal line CK and a start signal line STV, respectively, and are also coupled to multiple pixels. The cascaded EM GOAs are configured to transmit light-emitting control signals to the multiple pixels in response to a clock signal provided by the coupled clock signal line CK and a start signal provided by the coupled start signal line STV.

[0088] The reset driver circuit 03 includes multiple cascaded reset driver units (Reset GOAs). The cascaded Reset GOAs are coupled to a clock signal line CK and a start signal line STV, respectively, and are also coupled to multiple pixels. The cascaded Reset GOAs are configured to transmit reset control signals to the multiple pixels in response to a clock signal provided by the coupled clock signal line CK and a start signal provided by the coupled start signal line STV.

[0089] Optionally, for any of the drive circuits in the scan drive circuit 01, the light-emitting drive circuit 02, and the reset drive circuit 03, the multiple cascaded GOAs included therein can be coupled to the start signal line STV via one of the GOAs, typically via the first-stage GOA coupled to the start signal line STV, and then cascaded sequentially starting from the first stage. The start signal provided by the start signal line STV can be used to drive the multiple cascaded GOAs to operate. Each stage of the GOA is coupled to the clock signal line CK. The pixel can be used to emit light in response to the received scan drive signal, light-emitting control signal, and reset control signal, so that the display panel displays.

[0090] It should be noted that a pixel generally includes a mutually coupled pixel circuit and a light-emitting element. Here, the multiple cascaded scan drive units Gate GOA in the scan drive circuit 01, the multiple cascaded light-emitting drive units EM GOA in the light-emitting drive circuit 02, and the multiple cascaded reset drive units Reset GOA in the reset drive circuit 03 can all be coupled to the pixel circuit in the pixel and transmit scan drive signals, light-emitting control signals, and reset control signals to the pixel circuit, respectively. Accordingly, the pixel circuit can drive the light-emitting element to emit light in response to the received scan drive signals, light-emitting control signals, and reset control signals.

[0091] 1 , it can be seen that, in the embodiment of the present disclosure, the clock signal line CK coupled to multiple scan drive units Gate GOA, the clock signal line CK coupled to multiple light-emitting drive units EM GOA, and the clock signal line CK coupled to multiple reset drive units Reset GOA are shared. Furthermore, the start signal lines STV coupled to multiple scan drive units Gate GOA, the start signal lines STV coupled to multiple light-emitting drive units EM GOA, and the start signal lines STV coupled to multiple reset drive units Reset GOA are independent of each other. To distinguish, in the figure, the start signal line STV coupled to the scan drive unit Gate GOA is labeled as GSTV; the start signal line STV coupled to the light-emitting drive unit EM GOA is labeled as ESTV; and the start signal line STV coupled to the reset drive unit Reset GOA is labeled as RSTV.

[0092] That is, in the disclosed embodiment, only one clock signal line CK can be provided to couple with circuits in the display driver circuit that provide different signals; and three start-up signal lines STV can be provided to couple with circuits in the display driver circuit that provide different signals. The circuits providing different signals include the scan driver circuit 01 that provides the scan drive signal, the light driver circuit 02 that provides the light control signal, and the reset driver circuit 03 that provides the reset control signal, as described in the above embodiment. This ensures independent and reliable outputs from the different driver circuits while reducing the number of required signal lines, facilitating a narrow-frame design for the display device.

[0093] In summary, an embodiment of the present disclosure provides a display driving circuit. The display driving circuit includes a scanning driving circuit, a light-emitting driving circuit and a reset driving circuit. Among them, the multiple scanning driving units cascaded in the scanning driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the scanning driving signal to the pixel based on the signal provided by the coupled signal line; the multiple light-emitting driving units cascaded in the light-emitting driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the light-emitting control signal to the pixel based on the signal provided by the coupled signal line; the multiple reset driving units cascaded in the reset driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the reset control signal to the pixel based on the signal provided by the coupled signal line, so as to drive the pixel to emit light. In addition, the scanning driving circuit, the light-emitting driving circuit and the reset driving circuit that provide different signals to the pixel share a clock signal line, which can facilitate a narrow frame design.

[0094] Optionally, referring to FIG2 , in the embodiment of the present disclosure, at least one of the scan driving unit Gate GOA, the light emitting driving unit EM GOA, and the reset driving unit Reset GOA may include: a first gate circuit 001 and a second gate circuit 002. For example, FIG2 may show the Gate GOA.

[0095] The first gate circuit 001 is coupled to the start signal line STV, the clock signal line CK, the first power line VGH, the second power line VGL, and the output node N1. The first gate circuit 001 is configured to control the connection between the first power line VGH and the output node N1, and to control the connection between the second power line VGL and the output node N1, in response to the clock signal and the start signal.

[0096] The second gate circuit 002 is coupled to the output node N1, the first power line VGH, the second power line VGL, and the output terminal OUT. The second gate circuit 002 is configured to control the connection between the first power line VGH and the output terminal OUT, and to control the connection between the second power line VGL and the output terminal OUT, in response to the potential of the output node N1.

[0097] When the first gate circuit 001 controls the first power line VGH and the output node N1 to be turned on, the first power signal provided by the first power line VGH can be transmitted to the output node N1; when the first gate circuit 001 controls the second power line VGL and the output node N1 to be turned on, the second power signal provided by the second power line VGL can be transmitted to the output node N1.

[0098] Similarly, when the second gate circuit 002 controls the first power line VGH to be conductive with the output terminal OUT, the first power signal provided by the first power line VGH can be transmitted to the output terminal OUT; when the second gate circuit 002 controls the second power line VGL to be conductive with the output terminal OUT, the second power signal provided by the second power line VGL can be transmitted to the output terminal OUT.

[0099] Optionally, the potential of the first power signal provided by the first power line VGH can be a high potential, and the potential of the second power signal provided by the second power line VGL can be a low potential. Here, high potential and low potential are relative. Based on this, it can also be seen that the first gate circuit 001 can be used to control the potential of the output node N1 to be high or low in response to the clock signal and the start signal. The second gate circuit 002 can be used to output the high potential first power signal or the low potential second power signal to the output terminal OUT in response to the potential of the output node N1.

[0100] The output terminals OUT of multiple scan drive units Gate GOA can be coupled to multiple pixels via multiple scan lines. The output terminals OUT of multiple light-emitting drive units EM GOA can be coupled to multiple pixels via multiple light-emitting control lines. The output terminals OUT of multiple reset drive units Reset GOA can be coupled to multiple pixels via multiple reset control lines. This can be a one-to-one coupling. In the disclosed embodiment, the output terminal OUT is also used to cascade with the next-stage GOA and serve as the input signal of the next-stage GOA.

[0101] Alternatively, based on FIG2 , referring to another schematic diagram of a driving unit shown in FIG3 , it can be seen that the output node N1 may include: a first output node N11 and a second output node N12 . The first gate circuit 001 may include: a first part 0011 and a second part 0012 .

[0102] The first portion 0011 can be coupled to the start signal line STV, the first power line VGH, the second power line VGL, and the input node N2, respectively. In response to the start signal, the first portion 0011 can control the connection between the first power line VGH and the input node N2, and control the connection between the second power line VGL and the input node N2, thereby inverting the start signal into an inverted start signal and transmitting it to the input node N2.

[0103] For example, when the potential of the start signal is high, the first part 0011 can control the first power line VGH to be disconnected from the input node N2, and control the second power line VGL to be conductive with the input node N2, so that the low-potential second power signal provided by the second power line VGL is transmitted to the input node N2. This low-potential second power signal is the inverted start signal obtained by inverting the high-potential start signal. Similarly, when the potential of the start signal is low, the first part 0011 can control the first power line VGH to be conductive with the input node N2, and control the second power line VGL to be disconnected from the input node N2, so that the high-potential first power signal provided by the first power line VGH is transmitted to the input node N2. This high-potential first power signal is the inverted start signal obtained by inverting the low-potential start signal. Accordingly, it can be seen that the first part 0011 is actually equivalent to an inverter.

[0104] The second portion 0012 can be coupled to the start signal line STV, the clock signal line CK, the first power line VGH, the second power line VGL, the input node N2, the first output node N11, and the second output node N12, respectively. The second portion 0012 can be used to control the connection between the first power line VGH and the first output node N11, and the connection between the second power line VGL and the first output node N11, in response to the start signal and the clock signal. Furthermore, the second portion 0012 can be used to control the connection between the first power line VGH and the second output node N12, and the connection between the second power line VGL and the second output node N12, in response to the inverted start signal and the clock signal.

[0105] For example, when the potential of the start signal is a high potential, that is, the potential of the inverted start signal is a low potential, if the potential of the clock signal is a high potential, the second part 0012 can respond to the high potential start signal and the high potential clock signal, control the first power line VGH to disconnect from the first output node N11, and control the second power line VGL to conduct with the first output node N11, so that the low potential second power signal provided by the second power line VGL is transmitted to the first output node N11; and can respond to the low potential inverted start signal and the high potential clock signal, control the first power line VGH to conduct with the second output node N12, and control the second power line VGL to disconnect from the second output node N12, so that the high potential first power signal provided by the first power line VGH is transmitted to the second output node N12. Furthermore, if the potential of the clock signal is low, the second part 0012 can control the first power line VGH to be turned on and the first output node N11 in response to the high-potential start signal and the low-potential clock signal, and control the second power line VGL to be disconnected from the first output node N11, so that the high-potential first power signal provided by the first power line VGH is transmitted to the first output node N11; and can control the first power line VGH to be turned on and the second output node N12 in response to the low-potential inverted start signal and the low-potential clock signal, and control the second power line VGL to be disconnected from the second output node N12, so that the high-potential first power signal provided by the first power line VGH is transmitted to the second output node N12.

[0106] Similarly, when the potential of the start signal is low, that is, the potential of the inverted start signal is high, if the potential of the clock signal is high, the second part 0012 can respond to the low-potential start signal and the high-potential clock signal to control the first power line VGH to be turned on and the first output node N11, and control the second power line VGL to be disconnected from the first output node N11, so that the high-potential first power signal provided by the first power line VGH is transmitted to the first output node N11; and can respond to the high-potential inverted start signal and the high-potential clock signal to control the first power line VGH to be disconnected from the second output node N12, and control the second power line VGL to be turned on and the second output node N12, so that the low-potential second power signal provided by the second power line VGL is transmitted to the second output node N12. If the potential of the clock signal is low, the second part 0012 can control the first power line VGH to be turned on and the first output node N11 in response to the low-potential start signal and the low-potential clock signal, and control the second power line VGL to be disconnected from the first output node N11, so that the high-potential first power signal provided by the first power line VGH is transmitted to the first output node N11; and can control the first power line VGH to be turned on and the second output node N12 in response to the high-potential inverted start signal and the low-potential clock signal, and control the second power line VGL to be disconnected from the second output node N12, so that the high-potential first power signal provided by the first power line VGH is transmitted to the second output node N12.

[0107] On this basis, the second gate circuit 002 can control the high-potential first power signal provided by the first power line VGH to be transmitted to the output terminal OUT, or control the low-potential second power signal provided by the second power line VGL to be transmitted to the output terminal OUT in response to the potential of the first output node N11 and the potential of the second output node N12.

[0108] In the structure shown in FIG3 , parasitic resistance and capacitance inevitably exist in the coupling circuit between the clock signal line CK / start signal line STV and the second portion 0012, resulting in RC loading. This results in poor reliability of the clock signal / start signal transmitted to the second portion 0012. This, in turn, can easily lead to poor reliability and stability of the signal ultimately transmitted to the output terminal OUT. For example, this can cause the signal transmitted to the output terminal OUT to exhibit secondary steps or glitches. Because the signal transmitted to the output terminal OUT is ultimately transmitted to the pixel, this can result in poor pixel luminescence and poor display quality on the display panel, such as dark lines appearing on the display panel.

[0109] On this basis, referring to the structural diagram of another driving unit shown in FIG. 4 , it can be seen that at least one driving unit provided by the embodiment of the present disclosure (GATE GOA is exemplified here) may further include: a third gate circuit 003 .

[0110] The third gate circuit 003 can be connected in series between the target signal line and the second portion 0012, and can also be coupled to the first power line VGH and the second power line VGL, respectively. The third gate circuit 003 can be used to control the connection and disconnection between the first power line VGH and the second portion 0012, and to control the connection and disconnection between the second power line VGL and the second portion 0012, in response to a target signal provided by the target signal line.

[0111] The target signal line may include at least one of a clock signal line CK and a start signal line STV. Specifically, the driver unit may include a third gate circuit 003 connected in series between the clock signal line CK and the second portion 0012. In other words, the clock signal line CK may be indirectly coupled to the second portion 0012 of the first gate circuit 001 via the third gate circuit 003. Furthermore, the driver unit may include another third gate circuit 003 connected in series between the start signal line STV and the second portion 0012. In other words, the start signal line STV may be indirectly coupled to the second portion 0012 of the first gate circuit 001 via the third gate circuit 003.

[0112] For example, the driver unit shown in FIG4 includes a third gate circuit 003 connected in series between the clock signal line CK and the second portion 0012, and another third gate circuit 003 connected in series between the start signal line STV and the second portion 0012. That is, the target signal line includes the clock signal line CK and the start signal line STV. The driver unit includes two third gate circuits 003.

[0113] Furthermore, in the embodiment of the present disclosure, when the target signal provided by the target signal line is at a high potential, the third gate circuit 003 can, in response to the high potential target signal, control the first power line VGH to conduct with the second portion 0012 and disconnect the second power line VGL from the second portion 0012, thereby transmitting the high potential first power signal provided by the first power line VGH to the second portion 0012. Furthermore, when the target signal provided by the target signal line is at a low potential, the third gate circuit 003 can, in response to the low potential target signal, control the first power line VGH to disconnect with the second portion 0012 and connect with the second power line VGL, thereby transmitting the low potential second power signal provided by the second power line VGL to the second portion 0012. In other words, the high potential target signal provided by the target signal line can be synchronously transmitted to the second portion 0012 via the third gate circuit 003.

[0114] In other words, if the target signal line is the clock signal line CK, the clock signal provided by the clock signal line CK can be indirectly and synchronously transmitted to the second portion 0012 via the third gate circuit 003, rather than directly transmitted to the second portion 0012 as shown in Figure 3. If the target signal line is the turn-on signal line STV, the turn-on signal provided by the turn-on signal line STV can be indirectly and synchronously transmitted to the second portion 0012 via the third gate circuit 003, rather than directly transmitted to the second portion 0012 as shown in Figure 3. In this way, the larger first power signal provided by the first power line VGH / the larger second power signal provided by the second power line VGL can filter out signal glitches, ensuring better stability of the clock signal / turn-on signal transmitted to the second portion 0012. Furthermore, the reliability and stability of the signal transmitted to the output terminal OUT can be ensured. For example, the signal transmitted to the output terminal OUT can be smoother and free of steps, thereby ensuring a better display effect.

[0115] Optionally, based on Figure 3, Figure 5 shows a schematic diagram of the circuit structure of a driving unit. Based on Figure 4, Figure 6 shows a schematic diagram of the circuit structure of another driving unit. Figure 7 shows a schematic diagram of the circuit structure of yet another driving unit.

[0116] 5 to 7 , it can be seen that the first portion 0011 of the first gate circuit 001 may include a second logic gate, the second portion 0012 of the first gate circuit 001 may include a third logic gate and a fourth logic gate, and the second gate circuit 002 may include a fifth logic gate and a sixth logic gate.

[0117] The control end of the second logic gate can be coupled to the start signal line STV, the input end of the second logic gate can be coupled to the first power line VGH and the second power line VGL respectively, and the output end of the second logic gate can be coupled to the input node N2.

[0118] The control end of the third logic gate can be coupled to the start signal line STV and the clock signal line CK respectively, the input end of the third logic gate can be coupled to the first power line VGH and the second power line VGL respectively, and the output end of the third logic gate can be coupled to the first output node N11.

[0119] The control end of the fourth logic gate can be coupled to the clock signal line CK and the input node N2 respectively, the input end of the fourth logic gate can be coupled to the first power line VGH and the second power line VGL respectively, and the output end of the fourth logic gate can be coupled to the second output node N12.

[0120] A control terminal of the fifth logic gate may be coupled to the first output node N11 and the output terminal of the sixth logic gate, respectively. An input terminal of the fifth logic gate may be coupled to the first power line VGH and the second power line VGL, respectively.

[0121] The control end of the sixth logic gate can be coupled to the second output node N12 and the output end of the fifth logic gate respectively, the input end of the sixth logic gate can be coupled to the first power line VGH and the second power line VGL respectively, and the output end of the fifth logic gate can also be coupled to the pixel as the output end OUT of the second gate circuit 002.

[0122] For example, as shown in Figures 5 to 7, the second logic gate can include a second NOT gate. The third, fourth, fifth, and sixth logic gates can each include a NAND gate. Furthermore, based on the coupling method of the fifth and sixth logic gates included in the second gate circuit 002, it can be seen that the second gate circuit 002 is actually an RS latch. This also shows that, in the disclosed embodiment, the first gate circuit 001 can actually include a NOT gate and two NAND gates; and the second gate circuit 002 can include an RS latch.

[0123] Optionally, with continued reference to FIG. 6 and FIG. 7 , it can be seen that the third gate circuit 003 may include at least one first logic gate.

[0124] In which, the control end of at least one first logic gate can be coupled to the target signal line (including the clock signal line CK and the start signal line STV), the input end of at least one first logic gate can be coupled to the first power line VGH and the second power line VGL respectively, and the output end of at least one first logic gate can be coupled to the second part 0012.

[0125] As an optional implementation: referring to FIG6 , the at least one first logic gate may include: a transmission gate.

[0126] As another optional implementation: referring to Figure 7 , the at least one first logic gate may include: an even number of first NOT gates connected in series. For example, the structure shown in Figure 7 includes: two first NOT gates connected in series.

[0127] In other words, Figure 7 can refer to a modified even-numbered NOT gate structure utilizing the characteristics of the transmission gate shown in Figure 6. This can also reduce the loading effects of the high-potential first power signal provided by the first power terminal VGH and the low-potential second power signal provided by the second power line VGL in the circuit. Specifically, if only one of the high-potential first power signal and the low-potential second power signal is used, the high-potential first power signal or the low-potential second power signal will fluctuate due to loading variations. By using multiple NOT gates connected in series in an even number of stages, the high-potential first power signal and the low-potential second power signal can be used alternately. For example, in a configuration including two NOT gates connected in series, the first NOT gate can output the low-potential second power signal based on the high-potential target signal, while the second NOT gate can output the high-potential first power signal, thus staggering the output. By staggering the high-potential first power signal and the low-potential second power signal, differential-mode output can be reduced, while stabilizing circuit operation and minimizing signal loss.

[0128] Optionally, referring to FIG. 5 to FIG. 7 , it can be seen that the logic gate included in at least one gate circuit in the first gate circuit 001 , the second gate circuit 002 , and the third gate circuit 003 may include at least one P-type transistor and at least one N-type transistor.

[0129] Among them, any transistor among the P-type transistor and the N-type transistor can be a Metal-Oxide-Semiconductor (MOS) tube. The P-type transistor is also called a PMOS tube; the N-type transistor is also called an NMOS tube. The MOS tube has a gate, a first electrode and a second electrode. In combination with the above embodiment, the gate can serve as the control terminal of the logic gate; the first electrode can serve as the input terminal of the logic gate, and the second electrode can serve as the output terminal of the logic gate. Of the first electrode and the second electrode, one electrode can be called a source electrode, and the other electrode can be called a drain electrode. The P-type transistor can be turned on in response to a low-potential signal received by the gate, and turned off in response to a high-potential signal received by the gate; the N-type transistor can be turned on in response to a high-potential signal received by the gate, and turned off in response to a low-potential signal received by the gate.

[0130] For example, referring to Figures 5 to 7 , the second logic gate including a second NOT gate may include a P-type transistor M1 and an N-type transistor M2. The third logic gate including a NAND gate may include two P-type transistors M3 and M4, and two N-type transistors M5 and M6. The fourth logic gate including a NAND gate may include two P-type transistors M7 and M8, and two N-type transistors M9 and M10. The fifth logic gate including a NAND gate may include two P-type transistors M11 and M12, and two N-type transistors M13 and M14. The sixth logic gate including a NAND gate may include two P-type transistors M15 and M16, and two N-type transistors M17 and M18. Referring to Figure 6 , on the start signal line STV, the first logic gate including a transmission gate may include a P-type transistor M19 and an N-type transistor M20. On the clock signal line CK, the first logic gate including a transmission gate may include a P-type transistor M21 and an N-type transistor M22. 7 , on the start signal line STV, the first logic gate including two first NOT gates may include two P-type transistors M23 and M24, and two N-type transistors M25 and M26. On the clock signal line CK, the first logic gate including two first NOT gates may include two P-type transistors M27 and M28, and two N-type transistors M29 and M30.

[0131] For the structures shown in Figures 5 to 7:

[0132] The gate of the P-type transistor M1 and the gate of the N-type transistor M2 can be coupled to the start signal line STV as the control end of the second logic gate; the first electrode of the P-type transistor M1 and the first electrode of the N-type transistor M2 can be coupled to the first power line VGH and the second power line VGL as the input ends of the second logic gate respectively; the second electrode of the P-type transistor M1 and the second electrode of the N-type transistor M2 can be coupled to the input node N2 as the output end.

[0133] The gate of the P-type transistor M11 and the gate of the N-type transistor M13 can be coupled to the first output node N11 as the control end of the fifth logic gate; the gate of the P-type transistor M12 and the gate of the N-type transistor M14 can be coupled to the output end of the sixth logic gate as the control end of the fifth logic gate; the first electrode of the P-type transistor M11 and the first electrode of the P-type transistor M12 can be coupled to the first power line VGH as the input end of the fifth logic gate; the first electrode of the N-type transistor M14 can be coupled to the second power line VGL as the input end of the fifth logic gate; and the second electrode of the N-type transistor M14 can also be coupled to the first electrode of the N-type transistor M13; the second electrode of the P-type transistor M11, the second electrode of the P-type transistor M12 and the second electrode of the N-type transistor M13 can be coupled to the pixel as the output end of the fifth logic gate.

[0134] The gate of the P-type transistor M15 and the gate of the N-type transistor M17 can be coupled as the control end of the sixth logic gate to the output end of the fifth logic gate (i.e., the second electrode of the P-type transistor M11, the second electrode of the P-type transistor M12, and the second electrode of the N-type transistor M13); the gate of the P-type transistor M16 and the gate of the N-type transistor M18 can be coupled as the control end of the sixth logic gate to the second output node N12; the first electrode of the P-type transistor M15 and the first electrode of the P-type transistor M16 can be coupled as the input end of the sixth logic gate to the first power line VGH; the first electrode of the N-type transistor M18 can be coupled as the input end of the sixth logic gate to the second power line VGL; and the second electrode of the N-type transistor M18 can also be coupled to the first electrode of the N-type transistor M17; the second electrode of the P-type transistor M15, the second electrode of the P-type transistor M16, and the second electrode of the N-type transistor M17 can be coupled as the output end of the sixth logic gate to the control end of the fifth logic gate (i.e., the gate of the P-type transistor M12 and the gate of the N-type transistor M14).

[0135] For the structure shown in Figure 5:

[0136] The gate of the P-type transistor M3 and the gate of the N-type transistor M5 can be coupled to the start signal line STV as the control end of the third logic gate; the gate of the P-type transistor M4 and the gate of the N-type transistor M6 can be coupled to the clock signal line CK as the control end of the third logic gate; the first electrode of the P-type transistor M3 and the first electrode of the P-type transistor M4 can be coupled to the first power line VGH as the input end of the third logic gate; the first electrode of the N-type transistor M6 can be coupled to the second power line VGL as the input end of the third logic gate; and the second electrode of the N-type transistor M6 can also be coupled to the first electrode of the N-type transistor M5; the second electrode of the P-type transistor M3, the second electrode of the P-type transistor M4 and the second electrode of the N-type transistor M5 can be coupled to the first output node N11 as the output end of the third logic gate.

[0137] The gate of the P-type transistor M7 and the gate of the N-type transistor M9 can be coupled to the clock signal line CK as the control end of the fourth logic gate; the gate of the P-type transistor M8 and the gate of the N-type transistor M10 can be coupled to the input node N2 as the control end of the fourth logic gate; the first electrode of the P-type transistor M7 and the first electrode of the P-type transistor M8 can be coupled to the first power line VGH as the input end of the fourth logic gate; the first electrode of the N-type transistor M10 can be coupled to the second power line VGL as the input end of the fourth logic gate; and the second electrode of the N-type transistor M10 can also be coupled to the first electrode of the N-type transistor M9; the second electrode of the P-type transistor M7, the second electrode of the P-type transistor M8 and the second electrode of the N-type transistor M9 can be coupled to the second output node N12 as the output end of the fourth logic gate.

[0138] For the structure shown in Figure 6:

[0139] On the start signal line STV, the gate of the P-type transistor M19 and the gate of the N-type transistor M20 can be coupled to the start signal line STV as the control end of the first logic gate; the first electrode of the P-type transistor M19 and the first electrode of the N-type transistor M20 can be coupled to the second power line VGL and the first power line VGH as the input end of the first logic gate respectively; the second electrode of the P-type transistor M19 and the second electrode of the N-type transistor M20 can be coupled to the control end of the third logic gate in the second part 0012 (that is, the gate of the P-type transistor M3 and the gate of the N-type transistor M5) as the output end of the first logic gate.

[0140] On the clock signal line CK, the gate of the P-type transistor M21 and the gate of the N-type transistor M22 can be coupled to the clock signal line CK as the control end of the first logic gate; the first electrode of the P-type transistor M21 and the first electrode of the N-type transistor M22 can be coupled to the second power line VGL and the first power line VGH as the input ends of the first logic gate respectively; the second electrode of the P-type transistor M21 and the second electrode of the N-type transistor M22 can be coupled to the control end of the third logic gate in the second part 0012 (i.e., the gate of the P-type transistor M4 and the gate of the N-type transistor M6) as the output end of the first logic gate, and coupled to the control end of the fourth logic gate in the second part 0012 (i.e., the gate of the P-type transistor M7 and the gate of the N-type transistor M9).

[0141] For the structure shown in Figure 7:

[0142] On the start signal line STV, the gate of the P-type transistor M23 and the gate of the N-type transistor M25 can be coupled to the start signal line STV as the control end of the first logic gate; the first electrode of the P-type transistor M23 and the first electrode of the P-type transistor M24 can be coupled to the first power line VGH as the input end of the first logic gate; the first electrode of the N-type transistor M25 and the first electrode of the N-type transistor M26 can be coupled to the second power line VGL as the input end of the first logic gate; the second electrode of the P-type transistor M23 and the second electrode of the N-type transistor M25 can both be coupled to the gate of the P-type transistor M24 and the gate of the N-type transistor M26; the second electrode of the P-type transistor M24 and the second electrode of the N-type transistor M26 can be coupled to the control end of the third logic gate in the second part 0012 (that is, the gate of the P-type transistor M3 and the gate of the N-type transistor M5) as the output end of the first logic gate.

[0143] On the clock signal line CK, the gate of the P-type transistor M27 and the gate of the N-type transistor M29 can be coupled to the clock signal line CK as the control terminal of the first logic gate; the first electrode of the P-type transistor M27 and the first electrode of the P-type transistor M28 can be coupled to the first power line VGH as the input terminal of the first logic gate; the first electrode of the N-type transistor M29 and the first electrode of the N-type transistor M30 can be coupled to the second power line VGL as the input terminal of the first logic gate; the second electrode of the P-type transistor M27 and the second electrode of the N-type transistor M29 can both be coupled to the gate of the P-type transistor M28 and the gate of the N-type transistor M30; the second electrode of the P-type transistor M28 and the second electrode of the N-type transistor M30 can be coupled to the control terminal of the third logic gate in the second part 0012 (i.e., the gate of the P-type transistor M4 and the gate of the N-type transistor M6) as the output terminal of the first logic gate, and coupled to the control terminal of the fourth logic gate in the second part 0012 (i.e., the gate of the P-type transistor M7 and the gate of the N-type transistor M9).

[0144] Optionally, FIG6 and FIG7 further schematically illustrate parasitic resistance R1 and parasitic capacitance C1 on the start signal line STV and the clock signal line CK.

[0145] Optionally, the material of the P-type transistor may include: Low Temperature Poly-Silicon (LTPS) material. The material of the N-type transistor may include: Oxide material. The transistor material here refers to the material of the active layer included in the transistor. Because the threshold voltage of the N-type transistor made of oxide material is smaller than that of the P-type transistor made of LTPS material, the conduction threshold of the transistor can be adjusted by the width-to-length ratio of the P-type transistor. That is, the transistor made of low-temperature polysilicon material has the advantages of high mobility and fast charging, and the transistor made of oxide material has the advantages of low leakage current. Integrating the two on a display panel, that is, an LTPS+Oxide (LTPO for short) display panel, can take advantage of the advantages of both to achieve low-frequency driving, reduce power consumption, and thus improve display quality.

[0146] It should be noted that, in combination with Figures 5 to 7, it can be seen that the driving unit recorded in the embodiment of the present disclosure only includes multiple transistors and does not include capacitors. Therefore, the problem of poor stability of the output signal to the output terminal OUT caused by coupling between capacitors is avoided, which can further ensure a better display effect.

[0147] Based on the working principle of the NOT gate: if the input is a high potential (logic 1), the output is a low potential (logic 0); conversely, if the input is a low potential (logic 0), the output is a high potential (logic 1); the working principle of the NAND gate: if there are one or more low potentials in the input, the output is a high potential; if all inputs are high potentials, the output is a low potential; and the working principle of the transmission gate: the output and input potentials are the same. It can be seen that by adopting the design method of Figures 5 to 7, the first gate circuit 001, the second gate circuit 002 and the third gate circuit 003 can realize the functions described in the above embodiments. That is, the working principle of the driving unit described in the embodiment of the present disclosure can be summarized as follows:

[0148] Under the control of the clock signal provided by the clock signal line CK, the start signal provided by the start signal line STV can pass through four NAND gates (including two NAND gates in the first gate circuit 001 and two NAND gates in the second gate circuit 002) and be transmitted to the output terminal OUT. The two NAND gates in the first gate circuit 001 have the following transmission characteristics: as long as the potential of the clock signal is high, the output is low. The two NAND gates in the second gate circuit 002 form an RS latch, and the transmission characteristics meet the following requirements: as long as there is a high potential at the input, the output will not change, that is, it will be in a hold state. Accordingly, it can be seen that the transmission characteristics of the entire drive unit can meet the following requirements: if the potential of the clock signal is high, the start signal is changed to the output signal, that is, the start signal can be transmitted to the output terminal OUT. The potential of the clock signal is inverted at the next level, thereby completing the shift register function.

[0149] On this basis, taking the structure shown in FIG5 as an example, FIG8 shows a signal simulation diagram; taking the structure shown in FIG6 as an example, FIG9 shows another signal simulation diagram, and FIG10 shows another signal simulation diagram. Among them, the signal simulation diagram shown in FIG9 can be a driving signal that transmits a low potential to the pixel as the effective potential; the signal simulation diagram shown in FIG10 can be a driving signal that transmits a high potential to the pixel as the effective potential. Moreover, in the signal simulation diagrams shown in FIG8 to FIG10, the horizontal axis refers to time, and the unit can be microseconds (μs), and the vertical axis refers to voltage, and the unit can be volts (V).

[0150] Referring to Figures 8 to 10 , it can be seen that the clock signal provided by the clock signal line CK can be a periodically changing pulse signal, with each waveform transition representing the charging time for a row of pixels, measured in units of 1 hour. Comparing Figures 8 and 9 / 10 further demonstrates that without the addition of the third gate circuit 003, the RC loading effect will cause steps and glitches in the signal transmitted to the output terminal OUT. These glitches are typically at half-peak of the output voltage level. However, with the addition of the third gate circuit 003, since the glitches cannot change the state of the transistors in the third gate circuit 003, they can be effectively filtered out, improving output stability. This means that the signal transmitted to the output terminal OUT does not exhibit the steps and glitches shown in Figure 8 .

[0151] It should be noted that the above designs of the circuit structure are only schematic illustrations, and any structure that can realize the circuit functions recorded in the embodiments of the present disclosure is within the protection scope of the embodiments of the present disclosure.

[0152] Optionally, Figure 11 is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure. As shown in Figure 11, the display panel 10 may further include: a substrate 101, the substrate 101 may have a display area A1 and a non-display area A2 at least partially surrounding the display area. For example, referring to Figure 11, the substrate 101 shown therein has a display area A1, and non-display areas A2 located on the left and right sides of the display area A1. Of course, this is only a schematic illustration. A plurality of pixels may be located in the display area A1 and arranged in an array, that is, may include multiple rows and columns of pixels. The display driving circuit 00 may be located in the non-display area A2. That is, as described in the above embodiment, the display driving circuit 00 may be integrated on the substrate of the display panel, which may be referred to as a GOA circuit.

[0153] Optionally, referring to FIG11 , it can be seen that the scan driving circuit 01 may include: a first scan driving circuit 011 and a second scan driving circuit 012 . The reset driving circuit 03 may include: a first reset driving circuit 031 and a second reset driving circuit 032 .

[0154] The start signal line STV coupled to the first scan driving circuit 011 and the start signal line STV coupled to the second scan driving circuit 012 can be independent of each other. The start signal line STV coupled to the first reset driving circuit 031 and the start signal line STV coupled to the second reset driving circuit 032 can be independent of each other.

[0155] Furthermore, the effective level of the scan drive signal transmitted by the scan drive unit Gate GOA in the first scan drive circuit 011 is opposite to the effective level of the scan drive signal transmitted by the scan drive unit Gate GOA in the second scan drive circuit 012. The effective level of the reset control signal transmitted by the reset drive unit Reset GOA in the first reset drive circuit 031 is opposite to the effective level of the reset control signal transmitted by the reset drive unit Reset GOA in the second reset drive circuit 032. In conjunction with the above embodiments, the effective level here may refer to the effective level that controls the conduction of the transistor; the effective level corresponds to the ineffective level that controls the turn-off of the transistor, i.e., the ineffective level.

[0156] For example, the effective potential of the scan drive signal transmitted by the scan drive unit Gate GOA in the first scan drive circuit 011 can be a low potential, while the effective potential of the scan drive signal transmitted by the scan drive unit Gate GOA in the second scan drive circuit 012 can be a high potential. That is, the effective potential of the scan drive signal transmitted by the scan drive unit Gate GOA in the first scan drive circuit 01 can be lower than the effective potential of the scan drive signal transmitted by the scan drive unit Gate GOA in the second scan drive circuit 01. The effective potential of the reset control signal transmitted by the reset drive unit Reset GOA in the first reset drive circuit 031 can be a low potential, while the effective potential of the reset control signal transmitted by the reset drive unit Reset GOA in the second reset drive circuit 032 can be a high potential. That is, the effective potential of the scan drive signal transmitted by the reset drive unit Reset GOA in the first reset drive circuit 031 can be lower than the effective potential of the scan drive signal transmitted by the reset drive unit Reset GOA in the second reset drive circuit 032.

[0157] For pixels, the pixel circuit generally includes a P-type transistor and an N-type transistor. The P-type transistor is turned on in response to a low-potential signal received by the gate; the N-type transistor is turned on in response to a high-potential signal received by the gate. Therefore, the scan drive unit Gate GOA in the first scan drive circuit 011 can also be called PGate GOA; the scan drive unit Gate GOA in the second scan drive circuit 012 can also be called NGate GOA. Similarly, the reset drive unit Reset GOA in the first reset drive circuit 031 can also be called ResetP GOA, and the reset drive unit Reset GOA in the second reset drive circuit 032 can also be called ResetH GOA. The signal simulation diagram shown in Figure 9 may refer to the signal simulation diagram corresponding to PGate GOA; the signal simulation diagram shown in Figure 10 may refer to the signal simulation diagram corresponding to NGate GOA. In addition, for distinction, the start signal line coupled to PGate GOA is labeled as PGSTV; the start signal line coupled to NGate GOA is labeled as NGSTV; the start signal line coupled to ResetP GOA is labeled as RPSTV; and the start signal line coupled to ResetH GOA is labeled as RHSTV.

[0158] In the embodiment of the present disclosure, the first scan driver circuit 011, the second scan driver circuit 012, the first reset driver circuit 031, the second reset driver circuit 032, and the light-emitting control circuit 02 can all share a single clock signal line CK. Furthermore, considering that a single clock signal line CK may have a heavy load, the line width of the clock signal line CK can be increased to reduce the impedance and parasitic capacitance of the single line.

[0159] Continuing with FIG11 , it can be seen that the first scan driver circuit 011, the second scan driver circuit 012, the first reset driver circuit 031, the second reset driver circuit 032, and the light-emitting driver circuit 02 included in the display driver circuit 00 can be distributed on both sides of multiple rows of pixels in the first direction X. This facilitates a narrow bezel design on both sides. Accordingly, the first direction X can also refer to the row direction.

[0160] 11 , it can be seen that the scan driving circuit 01 may include two first scan driving circuits 011. Since the pixel circuit in a pixel generally includes a large number of P-type transistors, providing two first scan driving circuits 011 here can ensure reliable driving of the P-type transistors.

[0161] Furthermore, the two first scan driving circuits 011, the second scan driving circuit 012, the first reset driving circuit 031, the second reset driving circuit 032, and the light-emitting driving circuit 02 can be evenly distributed in groups of three on both sides in the first direction X. This can further facilitate the narrow bezel design on both sides, so that the areas occupied by the non-display areas A2 on both sides are as similar as possible.

[0162] For example, referring to Figure 11, among the two first scan drive circuits 011, the cascaded multiple scan drive units PGate GOA included in one first scan drive circuit 011 can be located on the first side of the two sides (e.g., the left side of the figure, the following embodiments will not be repeated). The cascaded multiple scan drive units PGate GOA included in the other first scan drive circuit 011 can be located on the second side of the two sides (e.g., the right side of the figure, the following embodiments will not be repeated). That is, the two first scan drive circuits 011 can be distributed on both sides. In this way, reliable driving of the pixels close to the left / right side of the display area A1 can be ensured, avoiding differences in signals output to pixels at different positions due to the influence of Loading, and ensuring better display uniformity.

[0163] Based on Figure 11, as an optional implementation method:

[0164] The cascaded multiple scan driving units NGate GOA included in the second scan driving circuit 012 can be located on the same side of the two sides, the cascaded multiple reset driving units ResetP GOA included in the first reset driving circuit 031 can be located on the same side of the two sides, the cascaded multiple reset driving units ResetH GOA included in the second reset driving circuit 032 are located on the same side of the two sides, and the cascaded multiple light emitting driving units EM GOA included in the light emitting driving circuit 02 can be located on the same side of the two sides.

[0165] For example, on the basis of being evenly distributed in groups of three on both sides of multiple rows of pixels in the first direction X, as shown in FIG11 , the cascaded multiple reset driving units ResetP GOA included in the first reset driving circuit 031 and the cascaded multiple reset driving units ResetH GOA included in the second reset driving circuit 032 can both be located on the first side of the two sides. The cascaded multiple scan driving units NGate GOA included in the second scan driving circuit 012 and the cascaded multiple light emitting driving units EM GOA included in the light emitting driving circuit 02 can both be located on the second side of the two sides.

[0166] 11 , in the first direction X and in the direction close to the display area, on the first side, the second reset driver circuit 032 (i.e., ResetH GOA), the first reset driver circuit 031 (i.e., ResetP GOA), and one first scan driver circuit 011 (i.e., PGate GOA) can be arranged in that order. On the second side, the second scan driver circuit (i.e., NGate GOA), the light emitting driver circuit 02 (i.e., EM GOA), and another first scan driver circuit 012 (i.e., PGate GOA) can be arranged in that order.

[0167] That is, the first reset driving circuit 031 including the cascaded multiple reset driving units ResetP GOA, the second reset driving circuit 032 including the cascaded multiple reset driving units ResetH GOA, and the first scan driving circuit 011 including the cascaded multiple scan driving units PGate GOA are grouped together and disposed on the first of the two sides. The second scan driving circuit 012 including the cascaded multiple scan driving units, the scan driving circuit 02 including the cascaded multiple emission driving units EM GOA, and the other first scan driving circuit 011 including the cascaded multiple scan driving units PGate GOA are grouped together and disposed on the second of the two sides.

[0168] Based on FIG11 , refer to FIG12 as another optional implementation:

[0169] The multiple cascaded scan drive units NGate GOA included in the second scan drive circuit 012 can be located on the first and second sides of the two sides, respectively. The multiple cascaded reset drive units ResetP GOA included in the first reset drive circuit 031 can be located on the first and second sides of the two sides, respectively. The multiple cascaded reset drive units ResetH GOA included in the second reset drive circuit 032 can be located on the first and second sides of the two sides, respectively. Furthermore, the multiple cascaded light-emitting drive units EM GOA included in the light-emitting drive circuit 02 can be located on the first and second sides of the two sides, respectively.

[0170] For example, based on the uniform distribution of three scan drive units NGate GOA on both sides of multiple rows of pixels in the first direction X, as shown in FIG11 , the second scan drive circuit 012 can be configured such that every two adjacent scan drive units NGate GOA are located on the first side and the second side, respectively. The first reset drive circuit 031 can be configured such that every two adjacent reset drive units ResetP GOA are located on the first side and the second side, respectively. The second reset drive circuit 032 can be configured such that every two adjacent reset drive units ResetH GOA are located on the first side and the second side, respectively. The light emitting drive circuit 02 can be configured such that every two adjacent light emitting drive units EM GOA are located on the first side and the second side, respectively.

[0171] Furthermore, along the second direction Y of the multiple columns of pixels, the reset driving units ResetH GOA included in the second reset driving circuit 032 and the scan driving units NGate GOA included in the second scan driving circuit 012 can be arranged alternately on the first and second sides. The reset driving units ResetP GOA included in the first reset driving circuit 031 and the light-emitting driving units EM GOA included in the light-emitting driving circuit 02 can also be arranged alternately. Accordingly, the second direction Y can also refer to the column direction. The second direction Y and the first direction X can intersect. For example, referring to Figures 11 and 12, the second direction Y and the first direction X shown therein are perpendicular to each other.

[0172] That is, based on FIG11 , the cascaded multiple light-emitting driving units EM GOA included in the light-emitting driving circuit 02 and the cascaded multiple reset driving units ResetP GOA included in the first reset driving circuit 031 can be arranged alternately on the left and right sides; and the cascaded multiple reset driving units ResetH GOA included in the second reset driving circuit 032 and the cascaded multiple scan driving units NGate GOA included in the second scan driving circuit 012 can be arranged alternately on the left and right sides. In this way, the multiple light-emitting driving units EM GOA included in the light-emitting driving circuit 02, the multiple reset driving units ResetP GOA included in the first reset driving circuit 031, the multiple reset driving units ResetH GOA included in the second reset driving circuit 031, and the multiple scan driving units NGate GOA included in the second scan driving circuit 012 can all transmit required signals to pixels from the left and right sides, just like the multiple scan driving units PGate GOA included in the first scan driving circuit 011. Furthermore, compared with transmitting the required signal to the pixel from a single side, it can avoid the difference in signals transmitted to pixels at different positions due to the influence of loading, and can further ensure better display uniformity of the display panel.

[0173] It should be noted that the above layout designs are merely illustrative. For example, the above embodiments illustrate the driving units included in different driving circuits by using one driving unit coupled to a row of pixels, with a one-push-one signal transmission method. However, in some embodiments, a one-push-multiple design may be employed. That is, one driving unit is coupled to multiple rows of pixels, simultaneously transmitting the required signals (e.g., light control signals) to the multiple rows of pixels.

[0174] Based on the above-mentioned embodiment records, it can be seen that the display driving circuit recorded in the embodiment of the present disclosure has the following advantages: First, it can reduce the required border area, which is conducive to the narrow border design of the display device; second, it can solve the problem of signal waveform disorder, ensure good output stability and reliability, and thus ensure that the display effect of the display panel can be better.

[0175] In summary, an embodiment of the present disclosure provides a display driving circuit. The display driving circuit includes a scanning driving circuit, a light-emitting driving circuit and a reset driving circuit. Among them, the multiple scanning driving units cascaded in the scanning driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the scanning driving signal to the pixel based on the signal provided by the coupled signal line; the multiple light-emitting driving units cascaded in the light-emitting driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the light-emitting control signal to the pixel based on the signal provided by the coupled signal line; the multiple reset driving units cascaded in the reset driving circuit are respectively coupled to the clock signal line and the turn-on signal line, and transmit the reset control signal to the pixel based on the signal provided by the coupled signal line, so as to drive the pixel to emit light. In addition, the scanning driving circuit, the light-emitting driving circuit and the reset driving circuit that provide different signals to the pixel share a clock signal line, which can facilitate a narrow frame design.

[0176] FIG13 is a flow chart of a display driving method provided by an embodiment of the present disclosure, which can be applied to the display driving circuit described in the above embodiment and can be used to drive a display panel, wherein the display panel includes a plurality of pixels. As shown in FIG13 , the method includes:

[0177] Step 1301: Provide an enable signal to the enable signal line, and provide a clock signal to the clock signal line.

[0178] Step 1302: The scan driving circuit transmits a scan driving signal to a plurality of pixels based on the received start signal and clock signal.

[0179] Step 1303: The light driving circuit transmits a light control signal to a plurality of pixels based on the received start signal and clock signal.

[0180] Step 1304: The reset driving circuit transmits a reset control signal to the plurality of pixels based on the received start signal and clock signal.

[0181] The scan drive signal, the light emitting control signal and the reset control signal can be used to drive a plurality of pixels to emit light, so that the display panel performs display.

[0182] Since the driving method can have substantially the same implementation manner and technical effects as the display driving circuit described in the previous embodiment, for the purpose of brevity, the implementation manner and technical effects of the driving method will not be repeatedly described here.

[0183] FIG14 is a schematic structural diagram of a display device provided by an embodiment of the present disclosure. As shown in FIG14 , the display device includes: a display panel 10 and a display driving circuit 00 as described in the above embodiment.

[0184] The display driving circuit 00 is coupled to a plurality of pixels in the display panel 10 and is used to drive the plurality of pixels to emit light.

[0185] Optionally, the display device may be an OLED display device, an active-matrix organic light-emitting diode (AMOLED) display device, or any product or component having a display function.

[0186] Since the display device can have substantially the same technical effects as the display driving circuit described in the previous embodiment, for the purpose of brevity, the implementation manner and technical effects of the display device will not be repeatedly described here.

[0187] It should be noted that the terms used in the examples of this disclosure are only used to explain the examples and are not intended to limit the present disclosure. Unless otherwise defined, technical terms or scientific terms used in the embodiments of this disclosure should have the common meanings understood by people with ordinary skills in the field to which this disclosure belongs.

[0188] For example, the words "first", "second" or "third" and similar words used in the patent application specification and claims of this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components.

[0189] When we say an element is "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intermediate elements may be present. In addition, "connected" or "coupled" as used herein may include wireless connection or wireless coupling.

[0190] Likewise, the words “a” or “an” and the like do not denote a limitation of quantity, but rather denote the presence of at least one.

[0191] Words such as “include” or “comprising” mean that the elements or objects preceding “include” or “comprising” include the elements or objects listed after “include” or “comprising” and their equivalents, and do not exclude other elements or objects.

[0192] “Up,” “down,” “left,” or “right” are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0193] The above description is merely an optional embodiment of the present disclosure and is not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure shall be included in the scope of protection of the present disclosure.

Claims

1. A display driving circuit, applied to a display panel, wherein the display panel comprises a plurality of pixels; the display driving circuit comprises: A scan driving circuit, comprising a plurality of cascaded scan driving units, respectively coupled to the clock signal line and the start signal line, and also coupled to the plurality of pixels, and used for transmitting a scan driving signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and a start signal provided by the coupled start signal line; A light-emitting driving circuit, comprising a plurality of light-emitting driving units connected in cascade, respectively coupled to a clock signal line and an opening signal line, and also coupled to the plurality of pixels, and used for transmitting a light-emitting control signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and an opening signal provided by the coupled opening signal line; A reset driving circuit, comprising a plurality of reset driving units connected in cascade, respectively coupled to the clock signal line and the start signal line, and also coupled to the plurality of pixels, and used for transmitting a reset control signal to the plurality of pixels in response to a clock signal provided by the coupled clock signal line and a start signal provided by the coupled start signal line; Wherein, the clock signal lines coupled to the plurality of scan driving units, the clock signal lines coupled to the plurality of light-emitting driving units, and the clock signal lines coupled to the plurality of reset driving units are shared; Furthermore, the start signal lines coupled to the plurality of scan driving units, the start signal lines coupled to the plurality of light emitting driving units, and the start signal lines coupled to the plurality of reset driving units are independent of each other.

2. The display driving circuit according to claim 1, wherein: At least one of the scanning driving unit, the light emitting driving unit and the reset driving unit comprises: A first gate circuit is coupled to the start signal line, the clock signal line, the first power line, the second power line and the output node respectively, and is used to control the connection and disconnection between the first power line and the output node, and control the connection and disconnection between the second power line and the output node in response to the clock signal and the start signal; a second gate circuit, coupled to the output node, the first power line, the second power line and the output terminal respectively, and used to control the connection and disconnection between the first power line and the output terminal and the connection and disconnection between the second power line and the output terminal in response to the potential of the output node; Among them, the output ends of the multiple scan driving units are coupled to the multiple pixels through multiple scan lines, the output ends of the multiple light-emitting driving units are coupled to the multiple pixels through multiple light-emitting control lines, and the output ends of the multiple reset driving units are coupled to the multiple pixels through multiple reset control lines.

3. The display driving circuit according to claim 2, wherein: The output node includes: a first output node and a second output node; the first gate circuit includes: The first part is coupled to the start signal line, the first power line, the second power line and the input node respectively, and is used to control the connection and disconnection between the first power line and the input node and the connection and disconnection between the second power line and the input node in response to the start signal, so as to invert the start signal into an inverted start signal and then transmit it to the input node; The second part is coupled to the start signal line, the clock signal line, the first power line, the second power line, the input node, the first output node and the second output node, respectively, and is used to control the on-off of the first power line and the first output node, and control the on-off of the second power line and the first output node in response to the start signal and the clock signal; and control the on-off of the first power line and the second output node, and control the on-off of the second power line and the second output node in response to the inverted start signal and the clock signal.

4. The display driving circuit according to claim 3, wherein: The at least one driving unit further comprises: a third gate circuit, connected in series between the target signal line and the second part, and also coupled to the first power line and the second power line respectively, and used for controlling the on-off of the first power line and the second part, and controlling the on-off of the second power line and the second part in response to the target signal provided by the target signal line; Wherein, the target signal line includes: at least one of the clock signal line and the start signal line.

5. The display driving circuit according to claim 4, wherein: The target signal line includes: the clock signal line and the start signal line.

6. The display driving circuit according to claim 4, wherein: The third gate circuit includes: at least one first logic gate; Wherein, the control end of the at least one first logic gate is coupled to the target signal line, the input end of the at least one first logic gate is coupled to the first power line and the second power line respectively, and the output end of the at least one first logic gate is coupled to the second part.

7. The display driving circuit according to claim 6, wherein: The at least one first logic gate includes: a transmission gate.

8. The display driving circuit according to claim 6, wherein: The at least one first logic gate includes: an even number of first NOT gates connected in series.

9. The display driving circuit according to claim 8, wherein: The at least one first logic gate includes: two first NOT gates connected in series.

10. The display driving circuit according to any one of claims 3 to 9, wherein: The first part of the first gate circuit includes: a second logic gate; the second part of the first gate circuit includes: a third logic gate and a fourth logic gate; the second gate circuit includes: a fifth logic gate and a sixth logic gate; The control end of the second logic gate is coupled to the start signal line, the input end of the second logic gate is coupled to the first power line and the second power line respectively, and the output end of the second logic gate is coupled to the input node; The control end of the third logic gate is coupled to the start signal line and the clock signal line respectively, the input end of the third logic gate is coupled to the first power line and the second power line respectively, and the output end of the third logic gate is coupled to the first output node; The control end of the fourth logic gate is coupled to the clock signal line and the input node respectively, the input end of the fourth logic gate is coupled to the first power line and the second power line respectively, and the output end of the fourth logic gate is coupled to the second output node; The control end of the fifth logic gate is coupled to the first output node and the output end of the sixth logic gate respectively, and the input end of the fifth logic gate is coupled to the first power line and the second power line respectively; The control end of the sixth logic gate is connected to the second output node and the input end of the fifth logic gate respectively. The output end of the sixth logic gate is coupled to the first power line and the second power line respectively, and the output end of the fifth logic gate is also coupled to the pixel as the output end of the second gate circuit.

11. The display driving circuit according to claim 10, wherein: The second logic gate includes: a second NOT gate; the third logic gate, the fourth logic gate, the fifth logic gate and the sixth logic gate all include: a NAND gate.

12. The display driving circuit according to any one of claims 4 to 11, wherein: Among the first gate circuit, the second gate circuit and the third gate circuit, at least one gate circuit includes a logic gate including: at least one P-type transistor and at least one N-type transistor.

13. The display driving circuit according to claim 12, wherein: The material of the P-type transistor includes: low-temperature polysilicon material; the material of the N-type transistor includes: oxide material.

14. The display driving circuit according to any one of claims 1 to 13, wherein: The display panel further comprises: a substrate, the substrate having a display area and a non-display area at least partially surrounding the display area, the plurality of pixels being located in the display area and arranged in an array; The scan driving circuit includes: a first scan driving circuit and a second scan driving circuit; the reset driving circuit includes: a first reset driving circuit and a second reset driving circuit; The start signal line coupled to the first scan driving circuit and the start signal line coupled to the second scan driving circuit are independent of each other; the start signal line coupled to the first reset driving circuit and the start signal line coupled to the second reset driving circuit are independent of each other; Furthermore, the potential of the effective level of the scan driving signal transmitted by the scan driving unit in the first scan driving circuit is opposite to the potential of the effective level of the scan driving signal transmitted by the scan driving unit in the second scan driving circuit; the potential of the effective level of the reset control signal transmitted by the reset driving unit in the first reset driving circuit is opposite to the potential of the effective level of the reset control signal transmitted by the reset driving unit in the second reset driving circuit; The display driving circuit is located in the non-display area; and the display driving circuit includes a first scanning driving circuit, a second scanning driving circuit, a first reset driving circuit, a second reset driving circuit and a light-emitting driving circuit distributed on both sides of multiple rows of pixels in the first direction.

15. The display driving circuit according to claim 14, wherein: The potential of the scan driving signal transmitted by the scan driving unit in the first scan driving circuit is lower than the potential of the scan driving signal transmitted by the scan driving unit in the second scan driving circuit; The scanning driving circuit comprises: two first scanning driving circuits; Furthermore, the two first scan driving circuits, the second scan driving circuit, the first reset driving circuit, the second reset driving circuit and the light emitting driving circuit are evenly distributed on both sides in the first direction in groups of three.

16. The display driving circuit according to claim 15, wherein: Among the two first scan driving circuits, a plurality of cascaded scan driving units included in one first scan driving circuit are located on a first side of the two sides; and a plurality of cascaded scan driving units included in the other first scan driving circuit are located on a second side of the two sides; The plurality of cascaded scan driving units included in the second scan driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides; The plurality of cascaded reset driving units included in the first reset driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides; The plurality of cascaded reset driving units included in the second reset driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides; The plurality of cascaded light emitting driving units included in the light emitting driving circuit are located on the same side of the two sides, or are respectively located on the first side and the second side of the two sides.

17. The display driving circuit according to claim 16, wherein: The plurality of cascaded scan driving units included in the second scan driving circuit are located on the same side of the two sides, the plurality of cascaded reset driving units included in the first reset driving circuit are located on the same side of the two sides, the plurality of cascaded reset driving units included in the second reset driving circuit are located on the same side of the two sides, and the plurality of cascaded light emitting driving units included in the light emitting driving circuit are located on the same side of the two sides; Wherein, the cascaded multiple reset driving units included in the first reset driving circuit and the cascaded multiple reset driving units included in the second reset driving circuit are both located on the first side of the two sides; The second scanning driving circuit includes a plurality of scanning driving units connected in cascade and the light emitting driving circuit The plurality of cascaded light-emitting driving units included in the circuit are all located on the second side of the two sides; Furthermore, in the first direction and along the direction close to the display area, on the first side, the second reset drive circuit, the first reset drive circuit and a first scan drive circuit are arranged in order; on the second side, the second scan drive circuit, the light emitting drive circuit and another first scan drive circuit are arranged in order.

18. The display driving circuit according to claim 16, wherein: The plurality of cascaded scan driving units included in the second scan driving circuit are respectively located on the first side and the second side of the two sides; the plurality of cascaded reset driving units included in the first reset driving circuit are respectively located on the first side and the second side of the two sides; the plurality of cascaded reset driving units included in the second reset driving circuit are respectively located on the first side and the second side of the two sides; the plurality of cascaded light-emitting driving units included in the light-emitting driving circuit are respectively located on the first side and the second side of the two sides; Among the plurality of cascaded scan driving units included in the second scan driving circuit, every two adjacent scan driving units are located at the first side and the second side respectively; Among the plurality of cascaded reset driving units included in the first reset driving circuit, every two adjacent reset driving units are located at the first side and the second side respectively; Among the plurality of cascaded reset driving units included in the second reset driving circuit, every two adjacent reset driving units are located at the first side and the second side respectively; Among the plurality of cascaded light-emitting driving units included in the light-emitting driving circuit, every two adjacent light-emitting driving units are located at the first side and the second side respectively; Furthermore, along the second direction of the multiple columns of pixels, on the first side and the second side, the reset driving units included in the second reset driving circuit and the scanning driving units included in the second scanning driving circuit are arranged alternately; the reset driving units included in the first reset driving circuit and the light-emitting driving units included in the light-emitting driving circuit are arranged alternately, and the second direction intersects with the first direction.

19. A display driving method, applied to the display driving circuit according to any one of claims 1 to 18, and used to drive a display panel to display, wherein the display panel comprises a plurality of pixels; the method comprising: providing an enable signal to the enable signal line and providing a clock signal to the clock signal line; The scan driving circuit transmits a scan driving signal to the plurality of pixels based on the received start signal and the clock signal; The light-emitting driving circuit transmits a light-emitting control signal to the plurality of pixels based on the received start-up signal and the clock signal; The reset driving circuit transmits a reset control signal to the plurality of pixels based on the received start signal and the clock signal; The scan drive signal, the light emitting control signal and the reset control signal are used to drive the plurality of pixels to emit light, so that the display panel performs display.

20. A display device, comprising: A display panel, and a display driving circuit as claimed in any one of claims 1 to 18; The display driving circuit is coupled to a plurality of pixels in the display panel and is used to drive the plurality of pixels to emit light.

Images