Critical path sorting method based on graph neural network

Abstract

The present invention relates to the technical field of calculation, estimation or counting. Disclosed is a critical path sorting method based on a graph neural network. The method comprises: first, obtaining a potential critical path set in a netlist by means of a static timing analysis tool; next, converting a netlist file comprising circuit function information into a graph data structure, and obtaining an initial training set on the basis of a relevant process configuration file; then, inputting the initial training set into a graph neural network for training to obtain a critical unit prediction model, wherein the critical unit prediction model consists of three parts, namely, a deep structure auto-encoder, a nonlinear attribute auto-encoder and a joint error reconstruction module; and finally, quantifying the criticality of each path in the potential critical path set on the basis of critical unit information and a path criticality calculation algorithm in the netlist, and obtaining a critical path sequence under process awareness. According to the method, critical paths in circuits influenced by process deviations can be effectively sorted, providing valuable reference for circuit optimization.

Description

A critical path sorting method based on graph neural network Technical Field

[0001] The present invention relates to integrated circuit design automation (EDA) technology, and specifically discloses a critical path sorting method based on a graph neural network, belonging to the technical field of calculation, inference or counting. Background Art

[0002] As the demand for chip data processing capabilities and battery life continues to increase in the Internet of Things and mobile devices, reducing chip data processing power consumption and improving energy efficiency have become core issues in chip design. Traditional low-power technologies exploit the fact that power consumption decreases with the square of voltage, reducing power consumption by lowering the supply voltage. Subthreshold circuit design significantly reduces circuit power consumption by lowering the supply voltage below the threshold voltage. This design approach is being applied to devices such as wireless sensors that require lower performance but extremely low power consumption.

[0003] Process variation refers to the phenomenon in which process parameters such as transistor length, gate oxide thickness, and doping concentration deviate from their nominal values ​​during the integrated circuit manufacturing process due to factors such as equipment precision and process limitations. Due to process variation, the delay characteristics of a circuit will change as the process parameters change. Ultimately, if the delay variation on a critical path exceeds the set timing constraints, the circuit may fail. Therefore, in low-voltage integrated circuit design, accurately identifying and optimizing critical paths that are most affected by process variation is a key approach to improving chip performance and reliability.

[0004] At conventional voltages, delay fluctuations due to process variations are small, so the critical paths of the circuit can be selected by ranking the paths based on their timing margins, as determined by traditional timing analysis methods. However, as the supply voltage decreases, delay fluctuations due to process variations increase, and different units exhibit different timing behaviors due to process variations, potentially changing the critical path ranking.

[0005] Existing static timing analysis tools cannot accurately consider the impact of process variations, making it difficult to accurately determine the critical path in a circuit after being affected by process variations. Existing circuit simulation tools can perform process variation-aware circuit simulation of the entire circuit, and the results obtained are very accurate, but this is not feasible due to the excessive time required.

[0006] Graph Neural Networks (GNNs) have demonstrated powerful processing capabilities for irregular, disordered, and unstructured non-Euclidean spatial data, providing a new approach for pattern recognition and data mining. This application aims to combine GNNs with integrated circuit design automation technology to accurately identify critical paths in low-voltage power supply situations through a GNN-based critical path sorting method.

[0007] Summary of the Invention

[0008] The purpose of the present invention is to address the deficiencies of the above-mentioned background technology and provide a critical path sorting method based on graph neural network, so as to achieve the invention purpose of more accurately sorting the critical paths in integrated circuits affected by process deviations in low-voltage integrated circuit design, so as to solve the technical problem that traditional static timing analysis technology cannot accurately identify critical paths that are greatly affected by process deviations under low-voltage power supply conditions.

[0009] The present invention adopts the following technical solutions to achieve the above-mentioned purpose:

[0010] A critical path sorting method based on graph neural network includes the following steps:

[0011] Step S1, obtaining a potential critical path set from a circuit netlist using a static timing analysis tool;

[0012] Step S2, converting the circuit netlist file into a graph data structure and initializing a training set according to the configuration file;

[0013] Step S3: training the graph neural network using the initialized training set to obtain a key unit prediction model for predicting unit criticality scores;

[0014] In step S4, the read netlist of the circuit to be tested is input into the trained critical unit prediction model to obtain the criticality score of each unit in the circuit to be tested, and the criticality of all potential critical paths is calculated by combining the unit parameters that characterize the relationship between the critical unit and the potential critical path and the timing margin of the potential critical path. The criticality calculation results of all potential critical paths are sorted to obtain the critical path ranking after the circuit to be tested is affected by process deviation.

[0015] As a further optimization scheme of the critical path sorting method based on graph neural network, the potential critical path set obtained from the circuit netlist by the static timing analysis tool in step S1 includes the path set passing through the timing endpoint and the path set passing through the unit.

[0016] As a further optimization scheme of the critical path sorting method based on graph neural network, the method for obtaining the path set passing through the timing endpoint is: for at least one path passing through the current timing endpoint, n paths with the smallest timing slack are extracted as the path set passing through the current timing endpoint, and the path sets passing through each timing endpoint constitute the path set passing through the timing endpoint, where n is an integer greater than or equal to 1.

[0017] As a further optimization scheme of the critical path sorting method based on graph neural network, the method for obtaining the path set passing through the unit is: for at least one path passing through the current unit, extract the path with the smallest timing slack as the path passing through the current unit, and the paths through each unit in the circuit constitute the path set passing through the unit.

[0018] As a further optimization scheme of the critical path sorting method based on graph neural network, the method of converting the circuit netlist file into a graph data structure in step S2 is as follows: define an undirected graph with nodes and attributes Represents a circuit, is the node set representing the unit, Indicates that the graph structure data has n nodes, v (1) ,v (2) ,...,v (n) is the 1st, 2nd, ..., nth node, ε is the edge set representing the connection relationship between units, |ε| = m means that the graph structure data has m edges, X is the node attribute set, The i-th row vector is the k-dimensional attribute information of the i-th node.

[0019] As a further optimization scheme for the critical path sorting method based on graph neural network, the specific method of step S2 and initializing the training set according to the configuration file is as follows:

[0020] Step S2.1, obtaining transistor-level primitive attributes and cell-level primitive attributes related to process variation effects from configuration files including but not limited to circuit netlist files, cell process library files, SPEF parasitic files, and timing reports, and constructing an attribute matrix based on the primitive attributes of each cell;

[0021] Step S2.2, obtaining the connection relationship between cells from the circuit netlist file, and constructing an adjacency matrix based on the connection relationship between cells;

[0022] Step S2.3, obtain the timing margin of each potential critical path set under process deviation, the units on the top K% potential critical paths with the smallest timing margin under process deviation are critical units, and the remaining units are non-critical units. According to whether each unit in the circuit is a critical unit, a binary label is assigned to each node in the graph data structure. The attribute matrix, adjacency matrix and binary labels of each node constitute the initialized training set.

[0023] As a further optimization scheme of the critical path sorting method based on graph neural network, the specific method of step S3 to train the graph neural network through the initialized training set is: obtain the node embedding matrix and the structural reconstruction error of each node according to the attribute matrix and adjacency matrix of the graph structure data, obtain the attribute reconstruction error of each node according to the attribute matrix and node embedding matrix of the graph structure data, and calculate the unit criticality score according to the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node.

[0024] As a further optimization scheme of the critical path ranking method based on graph neural network, the expression of the unit criticality score is calculated based on the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node: in, is the criticality score of the unit mapped to the vth node, The normalized value of the abnormality score of the unit mapped to the vth node, s (v) is the average of the structure reconstruction error and attribute reconstruction error of the vth node.

[0025] As a further optimization scheme for the critical path sorting method based on graph neural networks, the cell parameters that characterize the relationship between the critical cell and the potential critical path in step S4 include but are not limited to cell location information, the number of transistors in the cell, and the drive strength. The expression for calculating the criticality of all potential critical paths by combining the cell parameters that characterize the relationship between the critical cell and the potential critical path and the potential critical path timing margin is: Among them, PC j is the criticality calculation result of the jth potential critical path of the circuit under test, N j is the unit set of the jth potential critical path of the circuit under test, is the location information of the i-th unit on the j-th potential critical path, is the number of transistors in the i-th unit on the j-th potential critical path, is the driving strength of the i-th unit on the j-th potential critical path, is the criticality score of the i-th unit on the j-th potential critical path, is the normalized value of the timing slack of the jth potential critical path.

[0026] As a further optimization scheme of the critical path sorting method based on graph neural network, the key unit prediction model includes: a deep structure autoencoder, a nonlinear attribute autoencoder and a joint reconstruction error module; the deep structure autoencoder is used to encode the attribute matrix and adjacency matrix of the graph structure data, generate a node embedding matrix, reconstruct the adjacency matrix of the graph structure data according to the node embedding matrix, obtain the reconstructed adjacency matrix, and generate the structural reconstruction error of each node according to the adjacency matrix of the graph structure data and the reconstructed adjacency matrix; the nonlinear attribute autoencoder is used to encode the attribute matrix of the graph structure data, generate a deep attribute embedding matrix, reconstruct the attribute matrix of the graph structure data according to the deep attribute embedding matrix and the node embedding matrix, obtain the reconstructed attribute matrix, and generate the attribute reconstruction error of each node according to the attribute matrix of the graph structure data and the reconstructed attribute matrix; the joint reconstruction error module is used to calculate the unit criticality score according to the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node.

[0027] The present invention adopts the above technical solution and has the following beneficial effects:

[0028] (1) The present invention utilizes graph neural network technology, especially the concept of anomaly detection through graph neural networks. First, by utilizing the attribute characteristics and structural characteristics of the graph structure corresponding to the circuit, it can identify the units of the integrated circuit that are more affected by process deviations in low-voltage design; then, combined with the critical path identification algorithm, it gives a more accurate ranking of the critical paths in the integrated circuit affected by process deviations, with fast speed and high accuracy.

[0029] (2) The critical path sorting method proposed in the present invention can accurately give the critical path sorting of the circuit affected by process deviation in the static timing analysis tool in the integrated circuit design, accelerate the timing convergence speed of the integrated circuit design to meet the integrated circuit timing requirements, shorten the integrated circuit design cycle, improve the reliability of the integrated circuit design, and improve the integrated circuit production yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] FIG1 is a flowchart of a critical path sorting method based on a graph neural network proposed in the present invention.

[0031] Figure 2 is a specific flow chart of a key path sorting method based on graph neural network of the present invention.

[0032] FIG3 is a specific flow chart of step S3 of the critical path sorting method proposed in the present invention, in which the initial training set is input into the graph neural network training to obtain the key unit prediction model. DETAILED DESCRIPTION

[0033] The technical solution of the invention is described in detail below with reference to the accompanying drawings.

[0034] This paper proposes a critical path ranking method based on graph neural networks, which consists of two parts: critical cell detection and path criticality calculation. Critical cells are cells in a circuit that are significantly affected by process variations. We use graph neural networks to predict critical cells in low-voltage circuits that are significantly affected by process variations. We also employ a path criticality calculation algorithm that considers both circuit-level and transistor-level parameters to generate a ranked list of path criticality.

[0035] The present invention proposes a critical path sorting method based on graph neural network, as shown in Figure 1-2, including the following steps S1 to S4.

[0036] S1, using the static timing analysis (STA) tool to obtain the potential critical path set from the circuit netlist. The potential critical path set is the path set with relatively critical timing before considering process deviations.

[0037] The number of paths in a circuit is often very large, making timing simulation of the entire circuit extremely time-consuming and unnecessary. Therefore, when screening critical paths from a circuit, we can preemptively remove a large number of paths that are unlikely to cause timing issues and screen only from the set of potential critical paths. Using the STA tool, we extract the set of paths that pass through the timing endpoint and the set of paths that pass through each cell. The method for extracting the set of paths that pass through the timing endpoint is as follows: for multiple paths that pass through the current timing endpoint, we extract the n paths with the smallest timing slack as the path set that passes through the current timing endpoint. The set of paths that pass through each timing endpoint forms the set of paths that pass through the timing endpoint. The method for extracting the set of paths that pass through each cell is as follows: for multiple paths that pass through the current cell, we extract the path with the smallest timing slack as the path that passes through the current cell. The paths that pass through each cell in the circuit form the set of paths that pass through the cell. The set of paths that pass through the timing endpoint and the set of paths that pass through the cell are combined to form the set of potential critical paths. The size of the potential critical path set is ultimately affected by the number n. The timing margins of all paths in this potential critical path set are already determined during path extraction. The final critical path after process deviation will be generated from this set.

[0038] S2, convert the netlist file into a graph data structure and obtain the initial training set according to the relevant configuration file;

[0039] From a machine learning research perspective, detecting key units should be considered an anomaly detection task. Furthermore, circuits are easily represented as graphs, where units are considered nodes and connections between units are considered edges. Therefore, in this paper, a graph neural network is used to learn the latent representations of units and predict key units in the circuit.

[0040] We define an undirected graph with nodes and attributes To represent the circuit, it includes: (1) node set in That is, the graph structure has n nodes; (2) edge set ε, where |ε| = m, that is, the graph structure has m edges; (3) node attributes The i-th row vector is the attribute information of the i-th node, indicating that the node v (i) This application uses attribute network Correspondingly, the graph structure information is represented by the attribute matrix X of the characteristics of each node in the circuit and the adjacency matrix A of the circuit topology structure. Combined with the label vector y indicating whether the unit is critical, it constitutes the initial training set of the critical unit prediction model under the training process deviation.

[0041] In order to obtain the initial training set, we need three steps S2.1 to S2.3.

[0042] S2.1, obtain the original attribute information of the node:

[0043] Before using graph neural networks, a raw attribute matrix is ​​required. We obtain transistor-level and cell-level raw attributes related to process variation effects from configuration files such as circuit netlist files, cell process library files, SPEF parasitic files, and timing reports. When determining the initial attributes of a target cell, we need to consider not only the attributes of the cell itself but also the attributes of its input and output cells.

[0044] S2.2, obtain the adjacency matrix of the network:

[0045] We obtain the connection relationship between cells through the circuit netlist file. If two cells are directly connected to each other, their corresponding values ​​in the adjacency matrix are assigned to 1, otherwise they are assigned to 0.

[0046] S2.3, assign labels to nodes;

[0047] Each node in the graph structure has a binary label y (v) , "0" indicates that the cell is not critical, and "1" indicates that the cell is critical. Using process variation-aware circuit simulation software, the potential critical path set is simulated to obtain the top K% of paths with the smallest timing margins, which is the "Top-K% Critical Path Set" under process variation. Critical cells are those located on the Top-K% critical path set, while the remaining cells are considered non-critical. The value of "K" can be adjusted to meet critical path selection requirements of varying degrees of severity.

[0048] The attribute matrix, adjacency matrix, and labels of each node will be used as the initial training set to train the graph neural network.

[0049] S3, input the initial training set into the graph neural network training to obtain the key unit prediction model;

[0050] Figure 3 shows the flowchart of this step. The graph neural network uses the method of node anomaly detection to identify key units in the circuit. The framework consists of three basic components: deep structure autoencoder, nonlinear attribute autoencoder, and joint reconstruction error module.

[0051] The deep structured autoencoder consists of two parts: a structure encoder and a structure decoder. The structure encoder captures the potential structural information of the circuit through a graph neural network. Specifically, first, the deep graph structure encoder takes the attribute matrix X and the adjacency matrix A of the original circuit as input, and generates a node embedding matrix E through graph neural network encoding. The node embedding matrix E represents the deep information of each node in the graph structure used by the graph neural network; then, the structure decoder reconstructs the adjacency matrix of the original graph structure data based on the embedding result E to generate a reconstructed adjacency matrix This matrix can be used to output the structural reconstruction error of each node from the perspective of the circuit network structure: where a (v) ∈A, They respectively represent the adjacency relationship of the node in the original adjacency matrix and the adjacency relationship of the node in the reconstructed adjacency matrix.

[0052] Similar to the deep structure autoencoder, the nonlinear attribute autoencoder consists of two parts: the attribute encoder and the attribute decoder. First, the attribute encoder transforms the unit attribute matrix X through a nonlinear transformation layer to generate a deep attribute embedding matrix Z, which represents the deep information of the unit attribute; then, the attribute decoder reconstructs the attribute information of the original graph structure data based on the embedding result E generated by the deep structure encoder in the previous step and the deep attribute embedding matrix Z to obtain the reconstructed attribute matrix It can be used to output the cell attribute reconstruction error of each node from the perspective of cell attributes where x (v) ∈X, They respectively represent the original attribute characteristics and the new reconstructed attribute characteristics of the node.

[0053] We define the joint reconstruction error s (v) , To reflect the abnormality of each node. (v)is the abnormality score of each node. The joint reconstruction error is obtained by combining the circuit structure reconstruction error and the unit attribute reconstruction error. Generally, the average of the two is taken, that is, s (v) =(s A (v) +s X (v) ) / 2, In this way, the abnormality score s of each node is obtained (v) ; will s (v) Normalization obtains the normalized joint reconstruction error The subscript N indicates that the value has been normalized; finally, the sigmoid function is used to convert Mapped to a criticality score reflecting the criticality of the unit in the circuit diagram The criticality score also represents the likelihood that the unit is a critical unit.

[0054] S4, using the critical unit prediction model trained in S3 to predict the criticality scores of all units in the circuit under test, combined with the path criticality calculation algorithm, quantifies the criticality of the paths in the potential critical path set in the circuit under test;

[0055] For a new circuit under test, in order to give the path criticality ranking in the potential critical path set of the circuit under test after experiencing process deviation, we need to perform a series of operations on it.

[0056] First, similar to the method in S1, we need to obtain the potential critical path set of the circuit under test and the timing margin S of each path in the path set. test .

[0057] Then, similar to the methods in S2.1 and S2.2, we obtain the property matrix X of the new circuit under test test and the adjacency matrix A test . test and A test By inputting the key unit prediction model obtained by S3, we can obtain the criticality score of each unit of the circuit under test after experiencing process deviation.

[0058] Finally, the criticality of each path in the potential critical path set of the circuit under test is calculated. When calculating the criticality of the path, the physical parameters of each unit on the path need to be considered. The physical parameters of the unit selected by the present invention include: (1) position information L, the position information of the unit is collected from the unit-level timing report, which indicates the position of the unit in the path; (2) the number of transistors T, the number of transistors T in the unit is used to represent the characteristics of the unit type, and the unit types include multi-input DFF, BUFF, NOT, AND, NAND, OR, NOR, XOR and XNOR, etc.; (3) drive strength R, the size of the unit's transistor can represent the characteristics of the drive strength R. These three values ​​can be obtained directly from the standard unit library, and all these data must be normalized to L N , T N and R N , the subscript N indicates that the value has been normalized.

[0059] After obtaining the various parameters, the path criticality algorithm can be used to calculate the criticality of the jth potential critical path in the potential critical path set. The formula is:

[0060] In the above formula, N j is the unit set of the potential critical path j of the circuit to be tested, i represents the i-th unit on the potential critical path j, represents the possibility that the i-th unit is a key unit, is the normalized timing margin of potential critical path j, and the timing margin S of potential critical path j is test When obtaining the potential critical path set of the circuit under test, it has been obtained and normalized to obtain

[0061] The algorithm can be used to obtain the criticality score of each potential critical path in the potential critical path set of the circuit under test. After obtaining the criticality score of each potential critical path, the critical paths are sorted to obtain the critical path ranking of the circuit under test after experiencing process deviation.

[0062] In one embodiment of the present invention, an electronic device is provided, including a memory and a processor. The memory stores a computer program running on the processor, and the processor executes the steps of the critical path sorting method as described above when running the computer program.

[0063] In one embodiment of the present invention, a computer-readable storage medium is further provided, on which a computer program is stored. When the computer program is run, the steps of the critical path sorting method described above are executed.

[0064] The above specific implementation methods and examples are specific support for the technical ideas proposed in the present invention, and cannot be used to limit the scope of protection of the present invention. Any equivalent changes or equivalent modifications made on the basis of the technical solution of the present invention in accordance with the technical ideas proposed in the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A critical path sorting method based on graph neural network, characterized in that: The steps include: Step S1, obtaining a potential critical path set from a circuit netlist using a static timing analysis tool; Step S2, converting the circuit netlist file into a graph data structure, and initializing a training set according to the configuration file; Step S3, training the graph neural network using the initialized training set to obtain a key unit prediction model for predicting unit criticality scores; Step S4, input the read netlist of the circuit to be tested into the trained key unit prediction model, obtain the criticality score of each unit in the circuit to be tested, combine the unit parameters that characterize the relationship between the key unit and the potential critical path and the timing margin of the potential critical path to perform criticality calculation on all potential critical paths, sort the criticality calculation results of all potential critical paths, and obtain the critical path ranking after the circuit to be tested is affected by process deviation.

2. According to claim 1, a critical path sorting method based on graph neural network is characterized in that: The potential critical path set obtained from the circuit netlist by the static timing analysis tool in step S1 includes a path set passing through the timing endpoint and a path set passing through the unit.

3. According to claim 2, a critical path sorting method based on graph neural network is characterized in that: The method for obtaining the path set passing through the timing endpoint is: for at least one path passing through the current timing endpoint, n paths with the smallest timing relaxation are extracted as the path set passing through the current timing endpoint, and the path sets passing through each timing endpoint constitute the path set passing through the timing endpoint, where n is an integer greater than or equal to 1.

4. According to claim 3, a critical path sorting method based on graph neural network is characterized in that: The method for obtaining the path set passing through the unit is: for at least one path passing through the current unit, a path with the smallest timing relaxation is extracted as the path passing through the current unit, and the paths passing through each unit in the circuit form a path set passing through the unit.

5. According to claim 4, a critical path sorting method based on graph neural network is characterized in that: Step S2 converts the circuit netlist file into a graph data structure by defining an undirected graph with nodes having attributes. Represents a circuit, is the node set representing the unit, Indicates that the graph structure data has n nodes, v (1) ,v (2) ,...,v (n) is the 1st, 2nd, ..., nth node, ε is the edge set representing the connection relationship between units, |ε| = m means that the graph structure data has m edges, X is the node attribute set, The i-th row vector is the k-dimensional attribute information of the i-th node.

6. According to claim 5, a critical path sorting method based on graph neural network is characterized in that: The specific method of initializing the training set according to the configuration file in step S2 is: Step S2.1, obtaining transistor-level original attributes and cell-level original attributes related to process deviation effects from configuration files including but not limited to circuit netlist files, cell process library files, SPEF parasitic files, and timing reports, and constructing an attribute matrix according to the original attributes of each cell; Step S2.2, obtaining the connection relationship between units from the circuit netlist file, and constructing an adjacency matrix according to the connection relationship between units; Step S2.3, obtain the timing margin of each path in the potential critical path set under process deviation. The units on the top K% potential critical paths with the smallest timing margin under process deviation are critical units, and the remaining units are non-critical units. According to whether each unit in the circuit is a critical unit, a binary label is assigned to each node in the graph data structure. The attribute matrix, adjacency matrix and binary labels of each node constitute the initialized training set.

7. According to claim 6, a critical path sorting method based on graph neural network is characterized in that: The specific method of step S3 training the graph neural network through the initialized training set is: obtaining the node embedding matrix and the structural reconstruction error of each node according to the attribute matrix and the adjacency matrix of the graph structure data, obtaining the attribute reconstruction error of each node according to the attribute matrix and the node embedding matrix of the graph structure data, and calculating the unit criticality score according to the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node.

8. According to claim 7, a critical path sorting method based on graph neural network is characterized in that: The expression for calculating the criticality score of the unit based on the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node is: in, is the criticality score of the unit mapped to the vth node, is the normalized value of the abnormality score of the unit mapped to the vth node, s (v) is the average of the structure reconstruction error and attribute reconstruction error of the vth node.

9. According to claim 8, a critical path sorting method based on graph neural network is characterized in that: The cell parameters characterizing the relationship between the key cell and the potential critical path in step S4 include but are not limited to cell location information, the number of transistors in the cell, and the driving strength. The expression for performing critical calculation on all potential critical paths by combining the cell parameters characterizing the relationship between the key cell and the potential critical path and the timing margin of the potential critical path is: Among them, PC j is the criticality calculation result of the jth potential critical path of the circuit under test, N j is the unit set of the jth potential critical path of the circuit under test, is the location information of the i-th unit on the j-th potential critical path, is the number of transistors in the ith cell on the jth potential critical path, is the driving strength of the ith unit on the jth potential critical path, is the criticality score of the i-th unit on the j-th potential critical path, is the normalized value of the timing margin of the jth potential critical path.

10. A critical path sorting method based on graph neural network according to any one of claims 1 to 9, characterized in that: The key unit prediction model includes: A deep structure autoencoder is used to encode the attribute matrix and the adjacency matrix of the graph structure data, generate a node embedding matrix, reconstruct the adjacency matrix of the graph structure data according to the node embedding matrix, obtain a reconstructed adjacency matrix, and generate a structural reconstruction error of each node according to the adjacency matrix of the graph structure data and the reconstructed adjacency matrix; A nonlinear attribute autoencoder is used to encode the attribute matrix of the graph structure data, generate a deep attribute embedding matrix, reconstruct the attribute matrix of the graph structure data according to the deep attribute embedding matrix and the node embedding matrix, obtain a reconstructed attribute matrix, and generate an attribute reconstruction error of each node according to the attribute matrix of the graph structure data and the reconstructed attribute matrix; and The joint reconstruction error module is used to calculate the unit criticality score according to the joint reconstruction error composed of the structural reconstruction error and the attribute reconstruction error of each node.

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