Digital circuit aging simulation method based on critical path

Abstract

The invention discloses a digital circuit aging simulation method based on a critical path. The method comprises the following steps: extracting the critical path of a digital circuit by using a static time sequence analysis tool; screening potential critical paths by utilizing an aging worst-case analysis method; obtaining a key path and a netlist file excited by the key path; obtaining time delay, not including aging, of the key path through simulation before aging; changing the excitation of the key path and generating dynamic simulation excitation; performing key path dynamic aging simulation in combination with an existing aging model to obtain electrical parameter degradation amounts of all devices; converting the device degradation amount into an aged model netlist; and in combination with the aged model netlist, performing simulation after aging of the key path to obtain delay after aging of the path. According to the method, SPICE-level aging simulation is carried out on the critical path of the digital circuit to predict the actual performance degradation condition of the circuit, so that more accurate data support is provided for circuit optimization design.

Description

Technical Field

[0001] This invention relates to a digital circuit aging simulation method based on the critical path, belonging to the field of integrated circuit aging effect simulation technology. Background Technology

[0002] Given the limitations of computing resources, directly performing SPICE aging simulations on large-scale digital circuit netlists is impractical. To balance reliability, accuracy, and simulation efficiency, SPICE aging simulations must target a set of true critical paths. Analyzing critical paths effectively improves simulation efficiency and has gradually become a representative method for assessing the aging trends of large-scale circuits. However, existing methods may overlook the impact of dynamic changes in actual circuit operation on the aging process. Since devices, cells, modules, and paths in a chip operate dynamically according to functional requirements, and critical paths extracted by static timing analysis are usually based on preset operating conditions, the input vectors within the path change the switching states of devices under actual operating conditions, thus affecting the aging degree of the circuit. This means that ignoring the dynamic changes of input vectors may miss the worst-case path aging situation in the analysis, leading to inaccurate predictions of delays after critical path aging, thereby affecting the consideration of timing margins in digital circuit design. Regarding the above issues, current technologies have the following problems: excessive timing margins may lead to reduced circuit performance, increased power consumption, and increased costs, while insufficient timing margins may increase the risk of timing violations, reduce reliability, and shorten product lifespan. Therefore, there is an urgent need to study a more accurate method for predicting circuit aging in order to better guide circuit design. Summary of the Invention

[0003] The technical problem solved by this invention is to overcome the shortcomings of the prior art and provide a digital circuit aging simulation method based on the critical path. It combines static timing analysis tools to perform aging analysis of the critical path and considers the changes in the cell input vector, forcing more transistors to reach the aging state, thereby predicting circuit degradation quickly and more accurately.

[0004] The technical solution of this invention is: a digital circuit aging simulation method based on the critical path, comprising:

[0005] S1. Use static timing analysis tools to analyze digital circuits and obtain information about each path in the digital circuit;

[0006] S2. Based on the worst-case aging analysis method, and combined with path information, screen potential critical paths in digital circuits.

[0007] S3. Use static time series analysis tools to generate netlist files and corresponding stimulus files for the critical paths in the potential critical paths;

[0008] S4. Combining the netlist file and corresponding stimulus file of the critical path, use circuit simulation tools to perform pre-aging simulation of the critical path to obtain the delay of the critical path before aging.

[0009] S5. Analyze the netlist file of the critical path, obtain the cell logic truth table of the critical path, and generate multiple dynamic stimulus files.

[0010] S6. Combine the aging model to perform aging simulation on the critical path, and calculate the degradation of electrical parameters of all devices in the critical path based on the dynamic excitation file.

[0011] S7. Convert the degradation of the device's electrical parameters into an aged model netlist;

[0012] S8. Combine the aged model netlist to perform post-aging simulation of the critical path and obtain the path delay after aging.

[0013] S9. Determine whether the traversal simulation based on all dynamic stimulus files has been completed. If not, return to step S6 and continue iterating to obtain the delay results of the critical path after aging for different dynamic stimulus files. If yes, the simulation is complete, and the path aging delay under different simulation vectors is output.

[0014] Preferably, the information for each path in the digital circuit includes: delay information, the start point of the path, and the end point of the path.

[0015] Preferably, in step S2, potential critical paths are screened based on worst-case aging analysis. The specific method is as follows:

[0016] Sort the delays of N paths in a digital circuit from largest to smallest, and represent the delay values ​​of each path as D1, D2, ..., D... i ... D N-1 D N And D1≥D2≥D3≥…≥D N ;

[0017] When the maximum degradation rate of a digital circuit under a given process is p%, the delay satisfies formula D. i The path ×(1+p%)<D1 is a potential critical path.

[0018] Preferably, in step S3, the netlist conversion function of the static timing analysis tool is used to generate the netlist file of the critical path and its stimuli. The specific method is as follows:

[0019] Select a critical path and obtain its information, including the cell names of the path's start and end points. Use the netlist extraction and transformation functions of the static time series analysis tool to generate the SPICE netlist file and its corresponding stimulus file for the critical path.

[0020] Preferably, in step S4, a circuit simulation tool is used to perform a pre-aging simulation of the critical path to obtain the delay of the critical path before aging, wherein:

[0021] The circuit simulation tool is the SPICE simulator. The input is the netlist file of the critical path and its corresponding stimulus file, and the output is the delay of the critical path without aging.

[0022] Preferably, in step S5, the unit logic truth table of the critical path is analyzed, the excitation signals are changed, and a dynamic excitation file is generated, specifically as follows:

[0023] By analyzing the unit logic truth table, the possible working states of each unit can be accurately identified, different working states can be recorded, and multiple corresponding dynamic stimulus files can be generated.

[0024] Preferably, in step S6, the aging model is established based on the Verilog-A model, the working state provided in the dynamic excitation file is read, the working conditions of each device are detected, and the device performance degradation formula is used to discretize and integrate the device to obtain the amount of electrical parameter degradation of the device performance during the simulation time.

[0025] Preferably, in step S7, when converting the degradation of device electrical parameters into the aged model netlist:

[0026] Matrix transformation is used to convert the degraded values ​​of device electrical parameters into corresponding SPICE model parameter changes:

[0027]

[0028] Where, ΔV th ΔI represents the threshold voltage degradation in the electrical parameter degradation. dsat Δv represents the degradation of saturation leakage current within the degradation of electrical parameters. th0 Δμ0 represents the zero bias threshold voltage in the changes of SPICE model parameters, Δμ0 represents the carrier mobility in the changes of SPICE model parameters, and A represents the conversion coefficient matrix.

[0029] Using the degradation of SPICE model parameters, a new aged model netlist file is generated, which includes circuit parameters that take into account the aging effect.

[0030] Preferably, in step S8, when performing post-aging simulation of the critical path using the aged model netlist,

[0031] Call the aged model netlist file generated in step S7, and simultaneously input the netlist file of the critical path and the corresponding stimulus file generated in step S3.

[0032] Compared with the prior art, the present invention has the following advantages:

[0033] (1) This invention can support SPICE-level simulation of critical paths in digital circuits and can improve the accuracy of simulation results based on accurate aging models; in addition, the efficiency of digital circuit aging assessment is improved by filtering the number of critical paths.

[0034] (2) This invention emphasizes that the dynamic changes of internal signals should be considered in the aging analysis of critical paths, so that each device on the path can operate more uniformly, thus better reflecting the actual aging conditions of the circuit. Compared with aging simulation under traditional static timing analysis, the accuracy of simulation results is improved;

[0035] (3) This invention proposes a SPICE aging simulation process based on the critical path, which includes two levels: device simulation and circuit simulation. It effectively transmits the degradation of device parameters to the degradation of circuit performance, providing a new method for aging prediction of large-scale digital integrated circuits.

[0036] (4) The present invention uses dynamic simulation vectors to perform aging simulation on the critical path of digital circuits, which can guide circuit design to reserve a more appropriate aging margin and help improve the reliability of the circuit during operation. Attached Figure Description

[0037] Figure 1 This is a flowchart of the digital circuit aging simulation method based on the critical path in this invention;

[0038] Figure 2 This is a schematic diagram of the path delay sorting method that does not consider aging in this invention.

[0039] Figure 3 This is a schematic diagram of the path delay screening method considering HCI aging in this invention;

[0040] Figure 4 This is a schematic diagram of data transmission within the selected critical path unit in this invention;

[0041] Figure 5 This is a simulation result of the aging of digital circuits based on the critical path in this invention. Detailed Implementation

[0042] This invention employs static timing analysis tools to extract critical paths in digital circuits; utilizes worst-case aging analysis to screen potential critical paths; obtains netlist files of the critical paths and their stimuli; acquires the critical path delays before aging through pre-aging simulation; modifies the critical path stimuli and generates dynamic simulation stimuli; combines existing aging models to perform dynamic aging simulations of the critical path to obtain the electrical parameter degradation of all devices; converts the device degradation values ​​into a post-aging model netlist; and combines the post-aging model netlist to perform post-aging simulations of the critical path to obtain the path delays after aging. This invention supports SPICE-level aging simulation of critical paths in digital circuits to predict the actual performance degradation of the circuit, thereby providing more accurate data support for circuit optimization design. This invention combines aging simulation tools and static timing analysis tools to avoid overly optimistic aging analysis of critical paths during circuit design.

[0043] like Figure 1 The diagram shows a flowchart of the digital circuit aging simulation method based on the critical path according to the present invention. The digital circuit aging simulation method based on the critical path includes the following steps:

[0044] Step 1: Extract the critical path of the digital circuit using static timing analysis tools. The main implementation method is as follows:

[0045] Use static timing analysis tools to sort the timing paths in the circuit from smallest to largest timing margin;

[0046] Obtain critical path information that does not meet timing requirements, including the path start and end points.

[0047] Step 2: Based on worst-case aging analysis, screen potential critical paths. The main implementation method is as follows:

[0048] First, define potential critical paths: some ordinary paths, after a period of aging stress, will become critical paths due to time-degradation to a certain extent.

[0049] By comparing the path delay of each path under the most severe aging condition with the timing margin given in the design, paths that would violate timing requirements after degradation reaches their maximum value are identified and further aging analysis is performed. The criteria for selecting potential critical paths are as follows: Figure 2 As shown, assuming a circuit has N paths, without considering aging effects, the timing information of each path can be obtained through the traditional Static Timing Analysis (STA) process. Then, the delays of these N paths can be sorted from largest to smallest, and these paths can be named P1, P2, P3, ..., P... N-1 P N Where P1 represents the first path with the longest delay, P NThis represents the Nth path with the minimum delay. The delay values ​​of these paths are denoted as D1, D2, D3, ..., D... N-1 D N Where D1 is the delay of P1, D N For P N The delay is such that D1≥D2≥D3≥…≥D N Next, we determine a split point and find the i-th path, whose delay satisfies the formula:

[0050] D i ×(1+p%)<D1

[0051] Where p% represents the maximum degradation rate the circuit may suffer under a given process. The above formula means that for a given P... i+1 To P N All paths, even under worst stress conditions where their delays degrade by p%, will not become the critical paths with the longest delays. However, for the path from P1 to P... i-1 The paths that, under worst-case HCI stress, are likely to become the critical paths with the longest delays. We define the potential critical path set (PCP) as follows. set ) and non-potential critical path set (NPCP) set ) is defined as:

[0052] PCP set ={P1,P2,…P i-2 ,P i-1}

[0053] NPCP set ={P i ,P i+1 ,…P N-1 ,P N}

[0054] This invention uses the hot carrier injection (HCI) effect as an example. Studies show that after 5-10 years of stress, the maximum path delay degradation caused by HCI does not exceed 20%. Assuming p% = 20%, if PCP... set If any path degrades by 20%, then that path is likely the critical path with the longest post-delay due to HCI stress. And NPCP set Even if any path degenerates to the worst 20%, it still cannot be a critical path. In the following steps, we only need to analyze the performance of these PCPs.

[0055] In addition, circuit designers typically leave a certain timing margin to ensure the performance stability of digital circuits after long-term operation. We define this margin as q% of the critical path delay (D1) without considering HCI.

[0056] like Figure 3 As shown, by comparing the value of each PCP after 20% degradation with the value of D1 after q% degradation (i.e., comparing the magnitude of PCP(1+20%) and D1(1+q%)), some paths whose delay values ​​after 20% PCP degradation exceed the predetermined timing margin can be further screened out. Next, aging analysis can be performed on PCPs that do not meet the timing margin under these worst-case conditions.

[0057] Step 3: After obtaining some critical paths based on Step 2, you can arbitrarily select one of the critical paths and use the netlist conversion function of the static timing analysis tool to generate the netlist file of the critical path and its stimuli. The specific method is as follows:

[0058] A critical path is selected and its information, including the cell names of the path's start and end points, is obtained. The SPICE netlist and its corresponding stimulus file for this critical path are generated using the netlist extraction and conversion functions of a static timing analysis tool. This invention selects the S5378 circuit from the ISCAS'89 reference circuit for static timing analysis and critical path aging analysis. By analyzing the information in the static timing analysis report from step 1, the specific start and end ports of the critical path can be determined, such as... Figure 4 The displayed paths "DFF_107 / CK" and "DFF_67 / D" contain eight combinational logic units. Subsequently, using commands such as "write spice deck," the selected critical path can be converted into the netlist format required for standard SPICE simulation and named (e.g., dut.spi). Simultaneously, the corresponding stimulus file (e.g., dut_stim.spi, which is the default stimulus file format generated by static timing analysis tools) will be output for subsequent SPICE simulations.

[0059] Step 4: Use the SPICE simulator to perform pre-aging simulation of the critical path to obtain the path delay excluding aging. The specific method is as follows:

[0060] Pre-aging simulation is performed using circuit simulation tools. The input is the SPICE netlist (dut.spi) of the critical path and its corresponding stimulus file (dut_stim.spi). The output is the delay of the critical path without aging.

[0061] Step 5: Based on the netlist transformed in Step 3, the cell logic truth table for this critical path can be obtained by analyzing the function of the netlist, thus changing the excitation signals and generating a dynamic excitation file. The specific method is as follows:

[0062] By analyzing the logic of the units contained in the critical path, we can accurately identify the possible operating states of each unit, thereby ensuring that data can be successfully transmitted from the input node to the output node; different operating states are recorded to generate multiple different simulation stimulus files.

[0063] Input signals within the critical path, such as Figure 4 As shown, by analyzing the logic of the eight combinational logic units contained in the critical path, the possible operating states of each unit are accurately identified, thereby ensuring that data can be successfully transmitted from the input node to the output node. This invention selects ten different stimuli to generate a dynamic stimulus file, named "stim_01-10.spi".

[0064] Step 6: Perform aging simulation on the critical path using the existing aging model to calculate the degradation of electrical parameters for all devices in the critical path. The specific method is as follows:

[0065] The aging model is based on the Verilog-A model. It automatically detects the operating conditions of each device and discretizes and integrates them according to the device performance degradation formula to obtain the device performance degradation value during the simulation time.

[0066] When using an aging model for circuit simulation, the inputs are the critical path netlist `dut.spi`, simulation stimuli (`dut_stim.spi` or `stim_01-10.spi`), and the aging model. The output is the degradation of the device's electrical parameters (e.g., the threshold voltage degradation ΔV). th and saturation leakage current degradation ΔI dsat ).

[0067] Step 7: Convert the degradation of device electrical parameters into the aged model netlist. The specific method is as follows:

[0068] The matrix transformation algorithm converts the device degradation values ​​into corresponding SPICE model parameter changes, as shown in the following equation. The matrix on the left side of the equation represents the device's electrical parameter degradation ΔV. th and ΔI dsat The matrix on the right represents the corresponding SPICE model parameter degradation (zero bias threshold voltage ΔV). th0 And the carrier mobility Δμ0), the value of matrix A can be obtained through simulation. Knowing matrix A, the conversion from device parameters to SPICE model parameters can be achieved;

[0069]

[0070] After calculating the degradation amount of the SPICE model parameters, the aged netlist file "Aged.scs" is generated by modifying the corresponding SPICE parameters. This netlist file contains circuit parameters that take into account the aging effect.

[0071] Step 8: Perform post-aging simulation of the critical path using the aged model netlist to obtain the path delay after aging. The specific method is as follows:

[0072] The inputs for the aging simulation are the critical path netlist "dut.spi" and the initial stimulus file "dut_stim.spi", and it also needs to call the aged netlist file "Aged.scs". The main function of the "Aged.scs" file is to incorporate the device degradation into the circuit level. The SPICE simulator can recognize the V values ​​in this file. th0 The μ0 value is used to calculate the electrical parameter degradation of each device in the critical path.

[0073] Step 9: Repeat steps (6) to (8) to obtain the critical path aging delay results under the 10 different stimuli selected in step 5. After aging simulation, different device parameter degradation amounts are obtained, thereby generating different aging model files. The aging delay of the critical path under different simulation vectors is obtained through aging simulation. The specific method is as follows:

[0074] First, aging simulation is performed using different excitation signals "stim_01-10.spi" and the netlist of the critical path "dut.spi" as input files. Through this process, 10 different device aging conditions can be obtained, i.e., the device saturation leakage current I... dsat and threshold voltage V th Degradation value;

[0075] Next, the device degradation values ​​are converted into corresponding SPICE model parameters to generate different files "Aged.scs". As mentioned earlier, these new netlist files contain circuit parameters that take into account aging effects.

[0076] Finally, an aging simulation is performed, using the critical path netlist, the default stimulus signal "dut_stim.spi", and a new aging file (Aged.scs) as input to obtain the path delay after aging. It is important to note that the default stimulus signal (dut_stim.spi) must be used during this process to ensure that the critical path remains unchanged. Changing the stimulus signal during the aging simulation is equivalent to changing the critical path itself, which will lead to inaccurate predictions.

[0077] Simulation results are as follows Figure 5As shown, the results indicate that under the default static simulation vector, the path delay after critical path aging is 0.72 ns. However, by changing the internal input signal, the delay obtained from the aging simulation shows a significant change, with both decreases and increases in delay. This phenomenon is related to the differences in transistor aging, which stem from changes in the switching states of the transistors. Dynamic simulation results show that the maximum delay in the aged path is 0.75 ns, an increase of 0.03 ns compared to the static vector. This phenomenon indicates that the excitation represented by the static vector is not the excitation most severely affected by aging on the critical path.

[0078] The contents not described in detail in this specification are existing technologies known to those skilled in the art.

Claims

1. A digital circuit aging simulation method based on the critical path, characterized in that... include: S1. Use static timing analysis tools to analyze digital circuits and obtain information about each path in the digital circuit; S2. Based on the worst-case aging analysis method, and combined with path information, screen potential critical paths in digital circuits. S3. Use static time series analysis tools to generate netlist files and corresponding stimulus files for the critical paths in the potential critical paths; S4. Combining the netlist file and corresponding stimulus file of the critical path, use circuit simulation tools to perform pre-aging simulation of the critical path to obtain the delay of the critical path before aging. S5. Analyze the netlist file of the critical path, obtain the cell logic truth table of the critical path, and generate multiple dynamic stimulus files. S6. Combine the aging model to perform aging simulation on the critical path, and calculate the degradation of electrical parameters of all devices in the critical path based on the dynamic excitation file. S7. Convert the degradation of the device's electrical parameters into an aged model netlist; S8. Combine the aged model netlist to perform post-aging simulation of the critical path and obtain the path delay after aging. S9. Determine whether the traversal simulation based on all dynamic stimulus files has been completed. If not, return to step S6 and continue iterating to obtain the delay results of the critical path after aging for different dynamic stimulus files. If yes, the simulation is complete, and the path aging delay under different simulation vectors is output.

2. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: Information for each path in a digital circuit includes: delay information, the start and end points of the path.

3. The digital circuit aging simulation method based on the critical path according to claim 2, characterized in that: In step S2, potential critical paths are screened based on worst-case aging analysis. The specific method is as follows: Sort the delays of N paths in a digital circuit from largest to smallest, and represent the delay values ​​of each path as D1, D2, ..., D... i ... D N-1 D N And D1≥D2≥D3≥…≥D N ; When the maximum degradation rate of a digital circuit under a given process is p%, the delay satisfies formula D. i The path ×(1+p%)<D1 is a potential critical path.

4. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: In step S3, the netlist conversion function of the static timing analysis tool is used to generate the netlist file of the critical path and its stimuli. The specific method is as follows: Select a critical path and obtain its information, including the cell names of the path's start and end points. Use the netlist extraction and transformation functions of the static time series analysis tool to generate the SPICE netlist file and its corresponding stimulus file for the critical path.

5. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: In step S4, a circuit simulation tool is used to perform a pre-aging simulation of the critical path to obtain the delay of the critical path before aging, wherein: The circuit simulation tool is the SPICE simulator. The input is the netlist file of the critical path and its corresponding stimulus file, and the output is the delay of the critical path without aging.

6. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: In step S5, the unit logic truth table of the critical path is analyzed, the excitation signals are changed, and a dynamic excitation file is generated, specifically as follows: By analyzing the unit logic truth table, the possible working states of each unit can be accurately identified, different working states can be recorded, and multiple corresponding dynamic stimulus files can be generated.

7. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: In step S6, the aging model is established based on the Verilog-A model. The working state provided in the dynamic excitation file is read, the working conditions of each device are detected, and the device performance degradation formula is used to discretize and integrate the device to obtain the amount of electrical parameter degradation of the device performance during the simulation time.

8. The digital circuit aging simulation method based on the critical path according to claim 1, characterized in that: In step S7, when converting the device electrical parameter degradation into the aged model netlist: Matrix transformation is used to convert the degraded values ​​of device electrical parameters into corresponding SPICE model parameter changes: Where, ΔV th ΔI represents the threshold voltage degradation in the electrical parameter degradation. dsat Δv represents the degradation of saturation leakage current within the degradation of electrical parameters. th0 Δμ0 represents the zero bias threshold voltage in the changes of SPICE model parameters, Δμ0 represents the carrier mobility in the changes of SPICE model parameters, and A represents the conversion coefficient matrix. Using the degradation of SPICE model parameters, a new aged model netlist file is generated, which includes circuit parameters that take into account the aging effect.

9. The digital circuit aging simulation method based on the critical path according to claim 8, characterized in that: In step S8, when performing post-aging simulation of the critical path using the aged model netlist, Call the aged model netlist file generated in step S7, and simultaneously input the netlist file of the critical path and the corresponding stimulus file generated in step S3.

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