Light-emitting chip, display device and manufacturing method

Abstract

A light-emitting chip, a display device and a manufacturing method. The light-emitting chip comprises a first light-emitting unit (2), a second light-emitting unit (3) and a third light-emitting unit (4); the first light-emitting unit (2) is configured to emit first color light; the second light-emitting unit (3) comprises a second light-emitting layer (6) and a first transflective layer (8), and the first transflective layer (8) is configured to filter out the first color light, so that the second light-emitting unit (3) emits second color light; and the third light-emitting unit (4) comprises a third light-emitting layer (7) and a second transflective layer (9), and the second transflective layer (9) is configured to filter out the first color light and / or the second color light, so that the third light-emitting unit (4) emits third color light.

Description

Light-emitting chip, display device, and manufacturing method

[0001] This application claims priority to the Chinese patent application filed on October 24, 2023, with application number 202311388822.7 and invention name “Light-emitting chip, display device and manufacturing method”, the content of which should be understood as incorporated into this application by reference. Technical Field

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a light-emitting chip, a display device, and a manufacturing method. Background Art

[0003] Micro-LEDs (micro-light emitting diodes) are densely integrated arrays of light-emitting diodes (LEDs). Each pixel in the array is self-luminous, with spacing of 10 microns. Micro-LEDs offer high brightness, high luminous efficiency, and low power consumption. However, current displays using Micro-LEDs lack ideal full-color performance and are also expensive to produce.

[0004] Summary of the Invention

[0005] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0006] The technical problem to be solved by the present disclosure is to provide a light-emitting chip, display device, and manufacturing method. These chips adopt a combination of light-emitting layers of multiple different colors, rather than a single light-emitting diode (LED). Furthermore, these chips have a transflective layer that filters the required color light, achieving a full-color solution with better display effects. Furthermore, these chips do not require quantum dots (QDs) to achieve full color, significantly reducing production costs.

[0007] At least one embodiment of the present disclosure provides a light-emitting chip, comprising a substrate and a first light-emitting unit, a second light-emitting unit, and a third light-emitting unit located on the same side of the substrate;

[0008] The first light-emitting unit includes a first light-emitting layer provided on the substrate, and the first light-emitting unit is configured to emit a first color light;

[0009] The second light-emitting unit includes a second light-emitting layer and a first transflective layer, the second light-emitting layer is disposed on the substrate, the first transflective layer is disposed on a side of the second light-emitting layer away from the substrate, and the first transflective layer is configured to filter out the first color light so that the second light-emitting unit emits the second color light;

[0010] The third light-emitting unit includes a third light-emitting layer and a second reflective layer. The third light-emitting layer is arranged on the substrate. The second reflective layer is arranged on a side of the third light-emitting layer away from the substrate. The second reflective layer is configured to filter out the first color light and / or the second color light, so that the third light-emitting unit emits the third color light.

[0011] In some exemplary embodiments, the first light emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially disposed on the substrate;

[0012] The second light-emitting layer includes a first electrode layer, a first semiconductor layer, a second electrode layer, and a second semiconductor layer sequentially arranged on the substrate, and the first transflective layer is located on a side of the second semiconductor layer away from the substrate;

[0013] The third light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially arranged on the substrate; the third light-emitting layer is provided with the second semiconductor and third semiconductor layers stacked on a side of the second electrode layer away from the first semiconductor layer, or the third light-emitting layer is provided with a third semiconductor layer on a side of the second electrode layer away from the first semiconductor layer, and the second reflective layer is located on a side of the third semiconductor layer away from the second electrode layer.

[0014] In some exemplary embodiments, the second light-emitting layer further includes a third electrode layer covering a surface of the second semiconductor layer away from the second electrode layer. In the second light-emitting layer, the first transflective layer covers a surface of the third electrode layer away from the second semiconductor layer, and the third electrode layer is electrically connected to the first electrode layer.

[0015] The third light-emitting layer also includes a third electrode layer and a fourth electrode layer. In the third light-emitting layer, the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer are arranged in sequence in a direction away from the substrate, the first electrode layer and the third electrode layer are electrically connected, the second electrode layer and the fourth electrode layer are electrically connected, and the second reflective layer covers the surface of the fourth electrode layer away from the third semiconductor layer.

[0016] In some exemplary embodiments, further comprising a first metal trace, a second metal trace, and a third metal trace;

[0017] The first metal trace is located lateral to the second light-emitting layer, one end of the first metal trace is connected to the first electrode layer, and the other end of the first metal trace is connected to the third electrode layer. The first semiconductor layer, the second electrode layer, and the second semiconductor layer are provided with a first insulating layer on a side facing the first metal trace;

[0018] The second metal wiring and the third metal wiring are respectively located on two opposite sides of the third light-emitting layer;

[0019] In the third light-emitting layer, one end of the second metal trace is connected to the first electrode layer, the other end of the second metal trace is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer and the second semiconductor layer are provided with a second insulating layer on the side facing the second metal trace; one end of the third metal trace is connected to the second electrode layer, the other end of the third metal trace is connected to the fourth electrode layer, and the second semiconductor layer, the third electrode layer and the third semiconductor layer are provided with a third insulating layer on the side facing the third metal trace.

[0020] In some exemplary embodiments, in the second light-emitting layer, orthographic projections of the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor layer, and the third electrode layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate;

[0021] In the third light-emitting layer, the orthographic projections of the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer on the substrate are all located within the orthographic projection of the second electrode layer on the substrate, and the orthographic projections of the second electrode layer and the first semiconductor layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate.

[0022] In some exemplary embodiments, in the third light-emitting unit, the second semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer, and the third semiconductor layer is arranged to cover a surface of the second semiconductor layer away from the second electrode layer;

[0023] The second reflective layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective layer is configured as a red-transmitting, blue-blocking, and green-blocking film.

[0024] In some exemplary embodiments, in the third light emitting unit, the third semiconductor layer is configured to cover a surface of the second electrode layer away from the first semiconductor layer;

[0025] The second reflective transmissive layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective transmissive layer is configured as a red-transmitting and blue-blocking film.

[0026] In some exemplary embodiments, a fourth metal trace and a fifth metal trace are further included;

[0027] The second light-emitting layer is arranged on the substrate, spaced apart from the first light-emitting layer and the third light-emitting layer, respectively; the fourth metal trace is located between the first light-emitting layer and the third light-emitting layer; and the second electrode layer of the second light-emitting layer is arranged to be electrically connected to the second electrode layer of the first light-emitting layer through the fourth metal trace;

[0028] The fifth metal wiring is located between the second light-emitting layer and the third light-emitting layer, and the second electrode layer of the second light-emitting layer is configured to be electrically connected to the second electrode layer of the third light-emitting layer through the fifth metal wiring.

[0029] In some exemplary embodiments, the first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer sequentially arranged in a direction away from the substrate;

[0030] The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer sequentially arranged in a direction away from the substrate;

[0031] The third semiconductor layer includes a third P-type contact layer, a third quantum well, and a third N-type contact layer sequentially arranged in a direction away from the substrate.

[0032] In some exemplary embodiments, the first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer sequentially arranged in a direction away from the substrate;

[0033] The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer sequentially arranged in a direction away from the substrate;

[0034] The third semiconductor layer includes a third N-type contact layer, a third quantum well, and a third P-type contact layer sequentially arranged in a direction away from the substrate.

[0035] In some exemplary embodiments, the first color light is set to blue light, the second color light is set to green light, and the third color light is set to red light;

[0036] The first transflective layer is configured as a conductive green light-transmitting film, and the second transflective layer is configured as a conductive red light-transmitting film.

[0037] In some exemplary embodiments, a reflective film is further included, and the reflective film is configured to wrap at least the sides of the first light emitting unit, the second light emitting unit, and the third light emitting unit.

[0038] In some exemplary embodiments, a packaging structure is further included, wherein the packaging structure is disposed on the substrate and covers the first light emitting unit, the second light emitting unit, and the third light emitting unit.

[0039] At least one embodiment of the present disclosure provides a display device including the above-mentioned light-emitting chip.

[0040] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, comprising:

[0041] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, a third conductive layer, a third epitaxial layer and a fourth conductive layer in sequence on the substrate to obtain a composite film layer;

[0042] Etching the composite film layer to form a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, and a third electrode layer; and the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, a third electrode layer, a third semiconductor layer, and a fourth electrode layer;

[0043] Depositing an insulating film and etching to obtain an insulating layer pattern, the insulating layer pattern comprising a first insulating layer, a second insulating layer, and a third insulating layer; the first insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer, and the second electrode layer facing the second light-emitting unit; the second insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer, and the second electrode layer facing the second light-emitting layer; and the third insulating layer covers the end faces of the second semiconductor layer, the third semiconductor layer, and the third electrode layer facing away from the second light-emitting layer;

[0044] Depositing a metal layer and etching to obtain a metal trace pattern, the metal trace pattern comprising a first metal trace, a second metal trace, and a third metal trace, the first metal trace corresponding to the first insulating layer and connecting the third electrode layer and the first electrode layer of the second light-emitting layer; the second metal trace corresponding to the second insulating layer and connecting the third electrode layer and the first electrode layer of the third light-emitting layer; and the third metal trace corresponding to the third insulating layer and connecting the fourth electrode layer and the second electrode layer of the third light-emitting layer;

[0045] Depositing a first transflective film on the metal trace pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0046] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit;

[0047] Performing packaging, rotating and filling the packaging structure on the substrate so that the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are all embedded in the packaging structure;

[0048] The substrate is peeled off and transferred to the base plate.

[0049] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, comprising:

[0050] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, and a third epitaxial layer in sequence on the substrate to obtain a composite film layer;

[0051] Etching the composite film layer to form a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer, and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, and a second semiconductor layer; and the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, and a third semiconductor layer;

[0052] Depositing an insulating film and etching to obtain an insulating layer pattern, the insulating layer pattern comprising a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer; the fourth insulating layer covers the first electrode layer and the first semiconductor layer of the first light-emitting layer and the end surface facing the second light-emitting layer; the fifth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer and the end surface facing the first light-emitting layer; the sixth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer and the end surface facing the third light-emitting layer; and the seventh insulating layer covers the first electrode layer and the first semiconductor layer of the third light-emitting layer and the end surface facing the second light-emitting layer;

[0053] Depositing a metal layer and etching to obtain a metal trace pattern, the metal trace pattern comprising a fourth metal trace and a fifth metal trace, the fourth metal trace connecting the first light-emitting layer and the second electrode layer of the second light-emitting layer; the fifth metal trace connecting the third light-emitting layer and the second electrode layer of the second light-emitting layer;

[0054] Depositing a first transflective film on the metal trace pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0055] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit;

[0056] Performing packaging, rotating and filling the packaging structure on the substrate so that the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are all embedded in the packaging structure;

[0057] The substrate is peeled off and transferred to the base plate.

[0058] At least one embodiment of the present disclosure provides a manufacturing method, which is applied to the above-mentioned light-emitting chip, comprising:

[0059] Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, and a second epitaxial layer in sequence on a substrate to obtain a composite film layer;

[0060] Etching the composite film layer to form a first light-emitting layer pattern from the composite film layer; the first light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer, and a third light-emitting blank layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, and a second semiconductor layer; and the third light-emitting blank layer includes a stacked first electrode layer, a first semiconductor layer, and a second electrode layer;

[0061] Depositing a third epitaxial layer on the first light-emitting layer pattern and etching to obtain a second light-emitting layer pattern; the second light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, and the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a third semiconductor layer;

[0062] Depositing an insulating film and etching to obtain an insulating layer pattern, the insulating layer pattern comprising a fourth insulating layer, a fifth insulating layer, a sixth insulating layer, and a seventh insulating layer; the fourth insulating layer covers the first electrode layer and the first semiconductor layer of the first light-emitting layer and the end surface facing the second light-emitting layer; the fifth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer and the end surface facing the first light-emitting layer; the sixth insulating layer covers the first electrode layer and the first semiconductor layer of the second light-emitting layer and the end surface facing the third light-emitting layer; and the seventh insulating layer covers the first electrode layer and the first semiconductor layer of the third light-emitting layer and the end surface facing the second light-emitting layer;

[0063] Depositing a metal layer and etching to obtain a metal trace pattern, the metal trace pattern comprising a fourth metal trace and a fifth metal trace, the fourth metal trace connecting the first light-emitting layer and the second electrode layer of the second light-emitting layer; the fifth metal trace connecting the third light-emitting layer and the second electrode layer of the second light-emitting layer;

[0064] Depositing a first transflective film on the metal trace pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer;

[0065] Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit;

[0066] Performing packaging, rotating and filling the packaging structure on the substrate so that the first light-emitting unit, the second light-emitting unit, and the third light-emitting unit are all embedded in the packaging structure;

[0067] The substrate is peeled off and transferred to the base plate.

[0068] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0069] Summary of the Figures

[0070] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0071] FIG1 is a schematic diagram of a light-emitting chip according to an exemplary embodiment of the present disclosure;

[0072] FIG2 is a schematic diagram of the first light-emitting unit in FIG1 ;

[0073] FIG3 is a schematic diagram of the second light-emitting unit in FIG1 ;

[0074] FIG4 is a schematic diagram of the third light-emitting unit in FIG1 ;

[0075] FIG5 is a schematic diagram of another light-emitting chip according to this exemplary embodiment;

[0076] FIG6 is a schematic diagram of another light-emitting chip according to this exemplary embodiment;

[0077] FIG7 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure;

[0078] FIG8 is a schematic diagram of the first light-emitting unit in FIG7 ;

[0079] FIG9 is a schematic diagram of the second light-emitting unit in FIG7 ;

[0080] FIG10 is a schematic diagram of the third light-emitting unit in FIG7 ;

[0081] FIG11 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure;

[0082] FIG12 is a schematic diagram of the first light-emitting unit in FIG11 ;

[0083] FIG13 is a schematic diagram of the second light-emitting unit in FIG11 ;

[0084] FIG14 is a schematic diagram of the third light-emitting unit in FIG11 ;

[0085] FIG15 a is a schematic diagram of a composite film layer according to an exemplary embodiment of the present disclosure;

[0086] FIG15 b is a schematic diagram of a light-emitting layer pattern according to an exemplary embodiment of the present disclosure;

[0087] FIG16 a is a schematic diagram of another composite film layer according to an exemplary embodiment of the present disclosure;

[0088] FIG16 b is a schematic diagram of another light-emitting layer pattern according to an exemplary embodiment of the present disclosure;

[0089] FIG17a is a schematic diagram of another composite film layer according to an exemplary embodiment of the present disclosure;

[0090] FIG17 b is a schematic diagram of a first blank according to an exemplary embodiment of the present disclosure;

[0091] FIG17c is a schematic diagram of deposition of a third epitaxial layer according to an exemplary embodiment of the present disclosure;

[0092] FIG17 d is a schematic diagram of another light-emitting layer pattern according to an exemplary embodiment of the present disclosure.

[0093] DESCRIPTION OF NUMERALS: 1-substrate; 2-first light-emitting unit; 3-second light-emitting unit; 4-third light-emitting unit; 5-first light-emitting layer; 6-second light-emitting layer; 7-third light-emitting layer; 8-first transflective layer; 9-second transflective layer; 10-first semiconductor layer; 11-second semiconductor layer; 12-third semiconductor layer; 13-first electrode layer; 14-second electrode layer; 15-third electrode layer; 16-fourth electrode layer; 17-first metal trace; 18-second metal trace; 19-third metal trace; 20-first N-type contact layer; 21-first quantum well; 22-first P-type contact layer; 23-second N-type contact layer; 24-second quantum well; 25-second P-type contact layer; 26-first insulating layer; 27-third N-type contact layer; 28-third quantum well; 29-third P-type contact layer; 30-second insulating layer; 31-third insulating layer; 32-fourth metal routing; 33-fifth metal routing; 34-first covering segment; 35-second covering segment; 36-third covering segment; 37-fourth covering segment; 38-fifth covering segment; 39-sixth covering segment; 40-fourth insulating layer; 41-fifth insulating layer; 42-sixth insulating layer; 43-seventh insulating layer; 44-reflective film; 45-packaging structure; 47-first conductive film; 48-first epitaxial layer; 49-second conductive film; 50-second epitaxial layer; 51-third conductive film; 52-third epitaxial layer; 53-fourth conductive film; 54-composite film layer; 55-light-emitting layer pattern; 56-first light-emitting layer pattern; 57-second light-emitting layer pattern.

[0094] Details

[0095] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0096] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0097] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0098] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0099] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0100] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0101] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0102] The term "about" in the embodiments of the present disclosure does not strictly define the limits and allows for numerical values ​​within the range of process and measurement errors.

[0103] In addition, when describing representative embodiments, the specification may have presented the method and / or process as a specific sequence of steps. However, to the extent that the method or process does not rely on the specific order of the steps described herein, the method or process should not be limited to the steps in the specific order described. As will be understood by those skilled in the art, other orders of steps are also possible. Therefore, the specific order of the steps set forth in the specification should not be interpreted as a limitation to the claims. In addition, the claims for the method and / or process should not be limited to performing their steps in the order written, and those skilled in the art can readily understand that these orders can be changed and still remain within the spirit and scope of the embodiments of the present application.

[0104] Currently, Micro-LEDs are vertically focused light-emitting diodes (LEDs). Due to the massive amount of mass transfer and the direct wafer-to-panel assembly process required during display device production, the light-emitting chips can only achieve full-color using single-color LEDs. Applicants have found that due to the single-light structure, full-color display performance using this structure is unsatisfactory. Furthermore, current Micro-LED products typically use a combination of blue LEDs and quantum dots (QDs) to achieve full color, but the production cost of QDs is also relatively high.

[0105] FIG1 is a schematic diagram of a light-emitting chip according to an exemplary embodiment of the present disclosure. The present disclosure provides a light-emitting chip. As shown in FIG1 , the light-emitting chip may include a substrate 1 and a first light-emitting unit 2, a second light-emitting unit 3, and a third light-emitting unit 4 located on the same side of the substrate 1. The first light-emitting unit 2 may include a first light-emitting layer 5 disposed on the substrate 1 and configured to emit light of a first color. The second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8. The second light-emitting layer 6 is disposed on the substrate 1, and the first transflective layer 8 is disposed on a side of the second light-emitting layer 6 away from the substrate 1. The first transflective layer 8 may be configured to filter out the first color light, allowing the second light-emitting unit 3 to emit light of a second color. The third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9. The third light-emitting layer 7 may be disposed on the substrate 1, and the second transflective layer 9 may be disposed on a side of the third light-emitting layer 7 away from the substrate 1. The second transflective layer 9 may be configured to filter out the first color light and / or the second color light, allowing the third light-emitting unit 4 to emit light of a third color. Therefore, the light-emitting chip utilizes the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 to emit light of different colors respectively, thereby realizing full-color display of non-monochromatic light, achieving better display effect and significantly reducing manufacturing costs.

[0106] In some exemplary embodiments, as shown in FIG1 , the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 are all located on one side of the substrate 1 in a direction perpendicular to the substrate 1, and are spaced apart from each other. The first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 are all configured to emit light away from the substrate 1. The first light-emitting unit 2 can emit light of a first color, the second light-emitting unit 3 can emit light of a second color, and the third light-emitting unit 4 can emit light of a third color. The first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 are arranged sequentially along a first direction parallel to the substrate 1, and the spacing between the first light-emitting unit 2 and the second light-emitting unit 3, as well as the spacing between the second light-emitting unit 3 and the third light-emitting unit 4, matches the pixel pitch.

[0107] FIG2 is a schematic diagram of the first light-emitting unit in FIG1 . In some exemplary embodiments, as shown in FIG1 and FIG2 , the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 all have a stacked structure. The first light-emitting unit 2 may include a single-layer first light-emitting layer 5. A single-layer structure refers to a structure having only one semiconductor layer. The first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10, and a second electrode layer 14. The first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 are stacked in sequence away from the substrate 1. The projections of the first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 may be an N-type electrode. The first electrode layer 1 may serve as an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can be a blue LED epitaxial layer, resulting in the first color light emitted by the first light-emitting unit 2 being blue, but this is not limited to this. For example, the first semiconductor layer 10 can be a red LED epitaxial structure or a green LED epitaxial structure, and the corresponding first color light will also vary accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged sequentially in a direction away from the substrate 1. The first quantum well 21 can be formed of indium gallium nitride (InGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth. The number of quantum well layers 27 ranges from 1 to 10. The material of the first P-type contact layer 22 can be GaN gallium nitride doped with magnesium (Mg), aluminum nitride (AlN) doped with magnesium (Mg), or aluminum gallium nitride (AlGaN) doped with magnesium (Mg). The material of the first N-type contact layer 20 can be GaN gallium nitride doped with silicon (Si), aluminum nitride (AlN) doped with silicon (Si), or aluminum gallium nitride (AlGaN) doped with silicon (Si).

[0108] FIG3 is a schematic diagram of the second light-emitting unit in FIG1 . In some exemplary embodiments, as shown in FIG1 and FIG3 , the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8 . The second light-emitting layer 6 may be a double-layer semiconductor structure and may include a stacked first electrode layer 13 , a first semiconductor layer 10 , a second electrode layer 14 , a second semiconductor layer 11 , and a third electrode layer 15 . The first electrode layer 13 , the first semiconductor layer 10 , the second electrode layer 14 , the second semiconductor layer 11 , and the third electrode layer 15 are sequentially arranged away from the substrate 1 . The first electrode layer 13 may be an N-type electrode. The first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The third electrode layer 15 may be an N-type electrode and may be a light-transmitting electrode. The material of the third electrode layer 15 may be the same as that of the second electrode 14 . The first semiconductor layer 10 can adopt a blue LED epitaxial structure, and the second semiconductor layer 11 can adopt a green LED epitaxial structure, but the present invention is not limited thereto. For example, the second semiconductor layer 11 can adopt a red LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 can be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5. "In the same layer" means that both are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged in sequence away from the substrate 1. The orthographic projections of the first N-type contact layer 20, the first quantum well 21, and the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23, arranged in sequence away from the substrate 1. The orthographic projections of the second P-type contact layer 25, the second quantum well 24, and the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown alternately over multiple cycles, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown alternately over multiple cycles, with the number of quantum well layers ranging from 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of silicon-doped GaN-gallium nitride, silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN).The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0109] In some exemplary embodiments, as shown in Figures 1 and 3, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15, and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1. The end of the first electrode layer 13 close to the first light-emitting unit 2 protrudes beyond the other structural layers of the second light-emitting unit 3, so that the end surface of the first electrode layer 13 away from the substrate 1 is partially uncovered by the first semiconductor layer 10. The lateral direction of the second light-emitting layer 6 is the sidewall of the second light-emitting layer 6 in the first direction.

[0110] In some exemplary embodiments, as shown in Figures 1 and 3, the second light-emitting unit 3 further includes a first metal trace 14 and a first insulating layer 26. The first metal trace 14 is located lateral to the second light-emitting layer 6. The first insulating layer 26 prevents the first metal trace 14 from contacting the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14. The first insulating layer 26 covers the end surfaces of the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 facing the first light-emitting unit 2. The first metal trace 14 is located on the side of the second light-emitting layer 6 facing the first light-emitting unit 2. One end of the first metal trace 14 is connected to the third electrode layer 15, and the other end of the first metal trace 14 extends toward the substrate 1 and to the end surface of the first electrode layer 13 not covered by the first semiconductor layer 10. The first metal trace 14 is also separated from the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 by the first insulating layer 26.

[0111] Figure 4 is a schematic diagram of the third light-emitting unit in Figure 1. In some exemplary embodiments, as shown in Figures 1 and 4, the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9, wherein the third light-emitting layer 7 may be a three-layer semiconductor structure, and the third light-emitting layer 7 may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, a third electrode layer 15, a third semiconductor layer 12 and a fourth electrode layer 16, and the first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15, the third semiconductor layer 12 and the fourth electrode layer 16 are arranged in sequence in a direction away from the substrate 1. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can be an opaque electrode that is not light-transmissive, but is not limited to this and can also be a transparent electrode. The second electrode layer 14 can be a P-type electrode and can be a light-transmissive electrode. The light-transmissive electrode is a transparent electrode material that is light-transmissive. The light-transmissive electrode can be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The third electrode layer 15 can be an N-type electrode and can be a light-transmissive electrode. The material of the third electrode layer 15 can be the same as that of the second electrode 14. The fourth electrode layer 16 can be a P-type electrode and can be a light-transmissive electrode. The material of the fourth electrode layer 16 can be the same as that of the second electrode 14. The first semiconductor layer 10 can adopt a blue LED epitaxial structure, the second semiconductor layer 11 can adopt a green LED epitaxial structure, and the third semiconductor layer 12 can adopt a red LED epitaxial structure, but is not limited to this. For example, the second semiconductor layer 11 can adopt a red LED epitaxial structure, and the third semiconductor layer 12 can adopt a green LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 can be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the second semiconductor layer 11 of the third light-emitting layer 7 can be arranged in the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, which are sequentially arranged in a direction away from the substrate 1. The orthographic projections of the first N-type contact layer 20, the first quantum well 21, and the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the third light-emitting layer 7 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23, which are sequentially arranged in a direction away from the substrate 1. The orthographic projections of the second P-type contact layer 25, the second quantum well 24, and the second N-type contact layer 23 on the substrate 1 overlap. The third semiconductor layer 12 of the third light-emitting layer 7 includes a third N-type contact layer 27, a third quantum well 28 and a third P-type contact layer 29 arranged in sequence in a direction away from the substrate 1, wherein the orthographic projection of the third N-type contact layer 27 on the substrate 1, the orthographic projection of the third quantum well 28 on the substrate 1 and the orthographic projection of the third P-type contact layer 29 on the substrate 1 overlap.The first quantum well 21, the second quantum well 24, and the third quantum well 28 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth. The number of quantum well layers ranges from 1 to 10. The first p-type contact layer 22, the second p-type contact layer 25, and the third p-type contact layer 29 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The first n-type contact layer 20, the second n-type contact layer 23, and the third n-type contact layer 27 can be made of silicon-doped gallium nitride (GaN), silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN). The second reflective layer 9 covers the end face of the fourth electrode layer 16 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting blue-green blocking film. The red-transmitting blue-green blocking film can be a red-transmitting, blue-reflecting, and green-light-combining film. The red-transmitting, blue-reflecting, and green-light-combining film can transmit red light and reflect blue light and green light. The red-transmitting, blue-reflecting, and green-light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0112] In some exemplary embodiments, as shown in Figures 1 and 4 , in the third light-emitting unit 4, the orthographic projections of the second semiconductor layer 11, third electrode layer 15, third semiconductor layer 12, fourth electrode 16, and second transflective layer 9 on the substrate 1 are all located within the orthographic projection of the second electrode layer 14 on the substrate 1. The end of the second electrode layer 14 facing away from the second light-emitting unit 3 protrudes beyond the second semiconductor layer 11, third electrode layer 15, third semiconductor layer 12, fourth electrode 16, and second transflective layer 9 of the third light-emitting unit 3, such that the end surface of the second electrode layer 14 facing away from the substrate 1 is partially uncovered by the second semiconductor layer 11. The lateral direction of the third light-emitting layer 7 is the sidewall of the third light-emitting layer 7 in the first direction. The orthographic projections of the first semiconductor layer 10 and second electrode layer 14 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1. The end of the first electrode layer 13 closest to the second light-emitting unit 3 protrudes beyond the other structures of the third light-emitting unit 3, such that the end surface of the first electrode layer 13 facing away from the substrate 1 is partially uncovered by the first semiconductor layer 10.

[0113] In some exemplary embodiments, as shown in Figures 1 and 3, the second light-emitting unit 3 further includes a second metal trace 18 and a second insulating layer 30, as well as a third metal trace 19 and a third insulating layer 31. The second metal trace 18 and the third metal trace 19 are located on opposite sides of the second light-emitting layer 6, respectively. The second insulating layer 30 prevents the second metal trace 18 from contacting the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14, and the third insulating layer 31 prevents the third metal trace 19 from contacting the second semiconductor layer 11, the third semiconductor layer 12, and the third electrode layer 15. The second insulating layer 30 covers the end surfaces of the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 facing the second light-emitting unit 3, and the third insulating layer 31 covers the end surfaces of the second semiconductor layer 11, the third semiconductor layer 12, and the third electrode layer 15 facing away from the second light-emitting unit 3. A second metal trace 18 is located on the side of the third light-emitting layer 7 facing the second light-emitting unit 3. One end of the second metal trace 18 is connected to the third electrode layer 15. The other end of the first metal trace 14 extends toward the substrate 1 and extends to the end surface of the first electrode layer 13 not covered by the first semiconductor layer 10. At the same time, the second metal trace 18 is separated from the first semiconductor layer 10, the second semiconductor layer 11, and the second electrode layer 14 by the second insulating layer 30. A third metal trace 19 is located on the side of the third light-emitting layer 7 facing away from the second light-emitting unit 3. One end of the third metal trace 19 is connected to the fourth electrode layer 16. The other end of the third metal trace 19 extends toward the substrate 1 and extends to the end surface of the second electrode layer 14 not covered by the second semiconductor layer 11. At the same time, the third metal trace 19 is separated from the second semiconductor layer 11, the third semiconductor layer 12, and the third electrode layer 15 by the third insulating layer 31.

[0114] In some exemplary embodiments, as shown in Figures 1 to 4, when the light-emitting chip is powered, the first electrode layer 13 and the second electrode layer 14 are each electrically connected, and the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 each emit light. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, which transmits through the second electrode layer 14 and exits toward the first electrode layer 13, causing the first light-emitting unit 2 to emit blue light. When the first and second semiconductor layers 10, 11 of the second light-emitting unit 3 are powered, the first semiconductor layer 10 emits blue light, which transmits through the second electrode layer 13, the second semiconductor layer 11, and the third electrode layer 15. The second semiconductor layer 11 emits green light, which transmits through the third electrode layer 15. After the two colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through it, causing the second light-emitting unit 3 to electroluminesce green light. Simultaneously, in the second light-emitting unit 3, the blue light excites the second semiconductor layer 11 to emit green light, increasing the brightness of the green light. When power is applied to the first semiconductor layer 10, second semiconductor layer 11, and third semiconductor layer 12 of the second light-emitting unit 3, the first semiconductor layer 10 emits blue light, which is transmitted through the second electrode layer 13, second semiconductor layer 11, third electrode layer 15, third semiconductor layer 12, and fourth electrode layer 16 to the second transflective layer 9. The second semiconductor layer 11 emits green light, which is transmitted through the third electrode layer 15, third semiconductor layer 12, and fourth electrode layer 16 to the second transflective layer 9. The third semiconductor layer 12 emits red light, which is transmitted through the fourth electrode layer 16 to the second transflective layer 9. After the three colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue and green light and allows the red light to pass through the second transflective layer 9, causing the third light-emitting unit 4 to electroluminesce red light. Simultaneously, in the third light-emitting unit 4, the blue light excites the second semiconductor layer 11 to emit green light and the third semiconductor layer 12 to emit red light, thereby increasing the brightness of the red light.

[0115] Figure 5 is a schematic diagram of another light-emitting chip of this example embodiment. In some exemplary embodiments, as shown in Figure 5, the first electrode layer 13 of the first light-emitting layer 5, the first electrode layer 13 of the second light-emitting layer 6 and the first electrode layer 13 of the third light-emitting layer 7 are integrated into one piece, forming a first electrode layer 13 shared by the first light-emitting layer 5, the second light-emitting layer 6 and the third light-emitting layer 7.

[0116] FIG6 is a schematic diagram of another light-emitting chip according to this exemplary embodiment. In some exemplary embodiments, as shown in FIG6 , the light-emitting chip further includes a reflective film 44, wherein the reflective film 44 is configured to at least wrap around the lateral surfaces of the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4. That is, all outer surfaces of the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 except for the end surfaces facing and facing away from the substrate 1 are wrapped with the reflective film 44, thereby preventing the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 from emitting light laterally. The reflective film 44 can adopt a distributed Bragg reflector structure. A distributed Bragg reflector (DBR) is a periodic structure composed of two materials with different refractive indices arranged alternately in an ABAB manner. The thickness of each layer of material is 1 / 4 of the wavelength (center wavelength) of the reflected light. Therefore, it is a quarter-wave multilayer system, equivalent to a group of photonic crystals. In this embodiment, the two materials with different refractive indices can be aluminum gallium nitride (AlGaN) and gallium nitride (GaN), aluminum gallium arsenide (AlGaAs) and gallium arsenide (GaAs), hafnium dioxide (HfO2) and silicon dioxide (SiO2), or titanium dioxide (TiO2) / silicon dioxide (SiO2). The calculation formula for a distributed Bragg reflector (DBR) is d = λ / 4η, where d is the layer thickness, λ is the center wavelength, and η is the layer's refractive index. For example, if the DBR reflects blue light with a center wavelength of 450nm and uses TiO2 / SiO2, the refractive index η of SiO2 is 1.47, resulting in a layer thickness d of 76.5nm. If the refractive index η of TiO2 is 2.52, resulting in a layer thickness d of 44.64nm, the DBR can achieve a reflectivity exceeding 99% because electromagnetic waves with frequencies within the band gap cannot penetrate. This eliminates the absorption issues associated with metal mirrors, and the more repeated layers a distributed Bragg reflector has, the higher the reflection efficiency. In actual implementation, the band gap position can be adjusted by adjusting the thickness of each layer, or by adjusting the refractive index and thus the band gap position by adjusting the composition of the materials of each layer. It only requires matching the thickness, refractive index and central wavelength.

[0117] In some exemplary embodiments, as shown in FIG6 , the light-emitting chip further includes an encapsulation structure 45 , which is disposed on the substrate 1 and covers the first light-emitting unit 2 , the second light-emitting unit 3 , and the third light-emitting unit 4 . The encapsulation structure 45 embeds the first light-emitting unit 2 , the second light-emitting unit 3 , and the third light-emitting unit 4 therein, thereby combining the first light-emitting unit 2 , the second light-emitting unit 3 , and the third light-emitting unit 4 into one body. The encapsulation structure 45 is made of a transparent material and is a transparent, non-conductive medium, such as transparent silicon dioxide, transparent silicon nitride, or transparent aluminum nitride, which is permeable to light. The encapsulation structure 45 may have a first opening on a side of the first light-emitting unit 2 , the second light-emitting unit 3 , and the third light-emitting unit 4 away from the substrate 1 .

[0118] In some exemplary embodiments, a manufacturing method is used to prepare the light-emitting chip shown in FIG6 . The manufacturing method primarily includes deposition, etching, and packaging. First, a substrate is prepared. A first conductive layer 47 , a first epitaxial layer 48 , a second conductive layer 49 , a second epitaxial layer 50 , a third conductive layer 51 , a third epitaxial layer 52 , and a fourth conductive layer 53 are sequentially deposited on the prepared substrate. The first epitaxial layer 48 can adopt a blue light LED epitaxial structure, the second epitaxial layer 50 can adopt a green light LED epitaxial structure, and the third epitaxial layer 52 can adopt a red light LED epitaxial structure, resulting in a composite film layer 54 as shown in FIG15 a .

[0119] Secondly, the composite film layer 54 is etched to obtain a light-emitting layer pattern 55, and the above-mentioned composite film layer 54 is etched into an independent first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7 to obtain a light-emitting layer pattern 55 as shown in Figure 15b. The light-emitting layer pattern 55 may include a first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7; the first light-emitting layer 5 includes a stacked first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14; the second light-emitting layer 6 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11 and a third electrode layer 15; the third light-emitting layer 7 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, a third electrode layer 15, a third semiconductor layer 12 and a fourth electrode layer 16.

[0120] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, which includes a first insulating layer 26 as shown in Figure 3, and a second insulating layer 30 and a third insulating layer 31 as shown in Figure 4. The first insulating layer 26 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14 facing the second light-emitting unit 6; the second insulating layer 30 covers the end faces of the first semiconductor layer 10, the second semiconductor layer 11 and the second electrode layer 14 facing the second light-emitting layer 6; the third insulating layer 31 covers the end faces of the second semiconductor layer 11, the third semiconductor layer 12 and the third electrode layer 15 facing away from the second light-emitting layer 6.

[0121] Continue to deposit metal layers and etch to obtain a metal routing pattern, which includes a first metal routing 17, a second metal routing 18, and a third metal routing 19 as shown in FIG1 . The first metal routing 17 corresponds to the first insulating layer 26 and connects the third electrode layer 15 and the first electrode layer 13 of the second light-emitting layer 6; the second metal routing 18 corresponds to the second insulating layer 30 and connects the third electrode layer 15 and the first electrode layer 13 of the third light-emitting layer 7; the third metal routing 19 corresponds to the third insulating layer 31 and connects the fourth electrode layer 16 and the second electrode layer 14 of the third light-emitting layer 7.

[0122] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes the first transflective layer 8 as shown in FIG. 1 .

[0123] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes a second transflective layer 9 as shown in FIG. 1 , forming independent first light-emitting units 2 , second light-emitting units 3 and third light-emitting units 4 .

[0124] Subsequently, packaging is performed, and after depositing the reflective film, the packaging structure is rotated and filled on the substrate so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0125] Finally, the substrate is peeled off, and the first light-emitting unit 2 and other structures without the backing plate are transferred to the base plate 1, thereby completing the entire preparation process of the light-emitting chip.

[0126] FIG7 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure, and FIG8 is a schematic diagram of the first light-emitting unit in FIG7 . In some exemplary embodiments, as shown in FIG7 and FIG8 , the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 are arranged sequentially along a first direction parallel to the substrate 1. The spacing between the first light-emitting unit 2 and the second light-emitting unit 3, as well as the spacing between the second light-emitting unit 3 and the third light-emitting unit 4, all match the pixel pitch. The first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 all have a stacked structure. The first light-emitting unit 2 may include a single-layer first light-emitting layer 5. A single-layer structure refers to a structure having only one semiconductor layer. The first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10, and a second electrode layer 14. The first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 are stacked sequentially in a direction away from the substrate 1. The projections of the first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can serve as an opaque electrode that is not transparent to light, but is not limited to this. It can also be a transparent electrode. The second electrode layer 14 can be a P-type electrode and can be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that transmits light. The light-transmitting electrode can be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can be a blue light LED epitaxial layer, so that the first color light emitted by the first light-emitting unit 2 is blue light, but is not limited to this. For example, the first semiconductor layer 10 can be a red light LED epitaxial structure or a green light LED epitaxial structure, and the corresponding first color light will also change accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged in sequence away from the substrate 1. The first quantum well 21 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth. The number of quantum wells 27 layers ranges from 1 to 10. The material of the first P-type contact layer 22 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The material of the first N-type contact layer 20 can be made of silicon-doped GaN-gallium nitride, silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN).

[0127] FIG9 is a schematic diagram of the second light-emitting unit in FIG7 . In some exemplary embodiments, as shown in FIG7 and FIG9 , the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8 . The second light-emitting layer 6 may be a double-layer semiconductor structure and may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a second semiconductor layer 11. The first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, and the second semiconductor layer 11 are arranged sequentially away from the substrate 1 . The first electrode layer 13 may be an N-type electrode. The first electrode layer 1 may be an opaque electrode that is not transparent to light, but is not limited to this. A transparent electrode may also be provided. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that transmits light. The light-transmitting electrode may be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may employ a blue LED epitaxial structure, and the second semiconductor layer 11 may employ a green LED epitaxial structure, but is not limited to this. For example, the second semiconductor layer 11 may employ a red LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 can be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5. "In the same layer" means that the two are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, which are arranged in sequence in a direction away from the substrate 1. The orthographic projection of the first N-type contact layer 20, the orthographic projection of the first quantum well 21, and the orthographic projection of the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23, which are arranged in sequence in a direction away from the substrate 1. The orthographic projection of the second P-type contact layer 25, the orthographic projection of the second quantum well 24, and the orthographic projection of the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown alternately over multiple cycles, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown alternately over multiple cycles, with the number of quantum well layers ranging from 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of silicon-doped GaN-gallium nitride, silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN).The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0128] In some exemplary embodiments, as shown in Figures 7 and 9, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15 and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the second light-emitting layer 6 is the side wall of the second light-emitting layer 6 in the first direction.

[0129] In some exemplary embodiments, as shown in Figures 7, 8, and 9, the light-emitting chip further includes a fourth metal trace 32, a fourth insulating layer 40, and a fifth insulating layer 41. The fourth metal trace 32 is located between the second light-emitting layer 6 and the first light-emitting layer 5. The fourth insulating layer 40 prevents the fourth metal trace 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5. The fifth insulating layer 41 prevents the fourth metal trace 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The fourth insulating layer 40 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 that face the second light-emitting layer 6. The fifth insulating layer 41 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 that face the first light-emitting layer 5. The fourth metal trace 32 includes a first covering segment 34, a second covering segment 35, and a third covering segment 36, which are connected in sequence. The first covering segment 34 is located on the side of the first light-emitting layer 5 facing the second light-emitting layer 6. One end of the first covering segment 34 is connected to the end of the second electrode layer 14 of the first light-emitting layer 5 facing the second light-emitting layer 6. The other end of the first covering segment 34 extends to the substrate 1 and connects to the second covering segment 35. The second covering segment 35 covers the portion of the substrate 1 between the second light-emitting layer 6 and the first light-emitting layer 5. The third covering segment 36 is located on the side of the second light-emitting layer 6 facing the first light-emitting layer 5. One end of the third covering segment 36 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the first light-emitting layer 5. The other end of the third covering segment 36 extends to the substrate 1 and connects to the second covering segment 35. The first covering segment 34 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 by the fourth insulating layer 40, and the third covering segment 36 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the fifth insulating layer 41. As a result, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5 are electrically connected.

[0130] FIG10 is a schematic diagram of the third light-emitting unit in FIG7 . In some exemplary embodiments, as shown in FIG7 and FIG10 , the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9. The third light-emitting layer 7 may be a three-layer semiconductor structure and may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, a second semiconductor layer 11, and a third semiconductor layer 12. The first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, and the third semiconductor layer 12 are arranged in sequence away from the substrate 1. The first electrode layer 13 may be an N-type electrode. The first electrode layer 1 may serve as an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue LED epitaxial structure, the second semiconductor layer 11 may adopt a green LED epitaxial structure, and the third semiconductor layer 12 may adopt a red LED epitaxial structure, but the present invention is not limited thereto. For example, the second semiconductor layer 11 may adopt a red LED epitaxial structure, while the third semiconductor layer 12 may adopt a green LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 may be arranged on the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the second semiconductor layer 11 of the third light-emitting layer 7 may be arranged on the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged in sequence in a direction away from the substrate 1. The orthographic projections of the first N-type contact layer 20, the first quantum well 21, and the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the third light-emitting layer 7 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23, sequentially arranged in a direction away from the substrate 1. The orthographic projections of the second P-type contact layer 25, the second quantum well 24, and the second N-type contact layer 23 on substrate 1 overlap. The third semiconductor layer 12 of the third light-emitting layer 7 may include a third N-type contact layer 27, a third quantum well 28, and a third P-type contact layer 29, sequentially arranged in a direction away from the substrate 1. The orthographic projections of the third N-type contact layer 27, the third quantum well 28, and the third P-type contact layer 29 on substrate 1 overlap. The first quantum well 21, the second quantum well 24, and the third quantum well 28 may be formed by alternating multiple periods of indium gallium nitride (InGaN) and gallium nitride (GaN), or by alternating multiple periods of aluminum gallium nitride (AlGaN) and gallium nitride (GaN). The number of quantum well layers ranges from 1 to 10.The materials for the first P-type contact layer 22, the second P-type contact layer 25, and the third P-type contact layer 29 can be GaN-doped with magnesium (Mg), aluminum nitride (AlN) doped with magnesium (Mg), or aluminum gallium nitride (AlGaN) doped with magnesium (Mg). The materials for the first N-type contact layer 20, the second N-type contact layer 23, and the third N-type contact layer 27 can be GaN-doped with silicon (Si), aluminum nitride (AlN) doped with silicon (Si), or aluminum gallium nitride (AlGaN) doped with silicon (Si). The second reflective layer 9 covers the end face of the third semiconductor layer 12 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting, blue-green-blocking film. The red-transmitting, blue-green-blocking film can be a red-transmitting, blue-reflecting, and green-reflecting light-combining film that transmits red light and reflects blue and green light. The red-transmitting, blue-reflecting, and green-reflecting light-combining film can be prepared by an evaporation process or a deposition process.

[0131] In some exemplary embodiments, as shown in Figures 7 and 10, in the third light-emitting unit 4, the orthographic projections of the first semiconductor 10, the second electrode layer 14, the second semiconductor layer 11, the third semiconductor layer 12 and the second transflective layer 9 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the third light-emitting layer 7 is the side wall of the third light-emitting layer 7 in the first direction.

[0132] In some exemplary embodiments, as shown in Figures 7, 9, and 10, the light-emitting chip further includes a fifth metal trace 33, a sixth insulating layer 42, and a seventh insulating layer 43. The fifth metal trace 33 is located between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth insulating layer 42 prevents the fifth metal trace 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The seventh insulating layer 43 prevents the fifth metal trace 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7. The sixth insulating layer 42 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 5 that face the third light-emitting layer 7. The seventh insulating layer 43 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 that face the second light-emitting layer 6. The fifth metal trace 33 includes a fourth covering segment 37, a fifth covering segment 38, and a sixth covering segment 39, which are connected in sequence. The fourth covering segment 37 is located on the side of the second light-emitting layer 6 facing the third light-emitting layer 7. One end of the fourth covering segment 37 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the third light-emitting layer 7. The other end of the fourth covering segment 37 extends to the substrate 1 and connects to the fifth covering segment 38. The fifth covering segment 38 covers the portion of the substrate 1 between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth covering segment 39 is located on the side of the third light-emitting layer 7 facing the second light-emitting layer 6. One end of the sixth covering segment 39 is connected to the end of the second electrode layer 14 of the third light-emitting layer 7 facing the second light-emitting layer 6. The other end of the sixth covering segment 39 extends to the substrate 1 and connects to the fifth covering segment 38. The fourth covering segment 37 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the sixth insulating layer 42, and the sixth covering segment 39 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 by the seventh insulating layer 43. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, so that the second electrode layer 14 of the first light-emitting layer 5, the second light-emitting layer 6 and the third light-emitting layer 7 are electrically connected, forming a common electrode for the three.

[0133] In some exemplary embodiments, as shown in FIG7 , when the light-emitting chip is powered, the first electrode layer 13 and the second electrode layer 14 are electrically connected, and the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 each emit light. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, which passes through the second electrode layer 14 and exits toward the first electrode layer 13, causing the first light-emitting unit 2 to emit blue light through electroluminescence. The first semiconductor layer 10 of the second light-emitting unit 3 emits blue light, which passes through the second electrode layer 14 and strikes the second semiconductor layer 11. It then passes through the second semiconductor layer 11 and strikes the first transflective layer 8. Simultaneously, the blue light excites the second semiconductor layer 11 to emit green light, which strikes the first transflective layer 8. After both colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through it, causing the second light-emitting unit 3 to emit green light through photoluminescence. The first semiconductor layer 10 of the third light-emitting unit 4 emits blue light. The blue light passes through the second electrode layer 14, irradiating the second semiconductor layer 11. It can also pass through the second semiconductor layer 11 to irradiate the third semiconductor layer 12. The blue light excites the second semiconductor layer 11 to emit green light, which passes through the third semiconductor layer 12 to irradiate the second transflective layer 9. Simultaneously, the blue light also excites the third semiconductor layer 12 to emit red light, which then irradiates the second transflective layer 9. When the three colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue and green light and allows the red light to pass through the second transflective layer 9, causing the third light-emitting unit 4 to emit red light through photoluminescence.

[0134] In some exemplary embodiments, a manufacturing method is used to prepare the light-emitting chip shown in FIG7 . The manufacturing method primarily includes deposition, etching, and packaging. First, a substrate is prepared. A first conductive layer 47 , a first epitaxial layer 48 , a second conductive layer 49 , a second epitaxial layer 50 , and a third epitaxial layer 52 are sequentially deposited on the prepared substrate. The first epitaxial layer 48 can adopt a blue light LED epitaxial structure, the second epitaxial layer 50 can adopt a green light LED epitaxial structure, and the third epitaxial layer 52 can adopt a red light LED epitaxial structure, resulting in a composite film layer 54 as shown in FIG16 a .

[0135] Secondly, a first etching is performed to etch the above-mentioned composite film layer 54 into an independent first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7, to obtain a light-emitting layer pattern 55 as shown in Figure 16b. The light-emitting layer pattern 55 may include a first light-emitting layer 5, a second light-emitting layer 6 and a third light-emitting layer 7; the first light-emitting layer 5 includes a stacked first electrode layer 13, a first semiconductor layer 10 and a second electrode layer 14; the second light-emitting layer 6 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a second semiconductor layer 11; the third light-emitting layer 7 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a third semiconductor layer 12.

[0136] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, which includes a fourth insulating layer 40 as shown in Figure 8, a fifth insulating layer 41 and a sixth insulating layer 42 as shown in Figure 9, and a seventh insulating layer 43 as shown in Figure 10. The fourth insulating layer 40 covers the first electrode layer 13 of the first light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6, the fifth insulating layer 41 covers the first electrode layer 13 of the second light-emitting layer 6 and the end face of the first semiconductor layer 10 facing the first light-emitting layer 5; the sixth insulating layer 42 covers the first electrode layer 13 of the second light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the first electrode layer 13 of the third light-emitting layer 7 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6.

[0137] A metal layer is deposited and etched to obtain a metal wiring pattern, which includes a fourth metal wiring 32 and a fifth metal wiring 33 as shown in FIG7 , to obtain a first blank, wherein the fourth metal wiring 32 corresponds to the fourth insulating layer 40 and the fifth insulating layer 41 and connects the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5; the fifth metal wiring 33 corresponds to the sixth insulating layer 42 and the seventh insulating layer 43 and connects the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7.

[0138] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes a first transflective layer 8 as shown in FIG. 7 .

[0139] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes a second transflective layer 9 as shown in FIG. 7 , forming independent first light-emitting units 2 , second light-emitting units 3 and third light-emitting units 4 .

[0140] Subsequently, packaging is performed, and after depositing the reflective film, the packaging structure is rotated and filled on the substrate so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0141] Finally, the substrate is peeled off, and the first light-emitting unit 2 and other structures without the backing plate are transferred to the base plate 1, thereby completing the entire preparation process of the light-emitting chip.

[0142] FIG11 is a schematic diagram of another light-emitting chip according to an embodiment of the present disclosure, and FIG12 is a schematic diagram of the first light-emitting unit in FIG11 . In some exemplary embodiments, as shown in FIG11 and FIG12 , the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 are sequentially arranged along a first direction parallel to the substrate 1. The spacing between the first light-emitting unit 2 and the second light-emitting unit 3, as well as the spacing between the second light-emitting unit 3 and the third light-emitting unit 4, all match the pixel pitch. The first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 all have a stacked structure. The first light-emitting unit 2 may include a single-layer first light-emitting layer 5. A single-layer structure refers to a structure having only one semiconductor layer. The first light-emitting layer 5 may include a first electrode layer 13, a first semiconductor layer 10, and a second electrode layer 14. The first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 are sequentially stacked in a direction away from the substrate 1. The projections of the first electrode layer 13, the first semiconductor layer 10, and the second electrode layer 14 on the substrate 1 all overlap. The first electrode layer 13 can be an N-type electrode. The first electrode layer 1 can serve as an opaque electrode that is not transparent to light, but is not limited to this. It can also be a transparent electrode. The second electrode layer 14 can be a P-type electrode and can be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that transmits light. The light-transmitting electrode can be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can be a blue light LED epitaxial layer, so that the first color light emitted by the first light-emitting unit 2 is blue light, but is not limited to this. For example, the first semiconductor layer 10 can be a red light LED epitaxial structure or a green light LED epitaxial structure, and the corresponding first color light will also change accordingly. The first semiconductor layer 10 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged in sequence away from the substrate 1. The first quantum well 21 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth. The number of quantum wells 27 layers ranges from 1 to 10. The material of the first P-type contact layer 22 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The material of the first N-type contact layer 20 can be made of silicon-doped GaN-gallium nitride, silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN).

[0143] FIG13 is a schematic diagram of the second light-emitting unit in FIG11 . In some exemplary embodiments, as shown in FIG11 and FIG13 , the second light-emitting unit 3 may include a second light-emitting layer 6 and a first transflective layer 8 . The second light-emitting layer 6 may have a double-layer semiconductor structure and may include a stacked first electrode layer 13 , a first semiconductor layer 10 , a second electrode layer 14 , and a second semiconductor layer 11 . The first electrode layer 13 , the first semiconductor layer 10 , the second electrode layer 14 , and the second semiconductor layer 11 are sequentially arranged away from the substrate 1 . The first electrode layer 13 may be an N-type electrode, and the first electrode layer 1 may serve as an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 can adopt a blue LED epitaxial structure, and the second semiconductor layer 11 can adopt a green LED epitaxial structure, but the present invention is not limited thereto. For example, the second semiconductor layer 11 can adopt a red LED epitaxial structure. The first semiconductor layer 10 of the second light-emitting layer 6 can be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5. "In the same layer" means that both are formed simultaneously through the same patterning process. The first semiconductor layer 10 of the second light-emitting layer 6 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, arranged in sequence away from the substrate 1. The orthographic projections of the first N-type contact layer 20, the first quantum well 21, and the first P-type contact layer 22 on the substrate 1 overlap. The second semiconductor layer 11 of the second light-emitting layer 6 may include a second P-type contact layer 25, a second quantum well 24, and a second N-type contact layer 23, arranged in sequence away from the substrate 1. The orthographic projections of the second P-type contact layer 25, the second quantum well 24, and the second N-type contact layer 23 on the substrate 1 overlap. The first quantum well 21 and the second quantum well 24 can be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown alternately over multiple cycles, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown alternately over multiple cycles, with the number of quantum well layers ranging from 1 to 10. The materials of the first P-type contact layer 22 and the second P-type contact layer 25 can be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The materials of the first N-type contact layer 20 and the second N-type contact layer 23 can be made of silicon-doped GaN-gallium nitride, silicon-doped aluminum nitride (AlN), or silicon-doped aluminum gallium nitride (AlGaN).The first reflective layer 8 can filter light of different wavelengths. The first reflective layer 8 is a reflective film. The reflective film can be a conductive green-transmitting and blue-blocking film. The green-transmitting and blue-blocking film can be a green-transmitting and blue-reflecting light-combining film. The green-transmitting and blue-reflecting light-combining film can transmit green light with a larger wavelength and reflect blue light with a smaller wavelength. The green-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0144] In some exemplary embodiments, as shown in Figures 11 and 13, in the second light-emitting unit 3, the orthographic projections of the first semiconductor layer 10, the second electrode layer 14, the second semiconductor layer 11, the third electrode layer 15 and the first transflective layer 8 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the second light-emitting layer 6 is the side wall of the second light-emitting layer 6 in the first direction.

[0145] In some exemplary embodiments, as shown in Figures 11, 12, and 13, the light-emitting chip further includes a fourth metal trace 32, a fourth insulating layer 40, and a fifth insulating layer 41. The fourth metal trace 32 is located between the second light-emitting layer 6 and the first light-emitting layer 5. The fourth insulating layer 40 can prevent the fourth metal trace 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5. The fifth insulating layer 41 can prevent the fourth metal trace 32 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The fourth insulating layer 40 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 facing the second light-emitting layer 6, and the fifth insulating layer 41 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 facing the first light-emitting layer 5. The fourth metal trace 32 includes a first covering segment 34, a second covering segment 35, and a third covering segment 36, which are connected in sequence. The first covering segment 34 is located on the side of the first light-emitting layer 5 facing the second light-emitting layer 6. One end of the first covering segment 34 is connected to the end of the second electrode layer 14 of the first light-emitting layer 5 facing the second light-emitting layer 6. The other end of the first covering segment 34 extends to the substrate 1 and connects to the second covering segment 35. The second covering segment 35 covers the portion of the substrate 1 between the second light-emitting layer 6 and the first light-emitting layer 5. The third covering segment 36 is located on the side of the second light-emitting layer 6 facing the first light-emitting layer 5. One end of the third covering segment 36 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the first light-emitting layer 5. The other end of the third covering segment 36 extends to the substrate 1 and connects to the second covering segment 35. The first covering segment 34 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the first light-emitting layer 5 by the fourth insulating layer 40, and the third covering segment 36 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the fifth insulating layer 41. As a result, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5 are electrically connected.

[0146] FIG14 is a schematic diagram of the third light-emitting unit in FIG11 . In some exemplary embodiments, as shown in FIG11 and FIG14 , the third light-emitting unit 4 may include a third light-emitting layer 7 and a second transflective layer 9. The third light-emitting layer 7 may be a two-layer semiconductor structure and may include a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a third semiconductor layer 12. The first electrode layer 13, the first semiconductor layer 10, the second electrode layer 14, and the third semiconductor layer 12 are arranged in sequence away from the substrate 1. The first electrode layer 13 may be an N-type electrode. The first electrode layer 1 may serve as an opaque electrode that is not transparent to light, but is not limited thereto and may also be a transparent electrode. The second electrode layer 14 may be a P-type electrode and may be a light-transmitting electrode. The light-transmitting electrode is a transparent electrode material that is transparent to light. The light-transmitting electrode may be made of indium tin oxide (ITO), which has good visible light transmittance and low resistivity. The first semiconductor layer 10 may adopt a blue light LED epitaxial structure, and the third semiconductor layer 12 may adopt a red light LED epitaxial structure, but the present invention is not limited thereto. For example, the third semiconductor layer 12 may adopt a green light LED epitaxial structure. The first semiconductor layer 10 of the third light-emitting layer 7 may be arranged in the same layer as the first semiconductor layer 10 of the first light-emitting layer 5 and the second light-emitting layer 6, and the third semiconductor layer 12 of the third light-emitting layer 7 may be arranged in the same layer as the second semiconductor layer 11 of the second light-emitting layer 6. The first semiconductor layer 10 of the third light-emitting layer 7 includes a first N-type contact layer 20, a first quantum well 21, and a first P-type contact layer 22, which are sequentially arranged in a direction away from the substrate 1. The orthographic projections of the first N-type contact layer 20, the first quantum well 21, and the first P-type contact layer 22 on the substrate 1 overlap. The third semiconductor layer 12 of the third light-emitting layer 7 may include a third P-type contact layer 29, a third quantum well 28, and a third N-type contact layer 27, arranged sequentially in a direction away from the substrate 1. The orthographic projections of the third N-type contact layer 27, the third quantum well 28, and the third P-type contact layer 29 on the substrate 1 overlap. The first quantum well 21 and the third quantum well 28 may be made of indium gallium nitride (InGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth, or aluminum gallium nitride (AlGaN) / gallium nitride (GaN) grown in multiple cycles of alternating growth. The number of quantum well layers ranges from 1 to 10. The materials of the first P-type contact layer 22 and the third P-type contact layer 29 may be made of magnesium-doped GaN-gallium nitride, magnesium-doped aluminum nitride (AlN), or magnesium-doped aluminum gallium nitride (AlGaN). The materials of the first N-type contact layer 20 and the third N-type contact layer 27 can be silicon-Si-doped gallium nitride GaN, silicon-Si-doped aluminum nitride AlN, or silicon-Si-doped aluminum gallium nitride AlGaN.The second reflective layer 9 covers the end face of the third semiconductor layer 12 away from the substrate 1. The second reflective layer 9 can be a conductive red-transmitting and blue-blocking film. The red-transmitting and blue-blocking film can be a red-transmitting and blue-reflecting light-combining film. The red-transmitting and blue-reflecting light-combining film can transmit red light and reflect blue light. The red-transmitting and blue-reflecting light-combining film can be prepared by an evaporation process or can be manufactured by a deposition process.

[0147] In some exemplary embodiments, as shown in Figures 11 and 14, in the third light-emitting unit 4, the orthographic projections of the first semiconductor 10, the second electrode layer 14, the third semiconductor layer 12 and the second reflective layer 9 on the substrate 1 are all located within the orthographic projection of the first electrode layer 13 on the substrate 1, and the lateral direction of the third light-emitting layer 7 is the side wall of the third light-emitting layer 7 in the first direction.

[0148] In some exemplary embodiments, as shown in Figures 11, 13, and 14, the light-emitting chip further includes a fifth metal trace 33, a sixth insulating layer 42, and a seventh insulating layer 43. The fifth metal trace 33 is located between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth insulating layer 42 prevents the fifth metal trace 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6. The seventh insulating layer 43 prevents the fifth metal trace 33 from contacting the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7. The sixth insulating layer 42 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 5 that face the third light-emitting layer 7. The seventh insulating layer 43 covers the end surfaces of the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 that face the second light-emitting layer 6. The fifth metal trace 33 includes a fourth covering segment 37, a fifth covering segment 38, and a sixth covering segment 39, which are connected in sequence. The fourth covering segment 37 is located on the side of the second light-emitting layer 6 facing the third light-emitting layer 7. One end of the fourth covering segment 37 is connected to the end of the second electrode layer 14 of the second light-emitting layer 6 facing the third light-emitting layer 7. The other end of the fourth covering segment 37 extends to the substrate 1 and connects to the fifth covering segment 38. The fifth covering segment 38 covers the portion of the substrate 1 between the second light-emitting layer 6 and the third light-emitting layer 7. The sixth covering segment 39 is located on the side of the third light-emitting layer 7 facing the second light-emitting layer 6. One end of the sixth covering segment 39 is connected to the end of the second electrode layer 14 of the third light-emitting layer 7 facing the second light-emitting layer 6. The other end of the sixth covering segment 39 extends to the substrate 1 and connects to the fifth covering segment 38. The fourth covering segment 37 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the second light-emitting layer 6 by the sixth insulating layer 42, and the sixth covering segment 39 is separated from the first electrode layer 13 and the first semiconductor layer 10 of the third light-emitting layer 7 by the seventh insulating layer 43. Thus, the second electrode layer 14 of the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7 are electrically connected, so that the second electrode layer 14 of the first light-emitting layer 5, the second light-emitting layer 6 and the third light-emitting layer 7 are electrically connected, forming a common electrode for the three.

[0149] In some exemplary embodiments, as shown in FIG11 , when the light-emitting chip is powered, the first electrode layer 13 and the second electrode layer 14 are electrically connected, and the first light-emitting unit 2, the second light-emitting unit 3, and the third light-emitting unit 4 each emit light. The first semiconductor layer 10 of the first light-emitting unit 2 emits blue light, which passes through the second electrode layer 14 and exits toward the first electrode layer 13, causing the first light-emitting unit 2 to emit blue light through electroluminescence. The first semiconductor layer 10 of the second light-emitting unit 3 emits blue light, which passes through the second electrode layer 14 and strikes the second semiconductor layer 11. It then passes through the second semiconductor layer 11 and strikes the first transflective layer 8. Simultaneously, the blue light excites the second semiconductor layer 11 to emit green light, which strikes the first transflective layer 8. After both colors of light pass through the first transflective layer 8, the first transflective layer 8 reflects the blue light and allows the green light to pass through it, causing the second light-emitting unit 3 to emit green light through photoluminescence. The first semiconductor layer 10 of the third light-emitting unit 4 emits blue light. The blue light passes through the second electrode layer 14, irradiates the third semiconductor layer 12, and can pass through the third semiconductor layer 12 to irradiate the second transflective layer 9. The blue light can excite the third semiconductor layer 12 to emit red light, and the red light irradiates the second transflective layer 9. When the two colors of light pass through the second transflective layer 9, the second transflective layer 9 reflects the blue light and allows the red light to pass through the second transflective layer 9, so that the third light-emitting unit 4 emits red light through photoluminescence.

[0150] In some exemplary embodiments, a manufacturing method is used to prepare the light-emitting chip shown in Figure 11. The manufacturing method primarily includes deposition, etching, and packaging. First, a substrate is prepared. A first conductive layer 47, a first epitaxial layer 48, a second conductive layer 49, and a second epitaxial layer 50 are sequentially deposited on the prepared substrate. The first epitaxial layer 48 can adopt a blue LED epitaxial structure, and the second epitaxial layer 50 can adopt a green LED epitaxial structure, resulting in a composite film layer 54 as shown in Figure 17a.

[0151] Subsequently, the second epitaxial layer 50 is etched to form a first light emitting pattern 56 , and the second semiconductor layer 11 includes a second semiconductor layer 11 , as shown in FIG. 17 b .

[0152] Next, a third epitaxial layer 52 is deposited on the first light-emitting pattern 56 . The third epitaxial layer 52 may adopt a red LED epitaxial structure, as shown in FIG. 17 c .

[0153] The third epitaxial layer 52 is then etched to form independent first light-emitting layer 5, second light-emitting layer 6 and third light-emitting layer 7, and a second light-emitting layer pattern 55 as shown in Figure 17d is obtained. The light-emitting layer pattern 55 can be the third semiconductor layer 12 to form a third light-emitting layer 7. The third light-emitting layer 7 includes a stacked first electrode layer 13, a first semiconductor layer 10, a second electrode layer 14, and a third semiconductor layer 12.

[0154] Next, an insulating film is deposited and etched to obtain an insulating layer pattern, which includes a fourth insulating layer 40 as shown in Figure 12, a fifth insulating layer 41 and a sixth insulating layer 42 as shown in Figure 13, and a seventh insulating layer 43 as shown in Figure 14. The fourth insulating layer 40 covers the first electrode layer 13 of the first light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6, the fifth insulating layer 41 covers the first electrode layer 13 of the second light-emitting layer 6 and the end face of the first semiconductor layer 10 facing the first light-emitting layer 5; the sixth insulating layer 42 covers the first electrode layer 13 of the second light-emitting layer 5 and the end face of the first semiconductor layer 10 facing the third light-emitting layer 7, and the seventh insulating layer 43 covers the first electrode layer 13 of the third light-emitting layer 7 and the end face of the first semiconductor layer 10 facing the second light-emitting layer 6.

[0155] A metal layer is deposited and etched to obtain a metal wiring pattern, which includes a fourth metal wiring 32 and a fifth metal wiring 33 as shown in FIG11 , to obtain a first blank. The fourth metal wiring 32 corresponds to the fourth insulating layer 40 and the fifth insulating layer 41 and connects the second light-emitting layer 6 and the second electrode layer 14 of the first light-emitting layer 5; the fifth metal wiring 33 corresponds to the sixth insulating layer 42 and the seventh insulating layer 43 and connects the second light-emitting layer 6 and the second electrode layer 14 of the third light-emitting layer 7.

[0156] Then, a first transflective film is deposited on the metal wiring pattern and etched to obtain a first transflective pattern. The first transflective pattern includes a first transflective layer 8 as shown in FIG. 11 .

[0157] Next, a first transflective film is deposited on the first transflective pattern and etched to obtain a second transflective pattern. The second transflective pattern includes a second transflective layer 9 as shown in FIG. 11 , forming independent first light-emitting units 2 , second light-emitting units 3 and third light-emitting units 4 .

[0158] Subsequently, packaging is performed, and after depositing the reflective film, the packaging structure is rotated and filled on the substrate so that the first light-emitting unit 2, the second light-emitting unit 3 and the third light-emitting unit 4 are all embedded in the packaging structure;

[0159] Finally, the substrate is peeled off, and the first light-emitting unit 2 and other structures without the backing plate are transferred to the base plate 1, thereby completing the entire preparation process of the light-emitting chip.

[0160] In some exemplary embodiments, a display device includes the aforementioned light-emitting chip. The display device provided by the embodiments of the present disclosure can be applied to electronic devices such as mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo frames, navigation systems, and in-vehicle displays. It can also be any product or component with a display function, such as a wearable device, such as a smartwatch, smart bracelet, smart glasses, smart headphones, smart clothing, and head-mounted displays.

[0161] The light-emitting chip in the aforementioned embodiment utilizes a combination of blue, red, and green LEDs, rather than a single LED. A transflective layer filters the required color light, enabling RGB display and creating a full-color solution with enhanced display quality. Furthermore, this light-emitting chip eliminates the need for quantum dots (QDs) to achieve full color, significantly reducing production costs.

[0162] The above-described embodiments merely represent several embodiments of the present disclosure, and the descriptions thereof are relatively specific and detailed. However, the contents described are merely embodiments adopted to facilitate understanding of the present disclosure and are not intended to limit the present disclosure. Any person skilled in the art of the present disclosure may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall still be defined by the appended claims.

Claims

1. A light-emitting chip, wherein: It includes a substrate and a first light emitting unit, a second light emitting unit and a third light emitting unit located on the same side of the substrate; The first light-emitting unit includes a first light-emitting layer disposed on the substrate, and the first light-emitting unit is configured to emit a first color light; The second light-emitting unit includes a second light-emitting layer and a first transflective layer, the second light-emitting layer is arranged on the substrate, the first transflective layer is arranged on a side of the second light-emitting layer away from the substrate, and the first transflective layer is configured to filter out the first color light so that the second light-emitting unit emits the second color light; The third light-emitting unit includes a third light-emitting layer and a second reflective layer, the third light-emitting layer is arranged on the substrate, the second reflective layer is arranged on a side of the third light-emitting layer away from the substrate, and the second reflective layer is configured to filter out the first color light and / or the second color light so that the third light-emitting unit emits a third color light.

2. The light-emitting chip according to claim 1, wherein: The first light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially disposed on the substrate; The second light-emitting layer comprises a first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer sequentially arranged on the substrate, and the first transflective layer is located on a side of the second semiconductor layer away from the substrate; The third light-emitting layer includes a first electrode layer, a first semiconductor layer, and a second electrode layer sequentially arranged on the substrate; the third light-emitting layer is provided with the second semiconductor and third semiconductor layers stacked on a side of the second electrode layer away from the first semiconductor layer, or the third light-emitting layer is provided with a third semiconductor layer on a side of the second electrode layer away from the first semiconductor layer, and the second reflective layer is located on a side of the third semiconductor layer away from the second electrode layer.

3. The light-emitting chip according to claim 2, wherein: The second light-emitting layer further comprises a third electrode layer covering a surface of the second semiconductor layer away from the second electrode layer, in the second light-emitting layer, the first transflective layer covers a surface of the third electrode layer away from the second semiconductor layer, and the third electrode layer is electrically connected to the first electrode layer; The third light-emitting layer also includes a third electrode layer and a fourth electrode layer. In the third light-emitting layer, the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer are arranged in sequence in a direction away from the substrate, the first electrode layer and the third electrode layer are electrically connected, the second electrode layer and the fourth electrode layer are electrically connected, and the second reflective layer covers the surface of the fourth electrode layer away from the third semiconductor layer.

4. The light emitting chip according to claim 3, further comprising a first metal wiring, a second metal wiring and a third metal wiring; The first metal wiring is located at the side of the second light-emitting layer, one end of the first metal wiring is connected to the first electrode layer, and the other end of the first metal wiring is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer and the second semiconductor layer are provided with a first insulating layer on a side facing the first metal wiring; The second metal wiring and the third metal wiring are respectively located on two opposite sides of the third light-emitting layer; In the third light-emitting layer, one end of the second metal routing is connected to the first electrode layer, the other end of the second metal routing is connected to the third electrode layer, and the first semiconductor layer, the second electrode layer, and the second semiconductor layer are provided with a second insulating layer on the side facing the second metal routing; one end of the third metal routing is connected to the second electrode layer, the other end of the third metal routing is connected to the fourth electrode layer, and the second semiconductor layer, the third electrode layer, and the third semiconductor layer are provided with a third insulating layer on the side facing the third metal routing.

5. The light emitting chip according to claim 3, wherein: In the second light-emitting layer, the orthographic projections of the first electrode layer, the first semiconductor layer, the second electrode layer, the second semiconductor layer and the third electrode layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate; In the third light-emitting layer, the orthographic projections of the second semiconductor, the third electrode layer, the third semiconductor layer and the fourth electrode layer on the substrate are all located within the orthographic projection of the second electrode layer on the substrate, and the orthographic projections of the second electrode layer and the first semiconductor layer on the substrate are all located within the orthographic projection of the first electrode layer on the substrate.

6. The light emitting chip according to claim 2, wherein: In the third light-emitting unit, the second semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer, and the third semiconductor layer is arranged to cover a surface of the second semiconductor layer away from the second electrode layer; The second reflective layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective layer is configured as a red-transmitting, blue-blocking, and green-blocking film.

7. The light emitting chip according to claim 2, wherein: In the third light-emitting unit, the third semiconductor layer is arranged to cover a surface of the second electrode layer away from the first semiconductor layer; The second reflective transmissive layer covers the surface of the third semiconductor layer away from the second electrode layer, and the second reflective transmissive layer is configured as a red-transmitting and blue-blocking film.

8. The light-emitting chip according to claim 6 or 7, further comprising a fourth metal wiring and a fifth metal wiring; The second light-emitting layer is arranged on the substrate at intervals from the first light-emitting layer and the third light-emitting layer, respectively; the fourth metal wiring is located between the first light-emitting layer and the third light-emitting layer; and the second electrode layer of the second light-emitting layer is arranged to be electrically connected to the second electrode layer of the first light-emitting layer through the fourth metal wiring; The fifth metal wiring is located between the second light-emitting layer and the third light-emitting layer, and the second electrode layer of the second light-emitting layer is configured to be electrically connected to the second electrode layer of the third light-emitting layer through the fifth metal wiring.

9. The light-emitting chip according to claim 7, wherein the first semiconductor layer comprises a first N-type contact layer, a first quantum well, and a first P-type contact layer arranged in sequence in a direction away from the substrate; The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate; The third semiconductor layer includes a third P-type contact layer, a third quantum well, and a third N-type contact layer which are sequentially arranged in a direction away from the substrate.

10. The light-emitting chip according to any one of claims 2 to 6, wherein: The first semiconductor layer includes a first N-type contact layer, a first quantum well, and a first P-type contact layer which are sequentially arranged in a direction away from the substrate; The second semiconductor layer includes a second P-type contact layer, a second quantum well, and a second N-type contact layer which are sequentially arranged in a direction away from the substrate; The third semiconductor layer includes a third N-type contact layer, a third quantum well, and a third P-type contact layer which are sequentially arranged in a direction away from the substrate.

11. The light-emitting chip according to any one of claims 1 to 7, wherein: The first color light is set to blue light, the second color light is set to green light, and the third color light is set to red light; The first reflective layer is configured as a conductive green light-transmitting film, and the second reflective layer is configured as a conductive red light-transmitting film.

12. The light-emitting chip according to any one of claims 1 to 7, wherein: A reflective film is also included, and the reflective film is configured to at least wrap the sides of the first light emitting unit, the second light emitting unit, and the third light emitting unit. 13 . The light emitting chip according to claim 1 , further comprising a packaging structure, wherein the packaging structure is disposed on the substrate and covers the first light emitting unit, the second light emitting unit and the third light emitting unit.

14. A display device, wherein: The invention comprises a light-emitting chip as claimed in any one of claims 1 to 13.

15. A manufacturing method, applied to the light-emitting chip according to claim 1, wherein: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, a third conductive layer, a third epitaxial layer and a fourth conductive layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third electrode layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer, a third electrode layer, a third semiconductor layer and a fourth electrode layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a first insulating layer, a second insulating layer and a third insulating layer; the first insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting unit; the second insulating layer covers the end faces of the first semiconductor layer, the second semiconductor layer and the second electrode layer facing the second light-emitting layer; The third insulating layer covers the end surface of the second semiconductor layer, the third semiconductor layer and the third electrode layer facing away from the second light-emitting layer; Depositing a metal layer and etching to obtain a metal routing pattern, the metal routing pattern comprising a first metal routing, a second metal routing and a third metal routing, the first metal routing corresponding to the first insulating layer and connecting the third electrode layer and the first electrode layer of the second light-emitting layer; the second metal routing corresponding to the second insulating layer and connecting the third electrode layer and the first electrode layer of the third light-emitting layer; the third metal routing corresponding to the third insulating layer and connecting the fourth electrode layer and the second electrode layer of the third light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

16. A manufacturing method, applied to the light-emitting chip according to claim 1, wherein: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, a second epitaxial layer, and a third epitaxial layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a light-emitting layer pattern from the composite film layer; the light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting layer spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer, a second semiconductor layer and a third semiconductor layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; The fourth insulating layer covers the first electrode layer of the first light-emitting layer and the end surface of the first semiconductor layer facing the second light-emitting layer; the fifth insulating layer covers the first electrode layer of the second light-emitting layer and the end surface of the first semiconductor layer facing the first light-emitting layer; the sixth insulating layer covers the first electrode layer of the second light-emitting layer The seventh insulating layer covers the first electrode layer of the third light-emitting layer and the end surface of the first semiconductor layer facing the second light-emitting layer; Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

17. A manufacturing method, applied to the light-emitting chip according to claim 1, wherein: include: Depositing to form a composite film layer, depositing a first conductive layer, a first epitaxial layer, a second conductive layer, and a second epitaxial layer on the substrate in sequence to obtain a composite film layer; Etching the composite film layer to etch a first light-emitting layer pattern from the composite film layer; the first light-emitting layer pattern includes the first light-emitting layer, the second light-emitting layer and the third light-emitting blank layer which are spaced apart from each other, the first light-emitting layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; the second light-emitting layer includes a stacked first electrode layer, a first semiconductor layer, a second electrode layer and a second semiconductor layer; the third light-emitting blank layer includes a stacked first electrode layer, a first semiconductor layer and a second electrode layer; Depositing a third epitaxial layer on the first light-emitting layer pattern and etching to obtain a second light-emitting layer pattern; the second light-emitting layer pattern includes a third semiconductor layer, and the first electrode layer, the first semiconductor layer, the second electrode layer and the third semiconductor layer constitute the third light-emitting layer; Depositing an insulating film and etching to obtain an insulating layer pattern, wherein the insulating layer pattern includes a fourth insulating layer, a fifth insulating layer, a sixth insulating layer and a seventh insulating layer; The fourth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the first light-emitting layer facing the second light-emitting layer, and the fifth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the first light-emitting layer; the sixth insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the second light-emitting layer facing the third light-emitting layer, and the seventh insulating layer covers the end surface of the first electrode layer and the first semiconductor layer of the third light-emitting layer facing the second light-emitting layer; Depositing a metal layer and etching to obtain a metal wiring pattern, wherein the metal wiring pattern includes a fourth metal wiring and a fifth metal wiring, wherein the fourth metal wiring connects the first light-emitting layer and the second electrode layer of the second light-emitting layer; and the fifth metal wiring connects the third light-emitting layer and the second electrode layer of the second light-emitting layer; Depositing a first transflective film on the metal wiring pattern and etching to obtain a first transflective pattern, wherein the first transflective pattern includes a first transflective layer; Depositing a first transflective film on the first transflective pattern and etching to obtain a second transflective pattern, wherein the second transflective pattern includes a second transflective layer to form the first light-emitting unit, the second light-emitting unit and the third light-emitting unit independently; Performing packaging, rotating and filling the packaging structure on the substrate, so that the first light-emitting unit, the second light-emitting unit and the third light-emitting unit are all embedded in the packaging structure; The substrate is peeled off and transferred to the base plate.

Images