Control system hardware resource optimization method and apparatus

Abstract

A control system hardware resource optimization method and apparatus, relating to the technical field of simulation systems. The method comprises: dividing a system to be simulated into an electrical system and a control system, and on the basis of the topological structure and the computing type of the control system, constructing a control system solution hardware resource optimization model in which the minimum weighted sum of a control system solution computing resource, a storage resource and a time resource is used as an objective function; solving the control system solution hardware resource optimization model to output a hardware resource optimization result; and downloading the hardware resource optimization result to an FPGA real-time simulator for simulation. The technical problems in the prior art of long hardware debugging time and low efficiency caused by manual design of hardware in the simulation preparation process are solved.

Description

A control system hardware resource optimization method and device

[0001] This application claims priority to the Chinese patent application filed with the China Patent Office on October 27, 2023, with application number 202311407999.7 and invention name “A method and device for optimizing hardware resources of a control system”, the entire contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the technical field of simulation systems, and in particular to a method and device for optimizing control system hardware resources. Background Art

[0003] With the proposed "dual carbon" goals and in line with new economic and technological trends, electricity has become the main force in the energy battleground, with renewable energy generation at the vanguard. The randomness and volatility of wind and solar power generation have altered the structure and operation of power systems connected to renewable energy sources, posing significant challenges to the grid's robustness, security, economics, and institutional mechanisms. The widespread integration of renewable energy sources has led to a high proportion of power electronics in power systems. In this context, electromagnetic transient simulation technology provides a powerful means of studying the dynamic characteristics and underlying mechanisms of systems, becoming a crucial research tool in the development of new power systems. Due to the large power electronic converters and complex controllers of renewable energy sources, their electromagnetic transient models are typically extremely large. These models are generally divided into two parts: the electrical system model and the control system model. Transient modeling of renewable energy sources primarily focuses on the controller model. This results in control system models of hundreds of dimensions, while the electrical system model typically has tens of dimensions. To meet practical engineering requirements, high-precision, real-time transient simulations of the fast dynamic response characteristics of high-frequency power electronic commutation equipment typically require microsecond simulation steps and be completed in the shortest possible time. This requires high-efficiency simulation technology. Due to limited room for improvement in simulation algorithms and the constraints of limited CPU resources and frequency, practical projects often require heterogeneous, efficient parallel computing resources such as GPUs and FPGAs in conjunction with a CPU host computer to achieve simulation efficiency.

[0004] Due to the large control systems of renewable power sources and the fact that control system models are typically solved sequentially, solving these systems typically consumes 60%-80% of computing resources, resulting in low resource utilization efficiency. This represents an unacceptable computational resource overhead for mechanistic modeling simulations of renewable power clusters. Limited parallel computing resources in engineering projects require efficient hardware design to maximize resource utilization and meet the microsecond-level simulation speed requirements of large-scale renewable power generation. Time-division multiplexing (TDM) is a hardware design technique commonly used in digital communications to ensure efficient hardware resource utilization. TDM interweaves different data streams within different time periods, allowing multiple data streams that would otherwise utilize multiple hardware resources to utilize the same hardware resource at different times, significantly improving hardware resource utilization. TDM can effectively improve computational efficiency in transient control system simulation scenarios with limited computational complexity and a relatively small number of simulation types.

[0005] When it comes to large-scale simulations of renewable energy stations, system design for highly flexible parallel computing resources is extremely complex. During simulation preparation, control system simulation design often uses a "building blocks" approach, with manual hardware design. This often requires a long time of hardware debugging to achieve the desired simulation results when faced with simulation objects with complex controllers, such as renewable power sources. Manual time-division multiplexing of existing pipeline control system solution structures is undoubtedly even more difficult, and once the number of pipeline subsystems changes, the original time-division multiplexing design will cause data flow conflicts, requiring a new time-division multiplexing design.

[0006] Summary of the Invention

[0007] The present application provides a control system hardware resource optimization method and device for improving the technical problems of long hardware debugging time and low efficiency in the existing technology using manual hardware design during simulation preparation.

[0008] In view of this, a first aspect of the present application provides a control system hardware resource optimization method, comprising:

[0009] The system to be simulated is divided into an electrical system and a control system. Based on the topological structure and calculation type of the control system, a control system hardware resource optimization model is constructed with the objective function of minimizing the weighted sum of the control system solution computing resources, storage resources, and time resources.

[0010] Solving the hardware resource optimization model of the control system and outputting the hardware resource optimization result;

[0011] The hardware resource optimization result is downloaded to the FPGA real-time simulator for simulation.

[0012] Optionally, the step of constructing a control system hardware resource optimization model based on the topological structure and calculation type of the control system, with the objective function being to minimize the weighted sum of the control system's computing resources, storage resources, and time resources, includes:

[0013] According to the topological structure of the control system, the first intermediate node from the i-th computing node to the j-th computing node is numbered as R ij , Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m type of calculations performed a total of N m The flag that defines whether the result of the jth calculation of the mth type calculation is used as the input of the i-th calculation of the lth type calculation is

[0014] Initialize node R according to the dependency relationship and calculation type of each computing node in the topology of the control system ij , distance D ij And the flag

[0015] An objective function is constructed with the minimum weighted sum of control system solution computing resources, storage resources and time resources, and time series constraints on the control system calculation data flow and control system solution computing resource usage constraints are set to obtain a control system solution hardware resource optimization model.

[0016] Optionally, the objective function is: min f = w1A ctr +w2B ctr +pT p ;

[0017] Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computational and storage resource overheads of the control system solution, A ctr represents the computational resource overhead caused by the control system solution, Bctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, Indicates the computational resource overhead caused by data buffering in the control system solution, M indicates the total type of computation in the control system solution, Indicates that the control system solution uses computing units of the mth type, Indicates the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l Indicates the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth category and the ith calculation of the lth category. ms,ini A represents the computational resource overhead of the multiplexer when there is 0 input. ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses The first type of computing unit.

[0018] Optionally, the time series constraints for calculating the data flow of the control system include:

[0019] Where, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth category is used as the input of the i-th calculation of the lth category. A flag indicating whether the result of the i-th calculation of the l-th category calculation is used as the input of the k-th calculation of the o-th category calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Indicates the actual time elapsed by a single clock cycle, It indicates that the output of the jth computation of the mth category is delayed by the data stream that is used as input by the ith computation of the lth category, and C is a large number introduced to linearize the constraint;

[0020] The control system solves the computing resource usage constraints including:

[0021] Where, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has completed the calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Indicates the number of subsystems solved by the control system.

[0022] Optionally, the specific process of obtaining the shortest solution time cost of the control system based on the topological structure of the control system is:

[0023] generating a distance matrix according to the distances between computing nodes in the topological structure of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of another computing node from one computing node;

[0024] Generate a routing matrix based on the topology structure and the number of the first intermediate node between two computing nodes;

[0025] Determine the distance D between computing node i and computing node j ij The sum of the distances D from computing node i to intermediate node k and from intermediate node k to computing node j ik +D kj The size of D ik +D kj Greater than D ij, then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to R ij =R ik , until all intermediate nodes are traversed;

[0026] Get the maximum distance in the final distance matrix, calculate the product of the maximum distance and the actual time elapsed by a single clock cycle, and get the shortest solution time T of the control system min .

[0027] A second aspect of the present application provides a control system hardware resource optimization device, comprising:

[0028] A model building unit is used to divide the system to be simulated into an electrical system and a control system, and to build a control system solution hardware resource optimization model based on the topological structure and calculation type of the control system, with the objective function of minimizing the weighted sum of the control system solution computing resources, storage resources and time resources;

[0029] A model solving unit, configured to solve a hardware resource optimization model for the control system and output a hardware resource optimization result;

[0030] The simulation unit is used to download the hardware resource optimization result to the FPGA real-time simulator for simulation.

[0031] Optionally, the model building unit is specifically used to:

[0032] Divide the system to be simulated into electrical system and control system;

[0033] According to the topological structure of the control system, the first intermediate node from the i-th computing node to the j-th computing node is numbered as R ij , Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m type of calculations performed a total of N m The flag that defines whether the result of the jth calculation of the mth type calculation is used as the input of the i-th calculation of the lth type calculation is

[0034] Initialize node R according to the dependency relationship and calculation type of each computing node in the topology of the control system ij , distance D ij And the flag

[0035] An objective function is constructed with the minimum weighted sum of control system solution computing resources, storage resources and time resources, and time series constraints on the control system calculation data flow and control system solution computing resource usage constraints are set to obtain a control system solution hardware resource optimization model.

[0036] Optionally, the objective function is: min f = w1A ctr +w2B ctr +pT p ;

[0037] Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computational and storage resource overheads of the control system solution, A ctr represents the computational resource overhead caused by the control system solution, B ctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, Indicates the computational resource overhead caused by data buffering in the control system solution, M indicates the total type of computation in the control system solution, Indicates that the control system solution uses computing units of the mth type, Indicates the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l Indicates the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth category and the ith calculation of the lth category. ms,iniA represents the computational resource overhead of the multiplexer when there is 0 input. ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses The first type of computing unit.

[0038] Optionally, the time series constraints for calculating the data flow of the control system include:

[0039] Where, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth category is used as the input of the i-th calculation of the lth category. A flag indicating whether the result of the i-th calculation of the l-th category calculation is used as the input of the k-th calculation of the o-th category calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Indicates the actual time elapsed by a single clock cycle, It indicates that the output of the jth computation of the mth category is delayed by the data stream that is used as input by the ith computation of the lth category, and C is a large number introduced to linearize the constraint;

[0040] The control system solves the computing resource usage constraints including:

[0041] Where, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has completed the calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Indicates the number of subsystems solved by the control system.

[0042] Optionally, the specific process of obtaining the shortest solution time cost of the control system based on the topological structure of the control system is:

[0043] generating a distance matrix according to the distances between computing nodes in the topological structure of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of another computing node from one computing node;

[0044] Generate a routing matrix based on the topology structure and the number of the first intermediate node between two computing nodes;

[0045] Determine the distance D between computing node i and computing node j ij The sum of the distances D from computing node i to intermediate node k and from intermediate node k to computing node j ik +D kj The size of D ik +D kj Greater than D ij , then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to R ij =R ik , until all intermediate nodes are traversed;

[0046] Get the maximum distance in the final distance matrix, calculate the product of the maximum distance and the actual time elapsed by a single clock cycle, and get the shortest solution time T of the control system min .

[0047] It can be seen from the above technical solutions that this application has the following advantages:

[0048] The present application provides a control system hardware resource optimization method, comprising: dividing the system to be simulated into an electrical system and a control system, constructing a control system solution hardware resource optimization model based on the topological structure and calculation type of the control system, with the objective function being to minimize the weighted sum of the control system solution computing resources, storage resources, and time resources; solving the control system solution hardware resource optimization model and outputting the hardware resource optimization results; and downloading the hardware resource optimization results to an FPGA real-time simulator for simulation.

[0049] In this application, a control system hardware resource optimization model is constructed based on the topological structure and calculation type of the control system, with the objective function of minimizing the weighted sum of the control system's computing resources, storage resources and time resources. The hardware design of the entire control system is planned using the hardware resource optimization results obtained through the optimization model, thereby obtaining a hardware design solution with minimal resource overhead. This improves the technical problems of long hardware debugging time and low efficiency in the existing technology that uses manual hardware design during simulation preparation. BRIEF DESCRIPTION OF THE DRAWINGS

[0050] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0051] FIG1 is a flow chart of a method for optimizing hardware resources of a control system provided by an embodiment of the present application;

[0052] FIG2 is a schematic diagram of the structure of a permanent magnet direct-drive wind turbine cluster provided in an embodiment of the present application;

[0053] FIG3 is a schematic structural diagram of a permanent magnet direct-drive wind turbine control system provided in an embodiment of the present application;

[0054] FIG4 is a schematic diagram of a process for obtaining the shortest solution time of a control system according to an embodiment of the present application;

[0055] FIG5 is a schematic diagram of the overall architecture of the FPGA real-time simulator provided in an embodiment of the present application;

[0056] FIG6 is a structural diagram of a control system hardware resource optimization device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0057] In order to help those skilled in the art better understand the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of this application.

[0058] For ease of understanding, please refer to FIG1 . An embodiment of the present application provides a method for optimizing control system hardware resources, including:

[0059] Step 101: Divide the system to be simulated into an electrical system and a control system, and construct a control system solution hardware resource optimization model based on the topological structure and calculation type of the control system, with the objective function of minimizing the weighted sum of the control system solution computing resources, storage resources and time resources.

[0060] The system to be simulated is divided into electrical system and control system according to its function and structure. Based on the topological structure and calculation type of the control system, a control system hardware resource optimization model is constructed with the objective function of minimizing the weighted sum of the control system computing resources, storage resources and time resources. The specific construction process of the control system hardware resource optimization model can be as follows:

[0061] S1. According to the topological structure of the control system, the number of the first intermediate node from the i-th computing node to the j-th computing node is defined as R ij , Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m type of calculations performed a total of N m The flag that defines whether the result of the jth calculation of the mth type calculation is used as the input of the i-th calculation of the lth type calculation is

[0062] When the method in the embodiment of the present application is applied to the electromagnetic transient simulation FPGA accelerator, the permanent magnet direct-drive wind power cluster algorithm is shown in Figure 2, wherein the direct-drive permanent magnet synchronous wind turbine control system structure is shown in Figure 3, which consists of an aerodynamic system, a permanent magnet synchronous generator, a back-to-back converter and related controllers. Among them, the mathematical model of the aerodynamic system is used to describe the process of converting wind energy into wind turbine power output, and variable pitch control is used to ensure operation at maximum wind energy conversion efficiency; the permanent magnet synchronous generator part converts the motor model into the form of a transfer function to express the mathematical relationship of the model, and finally connects it to other electrical parts of the system in the form of a controlled current source to complete the modeling in the control system; the back-to-back converter is modeled using the converter switch function model of the power electronic switch, and the controller of the back-to-back converter consists of two parts: the machine-side converter controller and the grid-side converter controller.

[0063] S2. Initialize node R according to the dependencies and calculation types of each computing node in the topology of the control system. ij , distance D ij And the flag

[0064] S3. Construct an objective function with the minimum weighted sum of the control system solution computing resources, storage resources and time resources, and set the time series constraints of the control system calculation data flow and the control system solution computing resource usage constraints to obtain the control system solution hardware resource optimization model.

[0065] The objective function is: min f = w1A ctr +w2B ctr +pT p ;

[0066] Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computational and storage resource overheads of the control system solution, A ctr represents the computational resource overhead caused by the control system solution, B ctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, Indicates the computational resource overhead caused by data buffering in the control system solution, M indicates the total type of computation in the control system solution, Indicates that the control system solution uses computing units of the mth type, Indicates the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l Indicates the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth category and the ith calculation of the lth category. ms,ini A represents the computational resource overhead of the multiplexer when there is 0 input.ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses The first type of computing unit.

[0067] The time series constraints of the control system calculation data flow include:

[0068] Where, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth category is used as the input of the i-th calculation of the lth category. A flag indicating whether the result of the i-th calculation of the l-th category calculation is used as the input of the k-th calculation of the o-th category calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, which can be obtained by the Floyd algorithm based on the topology of the control system; T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Indicates the actual time elapsed by a single clock cycle, It indicates that the output of the jth computation of the mth category is delayed by the data stream that is used as input by the ith computation of the lth category, and C is a large number introduced to linearize the constraint;

[0069] The constraints on the use of computing resources for control system solution include:

[0070] Where, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has completed the calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Indicates the number of subsystems solved by the control system.

[0071] Furthermore, the specific process of obtaining the shortest solution time cost of the control system based on the topology of the control system is as follows:

[0072] (1) Constructing the distance matrix D of the control system topology: Generate a distance matrix based on the distances between computing nodes in the control system topology, where the distance between two computing nodes is the time cost of obtaining the computation result from one computing node to another.

[0073] Assume that the topology of the control system has H computing nodes. The time cost of obtaining the computation result of one computing node from another computing node is regarded as the directed distance between the two computing nodes. Then, the directed distance between each two computing nodes in the topology can form an H-order distance matrix D:

[0074] Among them, D ij The initial value of is the time from computing node i to computing node j directly, i, j = 1, 2, ..., H. If it is not directly reachable, it is recorded as negative infinity.

[0075] (2) Constructing the routing matrix R of the control system topology: Generate the routing matrix based on the topology structure and the number of the first intermediate node between the two computing nodes;

[0076] In the topology of the control system, the number of the first intermediate node from one computing node to another computing node can form an H-order routing matrix R:

[0077] (3) Traverse all intermediate nodes, update the distance matrix D and routing matrix R, and complete the search for the shortest solution time:

[0078] Determine the distance D between computing node i and computing node j ij The sum of the distances D from computing node i to intermediate node k and from intermediate node k to computing node j ik +D kj The size of D ik +D kj Greater than D ij , then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to Rij =R ik , until all intermediate nodes are traversed. The specific process can be referred to Figure 4;

[0079] Get the maximum distance in the final distance matrix and calculate the maximum distance and the actual time v elapsed in a single clock cycle c The product of the shortest solution time T of the control system is obtained. min .

[0080] Step 102: Solve the hardware resource optimization model of the control system and output the hardware resource optimization result.

[0081] A linear programming method is used to solve the control system hardware resource optimization model established in step 101, and the hardware resource optimization results are output, including: the number of computing units used in the control system solution, the start time and end time of each calculation in the control system solution, and the computing unit number used.

[0082] Step 103: Download the hardware resource optimization result to the FPGA real-time simulator for simulation.

[0083] The calculated hardware resource optimization results are downloaded to the FPGA real-time simulator, and the FPGA real-time simulator is started for simulation. A schematic diagram of the overall architecture of the FPGA real-time simulator can be found in Figure 5. In this application, a control system hardware resource optimization model is constructed based on the control system's topology and calculation type, with the objective function being to minimize the weighted sum of the control system's computing resources, storage resources, and time resources. The hardware design of the entire control system is planned using the hardware resource optimization results obtained by the optimization model, thereby obtaining a hardware design solution with minimal resource overhead. This improves the technical issues of long hardware debugging time and low efficiency that exist in the prior art of manually designing hardware during simulation preparation.

[0084] This embodiment of the application uses Altera's Stratix V series FPGA EP5SGSMD5K2F40C2 and its accompanying development board as the simulation platform. The real-time simulation system is driven by a 125MHz clock. The simulation step size is set to 9μs. For the permanent magnet direct-drive wind turbine cluster calculation example, the resource overhead of the general optimization design and the conventional design are shown in Table 1. Comparing resource overhead, the general optimization design significantly reduces computing resource overhead compared to the conventional design, demonstrating the effectiveness of the real-time simulation system designed in this embodiment of the application.

[0085] Table 1 Comparison of control system resource overhead

[0086] The embodiments of the present application aim to improve the utilization efficiency of computing resources and hardware design issues in complex control system simulation. For any control system topology, the control system topology can be analyzed through a program to obtain the shortest solution time of the entire control system; based on time division multiplexing technology, the hardware design of the entire control system is planned using a linear programming method, thereby obtaining a hardware design solution with minimal resource overhead; and the hardware design code of the control system is automatically obtained based on this solution through a program, which is a new general solution to the hardware design of real-time simulation of pipeline control systems.

[0087] The above is an embodiment of a control system hardware resource optimization method provided by the present application, and the following is an embodiment of a control system hardware resource optimization device provided by the present application.

[0088] Referring to FIG6 , an embodiment of the present application provides a control system hardware resource optimization device, including:

[0089] A model building unit is used to divide the system to be simulated into an electrical system and a control system, and to build a control system solution hardware resource optimization model based on the topological structure and calculation type of the control system, with the objective function being to minimize the weighted sum of the control system solution computing resources, storage resources, and time resources;

[0090] A model solving unit is used to solve the hardware resource optimization model of the control system and output the hardware resource optimization results;

[0091] The simulation unit is used to download the hardware resource optimization results to the FPGA real-time simulator for simulation.

[0092] As a further improvement, the model building unit is specifically used to:

[0093] Divide the system to be simulated into electrical system and control system;

[0094] According to the topological structure of the control system, the number of the first intermediate node from the i-th computing node to the j-th computing node is defined as Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m type of calculations performed a total of N m The flag that defines whether the result of the jth calculation of the mth type calculation is used as the input of the i-th calculation of the lth type calculation is

[0095] Initialize node R according to the dependency relationship and calculation type of each computing node in the topology of the control system ij , distance Dij And the flag

[0096] An objective function is constructed with the minimum weighted sum of control system solution computing resources, storage resources and time resources, and time series constraints on the control system calculation data flow and control system solution computing resource usage constraints are set to obtain a control system solution hardware resource optimization model.

[0097] As a further improvement, the objective function is: min f=w1A ctr +w2B ctr +pT p ;

[0098] Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computational and storage resource overheads of the control system solution, A ctr represents the computational resource overhead caused by the control system solution, B ctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, Indicates the computational resource overhead caused by data buffering in the control system solution, M indicates the total type of computation in the control system solution, Indicates that the control system solution uses computing units of the mth type, Indicates the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l Indicates the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth category and the ith calculation of the lth category. ms,ini A represents the computational resource overhead of the multiplexer when there is 0 input. ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses The first type of computing unit.

[0099] As a further improvement, the time series constraints of the control system calculation data flow include:

[0100] Where, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth category is used as the input of the i-th calculation of the lth category. A flag indicating whether the result of the i-th calculation of the l-th category calculation is used as the input of the k-th calculation of the o-th category calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Indicates the actual time elapsed by a single clock cycle, It indicates that the output of the jth computation of the mth category is delayed by the data stream that is used as input by the ith computation of the lth category, and C is a large number introduced to linearize the constraint;

[0101] The constraints on the use of computing resources for control system solution include:

[0102] Where, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has completed the calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Indicates the number of subsystems solved by the control system.

[0103] As a further improvement, the specific process of obtaining the shortest solution time cost of the control system based on the topology of the control system is as follows:

[0104] Generate a distance matrix according to the distances between computing nodes in the topology of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of another computing node from one computing node;

[0105] Generate a routing matrix based on the topology structure and the number of the first intermediate node between two computing nodes;

[0106] Determine the distance D between computing node i and computing node j ij The sum of the distances D from computing node i to intermediate node k and from intermediate node k to computing node j ik +D kj The size of D ik +D kj Greater than D ij , then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to R ij =R ik , until all intermediate nodes are traversed;

[0107] Get the maximum distance in the final distance matrix, calculate the product of the maximum distance and the actual time elapsed in a single clock cycle, and get the shortest solution time T of the control system min .

[0108] Those skilled in the art will clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0109] The terms "first", "second", "third", "fourth", etc. (if any) in the specification of the present application and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can, for example, be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0110] It should be understood that in this application, "at least one (item)" means one or more, and "plurality" means two or more. "And / or" is used to describe the association relationship of associated objects, indicating that three relationships may exist. For example, "A and / or B" can mean: only A exists, only B exists, and A and B exist at the same time, where A and B can be singular or plural. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. "At least one of the following items" or similar expressions refers to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b or c can mean: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, c can be single or multiple.

[0111] In the several embodiments provided in this application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are merely schematic. For example, the division of the units is merely a logical function division. In actual implementation, there may be other division methods, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0112] The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed across multiple network units. Some or all of these units may be selected to achieve the purpose of this embodiment according to actual needs.

[0113] In addition, the functional units in the various embodiments of the present application may be integrated into a single processing unit, or each unit may exist physically separately, or two or more units may be integrated into a single unit. The aforementioned integrated units may be implemented in the form of hardware or software functional units.

[0114] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for executing all or part of the steps of the method described in each embodiment of the present application through a computer device (which can be a personal computer, server, or network device, etc.). The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (English full name: Read-Only Memory, English abbreviation: ROM), random access memory (English full name: Random Access Memory, English abbreviation: RAM), disk or optical disk and other media that can store program code.

[0115] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A control system hardware resource optimization method, characterized in that: include: The system to be simulated is divided into an electrical system and a control system, and a control system solution hardware resource optimization model is constructed according to the topological structure and calculation type of the control system, with the objective function being the minimum weighted sum of control system solution computing resources, storage resources and time resources; Solving the hardware resource optimization model for the control system and outputting hardware resource optimization results; The hardware resource optimization result is downloaded to the FPGA real-time simulator for simulation.

2. The control system hardware resource optimization method according to claim 1, characterized in that: The control system hardware resource optimization model is constructed according to the topological structure and calculation type of the control system, with the weighted minimum of the control system computing resources, storage resources and time resources as the objective function, including: According to the topological structure of the control system, the number of the first intermediate node from the i-th computing node to the j-th computing node is defined as Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m-th type of calculations performed a total of N m The flag bit that defines whether the result of the jth calculation of the mth type of calculation is used as the input of the ith calculation of the lth type of calculation is Initialize node R according to the front-to-back dependency relationship and calculation type of each computing node in the topological structure of the control system ij , distance D ij And the flag An objective function is constructed with the minimum weighted sum of the control system solution computing resources, storage resources and time resources as the objective function, and the time series constraints of the control system calculation data flow and the control system solution computing resource usage constraints are set to obtain the control system solution hardware resource optimization model.

3. The control system hardware resource optimization method according to claim 2, characterized in that: The objective function is: min f = w1A ctr +w2B ctr +pT p ; Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computing and storage resource overhead caused by the control system solution, A ctr represents the computational resource overhead caused by the control system solution, B ctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, represents the computational resource overhead caused by data buffering in the control system solution, M represents the total type of calculation in the control system solution, Indicates that the control system solution uses There are m-th type of computing units, represents the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l represents the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth type of calculation and the ith calculation of the lth type of calculation. ms,ini A represents the computational resource overhead of the multiplexer when the input is 0. ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses A computing unit of the first type.

4. The control system hardware resource optimization method according to claim 3, characterized in that: The time series constraints of the control system calculation data flow include: In the formula, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth type of calculation is used as the input of the ith calculation of the lth type of calculation. Represents the first category The flag indicating whether the result of the ith calculation is used as the input of the kth calculation of the oth type calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is used as the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Represents the actual time elapsed by a single clock cycle, It means that the output result of the jth calculation of the mth type of calculation is delayed by the data stream that the ith calculation of the lth type of calculation takes as input, and C is a large number introduced to linearize the constraint; The control system solves the computing resource usage constraints including: In the formula, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has finished calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Represents the number of subsystems solved for the control system.

5. The control system hardware resource optimization method according to claim 4, characterized in that: The specific process of obtaining the shortest solution time cost of the control system based on the topological structure of the control system is: Generate a distance matrix according to the distances between computing nodes in the topological structure of the control system, wherein the distance between two computing nodes is the time cost of obtaining the computing result of another computing node from one computing node; Generate a routing matrix according to the topology structure and the number of the first intermediate node between two computing nodes; Determine the distance D from computing node i to computing node j ij With computing node i to intermediate node k and intermediate node k to Calculate the sum of distances D of node j ik +D kj If D ik +D kj Greater than D ij , then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to R ij =R ik , until all intermediate nodes are traversed; Get the maximum distance in the final distance matrix, calculate the product of the maximum distance and the actual time elapsed by a single clock cycle, and get the shortest solution time T of the control system min .

6. A control system hardware resource optimization device, characterized in that: include: A model building unit, used for dividing the system to be simulated into an electrical system and a control system, and building a control system solution hardware resource optimization model with the objective function of minimizing the weighted sum of control system solution computing resources, storage resources and time resources according to the topological structure and calculation type of the control system; A model solving unit, used to solve the hardware resource optimization model of the control system and output a hardware resource optimization result; The simulation unit is used to download the hardware resource optimization result to the FPGA real-time simulator for simulation.

7. The control system hardware resource optimization device according to claim 6, characterized in that: The model building unit is specifically used for: Divide the system to be simulated into electrical system and control system; According to the topological structure of the control system, the number of the first intermediate node from the i-th computing node to the j-th computing node is defined as Define the distance from the i-th computing node to the j-th computing node as D ij , define the control system to perform M types of calculations, the control system m-th type of calculations performed a total of N m The flag bit that defines whether the result of the jth calculation of the mth type of calculation is used as the input of the ith calculation of the lth type of calculation is Initialize node R according to the front-to-back dependency relationship and calculation type of each computing node in the topological structure of the control system ij , distance D ij And the flag An objective function is constructed with the minimum weighted sum of the control system solution computing resources, storage resources and time resources as the objective function, and the time series constraints of the control system calculation data flow and the control system solution computing resource usage constraints are set to obtain the control system solution hardware resource optimization model.

8. The control system hardware resource optimization device according to claim 7, characterized in that: The objective function is: min f = w1A ctr +w2B ctr +pT p ; Where f represents the objective function, w1 and w2 are the weighted coefficients of the computing resources and storage resources overhead caused by the control system solution, p is the penalty coefficient of the additional solution time overhead of the control system, and T p represents the additional solution time overhead of the control system, represents the computing and storage resource overhead caused by the control system solution, A ctr represents the computational resource overhead caused by the control system solution, B ctr represents the storage resource overhead caused by the control system solution, represents the computational resource overhead caused by the multiplexer used in the time-division multiplexing solution of the control system, represents the computational resource overhead caused by data buffering in the control system solution, M represents the total type of calculation in the control system solution, Indicates that the control system solution uses There are m-th type of computing units, represents the computing resource overhead caused by the computing unit used for the mth type of calculation, represents the storage resource overhead caused by data buffering in the control system solution, A represents the storage resource overhead caused by the computing unit used for the mth type of calculation. db,ALM represents the computing resource overhead caused by a single data delay, B db,BMB Represents the storage resource overhead caused by a single data delay, N m Indicates the number of times the control system solves the mth calculation type, N l represents the number of times the control system solves the calculation using the lth type, A flag indicating whether there is a data flow delay between the jth calculation of the mth type of calculation and the ith calculation of the lth type of calculation. ms,ini A represents the computational resource overhead of the multiplexer when the input is 0. ms,com The parameter representing the computational resource overhead of the multiplexer as the number of inputs increases, Indicates that the control system solution uses A computing unit of the first type.

9. The control system hardware resource optimization device according to claim 8, characterized in that: The time series constraints of the control system calculation data flow include: In the formula, represents the starting clock cycle of the ith calculation of the lth type of calculation, A flag indicating whether the result of the jth calculation of the mth type of calculation is used as the input of the ith calculation of the lth type of calculation. A flag indicating whether the result of the ith calculation of the lth category calculation is used as the input of the kth calculation of the oth category calculation. Indicates the end clock cycle of the jth calculation of the mth type of calculation whose output result is used as the input of the ith calculation of the lth type of calculation, represents the calculation output delay of the lth type of calculation, Indicates that the input of the o-th type of calculation is the starting clock cycle of the k-th calculation output result, is the time cost of solving the control system, T min represents the shortest time cost of solving the control system based on the topology of the control system, T p represents the additional solution time overhead caused by the control system solution in addition to the shortest solution time, v c Represents the actual time elapsed by a single clock cycle, It means that the output result of the jth calculation of the mth type of calculation is delayed by the data stream that the ith calculation of the lth type of calculation takes as input, and C is a large number introduced to linearize the constraint; The control system solves the computing resource usage constraints including: In the formula, A flag indicating whether the i-th calculation of the l-th type of calculation starts at the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation has finished calculation in the v-th clock cycle. A flag indicating whether the i-th calculation of the l-th type of calculation is calculated in the v-th clock cycle, n s Represents the number of subsystems solved for the control system.

10. The control system hardware resource optimization device according to claim 9, characterized in that: The specific process of obtaining the shortest solution time cost of the control system based on the topological structure of the control system is: A distance matrix is ​​generated based on the distances between the calculated nodes in the topological structure of the control system, where two The distance between computing nodes is the time cost of obtaining the computing result from one computing node to another computing node; Generate a routing matrix according to the topology structure and the number of the first intermediate node between two computing nodes; Determine the distance D from computing node i to computing node j ij The sum of the distances from computing node i to intermediate node k and from intermediate node k to computing node j D ik +D kj If D ik +D kj Greater than D ij , then update D ij =D ik +D kj , get the updated distance matrix, and update the first intermediate node from computing node i to computing node j to R ij =R ik , until all intermediate nodes are traversed; Get the maximum distance in the final distance matrix, calculate the product of the maximum distance and the actual time elapsed by a single clock cycle, and get the shortest solution time T of the control system min .

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