Data processing chip and manufacturing method therefor, and data processing system

Abstract

Provided in the present disclosure are a data processing chip and a manufacturing method therefor, and a data processing system. The data processing chip comprises a first wafer, a first die and a heat dissipation structure, wherein the first wafer comprises an arithmetic unit, which is located in a first region of the first wafer; the first die is located above the first region of the first wafer, and comprises a cache, which is coupled to the arithmetic unit by means of bonding, and the cache is configured to cache transmitted data when the arithmetic unit performs data transmission with a host or the arithmetic unit performs data transmission with a memory; and the heat dissipation structure is located above a second region of the first wafer, the second region being different from the first region.

Description

Data processing chip and manufacturing method thereof, and data processing system

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is based on the Chinese patent application with application number 202311411634.1 and application date October 27, 2023, and claims the priority of the Chinese patent application. The entire content of the Chinese patent application is hereby introduced into this application as a reference. Technical Field

[0003] The present disclosure relates to the field of data processing technology, and in particular to a data processing chip and a manufacturing method thereof, and a data processing system. Background Art

[0004] With the development of science and technology, more and more fields, such as artificial intelligence and secure computing, involve large amounts of data processing (i.e., big data processing). Big data processing will generate frequent and large-scale data exchanges between processors and memory, which requires memory with higher bandwidth and better heat dissipation performance.

[0005] However, in conventional architecture designs, memory bandwidth is limited and the chip's heat dissipation performance is poor.

[0006] Summary of the Invention

[0007] The present disclosure provides a data processing chip and a manufacturing method thereof, and a data processing system.

[0008] A first aspect of the present disclosure provides a data processing chip. The data processing chip includes:

[0009] A first wafer comprises: an arithmetic unit; wherein the arithmetic unit is located in a first region of the first wafer;

[0010] A first die is located on the first region and includes a buffer coupled to the computing unit via bonding; wherein the buffer is configured to cache the transmitted data when the computing unit is transmitting data to a host or when the computing unit is transmitting data to a memory;

[0011] The heat dissipation structure is located on the second area of ​​the first wafer; wherein the second area is different from the first area.

[0012] A second aspect of the present disclosure provides a method for manufacturing a data processing chip. The manufacturing method comprises:

[0013] Providing a first wafer; wherein the first wafer includes an arithmetic unit; the arithmetic unit is located in a first region of the first wafer;

[0014] forming a first die on the first region; wherein the first die includes a buffer coupled to the arithmetic unit by bonding; the buffer being configured to: cache the transmitted data when the arithmetic unit is transmitting data to a host or to a memory;

[0015] A heat dissipation structure is formed on a second region of the first wafer; wherein the second region is different from the first region.

[0016] A third aspect of the present disclosure provides a data processing system. The data processing system includes:

[0017] substrate;

[0018] The data processing chip provided in the first aspect is located on the substrate;

[0019] At least one of the memories is located on the substrate and is arranged in parallel with the first wafer along a first direction, where the first direction is perpendicular to a direction in which the first die and the first wafer are stacked.

[0020] In the present disclosure, on the one hand, by setting a first die and a first wafer stack, the cache and the operator can be coupled by chip-on-wafer bonding (CoW), thereby providing higher bandwidth for data transmission, achieving high computing power while reducing the bandwidth requirements of the system, and having good adaptability and applicable to different products; on the other hand, compared with setting an on-chip cache, the present disclosure sets the first die outside the first wafer (i.e., off-chip), and the cache in the first die is configured to cache data, which is beneficial to reducing the design complexity of the on-chip system and reducing the design and production costs of the data processing chip; on the third hand, the first die and the first wafer are bonded by the CoW process, and a heat dissipation structure can be set on the second area of ​​the first wafer to rationally utilize the space of the data processing chip and improve space utilization, and the heat dissipation structure can dissipate heat in a timely and effective manner to improve heat dissipation performance.

[0021] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the embodiments of the present disclosure.

[0023] FIG. 1 a is a diagram showing a maximum computing performance model that can be obtained theoretically according to an exemplary embodiment.

[0024] FIG1 b is a first schematic diagram of a data processing system according to an exemplary embodiment.

[0025] FIG1c is a second schematic diagram of a data processing system according to an exemplary embodiment.

[0026] FIG2 is a first schematic diagram of a data processing chip according to an embodiment of the present disclosure.

[0027] FIG3 is a second schematic diagram of a data processing chip according to an embodiment of the present disclosure.

[0028] FIG4 is a first schematic diagram of a data processing system according to an embodiment of the present disclosure.

[0029] FIG5 is a second schematic diagram of a data processing system according to an embodiment of the present disclosure.

[0030] FIG6 is a schematic diagram of another data processing system according to an embodiment of the present disclosure.

[0031] FIG7 is a flow chart of a method for manufacturing a data processing chip according to an embodiment of the present disclosure.

[0032] FIG8 a is a schematic diagram showing a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0033] FIG8 b is a schematic diagram illustrating a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0034] FIG8 c is a schematic diagram illustrating a manufacturing process of a data processing chip according to an embodiment of the present disclosure.

[0035] DESCRIPTION OF REFERENCE NUMERALS Data processing system 100, 3000, 4000; arithmetic units 111a, 111b, 1110, 6110; processors 113, 1130, 6130; wiring layers 130, 1310; wiring 131; caches 120a, 120b, 1210; data processing chip 1000; first wafer 1100, 6100; arithmetic unit 1120; SRAM cache 1140; memory interface circuit 1150; node interface circuit 1160; first die 1200, 6200; cache unit 1220; memory array chip 1221; second die 1300, 6300; bridge circuit 1320; first region 1100-1; second region 1100-2; heat dissipation structure 1400; memory 2000a, 2000b, 2000c, 2000d , 2000e, 2000f, 2000g, 2000h; substrate 3100; first heat sink 1700; first flat plate portion 1700a; first protruding portion 1700b; second heat sink 3200; second flat plate portion 3200a; second protruding portion 3200b; heat dissipation channel 3200c; first thermal interface material layer 1800; second thermal interface material layer 3300; base 1500; third region 1500-1; fourth region 1500-2; support structure 1600; node chips 4000a, 4000b, 4000c, 4000d; second wafer 6200A; third wafer 6300A. DETAILED DESCRIPTION

[0036] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible implementations consistent with the present disclosure. Rather, they are merely examples of apparatuses and methods consistent with certain aspects of the present disclosure.

[0037] The terms used in the embodiments of the present disclosure are for the purpose of describing specific embodiments only and are not intended to limit the embodiments of the present disclosure. The singular forms "a," "the," and "the" used in the present disclosure are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0038] It should be understood that although the terms first, second, third, etc. may be used to describe various information in the embodiments of the present disclosure, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of the present disclosure, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0039] As computing power increases significantly, system bandwidth requirements also rise. Otherwise, unlimited increases in computing power will not improve overall system performance. Figure 1a shows a theoretically achievable roof-line model of maximum computing performance, according to an exemplary embodiment. As shown in Figure 1a, due to the memory bandwidth bottleneck, the system's theoretical performance no longer increases with increasing computing power, as shown to the right of the dotted line in Figure 1a.

[0040] System bandwidth requirements continue to evolve across different memory form factors. Taking dynamic random access memory (DRAM) as an example, new memory types have been developed, including double data rate (DDR), low power double data rate (LPDDR), graphics double data rate (GDDR), and high bandwidth memory (HBM), to meet varying system bandwidth requirements.

[0041] However, increasing system bandwidth requirements comes at the cost of significantly increased costs and design complexity. For example, the bandwidth of the aforementioned memories satisfies the following order: HBM > GDDR > LPDDR > DDR; the design complexity satisfies the following order: HBM > GDDR > LPDDR = DDR; and the cost satisfies the following order: HBM > GDDR > LPDDR > DDR.

[0042] By adding on-chip cache, for example, integrating static random-access memory (SRAM) into the system on chip (SOC), the bandwidth required to access off-chip memory can be reduced. However, on-chip cache is expensive and has a small capacity (SRAM is at most in the MB range), which limits its effectiveness in reducing system bandwidth requirements.

[0043] By adding an off-chip cache, for example, integrating an off-chip cache using a wafer-on-wafer (WoW) bonding process, the system's bandwidth requirements can be met at a lower cost. Figure 1b is a first schematic diagram of a data processing system 100 according to an exemplary embodiment, and Figure 1c is a second schematic diagram of a data processing system 100 according to an exemplary embodiment. The off-chip integrated cache will be further described below in conjunction with Figures 1b and 1c.

[0044] 1b and 1c , data processing system 100 includes wafer 110, which includes a processor 113 and two arithmetic units (APUs) on either side of processor 113, for example, APUs 111a and 111b. To meet bandwidth requirements and reduce costs, buffers 120a and 120b may be provided for APUs 111a and 111b, respectively. Wafer 110, wiring layer 130, and the buffers are bonded together using WoW (WoW) bonding, with the APUs and buffers coupled via wiring 131 in wiring layer 130.

[0045] The problems with the above-mentioned WoW bonding scheme are: 1) WoW bonding has poor adaptability and cannot support splicing multiple independent blocks (for example, bonding buffer 120a and buffer 120b separately); 2) WoW bonding will cause the wiring in the wiring layer to be complicated, increasing the design difficulty; 3) WoW bonding has poor heat dissipation performance.

[0046] In view of this, the present disclosure provides a data processing chip and a manufacturing method thereof, and a data processing system.

[0047] Figure 2 is a schematic diagram of a data processing chip according to an embodiment of the present disclosure. Figure 3 is a schematic diagram of a data processing chip according to an embodiment of the present disclosure. The data processing chip provided by the embodiment of the present disclosure will be further described below in combination with Figures 2 and 3.

[0048] 2 and 3 , the data processing chip 1000 includes:

[0049] The first wafer 1100 includes an operation unit 1110 , wherein the operation unit 1110 is located in a first region 1100 - 1 of the first wafer 1100 ;

[0050] The first die 1200 is located on the first region 1100 - 1 and includes a buffer 1210 coupled to the computing unit 1110 via bonding. The buffer 1210 is configured to cache data when the computing unit 1110 is transmitting data to a host or to a memory.

[0051] The heat dissipation structure 1400 is located on the second region 1100 - 2 of the first wafer 1100 ; wherein the second region 1100 - 2 is different from the first region 1100 - 1 .

[0052] The first wafer 1100 includes but is not limited to a system-on-chip (SOC) integrated with multiple functional circuits. The first wafer 1100 includes an arithmetic unit 1110. In one example, the first wafer 1100 also includes a processor 1130, a memory interface circuit 1150, and a node interface circuit 1160, as shown in FIG4 . The processor 1130, the memory interface circuit 1150, and the node interface circuit 1160 will be described below. It should be noted that the functional circuit shown in FIG2 is shown only as an example, and the first wafer 1100 may also include other functional circuits known in the art. For example, the first wafer 1100 also includes a power supply, a power management circuit, and a timing control circuit.

[0053] The operator 1110 is configured to perform specific calculations in response to control commands and output calculation results. The operator 1110 includes a central processing unit (CPU), a graphics processing unit (GPU), a tensor processing unit (TPU), a data processing unit (DPU), an intelligent processing unit (IPU), or a neural network processing unit (NPU). The operator 1110 can execute a hash algorithm, a convolution algorithm, or a neural network algorithm.

[0054] In one example, the operator 1110 is a tensor processor TPU, which includes a matrix multiplication unit (MXU). The matrix multiplication unit is also called a systolic array, which can process 65536 multiplications and additions of 8-bit integers, greatly improving the computing power of the data processing chip 1000.

[0055] The first die 1200 can be a chip with complete functions cut from a wafer. The first die 1200 and the first wafer 1100 can be stacked through chip on wafer (CoW) bonding technology. The first die 1200 and the first wafer 1100 can be electrically connected through at least one of a bonding layer, through-silicon via (TSV), wiring or bump.

[0056] Buffer 1210 can cache data to be written to the memory during a write operation; cache data read from the memory during a read operation; cache data to be calculated by the arithmetic unit; or cache data output by the arithmetic unit after calculation. Buffer 1210 includes dynamic random access memory (DRAM), flash memory, phase change memory (PCM), or magnetic tunnel junction memory (MTJ). In other embodiments, buffer 1210 can also be other types of memory known in the art, and this disclosure is not particularly limited in this regard.

[0057] In one example, cache 1210 is a dynamic random access memory (DRAM). DRAM typically has a gigabyte (GB) capacity and a higher number of pins, enabling high bandwidth by operating low-speed digital circuits. It is understood that in this example, by using DRAM with a larger storage capacity and a higher number of pins as a cache for the data processing chip, the system's bandwidth requirements can be significantly reduced. Furthermore, compared to using expensive SRAM as a cache, using DRAM as a cache in this example significantly reduces costs.

[0058] It should be noted that the first wafer 1100 generally adopts an advanced process technology, such as a 5nm process, a 3nm process or a 1nm process, etc. Advanced process technology requires higher design and production costs, and integrating an on-chip cache in the on-chip system will undoubtedly lead to a waste of costs. Based on this, in other embodiments, the cache 1210 can also be an SRAM, and the SRAM can adopt a process technology greater than 20nm, such as a 22nm process, a 25nm process or a 28nm process, etc. It can be understood that in this example, by stacking the SRAM with lower process technology requirements with the first wafer 1100 and using it as a cache, the design and production costs of the data processing chip 1000 can be saved.

[0059] In some embodiments, the first wafer 1100 is manufactured using a first process, and the first die 1200 is manufactured using a second process; wherein the feature size corresponding to the second process is larger than the feature size corresponding to the first process. Of course, in other embodiments, the feature size corresponding to the second process may be smaller than or equal to the feature size corresponding to the first process.

[0060] As shown in FIG3 , the processor 1130 and the arithmetic unit 1110 are both located in the first wafer 1100 and are arranged side by side in a direction perpendicular to the stacking direction of the first wafer 1100 and the first die 1200. The arithmetic unit 1110 is located in a first region 1100-1, and the processor 1130 is located in a second region 1100-2 other than the first region 1100-1. The processor 1130 is configured to control logical operations of the memory, such as write operations, read operations, or erase operations. Here, the first region 1100-1 represents the region of the first wafer 1100 where the arithmetic unit 1110 is located, and the second region 1100-2 represents the region of the first wafer 1100 where other functional circuits (e.g., the processor 1130, etc.) are located.

[0061] Heat dissipation structure 1400 is located above second region 1100-2, for example, above processor 1130. Heat dissipation structure 1400 is made of a heat dissipation material, such as copper or other metals. By providing heat dissipation structure 1400 in second region 1100-2, the space surrounding the data processing chip is effectively utilized, improving space efficiency. Furthermore, the heat dissipation structure can effectively dissipate heat in a timely manner, preventing damage to the data processing chip caused by high temperatures.

[0062] In the embodiments of the present disclosure, on the one hand, by setting the first die and the first wafer to be stacked, the cache and the operator can be coupled by CoW bonding, thereby providing higher bandwidth for data transmission, achieving high computing power while reducing the bandwidth requirements of the system, and having good adaptability and applicable to different products; on the other hand, compared with setting an on-chip cache, the present disclosure sets the first die outside the first wafer (i.e., off-chip), and the cache in the first die is configured to cache data, which is beneficial to reducing the design complexity of the on-chip system and reducing the design and production costs of the data processing chip; on the third hand, the first die and the first wafer are bonded by the CoW process, and a heat dissipation structure can be set on the second area of ​​the first wafer to reasonably utilize the space of the data processing chip and improve space utilization, and the heat dissipation structure can dissipate heat in a timely and effective manner to improve heat dissipation performance.

[0063] In some embodiments, the data processing chip also includes: a wiring layer, located in the second die between the first wafer and the first die; or, located in the first wafer and between the operator and the first die; a bridge circuit, located in the wiring layer, the first port of the bridge circuit is coupled to the operator through a first interface protocol, and the second port of the bridge circuit is coupled to the buffer through a second interface protocol; wherein the second interface protocol is different from the first interface protocol.

[0064] FIG2 shows that the wiring layer 1310 is located in the second die 1300, and the first wafer 1100, the second die 1300, and the first die 1200 are stacked in sequence. In another example, the wiring layer 1310 is located in the first wafer 1100 (not shown in the figure), that is, the first wafer 1100 and the first die 1200 are stacked in sequence. In other embodiments, the wiring layer 1310 can also be located in the first die 1200 and between the buffer 1210 and the first wafer 1100.

[0065] In some embodiments, the second die 1300 is manufactured using a third process, and the feature size corresponding to the third process is larger than the feature size corresponding to the first process. Of course, in other embodiments, the feature size corresponding to the third process may be smaller than or equal to the feature size corresponding to the first process.

[0066] In some embodiments, the feature size corresponding to the third process technology may be the same as or different from the feature size corresponding to the second process technology.

[0067] The wiring layer 1310 includes an insulating layer and wiring (not shown) located in the insulating layer. The insulating layer is made of silicon oxide, oxynitride, or silicon oxynitride, and the wiring is made of a conductive material such as copper, aluminum, platinum, titanium, or tin.

[0068] Bridge circuit 1320 is configured to perform protocol conversion on data transmitted between processor 1110 and buffer 1210. Bridge circuit 1320 includes a first port, a conversion unit, and a second port. The first port is configured to couple to processor 1110, and the second port is configured to couple to buffer 1210. The conversion unit is configured to convert a first interface protocol used between the first port and processor 1110 into a second interface protocol used between the second port and buffer 1210, thereby ensuring data transmission between the processor 1110 and buffer 1210.

[0069] In one example, a first port of the bridge circuit 1320 is coupled to the input / output interface of the arithmetic unit 1110, and communication between the first port of the bridge circuit 1320 and the arithmetic unit 1110 may comply with an SRAM interface protocol (SRAM protocol). A second port of the bridge circuit 1320 is coupled to the input / output interface of the buffer 1210, and communication between the second port of the bridge circuit 1320 and the buffer 1210 may comply with a DRAM interface protocol (DRAM protocol). Of course, in other embodiments, the conversion unit may be omitted, and communication between the first port of the bridge circuit 1320 and the arithmetic unit 1110, and between the second port of the bridge circuit 1320 and the buffer 1210, may comply with a DRAM interface protocol.

[0070] In some embodiments, as shown in FIG. 2 , the arithmetic unit 1110 includes a plurality of arithmetic units 1120 ; the cache 1210 includes a plurality of cache units 1220 ; and the data processing chip 1000 includes a plurality of bridge circuits 1320 located in the wiring layer 1310 . Each of the arithmetic units 1120 is coupled to each of the cache units 1220 via the bridge circuits 1320 . The number of arithmetic units 1120 , the number of cache units 1220 , and the number of bridge circuits 1320 can be two or more. At least two of the number of arithmetic units 1120 , the number of cache units 1220 , and the number of bridge circuits 1320 can be the same or different.

[0071] In some embodiments, the number of computing units 1120, the number of cache units 1220, and the number of bridge circuits 1320 are the same. In one embodiment, the number of computing units 1120, the number of cache units 1220, and the number of bridge circuits 1320 are all 1024. It will be appreciated that, in this embodiment, each of the plurality of computing units 1120 can be coupled to each of the plurality of cache units 1220 via a plurality of bridge circuits 1320, and each computing unit 1120 can manage the data cached in the corresponding cache unit 1220, thereby improving the computing performance of the data processing chip 1000.

[0072] In some embodiments, the cache unit 1220 includes a plurality of memory array tiles (MATs) 1221. In the disclosed embodiments, by providing a wiring layer in the first wafer or the second die and providing a bridge circuit in the wiring layer, the operation unit accesses the corresponding cache unit through the wiring layer, thereby enabling data transmission between the operation unit and the cache while reducing data transmission latency. In addition, by providing a bridge circuit, data transmission between the operation unit and the cache can be achieved, which is compatible with existing interface protocols.

[0073] In some embodiments, in combination with Figure 5, the data processing chip 1000 also includes: a substrate 1500, including: a third area 1500-1 and a fourth area 1500-2; wherein the first wafer 1100 is located on the third area 1500-1; a support structure 1600, located on the fourth area 1500-2; wherein the surface of the support structure 1600 away from the substrate 1500 is basically flush with the surface of the heat dissipation structure 1400 away from the substrate 1500; a first heat sink 1700, covering the support structure 1600, the heat dissipation structure 1400 and the first die 1200; wherein the first heat sink 1700 is connected to the heat dissipation structure 1400.

[0074] The substrate 1500 may be a package carrier, which is configured to protect the chip and serve as an interface between the integrated circuit chip and the outside world (eg, a printed circuit board). The substrate 1500 includes a hard carrier, a flexible carrier, or a ceramic carrier.

[0075] The support structure 1600 is configured to provide support, and the material of the support structure 1600 includes a support material. In one example, the material of the support structure 1600 can be a stiffener material, and the support structure 1600 can be a thermo-compressive stiffener plate, a pressure-sensitive stiffener plate, or a heat-sensitive stiffener plate.

[0076] The surface of the support structure 1600 away from the substrate 1500 and the surface of the heat dissipation structure 1400 away from the substrate 1500 being substantially flush includes being completely flush or having an offset within an allowable error range. By setting the surface of the support structure away from the substrate and the surface of the heat dissipation structure away from the substrate substantially flush, flatness can be ensured, which is more conducive to subsequent packaging.

[0077] The first heat sink 1700 (heat sink) is made of a heat conductive material, such as aluminum or copper. The first heat sink 1700 can absorb heat from the heat dissipation structure 1400 and dissipate it into the external environment.

[0078] In some embodiments, as shown in FIG5 , first heat sink 1700 includes a first flat plate portion 1700a and multiple first protruding portions 1700b . First flat plate portion 1700a is located between heat dissipation structure 1400 and first protruding portions 1700b . A first gap is defined between two adjacent first protruding portions 1700b . By providing multiple first protruding portions and a first gap between two adjacent first protruding portions, the contact area between the first heat sink and the outside world can be increased, further improving heat dissipation performance while also minimizing resistance to the fluid.

[0079] In some embodiments, as shown in FIG5 , the data processing chip 1000 further includes a first thermal interface material (TIM) layer 1800, located at least between the heat dissipation structure 1400 and the first heat sink 1700. In one embodiment, the first TIM layer 1800 is located between the first die 1200 and the first heat sink 1700, between the heat dissipation structure 1400 and the first heat sink 1700, and between the support structure 1600 and the first heat sink 1700. Specifically, the first TIM layer 1800 covers the first die 1200, the heat dissipation structure 1400, and the support structure 1600. The material of the first TIM layer 1800 includes a flexible medium, such as a thermally conductive pad, thermally conductive silicone grease, or thermally conductive gel. The first TIM layer 1800 is used to fill small gaps between rigid solid contact surfaces, such as the gap between the heat dissipation structure 1400 and the first heat sink 1700.

[0080] In some embodiments, the orthographic projection of the first die 1200 substantially coincides with the orthographic projection of the operator, that is, the first die 1200 and the operator have the same size. For ease of illustration, the operator is not shown in FIG5 .

[0081] In some embodiments, the data processing chip 1000 further includes a second die 1300. The first die 1200, the second die 1300, and the computing unit are of the same size. For example, the orthographic projections of the first die 1200 and the second die 1300 substantially overlap with the orthographic projection of the computing unit. It should be noted that "substantially overlapping" includes completely overlapping or having a deviation, but the deviation is within an allowable error range. For ease of illustration, the computing unit is not shown in FIG5 .

[0082] In some embodiments, the storage capacity of the buffer 1210 is greater than a preset value; wherein the preset value is greater than 0 mebiByte (MB) and less than 1 gigaByte (GB).

[0083] It should be noted that, due to cost considerations, the capacity of on-chip SRAM is typically less than 1GB. For example, the capacity of on-chip SRAM can be in the MB range. In the disclosed embodiment, by setting the storage capacity of the buffer 1210 to be greater than a preset value, the storage capacity of the off-chip buffer 1210 can be increased, thereby reducing the bandwidth requirements of the system.

[0084] In one embodiment, in a system-on-chip (SoC) using SRAM as a cache, the SRAM has a storage capacity of megabytes, corresponding to a system bandwidth requirement of several terabytes per second. This requires the use of higher-bandwidth memory, such as high-bandwidth memory (HBM), to meet the system bandwidth requirement, at the expense of design complexity and high production costs. The present disclosure reduces the system bandwidth requirement to several gigabytes per second by using DRAM with a storage capacity of gigabytes as an off-chip cache, eliminating the need for higher-bandwidth memory, such as HBM. This simplifies the design complexity of the data processing chip 1000 while reducing costs.

[0085] In some embodiments, the data processing chip 1000 is applied to the field of artificial intelligence, and the data processing chip 1000 includes but is not limited to an artificial intelligence chip (AI).

[0086] Based on the above data processing chip, an embodiment of the present disclosure also provides a data processing system.

[0087] Figure 4 is a schematic diagram 1 of a data processing system according to an embodiment of the present disclosure, and Figure 5 is a schematic diagram 2 of a data processing system according to an embodiment of the present disclosure. The data processing system provided by the embodiment of the present disclosure will be further described below in combination with Figures 4 and 5.

[0088] 4 and 5 , the data processing system 3000 includes: a substrate 3100; a data processing chip 1000 such as that in any of the above embodiments, located on the substrate 3100; and at least one memory located on the substrate 3100 and arranged in parallel with the first wafer 1100 along a first direction, wherein the first direction is perpendicular to the direction in which the first die 1200 and the first wafer 1100 are stacked.

[0089] The substrate 3100 may be a package mainboard, and the substrate 3100 is electrically connected to the data processing chip 1000 via solder balls and a package carrier. The substrate 3100 includes but is not limited to a printed circuit board.

[0090] 4 , a first wafer 1100 and a plurality of memories are arranged in parallel along a first direction, and the first wafer 1100 is coupled to the memories via a memory interface circuit 1150. For example, FIG4 shows eight memories 2000a, 2000b, 2000c, 2000d, 2000e, 2000f, 2000g, and 2000h, where memories 2000a, 2000b, 2000c, and 2000d are located on one side of the first wafer 1100, and memories 2000e, 2000f, 2000g, and 2000h are located on the other side of the first wafer 1100.

[0091] Memory includes: Double Data Rate (DDR), Low Power Double Data Rate (LPDDR), Graphics Double Data Rate (GDDR), and High Bandwidth Memory (HBM). In one embodiment, the cache 1210 is a dynamic random access memory (DRAM), and the memory is the fifth-generation low-power DRAM LPDDR5, referred to as LP5.

[0092] In some embodiments, as shown in FIG4 , after a buffer is provided in the first die 1200, the SRAM cache 1140 in the first wafer 1100 (as shown in the dotted box in FIG4 ) can be omitted, which helps reduce the planar size of the data processing chip 1000. In other embodiments, as shown in FIG4 , after a buffer is provided in the first die 1200, the SRAM cache 1140 in the first wafer 1100 can also be retained. The SRAM and the cache 1210 in the first die 1200 can be used together as a cache, which helps further reduce bandwidth requirements. Those skilled in the art can make reasonable settings based on actual needs, and this disclosure is not limited thereto.

[0093] In the embodiment of the present disclosure, by setting up a stack of the first wafer and the first die, the buffer in the first die is used as a cache, which reduces the bandwidth requirement of the system, so that low-bandwidth and high-capacity memory can be selected, and there is no need to integrate multiple computing chip nodes, which is beneficial to reducing the design complexity and production cost of the data processing system and improving the integration.

[0094] In some embodiments, the first wafer 1100 and the plurality of memories are located in a first level of the data processing system 3000, the second die 1300 is located in a second level of the data processing system 3000, and the first die 1200 is located in a third level of the data processing system 3000. That is, the first wafer 1100 and the plurality of memories are located in the same level, the second die 1300 and the plurality of memories are located in a different level, and the first die 1200 and the plurality of memories are located in a different level.

[0095] It should be noted that the same level used in this disclosure means that the two grains (or the grain and the wafer) have the same distance from the top surface or bottom surface of the packaging substrate (not shown in the figure), and different levels means that the two grains have different distances from the top surface or bottom surface of the packaging substrate.

[0096] In some embodiments, as shown in FIG. 5 , the data processing system 3000 further includes a second heat sink 3200 comprising a heat dissipation channel 3200c extending through the substrate 3100 and connected to the first wafer 1100. The material of the second heat sink 3200 can be similar to that of the first heat sink 1700. In the disclosed embodiments, by providing heat sinks on both sides of the data processing chip 1000, heat can be dissipated from both sides, facilitating heat dissipation and preventing damage to the chip due to high temperatures.

[0097] In some embodiments, as shown in FIG5 , the second heat sink 3200 further includes: a second flat portion 3200a and a plurality of second protruding portions 3200b; wherein the second flat portion 3200a is located between the substrate 3100 and the second protruding portion 3200b; a first end of the second flat portion 3200a is connected to the heat dissipation channel 3200c; a second end of the second flat portion 3200a is connected to the plurality of second protruding portions 3200b, and the second end is disposed opposite the first end; and a second gap is defined between two adjacent second protruding portions 3200b. By providing the plurality of second protruding portions and the second gap between two adjacent second protruding portions, the contact area between the second heat sink and the outside world can be increased, further improving heat dissipation performance while also taking into account the resistance to the fluid.

[0098] 5 , the data processing system 3000 further includes a second thermal interface material layer 3300 located between the first wafer 1100 and the second heat sink 3200. The material of the second thermal interface material layer 3300 may be similar to that of the first thermal interface material layer 1800.

[0099] The data processing chip 1000 and at least one memory device in Figure 2 may constitute a node chip. Figure 6 is a schematic diagram of another data processing system 4000 according to an embodiment of the present disclosure. As shown in Figure 6, data processing system 4000 includes multiple node chips. For example, Figure 6 shows four node chips 4000a, 4000b, 4000c, and 4000d. The node chips can be connected via the node interface circuit 1160 in Figure 4. By connecting multiple node chips, the computing power of data processing system 4000 can be further improved.

[0100] In some embodiments, the data processing chip 1000 and the memory constitute a node chip; the data processing system 4000 includes: a plurality of node chips; wherein the plurality of node chips are arranged in parallel and connected in a cluster along a second direction, the second direction being perpendicular to the direction in which the first wafer and the first die are stacked, and the second direction intersecting the first direction. Here, cluster connection includes a series arrangement, a mesh network arrangement, a ring arrangement, or a one-to-many arrangement, etc. The embodiments of the present disclosure do not specifically limit the connection method of the plurality of node chips.

[0101] Based on the above data processing chip, an embodiment of the present disclosure further provides a method for manufacturing the data processing chip.

[0102] FIG7 is a flow chart of a method for manufacturing a data processing chip according to an embodiment of the present disclosure. Referring to FIG7 , the manufacturing method includes at least the following steps:

[0103] S5100: Providing a first wafer; wherein the first wafer includes an arithmetic unit; the arithmetic unit is located in a first region of the first wafer;

[0104] S5200: forming a first die on the first region; wherein the first die includes a buffer, the buffer being coupled to the arithmetic unit via bonding; the buffer being configured to: cache transmitted data when the arithmetic unit is transmitting data to a host or when the arithmetic unit is transmitting data to a memory;

[0105] S5300: forming a heat dissipation structure on a second region of the first wafer; wherein the second region is different from the first region.

[0106] It should be noted that the steps shown in FIG. 7 are not exclusive, and other steps may be performed before, after or between any steps in the shown operation; the steps shown in FIG. 7 may be adjusted in order according to actual needs.

[0107] 8a to 8c are schematic diagrams illustrating a manufacturing process of a data processing chip according to an embodiment of the present disclosure. The manufacturing method of the data processing chip provided by the embodiment of the present disclosure will be described in detail below in conjunction with FIG. 7 and FIG. 8a to 8c.

[0108] In step S5100, as shown in FIG8a, a first wafer 6100 is provided, wherein the first wafer 6100 includes an arithmetic unit 6110 located in a first region of the first wafer 6100. Furthermore, the first wafer 6100 also includes a processor 6130 located in a second region of the first wafer 6100.

[0109] In some embodiments, referring to Figure 8a, the above-mentioned manufacturing method also includes: providing a second wafer 6200A; wherein the second wafer 6200A includes a plurality of first grains 6200; providing a third wafer 6300A; wherein the third wafer 6300A includes a plurality of second grains 6300; the second grain 6300 includes a wiring layer (not shown in the figure) and a bridge circuit (not shown in the figure) located in the wiring layer.

[0110] The first wafer 6100, the second wafer 6200A, and the third wafer 6300A can be manufactured using processes known in the semiconductor field (e.g., thin film deposition process, photolithography process, etching process, particle implantation process, etc.). The first wafer 6100 uses a first process, the second wafer 6200A uses a second process, and the third wafer 6300A uses a third process. The feature size corresponding to the second process is larger than the feature size corresponding to the first process, and the feature size corresponding to the third process is larger than the feature size corresponding to the first process. The feature size corresponding to the third process and the feature size corresponding to the second process can be the same or different. Here, the feature size represents the smallest size among the first wafer 6100, the second wafer 6200A, or the third wafer 6300A. Of course, in other embodiments, the feature size corresponding to the second process can be smaller than or equal to the feature size corresponding to the first process, and the feature size corresponding to the third process can be smaller than or equal to the feature size corresponding to the first process.

[0111] The second wafer 6200A includes a plurality of first dies 6200 and a first scribe line between two adjacent first dies 6200 . The third wafer 6300A includes a plurality of second dies 6300 and a second scribe line between two adjacent second dies 6300 .

[0112] In some embodiments, referring to Figure 8b, the above-mentioned manufacturing method also includes: bonding the third wafer 6300A and the second wafer 6200A, so that the second port of the bridge circuit is coupled to the buffer through the second interface protocol; performing cutting processing on the bonded third wafer 6300A and the second wafer 6200A to form a bonded second grain 6300 and a first grain (not shown in the figure).

[0113] After the second wafer 6200A and the third wafer 6300A are manufactured, the second wafer 6200A is inverted and aligned with the third wafer 6300A and bonded. The bonded second wafer 6200A and the third wafer 6300A are cut into multiple chips along the first cutting street and the second cutting street. The chip includes a stacked first die and a second die 6300. The first die includes a buffer, and the second die 6300 includes a bridge circuit. The second port of the bridge circuit is coupled to the buffer by bonding. The bridge circuit transmits data to the buffer via a second interface protocol, and then the two chips are packaged together. Here, the bonding method between the second wafer 6200A and the third wafer 6300A includes WoW bonding. In one embodiment, the size of the first die is the same as the size of the second die 6300, and the size of the first cutting street is the same as the size of the second cutting street. For ease of illustration, the first die is not shown in Figure 8b.

[0114] In step S5200, a first die is formed on the first region; wherein the first die includes a buffer, and the buffer is coupled to the operator through bonding; the buffer is configured to: cache the transmitted data when the operator transmits data to the host or when the operator transmits data to the memory.

[0115] In some embodiments, referring to FIG. 8c , the step S5200 includes bonding the bonded second die 6300 and the first die to the operator 6110 so that the first port of the bridge circuit is coupled to the operator 6110 via a first interface protocol; wherein the second interface protocol is different from the first interface protocol.

[0116] The bonded and packaged chip is aligned with the computing unit 6110 in the first wafer 6100. Here, the first port of the bridge circuit in the second die 6300 is coupled to the computing unit via bonding. The bridge circuit receives data transmitted by the computing unit via a first interface protocol. The chip is then packaged together with the first wafer 6100. Here, the bonding method between the chip and the first wafer 6100 includes CoW bonding, and the first interface protocol and the second interface protocol are different.

[0117] In some embodiments, the above-mentioned step S5100 includes: forming an operator in the first area; forming a wiring layer on the operator; forming a bridge circuit in the wiring layer; wherein, the first port of the bridge circuit is coupled to the operator through a first interface protocol; the above-mentioned step S5200 includes: inverting the first die so that the wiring layer is located between the operator and the first die; bonding the bridge circuit and the first die so that the second port of the bridge circuit is coupled to the buffer through a second interface protocol; wherein, the second interface protocol is different from the first interface protocol.

[0118] In some embodiments, as shown in conjunction with FIG. 2 and FIG. 8 c , after forming the arithmetic unit 6110, an insulating layer is formed covering the arithmetic unit 6110. Wiring and bridge circuits are formed in the insulating layer through processes such as photolithography, etching, and thin film deposition. The bridge circuits are provided in a one-to-one correspondence with the arithmetic units. The bridge circuits and corresponding arithmetic units are coupled via interconnecting contacts and / or interconnecting lines. The bridge circuits receive data transmitted by the arithmetic units via a first interface protocol. After the second wafer is cut to form a first die, the first die is inverted and aligned with and bonded to the first wafer 6100. The alignment and bonding of the first die and the first wafer 6100 can refer to FIG. 8 b described above.

[0119] In step S5300 , as shown in FIG. 3 or FIG. 5 , a heat dissipation structure 1400 is formed on a second region of a first wafer; wherein the second region is different from the first region.

[0120] In some embodiments, in combination with Figure 5, the above-mentioned manufacturing method also includes: providing a substrate 1500; wherein the substrate includes a third region 1500-1 and a fourth region 1500-2; bonding the first wafer on the third region 1500-1; forming a support structure 1600 on the fourth region 1500-2; wherein the surface of the support structure 1600 away from the substrate is substantially flush with the surface of the heat dissipation structure 1400 away from the substrate; forming a first heat sink 1700 covering the support structure 1600, the heat dissipation structure 1400 and the first die; wherein the first heat sink 1700 is connected to the heat dissipation structure 1400.

[0121] In some embodiments, as shown in FIG5 , the manufacturing method further includes forming a first thermal interface material layer 1800 ; wherein the first thermal interface material layer 1800 is located at least between the heat dissipation structure 1400 and the first heat sink 1700 . Here, the first thermal interface material layer 1800 may be formed first, and then the first heat sink 1700 is formed.

[0122] In the above embodiments, the description of each embodiment has different emphases. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0123] The above description is merely an exemplary embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in the present disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A data processing chip, comprising: A first wafer, comprising: an operator; wherein the operator is located in a first area of ​​the first wafer; A first die is located on the first region, and includes: a buffer, the buffer is coupled to the operator through bonding; wherein the buffer is configured to: cache the transmitted data when the operator transmits data to a host or transmits data to a memory; The heat dissipation structure is located on a second area of ​​the first wafer; wherein the second area is different from the first area.

2. The data processing chip according to claim 1, wherein: The data processing chip also includes: A wiring layer is located in a second die between the first wafer and the first die; or, is located in the first wafer and between the operator and the first die; A bridge circuit is located in the wiring layer, wherein a first port of the bridge circuit is coupled to the operator via a first interface protocol, and a second port of the bridge circuit is coupled to the buffer via a second interface protocol; wherein the second interface protocol is different from the first interface protocol.

3. The data processing chip according to claim 1 or 2, wherein: The data processing chip also includes: A substrate, comprising: a third region and a fourth region; wherein the first wafer is located on the third region; A support structure, located on the fourth region; wherein a surface of the support structure away from the substrate is substantially flush with a surface of the heat dissipation structure away from the substrate; A first heat sink covers the support structure, the heat dissipation structure and the first die; wherein the first heat sink is connected to the heat dissipation structure.

4. The data processing chip according to claim 3, wherein: The first heat sink includes: a first flat plate portion and a plurality of first protruding portions; wherein the first flat plate portion is located between the heat dissipation structure and the first protruding portions; and a first gap is provided between two adjacent first protruding portions.

5. The data processing chip according to claim 3, wherein: The data processing chip also includes: The first thermal interface material layer is located at least between the heat dissipation structure and the first heat sink.

6. The data processing chip according to claim 1, wherein: The orthographic projection of the first grain substantially coincides with the orthographic projection of the operator.

7. A method for manufacturing a data processing chip, comprising: Providing a first wafer; wherein the first wafer comprises an operator; the operator is located in a first region of the first wafer; A first crystal grain is formed on the first region; wherein the first crystal grain includes a buffer, and the buffer is coupled to the operator through bonding; the buffer is configured to: perform data transmission between the operator and the host or When the computing unit and the memory perform data transmission, the transmitted data is cached; A heat dissipation structure is formed on a second region of the first wafer; wherein the second region is different from the first region.

8. The manufacturing method according to claim 7, wherein: The manufacturing method further comprises: Providing a second wafer; wherein the second wafer includes a plurality of the first dies; Providing a third wafer; wherein the third wafer comprises a plurality of second dies; the second dies comprise a wiring layer and a bridge circuit located in the wiring layer; Bonding the third wafer and the second wafer so that the second port of the bridge circuit is coupled to the buffer through a second interface protocol; Performing a dicing process on the bonded third wafer and the second wafer to form the bonded second die and the first die; The forming of a first crystal grain on the first region includes: The bonded second die and the first die are bonded to the operator so that the first port of the bridge circuit is coupled to the operator through a first interface protocol; wherein the second interface protocol is different from the first interface protocol.

9. The manufacturing method according to claim 7, wherein: The providing of a first wafer comprises: forming the operator in the first region; forming a wiring layer on the operator; A bridge circuit is formed in the wiring layer; wherein a first port of the bridge circuit is coupled to the operator via a first interface protocol; The forming of a first crystal grain on the first region includes: Inverting the first die so that the wiring layer is located between the operator and the first die; The bridge circuit and the first die are bonded so that a second port of the bridge circuit is coupled to the buffer via a second interface protocol; wherein the second interface protocol is different from the first interface protocol.

10. The manufacturing method according to claim 8 or 9, wherein: The manufacturing method further comprises: Providing a substrate; wherein the substrate includes a third region and a fourth region; bonding the first wafer onto the third region; forming a support structure on the fourth region; wherein a surface of the support structure away from the substrate is substantially flush with a surface of the heat dissipation structure away from the substrate; A first heat sink is formed to cover the support structure, the heat dissipation structure and the first die; wherein the first heat sink is connected to the heat dissipation structure.

11. The manufacturing method according to claim 10, wherein: The manufacturing method further comprises: Forming a first thermal interface material layer; wherein the first thermal interface material layer is at least located between the heat dissipation structure and the between the first radiators.

12. A data processing system comprising: substrate; The data processing chip according to any one of claims 1 to 6, located on the substrate; At least one of the memories is located on the substrate and is arranged in parallel with the first wafer along a first direction, and the first direction is perpendicular to a direction in which the first die and the first wafer are stacked.

13. The data processing system according to claim 12, wherein: The data processing system further comprises: The second heat sink includes a heat dissipation channel, which passes through the substrate and is connected to the first wafer.

14. The data processing system according to claim 13, wherein: The second heat sink also includes: A second flat plate portion and a plurality of second protruding portions; wherein the second flat plate portion is located between the substrate and the second protruding portions, a first end of the second flat plate portion is connected to the heat dissipation channel, a second end of the second flat plate portion is connected to a plurality of second protruding portions, and the second end is arranged opposite to the first end; a second gap is provided between two adjacent second protruding portions.

15. The data processing system according to claim 13, wherein: The data processing system further comprises: The second thermal interface material layer is located between the first wafer and the second heat sink.

Images