Semiconductor device structure, radio frequency switch and electronic apparatus

Abstract

A semiconductor device structure, a radio frequency switch and an electronic apparatus, belonging to the technical field of radio frequency devices. The semiconductor device structure comprises a base substrate (1), and at least one PIN unit, a first connection electrode (40) and a second connection electrode (50) which are arranged on the base substrate (1). The PIN unit comprises a plurality of PIN devices which are successively arranged in the direction away from the base substrate, and interlayer insulating layers are provided between the layers where adjacent PIN devices are located. Each PIN device comprises a P-type semiconductor (10), an N-type semiconductor (30) and an I-type semiconductor (20) which are arranged on a same layer and are arranged side by side in a first direction, the I-type semiconductor (20) being located between the P-type semiconductor (10) and the N-type semiconductor (30). In the PIN unit, the orthographic projections of the I-type semiconductors (20) of any two PIN devices on the base substrate (1) at least partially overlap each other. The first connection electrode (40) and the second connection electrode (50) are located on the side of the PIN unit facing away from the base substrate (1), the P-type semiconductor (10) of each PIN device being connected to the first connection electrode (40), and the N-type semiconductor (30) of each PIN device being connected to the second connection electrode (50).

Description

Semiconductor device structures, radio frequency switches and electronic equipment Technical Field

[0001] The present disclosure belongs to the technical field of radio frequency devices, and in particular relates to a semiconductor device structure, a radio frequency switch, and an electronic device. Background Art

[0002] In existing technology, the design and fabrication of vertical PIN structures is generally the mainstream. The fabrication process requires a-Si deposition, dehydrogenation, and ELA crystallization for each layer of the P-type semiconductor, I-type semiconductor, and N-type semiconductor. In particular, the high-temperature dehydrogenation process can easily affect the functionality of the PIN structure. Furthermore, the doping process used to fabricate the P-type semiconductor on the upper surface of the I-type semiconductor also inevitably affects both the I-type and N-type semiconductors. Furthermore, the P-type semiconductor vertically positioned above the I-type semiconductor affects the I-type semiconductor's light absorption efficiency, resulting in lower photoelectric efficiency and recognition capabilities for the PIN structure.

[0003] Summary of the Invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art and provides a semiconductor device structure, a radio frequency switch and an electronic device.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device structure, comprising a substrate, and at least one PIN unit, a first connection electrode, and a second connection electrode disposed on the substrate; wherein,

[0006] The PIN unit includes a plurality of PIN devices sequentially arranged in a direction away from the substrate, with an interlayer insulating layer provided between layers of adjacent PIN devices; the PIN devices include a P-type semiconductor, an N-type semiconductor, and an I-type semiconductor arranged side by side in the same layer and along a first direction, with the I-type semiconductor located between the P-type semiconductor and the N-type semiconductor; in the PIN unit, the orthographic projections of the I-type semiconductors of any two PIN devices on the substrate at least partially overlap;

[0007] The first connection electrode and the second connection electrode are located on a side of the PIN unit away from the dielectric substrate, and the P-type semiconductor of each PIN device is connected to the first connection electrode, and the N-type semiconductor of each PIN device is connected to the second connection electrode.

[0008] The plurality of PIN devices in the PIN unit include a first PIN device and a second PIN device sequentially arranged in a direction away from the substrate; the interlayer insulating layer between the layer where the first PIN device is located and the layer where the second PIN device is located is a first interlayer insulating layer;

[0009] The P-type semiconductor, N-type semiconductor and I-type semiconductor of the first PIN device are a first P-type semiconductor, a first N-type semiconductor and a first I-type semiconductor; the P-type semiconductor, N-type semiconductor and I-type semiconductor of the second PIN device are a second P-type semiconductor, a second N-type semiconductor and a second I-type semiconductor.

[0010] The first connecting electrode includes a first sub-electrode and a second sub-electrode sequentially arranged in a direction away from the base substrate; the second connecting electrode includes a third sub-electrode and a fourth sub-electrode sequentially arranged in a direction away from the base substrate;

[0011] A second interlayer insulating layer is provided on a side of the second PIN device facing away from the dielectric substrate, the first sub-electrode and the third sub-electrode are provided on the same layer, and a third interlayer insulating layer is provided on a side of the layer where the first sub-electrode is located facing away from the base substrate;

[0012] The PIN unit further includes a first via, a second via, a third via, a fourth via, a fifth via, and a sixth via; the first via penetrates the second P-type semiconductor and the first interlayer insulating layer; the second via and the fifth via both penetrate the second interlayer insulating layer; the third via and the sixth via both penetrate the third interlayer insulating layer; the fourth via penetrates the second N-type semiconductor and the first interlayer insulating layer;

[0013] The first sub-electrode is electrically connected to the second P-type semiconductor through the second via hole, and the first P-type semiconductor in the PIN unit is electrically connected to the second P-type semiconductor through the first via hole; the second sub-electrode is electrically connected to the first sub-electrode through the third via hole;

[0014] The third sub-electrode is electrically connected to the second N-type semiconductor through the fifth via, the first N-type semiconductor in the PIN unit is electrically connected to the second N-type semiconductor through the fourth via; the fourth sub-electrode is electrically connected to the third sub-electrode through the sixth via.

[0015] For the PIN unit, the orthographic projection of the first via on the base substrate is located within the orthographic projection of the second via on the base substrate; and / or the orthographic projection of the fourth via on the base substrate is located within the orthographic projection of the fifth via on the base substrate.

[0016] For the PIN unit, when the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the second via hole on the base substrate, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate coincide with each other;

[0017] When the orthographic projection of the fourth via hole on the base substrate is located within the orthographic projection of the fifth via hole on the base substrate, the orthographic projections of the center of the fourth via hole and the center of the fifth via hole on the base substrate coincide with each other.

[0018] For one PIN unit, the number of the first via, the second via, the third via, the fourth via, the fifth via, and the sixth via are all plural, and the orthographic projections of the second via and the third via on the dielectric substrate are alternately arranged, and the orthographic projections of the fifth via and the sixth via on the dielectric substrate are alternately arranged.

[0019] The number of the PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the first P-type semiconductor of the i-th PIN unit is shared with the i-1-th first P-type semiconductor, and the second P-type semiconductor of the i-th PIN unit is shared with the i-1-th second P-type semiconductor; the first N-type semiconductor of the i-th PIN unit is shared with the i+1-th first N-type semiconductor, and the second N-type semiconductor of the i-th PIN unit is shared with the i+1-th second N-type semiconductor; N≥3, and N is a positive integer, and i is 1 to (N-1).

[0020] The third via hole and the sixth via hole in the PIN unit are arranged alternately, and the first via hole and the fourth via hole are arranged alternately.

[0021] For one of the PIN units, the sizes of the orthographic projections of the first via hole and the second via hole on the base substrate are both larger than the size of the orthographic projection of the third via hole on the base substrate; and / or,

[0022] The orthographic projection sizes of the fourth via hole and the fifth via hole on the base substrate are both larger than the orthographic projection size of the sixth via hole on the base substrate.

[0023] Among them, for one of the PIN units, the width of the orthographic projection of the third via on the substrate in the first direction is approximately equal to the width of the orthographic projection of the corresponding first sub-electrode on the substrate in the first direction; and / or, the width of the orthographic projection of the sixth via on the substrate in the first direction is approximately equal to the width of the orthographic projection of the corresponding third sub-electrode on the substrate in the first direction.

[0024] wherein the first sub-electrode includes at least one first branch, the second sub-electrode includes at least one second branch, and the first branch and the second branch are arranged in a one-to-one correspondence; for the correspondingly arranged first branch and second branch, the first branch is connected to the first P-type semiconductor through the first via, connected to the second P-type semiconductor through the second via, and the second branch is connected to the first branch through the third via; and / or,

[0025] The third sub-electrode includes at least one third branch, and the fourth sub-electrode includes at least one fourth branch, and the third branch and the fourth branch are arranged in a one-to-one correspondence; for the correspondingly arranged third branch and the fourth branch, the third branch is connected to the first N-type semiconductor through the fourth via, and is connected to the second N-type semiconductor through the fourth via, and the fourth branch is connected to the third branch through the sixth via.

[0026] When the first sub-electrode includes at least one first branch, the second sub-electrode includes at least one second branch, and the first branch and the second branch are arranged in a one-to-one correspondence, the center lines of the corresponding first branch and second branch in their respective trace directions coincide with the orthographic projection of the center line of the first P-type semiconductor in its trace direction on the substrate;

[0027] When the third sub-electrode includes at least one third branch, the fourth sub-electrode includes at least one fourth branch, and the third branches and the fourth branches are arranged in a one-to-one correspondence, for the correspondingly arranged third branches and the fourth branches, the midlines of both in their respective trace directions coincide with the orthographic projection of the midline of the first N-type semiconductor in its trace direction on the substrate.

[0028] When the first sub-electrode includes a plurality of first branches and the second sub-electrode includes a plurality of second branches, the first sub-electrode further includes a first connecting portion, and each of the first branches is connected to the first connecting portion to form the first sub-electrode with a comb-like structure; the second sub-electrode further includes a second connecting portion, and each of the second branches is connected to the second connecting portion to form the second sub-electrode with a comb-like structure;

[0029] When the third sub-electrode includes a plurality of third branches and the fourth sub-electrode includes a plurality of fourth branches, the third sub-electrode further includes a third connecting portion, and each of the third branches is connected to the third connecting portion to form the third sub-electrode with a comb-like structure; the fourth sub-electrode further includes a fourth connecting portion, and each of the fourth branches is connected to the fourth connecting portion to form the fourth sub-electrode with a comb-like structure;

[0030] The orthographic projections of the first connecting portion and the second connecting portion on the substrate are located on the same side of the orthographic projection of the PIN unit on the substrate, and the orthographic projections of the third connecting portion and the fourth connecting portion on the substrate are located on the same side of the orthographic projection of the PIN unit on the substrate, and are both located on a different side from the orthographic projection of the first connecting portion and the third connecting portion on the substrate.

[0031] The orthographic projections of the first sub-electrode and the second sub-electrode on the base substrate completely overlap, or the orthographic projection of the second sub-electrode on the base substrate is located within the orthographic projection of the first sub-electrode on the base substrate.

[0032] The orthographic projections of the third sub-electrode and the fourth sub-electrode on the base substrate completely overlap, or the orthographic projection of the fourth sub-electrode on the base substrate is located within the orthographic projection of the third sub-electrode on the base substrate.

[0033] The orthographic projections of the first branch, the corresponding second branch, and the first P-type semiconductor on the substrate completely overlap; and / or the orthographic projections of the third branch, the corresponding fourth branch, and the first N-type semiconductor on the substrate completely overlap.

[0034] wherein the orthographic projections of the first branch and the corresponding second branch on the substrate are both located within the orthographic projections of the first P-type semiconductor on the substrate, and the widths of the first branch and the corresponding second branch along the first direction are both smaller than the width of the first P-type semiconductor along the first direction; and / or,

[0035] The orthographic projections of the third branch and the corresponding fourth branch on the substrate are both located within the orthographic projections of the first N-type semiconductor on the substrate, and the widths of the third branch and the corresponding fourth branch along the first direction are both smaller than the width of the first N-type semiconductor along the first direction.

[0036] Wherein, a second interlayer insulating layer is provided on a side of the second PIN device facing away from the dielectric substrate;

[0037] The PIN unit further includes a first via hole, a second via hole, a third via hole, and a fourth via hole; the first via hole and the third via hole both penetrate the second P-type semiconductor, the first interlayer insulating layer, and the second interlayer insulating layer; the second via hole and the fourth via hole both penetrate the second interlayer insulating layer;

[0038] The first connecting electrode is connected to the first P-type semiconductor through the first via hole, and is connected to the second P-type semiconductor through the second via hole; the second connecting electrode is connected to the first N-type semiconductor through the third via hole, and is connected to the second N-type semiconductor through the fourth via hole.

[0039] In which, the PIN unit includes multiple first via groups and multiple second via groups; the first via group includes one first via and two second vias, and the two second vias are arranged on both sides of the first via that are opposite to each other in the first direction; the second via group includes one third via and two fourth vias, and the two fourth vias are arranged on both sides of the third via that are opposite to each other in the first direction.

[0040] The first via hole and the second via hole in the first via hole group are connected to each other; and / or the third via hole and the fourth via hole in the second via hole group are connected to each other.

[0041] Wherein, for the PIN unit, the first via hole group and the second via hole group are arranged alternately.

[0042] The number of the PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the first P-type semiconductor of the i-th PIN unit is shared with the i-1-th first P-type semiconductor, and the second P-type semiconductor of the i-th PIN unit is shared with the i-1-th second P-type semiconductor; the first N-type semiconductor of the i-th PIN unit is shared with the i+1-th first N-type semiconductor, and the second N-type semiconductor of the i-th PIN unit is shared with the i+1-th second N-type semiconductor; N≥3, and N is a positive integer, and i is 1 to (N-1).

[0043] Wherein, the first connecting electrode includes a plurality of first branch structures and a first main structure connecting the first branch structures; one of the first branch structures is connected to the first P-type semiconductor through the first via hole and is connected to the second P-type semiconductor through the second via hole; and / or,

[0044] The second connecting electrode includes a plurality of second branch structures and a second main body structure connecting the second branch structures; the second branch structures are connected to the first N-type semiconductor through the fourth via hole and connected to the second N-type semiconductor through the fourth via hole.

[0045] When the first connecting electrode includes a first branch structure, the first branch structure and the corresponding first P-type semiconductor have orthographic projections on the substrate of the first branch structure and the corresponding first P-type semiconductor along a center line extending perpendicular to the first direction that coincide with each other;

[0046] When the second connecting electrode includes a second branch structure, the orthographic projections of the second branch structure and the corresponding first N-type semiconductor along a center line extending perpendicular to the first direction on the substrate coincide with each other.

[0047] When the first connecting electrode includes a plurality of first branch structures and a first main body structure, and the second connecting electrode includes a plurality of second branches and a second main body structure, the plurality of first branch structures and the first main body structure are connected to form a first connecting electrode with a comb-shaped structure, and the plurality of second branch structures and the second main body structure are connected to form a second connecting electrode with a comb-shaped structure.

[0048] The orthographic projections of the first main structure and the second main structure on the base substrate are located on different sides of the orthographic projection of the PIN unit on the base substrate.

[0049] When the first connecting electrode includes a first branch structure, the orthographic projections of the first branch structure and the corresponding first P-type semiconductor on the substrate completely overlap;

[0050] When the second connecting electrode includes a second branch structure, the orthographic projections of the second branch structure and the corresponding first N-type semiconductor on the substrate completely overlap.

[0051] In a second aspect, an embodiment of the present disclosure provides a radio frequency switch, comprising a transmission line and a semiconductor device structure disposed on the transmission line, wherein the semiconductor device structure is any of the semiconductor device structures described above.

[0052] The radio frequency switch further includes a capacitor and an inductor, both of which are connected to the transmission line.

[0053] In a third aspect, an embodiment of the present disclosure provides an electronic device comprising the above-mentioned radio frequency switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] FIG1 is a cross-sectional view of an exemplary semiconductor device structure.

[0055] FIG. 2 is a cross-sectional view of a semiconductor device structure according to an embodiment of the present disclosure.

[0056] FIG3 is a top view of a semiconductor device structure according to a first example of an embodiment of the present disclosure.

[0057] FIG4 is a top view of the first sub-electrode and the third sub-electrode in FIG3 .

[0058] FIG5 is a top view of the second sub-electrode and the fourth sub-electrode in FIG3 .

[0059] FIG. 6 is a top view of the first PIN device / the second PIN device in FIG. 3 .

[0060] FIG. 7 is a cross-sectional view taken along line AA′ in FIG. 3 .

[0061] FIG8 is a top view of another semiconductor device structure according to the first example of the embodiment of the present disclosure.

[0062] FIG. 9 is a top view of a second exemplary semiconductor device structure according to an embodiment of the present disclosure.

[0063] FIG10 is a cross-sectional view taken along line BB′ in FIG9 .

[0064] FIG11 is a top view of a semiconductor device structure according to a third example of an embodiment of the present disclosure.

[0065] FIG. 12 is a top view of the second PIN device in FIG. 11 .

[0066] FIG13 is a cross-sectional view taken along line CC′ in FIG11 .

[0067] FIG14 is a top view of another semiconductor device structure according to a third example of an embodiment of the present disclosure.

[0068] FIG15 is a top view of a semiconductor device structure according to a fourth example of an embodiment of the present disclosure.

[0069] FIG16 is a cross-sectional view taken along line DD′ in FIG15 .

[0070] FIG17 is a top view of another semiconductor device structure according to a fourth example of an embodiment of the present disclosure.

[0071] FIG18 is a cross-sectional view of the radio frequency switch according to an embodiment of the present disclosure.

[0072] FIG19 is a partial diagram of the connection between the semiconductor device structure and the transmission line.

[0073] FIG20 is a partial diagram of the connection between the capacitor and the transmission line.

[0074] FIG21 is a partial diagram of the connection between the inductor and the transmission line. DETAILED DESCRIPTION

[0075] In order to enable those skilled in the art to better understand the technical solution of the present invention, the present invention is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0076] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0077] Figure 1 is a cross-sectional view of an exemplary semiconductor device structure. As shown in Figure 1 , the semiconductor device structure includes a substrate 1, at least one PIN cell disposed on the substrate 1, a first connection electrode 40, and a second connection electrode 50. Figure 1 illustrates only a cross-sectional view of a single PIN cell, which includes a P-type semiconductor 10, an I-type semiconductor 20, and an N-type semiconductor 30 disposed side by side in the same layer. A gate insulating layer 3 and an interlayer insulating layer 2 are sequentially disposed on the side of the PIN cell facing away from the substrate 1. The first connection electrode 40 is connected to the P-type semiconductor 10 via a via extending through the gate insulating layer 3 and the interlayer insulating layer 2. The second connection electrode 50 is connected to the N-type semiconductor 30 via a via extending through the gate insulating layer 3 and the interlayer insulating layer 2.

[0078] It should be noted that two insulating layers are provided between the first and second connecting electrodes 40, 50 and the layer where the PIN unit is located because a semiconductor active layer of a thin-film transistor may also be formed on the substrate at the same time as the PIN unit is formed. In other words, a substrate with an integrated semiconductor device structure may include not only the device structure but also other electrical components. Therefore, multiple insulating layers may exist between the first and second connecting electrodes 40, 50 and the layer where the PIN unit is located. Of course, it should be understood that a single insulating layer between the first and second connecting electrodes 40, 50 and the layer where the PIN unit is located is also sufficient.

[0079] The specific materials of the P-type semiconductor 10, I-type semiconductor 20, and N-type semiconductor 30 in the PIN unit are not particularly limited, and those skilled in the art can select them according to the use requirements of the PIN unit. In the embodiment of the present disclosure, the materials of the P-type semiconductor 10, I-type semiconductor 20, and N-type semiconductor 30 can all be low-temperature polycrystalline silicon (LTPS). In some examples, the P-type semiconductor 10 can be doped with B 3+ The N-type semiconductor 30 may be a doped P 3+ Thus, the P-type semiconductor 10 and the N-type semiconductor 30 made of the above materials can form a PIN unit with the highest photoelectric conversion efficiency.

[0080] The inventors discovered that due to the limitations of the LTPS process structure, the current thickness of LTPS can only be 50nm, which results in a relatively large resistance of the lateral semiconductor device structure. For RF switches using semiconductor device structures, the on-state resistance Ron and off-state capacitance Coff of the semiconductor device structure are the main parameters that determine the performance of the switch. The ideal device should have a low Ron*Coff value. The current ideal value should be around 1ps (ohm*pF) to meet the needs of 3.5GHz RF switches. However, devices based on the existing LTPS process can only reach 3ps. How to further reduce the Ron*Coff value is a technical problem that urgently needs to be solved.

[0081] In response to the above technical problems, the embodiments of the present disclosure provide the following technical solutions.

[0082] In a first aspect, FIG2 is a cross-sectional view of a semiconductor device structure according to an embodiment of the present disclosure. As shown in FIG2 , an embodiment of the present disclosure provides a semiconductor device structure comprising a substrate 1, and at least one PIN unit, a first connection electrode 40, and a second connection electrode 50 disposed on the substrate 1. The PIN unit comprises a plurality of PIN devices arranged sequentially in a direction away from the substrate 1. Each PIN device comprises a P-type semiconductor 10, an I-type semiconductor 20, and an N-type semiconductor 30 arranged in parallel in a first direction and in the same layer. The orthographic projections of the I-type semiconductors 20 of any two PIN devices in the PIN unit on the substrate 1 at least partially overlap. The P-type semiconductor 10 of each PIN device is electrically connected to the first connection electrode 40, and the N-type semiconductor 30 of each PIN device is connected to the second connection electrode 50.

[0083] In the embodiment of the present disclosure, the PIN devices in each PIN unit are designed to be multiple stacked, and the orthographic projections of the I regions of each PIN device on the substrate 1 at least partially overlap, so as to increase the thickness of the I region in each PIN unit. This can effectively reduce the resistance of each PIN unit and simultaneously reduce the off-state capacitance C of the PIN unit, thereby improving the performance of the RF switch using this semiconductor device structure.

[0084] It should be noted that, referring to Figure 2, a buffer layer 4 is provided between the PIN unit and the substrate 1. The buffer layer can be a single-layer structure of silicon nitride or silicon oxide material, or a composite film structure of silicon nitride / silicon oxide. The provision of the buffer layer 4 facilitates the subsequent formation of the PIN device. It should also be noted that the semiconductor device structure of the embodiment of the present disclosure can be used in photoelectric detection and can also be used as a rectifier circuit. The application scenario of the semiconductor device structure is not limited here.

[0085] In some examples, the PIN devices in the PIN unit adopt the same structure, and the orthographic projections of the I regions of the PIN devices on the substrate 1 completely overlap. Accordingly, the P-type semiconductor 10 and the N-type semiconductor 30 of each PIN device are correspondingly arranged. In this case, the PIN devices are equivalent to an integral structure. For the entire PIN unit, compared with a structure with only one PIN device, the thickness of the I-type semiconductor 20 is increased, thereby effectively reducing the resistance of each PIN unit.

[0086] In some examples, the film thickness of the PIN cell is about 50 nm.

[0087] In the embodiments of the present disclosure, there is no limit on the number of PIN devices in each PIN unit. However, considering the overall thickness and cost of the device, a PIN unit comprising two PIN devices may be used. For ease of description and a clearer understanding of the semiconductor device structure of the embodiments of the present disclosure, as shown in FIG2 , each PIN unit is assumed to include only two PIN devices. For ease of description, the one of the two PIN devices in each PIN unit that is closer to the substrate 1 is referred to as the first PIN device, and the other is referred to as the second PIN device. The P-type semiconductor 10, I-type semiconductor 20, and N-type semiconductor 30 in the first PIN device are referred to as the first P-type semiconductor 11, the first I-type semiconductor 21, and the first N-type semiconductor 31, respectively. The P-type semiconductor 10, I-type semiconductor 20, and N-type semiconductor 30 in the second PIN device are referred to as the second P-type semiconductor 12, the second I-type semiconductor 22, and the second N-type semiconductor 32, respectively. The interlayer insulating layer 2 between the first and second PIN devices is referred to as the first interlayer insulating layer 21. The first connection electrode 40 and the second connection electrode 50 can both be disposed on a side of the layer where the PIN unit is located that is away from the substrate 1. In this case, a second interlayer insulating layer 22 is disposed between the first connection electrode 40, the second connection electrode 50, and the PIN unit. The first P-type semiconductor 11 and the second P-type semiconductor 12 are both connected to the first connection electrode 40, and the first N-type semiconductor 31 and the second N-type semiconductor 32 are both connected to the second connection electrode 50.

[0088] It should be noted that the connection between the first P-type semiconductor 11 and the second P-type semiconductor 12 and the first connecting electrode 40, as well as the connection between the first N-type semiconductor 31 and the second N-type semiconductor 32 and the second connecting electrode 50 need to be specifically designed in combination with the first connecting electrode 40 and the second connecting electrode 50. For details, please refer to the introduction below.

[0089] In some examples, the first connection electrode 40 and the second connection electrode 50 may both adopt a single-layer conductive structure, or a double-layer conductive structure. When the first connection electrode 40 and the second connection electrode 50 adopt a double-layer structure, the resistance can be further effectively reduced.

[0090] For example: when the first connecting electrode 40 and the second connecting electrode 50 both adopt a single-layer structure, the first connecting electrode 40 can be connected to the second P-type semiconductor 12 through a via hole penetrating the second interlayer insulating layer 22, and the first connecting electrode 40 is connected to the first P-type semiconductor 11 through a via hole penetrating the second interlayer insulating layer 22, the second P-type semiconductor 12 and the first interlayer insulating layer 21; the second connecting electrode 50 is connected to the second N-type semiconductor 32 through a via hole penetrating the second interlayer insulating layer 22, and the second connecting electrode 50 is connected to the first N-type semiconductor 31 through a via hole penetrating the second interlayer insulating layer 22, the second N-type semiconductor 32 and the first interlayer insulating layer 21.

[0091] For example, when both the first connection electrode 40 and the second connection electrode 50 adopt a double-layer structure, the first connection electrode 40 may include a first sub-electrode 41 and a second sub-electrode 42 sequentially arranged along a surface facing away from the base substrate 1, and the second connection electrode 50 may include a third sub-electrode 51 and a fourth sub-electrode 52 sequentially arranged along a surface facing away from the base substrate 1. In this case, the first sub-electrode 41 and the third sub-electrode 51 may be arranged on the same layer, and the second sub-electrode 42 and the fourth sub-electrode 52 may be arranged on the same layer, and a third interlayer insulating layer 23 is provided between the first sub-electrode 41 and the second sub-electrode 42, the second sub-electrode 42 is connected to the first sub-electrode 41 via a via hole penetrating the third interlayer insulating layer 23, and the fourth sub-electrode 52 is connected to the third sub-electrode 51 via a via hole penetrating the third interlayer insulating layer 23. The first sub-electrode 41 can be connected to the second P-type semiconductor 12 through a via hole penetrating the second interlayer insulating layer 22, and the first sub-electrode 41 is connected to the first P-type semiconductor 11 through a via hole penetrating the second interlayer insulating layer 22, the second P-type semiconductor 12 and the first interlayer insulating layer 21; the third sub-electrode 51 is connected to the second N-type semiconductor 32 through a via hole penetrating the second interlayer insulating layer 22, and the third sub-electrode 51 is connected to the first N-type semiconductor 31 through a via hole penetrating the second interlayer insulating layer 22, the second N-type semiconductor 32 and the first interlayer insulating layer 21.

[0092] In some examples, the number of PIN units in the embodiments of the present disclosure may be one or more. When there are multiple PIN units, the multiple PIN units can be connected in parallel to further reduce the resistance of the device. In the embodiments of the present disclosure, only the case of multiple PIN units connected in parallel is used as an example.

[0093] Specifically, the number of PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the first P-type semiconductor 11 of the i-th PIN unit is shared with the i-1-th first P-type semiconductor 11, and the second P-type semiconductor 12 of the i-th PIN unit is shared with the i-1-th second P-type semiconductor 12; the first N-type semiconductor 31 of the i-th PIN unit is shared with the i+1-th first N-type semiconductor 31, and the second N-type semiconductor 32 of the i-th PIN unit is shared with the i+1-th second N-type semiconductor 32; N≥3, and N is a positive integer, and i is 1 to (N-1).

[0094] In some examples, when there are multiple PIN cells, both the first connection electrode 40 and the second connection electrode 50 are comb-shaped electrodes, and the branches of the first connection electrode 40 are arranged corresponding to the first P-type semiconductor 11 and the second P-type semiconductor 12, while the branches of the second connection electrode 50 are arranged corresponding to the first N-type semiconductor 31 and the second N-type semiconductor 32. The following describes in detail the semiconductor device structure of the present disclosure in conjunction with examples in which the first connection electrode 40 and the second connection electrode 50 have a single-layer structure and a double-layer structure, respectively.

[0095] First Example: Figure 3 is a top view of a semiconductor device structure according to the first example of the presently disclosed embodiment; Figure 4 is a top view of the first sub-electrode 41 and the third sub-electrode 51 in Figure 3; Figure 5 is a top view of the second sub-electrode 42 and the fourth sub-electrode 52 in Figure 3; Figure 6 is a top view of the first PIN device / second PIN device in Figure 3; and Figure 7 is a cross-sectional view taken along line AA' in Figure 3. As shown in Figures 3-7, the semiconductor device structure includes a plurality of PIN units arranged side by side along a first direction, and the plurality of PIN units are connected in parallel. Each PIN unit includes the first and second PIN devices described above. The first connecting electrode 40 and the second connecting electrode 50 both have a double-layer structure; the first connecting electrode 40 includes a first sub-electrode 41 and a second sub-electrode 42 arranged sequentially in a direction away from the substrate 1; the second connecting electrode 50 includes a third sub-electrode 51 and a fourth sub-electrode 52 arranged sequentially in a direction away from the substrate 1. A second interlayer insulating layer 22 is provided on the side of the second PIN device facing away from the dielectric substrate. The first sub-electrode 41 and the third sub-electrode 51 are provided on the same layer. A third interlayer insulating layer 23 is provided on the side of the layer containing the first sub-electrode 41 facing away from the base substrate 1. The PIN unit also includes a first via VIA1, a second via VIA2, a third via VIA3, a fourth via VIA4, a fifth via VIA5, and a sixth via VIA6. The first via VIA1 extends through the second P-type semiconductor 12 and the first interlayer insulating layer 21; the second via VIA2 and the fifth via VIA5 both extend through the second interlayer insulating layer 22; the third via VIA3 and the sixth via VIA6 both extend through the third interlayer insulating layer 23; and the fourth via VIA4 extends through the second N-type semiconductor 32 and the first interlayer insulating layer 21. The first sub-electrode 41 is electrically connected to the second P-type semiconductor 12 through the second via VIA2. The first P-type semiconductor 11 in the PIN cell is electrically connected to the second P-type semiconductor 12 through the first via VIA1. The second sub-electrode 42 is electrically connected to the first sub-electrode 41 through the third via VIA3. The third sub-electrode 51 is electrically connected to the second N-type semiconductor 32 through the fifth via VIA5. The first N-type semiconductor 31 in the PIN cell is electrically connected to the second N-type semiconductor 32 through the fourth via VIA4. The fourth sub-electrode 52 is electrically connected to the third sub-electrode 51 through the sixth via VIA6.

[0096] Specifically, the first sub-electrode 41, the second sub-electrode 42, the third sub-electrode 51, and the fourth sub-electrode 52 can all be comb-shaped electrodes. For example, the first sub-electrode 41 includes a plurality of first branches 411 and a first connecting portion 412 connected to the plurality of first branches 411; the second sub-electrode 42 includes a plurality of second branches 421 and a second connecting portion 422 connected to the plurality of second branches 421; the third sub-electrode 51 includes a plurality of third branches 511 and a third connecting portion 512 connected to the plurality of third branches 511; and the fourth sub-electrode 52 includes a plurality of fourth branches 521 and a fourth connecting portion 522 connected to the plurality of fourth branches 521. The orthographic projections of the first connecting portion 412 and the second connecting portion 422 on the substrate 1 are located on the same side (the left side in Figures 4 and 5 ) of the orthographic projection of the PIN unit on the substrate 1. The orthographic projections of the third connecting portion 512 and the fourth connecting portion 522 on the substrate 1 are located on the same side (the right side in Figures 4 and 5 ) of the orthographic projection of the PIN unit on the substrate 1. Furthermore, the orthographic projections of the first connecting portion 412 and the third connecting portion 512 on the substrate 1 are located on different sides of the orthographic projection of the PIN unit on the substrate 1. For example, the orthographic projections of the first connecting portion 412 and the second connecting portion 422 on the substrate 1 overlap with the orthographic projection of the PIN unit on the substrate 1. The orthographic projections of the third connecting portion 512 and the fourth connecting portion 522 on the substrate 1 overlap with the orthographic projection of the PIN unit on the substrate 1, and do not overlap with the orthographic projections of the first connecting portion 412 and the third connecting portion 512 on the substrate 1 on the substrate 1.

[0097] The first branch 411 and the second branch 421 are provided in a one-to-one correspondence. For the corresponding first branch 411 and the second branch 421, the first branch 411 is connected to the first P-type semiconductor 11 through the first via VIA1 and to the second P-type semiconductor 12 through the second via VIA2. The second branch 421 is connected to the first branch 411 through the third via VIA3. Similarly, the third branch 511 and the fourth branch 521 are provided in a one-to-one correspondence. For the corresponding third branch 511 and the fourth branch 521, the third branch 511 is connected to the first N-type semiconductor 31 through the fourth via VIA4 and to the second N-type semiconductor 32 through the fourth via VIA4. The fourth branch 521 is connected to the third branch 511 through the sixth via VIA6.

[0098] Furthermore, for each PIN device, the first via VIA1 and the second via VIA2 are arranged in a one-to-one correspondence, and for the corresponding first via VIA1 and second via VIA2, the orthographic projection of the first via VIA1 on the substrate 1 is located within the orthographic projection of the second via VIA2 on the substrate 1. Similarly, the fourth via VIA4 and the fifth via VIA5 are arranged in a one-to-one correspondence, and for the corresponding fourth via VIA4 and fifth via VIA5, the orthographic projection of the fourth via VIA4 on the substrate 1 is located within the orthographic projection of the fifth via VIA5 on the substrate 1. In other words, the first via VIA1 and the second via VIA2 are nested, and the fourth via VIA4 and the fifth via VIA5 are nested.

[0099] Furthermore, when the first via VIA1 and the second via VIA2 correspond one-to-one and are nested, and the fourth via VIA4 and the fifth via VIA5 correspond one-to-one and are nested, for one PIN unit, the number of the first via VIA1, the second via VIA2, the third via VIA3, the fourth via VIA4, the fifth via VIA5 and the sixth via VIA6 are all multiple, and the orthographic projections of the second via VIA2 and the third via VIA3 on the dielectric substrate are alternately arranged, and the orthographic projections of the fifth via VIA5 and the sixth via VIA6 on the dielectric substrate are alternately arranged.

[0100] In one example, referring to Figure 3 , for a PIN unit, at least a portion of the first via VIA1 and the fourth via VIA4 are arranged side by side along the first direction, at least a portion of the second via VIA2 and the fifth via VIA5 are arranged side by side along the first direction, and at least a portion of the third via VIA3 and the sixth via VIA6 are arranged side by side along the first direction. In this case, the vias in the device are arranged in an array. For example, the first via VIA1 and the fourth via VIA4 located in the middle region of the PIN unit are arranged side by side along the first direction, the second via VIA2 and the fifth via VIA5 are arranged side by side along the first direction, and the third via VIA3 and the sixth via VIA6 are arranged side by side along the first direction.

[0101] In another example, Figure 8 is a top view of another semiconductor device structure according to the first example of the embodiment of the present disclosure. Referring to Figure 8 , for a PIN unit, the first via VIA1 and the fourth via VIA4 are arranged alternately along the first direction, the second via VIA2 and the fifth via VIA5 are arranged alternately along the first direction, and the third via VIA3 and the sixth via VIA6 are arranged alternately along the first direction. This arrangement can appropriately increase the spacing between adjacent branch openings, reducing the parasitic capacitance C generated by the vias connecting to the conductive structure at that location.

[0102] Regardless of any of the above via arrangement methods, the orthographic projections of the centers of the corresponding first via VIA1 and second via VIA2 on the substrate 1 coincide with each other; and the orthographic projections of the centers of the corresponding fourth via VIA4 and fifth via VIA5 on the substrate 1 coincide with each other. This approach can reduce the space occupied by the vias in the device.

[0103] In addition, for a PIN unit, the orthographic projections of the first via VIA1 and the second via VIA2 on the base substrate 1 are both larger than the orthographic projection of the third via VIA3 on the base substrate 1. Similarly, the orthographic projections of the fourth via VIA4 and the fifth via VIA5 on the base substrate 1 are both larger than the orthographic projection of the sixth via VIA6 on the base substrate 1.

[0104] For one PIN unit, the width of the orthographic projection of the third via VIA3 on the substrate 1 in the first direction is approximately equal to the width of the orthographic projection of the first branch 411 on the substrate 1 in the first direction; and / or the width of the orthographic projection of the sixth via VIA6 on the substrate 1 in the first direction is approximately equal to the width of the orthographic projection of the third branch 511 on the substrate 1 in the first direction. This arrangement can ensure a more reliable connection between the first branch 411 and the second branch 421, and a more reliable connection between the third branch 511 and the fourth branch 521.

[0105] In some examples, when the first branch 411 and the second branch 421 are arranged in a one-to-one correspondence, the center lines of the corresponding first branch 411 and second branch 421 in their respective trace directions coincide with the orthographic projection of the center line of the first P-type semiconductor 11 in its trace direction on the substrate 1. When the third sub-electrode 51 includes at least one third branch 511 and the fourth sub-electrode 52 includes at least one fourth branch 521, and the third branch 511 and the fourth branch 521 are arranged in a one-to-one correspondence, the center lines of the corresponding third branch 511 and fourth branch 521 in their respective trace directions coincide with the orthographic projection of the center line of the first N-type semiconductor 31 in its trace direction on the substrate 1. It should be noted that the trace direction refers to the path direction of the structure. For example, the trace direction of a straight-line structure is a straight line, and the trace direction of a serpentine-line structure is a serpentine line.

[0106] Furthermore, referring to Figures 3 and 7 , the orthographic projections of the first branch 411 of the first sub-electrode 41 and the second branch 421 of the second sub-electrode 42 on the substrate 1 completely overlap, and the orthographic projections of the first connecting portion 412 and the second connecting portion 422 on the substrate 1 overlap. The first branch 411 of the first sub-electrode 41 overlaps with the orthographic projection of the first P-type semiconductor 11 on the substrate 1, or the width of the orthographic projection of the first branch 411 on the substrate 1 along the first direction is slightly narrower than the width of the orthographic projection of the first P-type semiconductor 11 on the substrate 1 along the first direction. Similarly, the orthographic projections of the third branch 511 of the third sub-electrode 51 and the fourth branch 521 of the fourth sub-electrode 52 on the substrate 1 completely overlap, and the orthographic projections of the third connecting portion 512 and the fourth connecting portion 522 on the substrate 1 overlap. The third branch 511 of the third sub-electrode 51 overlaps with the orthographic projection of the first N-type semiconductor 31 on the substrate 1, or the width of the orthographic projection of the third branch 511 on the substrate 1 along the first direction is slightly narrower than the width of the orthographic projection of the first N-type semiconductor 31 on the substrate 1 along the first direction. This configuration is because the I-type semiconductor 20 acts like a channel region, carrying the voltage on the switch, while the P-type semiconductor 10 and the N-type semiconductor 30 serve as electrode lead-out regions with a high doping concentration, creating an ohmic contact with the metal electrode. If the heavily doped region is smaller than the branch shape, this will cause the I-type semiconductor 20 to contact the branch, and the undoped intrinsic silicon will contact the metal to form a Schottky junction, affecting the characteristics of the PIN diode in the low-voltage operating state. Considering the issue of exposure alignment accuracy, the PN heavily doped region is generally made slightly larger than the branch pattern.

[0107] Second example: FIG9 is a top view of the semiconductor device structure of the second example of the embodiment of the present disclosure; FIG10 is a cross-sectional view taken along line BB' of FIG9; as shown in FIG9 and FIG10, the structure of this example is substantially the same as that of the first example, with the only difference being that, in this example, the first branch 411 of the first sub-electrode 41 and the second branch 421 of the second sub-electrode 42 have different widths. The third branch 511 of the third sub-electrode 51 and the fourth branch 521 of the fourth sub-electrode 52 have different widths. For example, the width of the second branch 421 is smaller than the width of the first branch 411, and the width of the fourth branch 521 is smaller than the width of the third branch 511. In this way, the spacing between the branch electrodes can be increased, and the generation of parasitic capacitance C can be reduced.

[0108] For other structures in this example, the same structure as the first example can be adopted, so they will not be repeated here.

[0109] The third example: Figure 11 is a top view of a semiconductor device structure of the third example of the embodiment of the present disclosure; Figure 12 is a top view of the second PIN device in Figure 11; Figure 13 is a cross-sectional view of CC' in Figure 11; as shown in Figures 11-13, the structure of this example is roughly the same as that of the first example, the difference is that, in this example, the first connecting electrode 40 and the second connecting electrode 50 adopt a single-layer structure. Each PIN unit includes a first via VIA1, a second via VIA2, a third via VIA3 and a fourth via VIA4; the first via VIA1 and the third via VIA3 both penetrate the second P-type semiconductor 12, the first interlayer insulating layer 21 and the second interlayer insulating layer; the second via VIA2 and the fourth via VIA4 both penetrate the second interlayer insulating layer 22; the first connecting electrode 40 is connected to the first P-type semiconductor 11 through the first via VIA1, and is connected to the second P-type semiconductor 12 through the second via VIA2; the second connecting electrode 50 is connected to the first N-type semiconductor 31 through the third via VIA3, and is connected to the second N-type semiconductor 32 through the fourth via VIA4.

[0110] In this example, the first and second vias VIA1 and VIA2 in the PIN cell are discrete vias, while the third and fourth vias VIA3 and VIA4 are discrete vias. In this structure, since only one second interlayer insulating layer 22 is provided between the first and second connecting electrodes 40 and 50 and the PIN cell, and the first and second connecting electrodes 40 and 50 are single-layer structures, the first, second, third, and fourth vias VIA1, VIA2, VIA3, and VIA4 can be fabricated in a single process.

[0111] In one example, the PIN unit includes multiple first via VIA1 groups and multiple second via VIA2 groups; the first via VIA1 group includes one first via VIA1 and two second vias VIA2, and the two second vias VIA2 are arranged on both sides of the first via VIA1 that are opposite to each other in the first direction; the second via VIA2 group includes one third via VIA3 and two fourth vias VIA4, and the two fourth vias are arranged on both sides of the third via VIA3 that are opposite to each other in the first direction.

[0112] Furthermore, referring to Figure 11 , the first via group VIA1 and the second via group VIA2 in the PIN unit can be arranged side by side along the first direction. Figure 14 is a top view of another semiconductor device structure according to a third example of an embodiment of the present disclosure. Referring to Figure 14 , the first via group VIA1 and the second via group VIA2 in the PIN unit can also be arranged alternately along the first direction. This arrangement increases the spacing between the vias, thereby reducing the generation of parasitic capacitance C.

[0113] In some examples, both the first connecting electrode 40 and the second connecting electrode 50 can be comb-shaped electrodes. For example, the first connecting electrode 40 includes multiple first branch structures 401 and a first main structure 402 connecting the first branch structures 401. Each first branch structure 401 is connected to the first P-type semiconductor 11 via a first via VIA1 and to the second P-type semiconductor 12 via a second via VIA2. Similarly, the second connecting electrode 50 includes multiple second branch structures 501 and a second main structure 502 connecting the second branch structures 501. The second branch structures 501 are connected to the first N-type semiconductor 31 via a fourth via VIA4 and to the second N-type semiconductor 32 via a fourth via VIA4. The orthographic projections of the first main structure 402 and the second main structure 502 on the substrate 1 are located on different sides of the orthographic projection of the PIN unit on the substrate 1.

[0114] Furthermore, when the first connecting electrode 40 includes a first branch structure 401, the orthographic projections of the first branch structure 401 and the corresponding first P-type semiconductor 11 along a centerline extending perpendicular to the first direction on the substrate 1 overlap; when the second connecting electrode 50 includes a second branch structure 501, the orthographic projections of the second branch structure 501 and the corresponding first N-type semiconductor 31 along a centerline extending perpendicular to the first direction on the substrate 1 overlap. For example, when the first connecting electrode 40 includes a first branch structure 401, the orthographic projections of the first branch structure 401 and the corresponding first P-type semiconductor 11 on the substrate 1 completely overlap; when the second connecting electrode 50 includes a second branch structure 501, the orthographic projections of the second branch structure 501 and the corresponding first N-type semiconductor 31 on the substrate 1 completely overlap.

[0115] Furthermore, referring to Figure 11 , the first via group VIA1 and the second via group VIA2 in the PIN unit can be arranged side by side along the first direction. Figure 14 is a top view of another semiconductor device structure according to a third example of an embodiment of the present disclosure. Referring to Figure 14 , the first via group VIA1 and the second via group VIA2 in the PIN unit can also be arranged alternately along the first direction. This arrangement increases the spacing between the vias, thereby reducing the generation of parasitic capacitance C.

[0116] For this example, other structures can adopt the same structure as the first example, so they will not be repeated here.

[0117] Fourth example: FIG15 is a top view of a semiconductor device structure of the fourth example of the embodiment of the present disclosure; FIG16 is a cross-sectional view taken along line DD′ of FIG15 ; as shown in 15 and 16 , this example has substantially the same structure as the third example, with the only difference being that the first via VIA1 and the second via VIA2 in the first via VIA1 group are connected, and the third via VIA3 and the second via VIA2 in the second via VIA2 group are connected. In this case, etching a larger via is equivalent to simultaneously connecting the first connecting electrode 40 and the first P-type semiconductor 11 and the second P-type semiconductor 12. Similarly, etching a larger via is simultaneously connecting the second connecting electrode 50 and the first N-type semiconductor 31 and the second N-type semiconductor 32.

[0118] Furthermore, referring to Figure 15 , the first via group VIA1 and the second via group VIA2 in the PIN unit can be arranged side by side along the first direction. Figure 17 is a top view of another semiconductor device structure according to a fourth example of an embodiment of the present disclosure. Referring to Figure 17 , the first via group VIA1 and the second via group VIA2 in the PIN unit can also be arranged alternately along the first direction. This arrangement increases the spacing between the vias, thereby reducing parasitic capacitance C.

[0119] For this example, other structures can adopt the same structure as the third example, so they will not be repeated here.

[0120] On the second aspect, Figure 18 is a cross-sectional view of the RF switch of an embodiment of the present disclosure; as shown in Figure 18, the embodiment of the present disclosure provides a RF switch, which includes a transmission line 100 and a semiconductor device structure arranged on the transmission line 100, and the semiconductor device structure is any of the above-mentioned semiconductor device structures.

[0121] The transmission line 100 may be a coplanar waveguide (CPW) transmission line 100. Specifically, the transmission line includes a signal electrode 101, and first and second reference electrodes 102 and 103 disposed on either side of the signal electrode 101. The first and second reference electrodes 102 and 103 may be ground electrodes. The transmission line 100 may be disposed on the same layer as the first and second connection electrodes 40 and 50.

[0122] Furthermore, when the first connection electrode 40 and the second connection electrode 50 adopt a double-layer structure, the transmission line 100 can be provided in the same layer as the second sub-electrode 42 and the fourth sub-electrode 52 .

[0123] In some examples, the RF switch further includes a capacitor C and an inductor L. The coil structure of the inductor L and the second plate of the capacitor C can be disposed on the same layer as the transmission line 100 .

[0124] Specifically, Figure 19 is a partial diagram of the connection between a semiconductor device structure and a transmission line; Figure 20 is a partial diagram of the connection between a capacitor and a transmission line; and Figure 21 is a partial diagram of the connection between an inductor and a transmission line. As shown in Figures 19-21, transmission line 100 is a coplanar waveguide (CPW) transmission line 100, in which a signal electrode 101 is electrically connected to a semiconductor device PIN. Signal electrode 101 is electrically connected to one plate of the capacitor and can also be electrically connected to one lead terminal of the inductor.

[0125] In a third aspect, embodiments of the present disclosure provide an electronic device. The radio frequency switch described above can be used in the electronic device. The electronic device can be an antenna.

[0126] In some examples, the electronic device also includes a transceiver unit, a radio frequency transceiver, a signal amplifier, a power amplifier, and a filtering unit. The antenna in the communication device can be used as a transmitting antenna or a receiving antenna. The transceiver unit may include a baseband and a receiving end. The baseband provides signals of at least one frequency band, such as 2G signals, 3G signals, 4G signals, 5G signals, etc., and transmits the signals of at least one frequency band to the radio frequency transceiver. After the antenna in the communication system receives the signal, it can be processed by the filtering unit, power amplifier, signal amplifier, and radio frequency transceiver and then transmitted to the receiving end in the transceiver unit. The receiving end may be, for example, a smart gateway.

[0127] Furthermore, a radio frequency transceiver is connected to the transceiver unit and is used to modulate the signals sent by the transceiver unit or to demodulate the signals received by the antenna and transmit them back to the transceiver unit. Specifically, the radio frequency transceiver may include a transmitting circuit, a receiving circuit, a modulation circuit, and a demodulation circuit. After the transmitting circuit receives various types of signals provided by the baseband, the modulation circuit can modulate these various types of signals provided by the baseband and then transmit them to the antenna. The antenna receives the signal and transmits it to the receiving circuit of the radio frequency transceiver. The receiving circuit transmits the signal to the demodulation circuit, which demodulates the signal and transmits it to the receiving end.

[0128] Furthermore, the RF transceiver is connected to a signal amplifier and a power amplifier, which are then connected to a filtering unit, which is connected to at least one antenna. When the communication system transmits signals, the signal amplifier is used to increase the signal-to-noise ratio of the signal output by the RF transceiver before transmitting it to the filtering unit. The power amplifier is used to amplify the power of the signal output by the RF transceiver before transmitting it to the filtering unit. The filtering unit may specifically include a duplexer and a filtering circuit. The filtering unit combines the signals output by the signal amplifier and the power amplifier, filters out noise, and then transmits them to the antenna, which radiates the signal. When the communication system receives signals, the antenna receives the signal and transmits it to the filtering unit. The filtering unit filters out noise from the signal received by the antenna and transmits it to the signal amplifier and power amplifier. The signal amplifier amplifies the signal received by the antenna to increase the signal-to-noise ratio. The power amplifier amplifies the power of the signal received by the antenna. The signal received by the antenna is processed by the power amplifier and the signal amplifier before being transmitted to the RF transceiver, which then transmits it to the transceiver unit.

[0129] In some examples, the signal amplifier may include various types of signal amplifiers, such as a low noise amplifier, which is not limited herein.

[0130] In some examples, the electronic device provided by the embodiments of the present disclosure further includes a power management unit, which is connected to a power amplifier and provides the power amplifier with a voltage for amplifying a signal.

[0131] It will be understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present invention, and the present invention is not limited thereto. Those skilled in the art will appreciate that various modifications and improvements can be made without departing from the spirit and substance of the present invention, and such modifications and improvements are also considered to be within the scope of protection of the present invention.

Claims

1. A semiconductor device structure, comprising a substrate, and at least one PIN unit, a first connection electrode and a second connection electrode arranged on the substrate; wherein: The PIN unit comprises a plurality of PIN devices arranged in sequence in a direction away from the substrate, and an interlayer insulating layer is arranged between the layers where the adjacent PIN devices are located; the PIN devices comprise a P-type semiconductor, an N-type semiconductor and an I-type semiconductor arranged side by side in the same layer and in a first direction, and the I-type semiconductor is located between the P-type semiconductor and the N-type semiconductor; In the PIN unit, the orthographic projections of the I-type semiconductors of any two of the PIN devices on the substrate at least partially overlap; The first connection electrode and the second connection electrode are located on a side of the PIN unit away from the dielectric substrate, and the P-type semiconductor of each PIN device is connected to the first connection electrode, and the N-type semiconductor of each PIN device is connected to the second connection electrode.

2. The semiconductor device structure according to claim 1, wherein: The plurality of PIN devices in the PIN unit include a first PIN device and a second PIN device arranged in sequence in a direction away from the substrate; the interlayer insulating layer between the layer where the first PIN device is located and the layer where the second PIN device is located is a first interlayer insulating layer; The P-type semiconductor, N-type semiconductor and I-type semiconductor of the first PIN device are a first P-type semiconductor, a first N-type semiconductor and a first I-type semiconductor; the P-type semiconductor, N-type semiconductor and I-type semiconductor of the second PIN device are a second P-type semiconductor, a second N-type semiconductor and a second I-type semiconductor.

3. The semiconductor device structure according to claim 2, wherein: The first connecting electrode comprises a first sub-electrode and a second sub-electrode arranged in sequence along a direction away from the substrate; the second connecting electrode comprises a third sub-electrode and a fourth sub-electrode arranged in sequence along a direction away from the substrate; A second interlayer insulating layer is provided on a side of the second PIN device away from the dielectric substrate, the first sub-electrode and the third sub-electrode are provided on the same layer, and a third interlayer insulating layer is provided on a side of the layer where the first sub-electrode is located away from the base substrate; The PIN unit further includes a first via hole, a second via hole, a third via hole, a fourth via hole, a fifth via hole and a sixth via hole; the first via hole penetrates the second P-type semiconductor and the first interlayer insulating layer; The second via hole and the fifth via hole both penetrate the second interlayer insulating layer; The third via hole and the sixth via hole both penetrate the third interlayer insulating layer; the fourth via hole penetrates the second N-type semiconductor and the first interlayer insulating layer; The first sub-electrode is electrically connected to the second P-type semiconductor through the second via hole, and the first P-type semiconductor in the PIN unit is electrically connected to the second P-type semiconductor through the first via hole; the second sub-electrode is electrically connected to the first sub-electrode through the third via hole; The third sub-electrode is electrically connected to the second N-type semiconductor through the fifth via hole, the first N-type semiconductor in the PIN unit is electrically connected to the second N-type semiconductor through the fourth via hole; the fourth sub-electrode is electrically connected to the third sub-electrode through the sixth via hole.

4. The semiconductor device structure according to claim 3, wherein: For the PIN unit, an orthographic projection of the first via hole on the base substrate is located within an orthographic projection of the second via hole on the base substrate; And / or, the orthographic projection of the fourth via hole on the base substrate is located within the orthographic projection of the fifth via hole on the base substrate.

5. The semiconductor device structure according to claim 4, wherein: For the PIN unit, when the orthographic projection of the first via hole on the base substrate is located within the orthographic projection of the second via hole on the base substrate, the orthographic projections of the center of the first via hole and the center of the second via hole on the base substrate coincide with each other; When the orthographic projection of the fourth via hole on the base substrate is located within the orthographic projection of the fifth via hole on the base substrate, the orthographic projections of the center of the fourth via hole and the center of the fifth via hole on the base substrate coincide with each other.

6. The semiconductor device structure according to claim 4, wherein: For one PIN unit, the number of the first via hole, the second via hole, the third via hole, the fourth via hole, the fifth via hole and the sixth via hole are all multiple, and the orthographic projections of the second via hole and the third via hole on the dielectric substrate are alternately arranged, and the orthographic projections of the fifth via hole and the sixth via hole on the dielectric substrate are alternately arranged.

7. The semiconductor device structure according to claim 4, wherein: The number of the PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the first P-type semiconductor of the i-th PIN unit is shared with the i-1th first P-type semiconductor, and the second P-type semiconductor of the i-th PIN unit is shared with the i-1th second P-type semiconductor; the first N-type semiconductor of the i-th PIN unit is shared with the i+1th first N-type semiconductor, and the second N-type semiconductor of the i-th PIN unit is shared with the i+1th second N-type semiconductor; N≥3, and N is a positive integer, and i is 1 to (N-1).

8. The semiconductor device structure according to claim 7, wherein: The third via hole and the sixth via hole in the PIN unit are arranged alternately, and the first via hole and the fourth via hole are arranged alternately.

9. The semiconductor device structure according to claim 4, wherein: For one of the PIN units, the sizes of the orthographic projections of the first via hole and the second via hole on the base substrate are both larger than the size of the orthographic projection of the third via hole on the base substrate; and / or, The sizes of the orthographic projections of the fourth via hole and the fifth via hole on the base substrate are both larger than the size of the orthographic projection of the sixth via hole on the base substrate.

10. The semiconductor device structure according to claim 4, wherein: For one of the PIN units, a width of an orthographic projection of the third via hole on the substrate in the first direction is substantially equal to a width of an orthographic projection of the corresponding first sub-electrode on the substrate in the first direction; And / or, a width of an orthographic projection of the sixth via hole on the base substrate in the first direction is substantially equal to a width of an orthographic projection of the corresponding third sub-electrode on the base substrate in the first direction.

11. The semiconductor device structure according to any one of claims 3 to 10, wherein: The first sub-electrode includes at least one first branch, the second sub-electrode includes at least one second branch, and the first branch and the second branch are arranged in a one-to-one correspondence; for the first branch and the second branch arranged in a corresponding manner, the first branch is connected to the first P-type semiconductor through the first via hole, is connected to the second P-type semiconductor through the second via hole, and the second branch is connected to the first branch through the third via hole; and / or, The third sub-electrode includes at least one third branch, the fourth sub-electrode includes at least one fourth branch, and the third branch and the fourth branch are arranged in a one-to-one correspondence; for the correspondingly arranged third branch and the fourth branch, the third branch is connected to the first N-type semiconductor through the fourth via hole, and is connected to the second N-type semiconductor through the fourth via hole, and the fourth branch is connected to the third branch through the sixth via hole.

12. The semiconductor device structure according to claim 11, wherein: When the first sub-electrode includes at least one first branch, the second sub-electrode includes at least one second branch, and the first branch and the second branch are arranged in a one-to-one correspondence, for the first branch and the second branch arranged in a corresponding manner, the midlines of the first branch and the second branch in their respective trace directions coincide with the orthographic projection of the midline of the first P-type semiconductor in its trace direction on the substrate; When the third sub-electrode includes at least one third branch, the fourth sub-electrode includes at least one fourth branch, and the third branches and the fourth branches are arranged in a one-to-one correspondence, for the correspondingly arranged third branches and the fourth branches, the midlines of both in their respective trace directions coincide with the orthographic projection of the midline of the first N-type semiconductor in its trace direction on the substrate.

13. The semiconductor device structure according to claim 11, wherein: When the first sub-electrode includes a plurality of first branches and the second sub-electrode includes a plurality of second branches, the first sub-electrode further includes a first connecting portion, and each of the first branches is connected to the first connecting portion to form the first sub-electrode with a comb-shaped structure; the second sub-electrode further includes a second connecting portion, and each of the second branches is connected to the second connecting portion to form the second sub-electrode with a comb-shaped structure; When the third sub-electrode includes a plurality of third branches and the fourth sub-electrode includes a plurality of fourth branches, the third sub-electrode further includes a third connecting portion, and each of the third branches is connected to the third connecting portion to form the third sub-electrode with a comb-like structure; the fourth sub-electrode further includes a fourth connecting portion, and each of the fourth branches is connected to the fourth connecting portion to form the fourth sub-electrode with a comb-like structure; The orthographic projections of the first connection portion and the second connection portion on the substrate are located on the same side of the orthographic projection of the PIN unit on the substrate, and the orthographic projections of the third connection portion and the fourth connection portion on the substrate are located on the same side of the PIN unit on the substrate. The first connecting portion and the third connecting portion are located on the same side of the orthographic projection of the PIN unit on the substrate, and are located on different sides of the orthographic projection of the PIN unit on the substrate as the orthographic projections of the first connecting portion and the third connecting portion on the substrate.

14. The semiconductor device structure according to any one of claims 3 to 10, wherein: The orthographic projections of the first sub-electrode and the second sub-electrode on the base substrate completely overlap, or the orthographic projection of the second sub-electrode on the base substrate is located within the orthographic projection of the first sub-electrode on the base substrate.

15. The semiconductor device structure according to claim 11, wherein: The orthographic projections of the third sub-electrode and the fourth sub-electrode on the base substrate completely overlap, or the orthographic projection of the fourth sub-electrode on the base substrate is located within the orthographic projection of the third sub-electrode on the base substrate.

16. The semiconductor device structure according to claim 11, wherein: The orthographic projections of the first branch, the corresponding second branch, and the first P-type semiconductor on the substrate completely overlap; and / or the orthographic projections of the third branch, the corresponding fourth branch, and the first N-type semiconductor on the substrate completely overlap.

17. The semiconductor device structure according to claim 11, wherein: The orthographic projections of the first branch and the corresponding second branch on the substrate are both located within the orthographic projections of the first P-type semiconductor on the substrate, and the widths of the first branch and the corresponding second branch along the first direction are both smaller than the width of the first P-type semiconductor along the first direction; and / or, The orthographic projections of the third branch and the corresponding fourth branch on the substrate are both located within the orthographic projections of the first N-type semiconductor on the substrate, and the widths of the third branch and the corresponding fourth branch along the first direction are both smaller than the width of the first N-type semiconductor along the first direction.

18. The semiconductor device structure according to claim 2, wherein: A second interlayer insulating layer is provided on a side of the second PIN device away from the dielectric substrate; The PIN unit further includes a first via hole, a second via hole, a third via hole and a fourth via hole; the first via hole and the third via hole both penetrate the second P-type semiconductor, the first interlayer insulating layer and the second interlayer insulating layer; The second via hole and the fourth via hole both penetrate the second interlayer insulating layer; The first connection electrode is connected to the first P-type semiconductor through the first via hole, and is connected to the second P-type semiconductor through the second via hole; the second connection electrode is connected to the first N-type semiconductor through the third via hole, and is connected to the second N-type semiconductor through the fourth via hole.

19. The semiconductor device structure according to claim 18, wherein: The PIN unit includes multiple first via groups and multiple second via groups; the first via group includes one first via and two second vias, and the two second vias are arranged on two sides of the first via that are opposite to each other in the first direction; the second via group includes one third via and two fourth vias, and the two fourth vias are arranged on two sides of the third via that are opposite to each other in the first direction.

20. The semiconductor device structure according to claim 19, wherein: The first via hole and the second via hole in the first via hole group are connected to each other; and / or the third via hole and the fourth via hole in the second via hole group are connected to each other.

21. The semiconductor device structure according to claim 19 or 20, wherein: For the PIN unit, the first via group and the second via group are arranged alternately.

22. The semiconductor device structure according to claim 19, wherein: The number of the PIN units is N, and the N PIN units are arranged side by side along the first direction, wherein the first P-type semiconductor of the i-th PIN unit is shared with the i-1th first P-type semiconductor, and the second P-type semiconductor of the i-th PIN unit is shared with the i-1th second P-type semiconductor; the first N-type semiconductor of the i-th PIN unit is shared with the i+1th first N-type semiconductor, and the second N-type semiconductor of the i-th PIN unit is shared with the i+1th second N-type semiconductor; N≥3, and N is a positive integer, and i is 1 to (N-1).

23. The semiconductor device structure according to claim 22, wherein: The first connecting electrode includes a plurality of first branch structures and a first main body structure connecting the first branch structures; one of the first branch structures is connected to the first P-type semiconductor through the first via hole, and is connected to the second P-type semiconductor through the second via hole; and / or, The second connecting electrode includes a plurality of second branch structures and a second main body structure connecting the second branch structures; The second branch structure is connected to the first N-type semiconductor through the fourth via hole, and is connected to the second N-type semiconductor through the fourth via hole.

24. The semiconductor device structure according to claim 23, wherein: When the first connecting electrode includes a first branch structure, the first branch structure and the first P-type semiconductor corresponding thereto have their orthographic projections on the substrate coincident along a midline extending perpendicularly to the first direction; When the second connecting electrode includes a second branch structure, the second branch structure and the corresponding first N-type semiconductor have orthographic projections on the substrate coincident along a center line extending perpendicularly to the first direction.

25. The semiconductor device structure according to claim 23, wherein: When the first connecting electrode includes a plurality of first branch structures and a first main body structure, and the second connecting electrode includes a plurality of second branches and a second main body structure, the plurality of first branch structures and the first main body structure are connected to form a first connecting electrode with a comb-shaped structure, and the plurality of second branch structures and the second main body structure are connected to form a second connecting electrode with a comb-shaped structure; The orthographic projections of the first main structure and the second main structure on the base substrate are located on different sides of the orthographic projection of the PIN unit on the base substrate.

26. The semiconductor device structure according to claim 23, wherein: When the first connecting electrode includes a first branch structure, the first branch structure and the first P-type semiconductor corresponding thereto have their orthographic projections on the substrate completely overlap; When the second connecting electrode includes a second branch structure, the orthographic projections of the second branch structure and the first N-type semiconductor corresponding thereto on the substrate completely overlap.

27. A radio frequency switch, comprising a transmission line and a semiconductor device structure arranged on the transmission line, wherein the semiconductor device structure is the semiconductor device structure according to any one of claims 1 to 26.

28. The radio frequency switch according to claim 27, wherein: It also includes a capacitor and an inductor, both of which are connected to the transmission line.

29. An electronic device comprising the radio frequency switch according to claim 27 or 28.

Images