Back contact cell and manufacturing method therefor

Abstract

The present application relates to the technical field of back contact cells, and in particular to a back contact cell and a manufacturing method therefor. The back contact cell comprises a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a conductive film layer, wherein isolation grooves are formed in the conductive film layer. The back contact cell further comprises a plurality of insulating ink layers which are all disposed between the second semiconductor layer and the conductive film layer and arranged at intervals along a back surface in an X-axis direction, wherein the insulating ink layers are in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layers stretch across the edges of the side surfaces of second semiconductor opening regions and each have two ends extending respectively. The insulating ink layer satisfies the following conditions: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in raw materials of the insulating ink layer is not greater than 5%. The present application can effectively avoid electric leakage and improve the cell conversion efficiency and the cell yield, and the technological process of manufacturing is simpler.

Description

Back contact battery and manufacturing method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application with application number 202311444899.1 filed with the Chinese Patent Office on November 2, 2023, entitled “A back contact battery and its manufacturing method”, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application belongs to the technical field of back-contact batteries, and specifically relates to a back-contact battery and a method for manufacturing the same. Background Art

[0004] Back-contact cells using the Topcon process generally use a tunneling oxide layer as the first intrinsic semiconductor layer, a doped polycrystalline layer as the first conductive semiconductor layer, intrinsic amorphous silicon as the second intrinsic semiconductor layer, and doped amorphous / microcrystalline silicon as the second conductive semiconductor layer. The conductive film layer is etched in the upper area corresponding to the mask layer to form an isolation groove.

[0005] However, at the side edge of the second semiconductor opening region, there is a second conductive semiconductor layer (the resistivity of the second conductive semiconductor layer is about 10 -1 -10 9 Ω·cm, which is an N-type amorphous / microcrystalline silicon layer with a resistivity of about 10 -1 -10 3 Ω·cm, which is a P-type amorphous / microcrystalline silicon layer with a resistivity of about 10 4 -10 9 Ω·cm) and the first conductive semiconductor layer (the resistivity of the first conductive semiconductor layer is about 10 -3 Ω·cm) between the second intrinsic semiconductor layer (the resistivity of the second intrinsic semiconductor layer is about 10 5 -10 10 Ω·cm) insulation phenomenon. Because the first conductive semiconductor layer has very good conductivity, and the second intrinsic semiconductor layer has relatively low resistivity and very thin thickness (about 10nm), it is impossible to form good insulation between the first conductive semiconductor layer and the second conductive semiconductor layer. At the same time, the conductive film layer on the surface of the second semiconductor layer (conductive film layer resistivity ≤ 10 -4 Ω·cm) will cross the side edge of the second semiconductor opening region in the horizontal direction, making it easy for serious leakage to occur between the first semiconductor layer and the second semiconductor layer, thereby reducing the parallel resistance of the battery, and further reducing the battery conversion efficiency and battery yield.

[0006] CN116053331B relates to a back-contact cell, a method for manufacturing the same, and a photovoltaic module. The cell comprises a silicon substrate having a front and back surface, a first semiconductor layer having a second semiconductor opening region disposed on the back surface, and a second semiconductor layer. Furthermore, the cell comprises several insulating layers spaced apart along the X-axis of the back surface, the insulating layers being disposed on the outer surface of the second semiconductor layer. In the X-axis direction, the insulating layers extend across the side edges of the second semiconductor opening region and extend at both ends. Furthermore, the insulating layers are covered with a protective ink. However, this patent still suffers from the following shortcomings: the insulating properties of the edge protective ink are insufficient, failing to provide a good insulating effect. Therefore, the edge protective ink is used as an auxiliary layer in conjunction with an insulating film, which performs the primary insulating function, to reduce leakage. Furthermore, this patent takes into account the solvent diffusion that occurs after the protective ink is printed. Without the insulating film, the solvent would significantly increase the contact resistance between the transparent conductive film and the second semiconductor layer. This patent removes the insulating film outside the protective ink region through etching, thereby preventing the solvent from diffusing. However, etching and removing the insulating film outside the protective ink area will damage the first semiconductor layer and the second semiconductor layer, thereby reducing the battery conversion efficiency and battery yield.

[0007] Therefore, in the prior art, the battery structure of the back-contact battery cannot effectively avoid leakage and improve battery conversion efficiency and battery yield.

[0008] It should be noted that this part of the content of this application only provides background technology related to this application, and does not necessarily constitute prior art or public knowledge.

[0009] Summary of the Invention

[0010] The purpose of this application is to overcome the defect of the back-contact battery structure in the prior art that it is unable to effectively avoid leakage and improve battery conversion efficiency and battery yield, and to provide a back-contact battery and its manufacturing method, which can effectively avoid leakage and improve battery conversion efficiency and battery yield, and the manufacturing process is simpler.

[0011] In order to achieve the above-mentioned purpose, the present application provides a back-contact battery, comprising a silicon wafer, a first semiconductor layer having a second semiconductor opening area arranged on the back side of the silicon wafer, a second semiconductor layer arranged on the outer surface of the first semiconductor layer and in the second semiconductor opening area, the second semiconductor layer being provided with a first semiconductor opening area arranged at intervals with the second semiconductor opening area, and a conductive film layer arranged on the outer surface of the second semiconductor layer and in the first semiconductor opening area, an isolation groove being provided on the conductive film layer; and further comprising: an insulating ink layer, which is a plurality of layers and is all arranged between the second semiconductor layer and the conductive film layer and is arranged at intervals along the X-axis direction of the back side, and the insulating ink layer is in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layer spans the side edge of the second semiconductor opening area and extends at both ends respectively; wherein the insulating ink layer satisfies: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in the raw materials of the insulating ink layer is not greater than 5%; the isolation groove is located on the outer surface of the insulating ink layer.

[0012] In some preferred embodiments of the present application, the mass content of volatile substances in the raw materials of the insulating ink layer is no more than 2%.

[0013] In some preferred embodiments of the present application, the thickness of the insulating ink layer in the Z-axis direction is in the range of 2-10 μm.

[0014] Further preferably, the insulating ink layer is UV curable insulating ink or thermosetting insulating ink, more preferably UV curable insulating ink.

[0015] In some preferred embodiments of the present application, the width of the insulating ink layer in the X-axis direction is 40-150 μm, the cross width W11 of the insulating ink layer on the first semiconductor layer is ≥20 μm, and the cross width W12 of the insulating ink layer on the second semiconductor opening area is ≥20 μm.

[0016] In some preferred embodiments of the present application, the resistance between the conductive film layers on both sides of the isolation trench is greater than 5 kΩ.

[0017] In some preferred embodiments of the present application, in the X-axis direction, the width of the first semiconductor opening region is 0.1-0.3 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm; the width of the isolation trench in the X-axis direction is 10-190 μm.

[0018] In some preferred embodiments of the present application, the first semiconductor layer includes a tunneling oxide layer and an N-type doped polysilicon layer, or includes an intrinsic silicon layer and an N-type doped polysilicon layer; the second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped silicon layer.

[0019] In some preferred embodiments of the present application, the back contact battery further comprises:

[0020] a metal electrode, which is arranged on the outer surface of the conductive film layer and on the first semiconductor opening region and the second semiconductor opening region;

[0021] A front film layer, which is arranged on the front side of the silicon wafer and comprises a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer;

[0022] The front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening area is a textured surface or a polished surface.

[0023] The present application also provides a method for manufacturing a back-contact battery, wherein the back-contact battery is the back-contact battery described above.

[0024] And the production method includes the following steps:

[0025] S101, forming a first semiconductor layer and a second semiconductor layer on the back side of a silicon wafer, and forming a first semiconductor opening region and a second semiconductor opening region;

[0026] S102, forming an insulating ink layer on the outer surface of the side edge of the second semiconductor opening region on the back side obtained in S101 by inkjet printing or printing;

[0027] S103, depositing a conductive film layer on the back surface obtained in S102;

[0028] S104 , etching an opening on the conductive film layer on the back side obtained in S102 to form an isolation groove.

[0029] In some preferred embodiments of the present application, the insulating ink layer is formed by inkjet printing in S102.

[0030] In some preferred embodiments of the present application, the insulating ink layer is a UV curable insulating ink, and the UV curing energy is controlled to be 700-2000 mj / cm 2 .

[0031] In some preferred embodiments of the present application, when the insulating ink layer is a thermosetting insulating ink, the thermal curing conditions used include: a temperature of 150-180° C. and a time of 5-30 minutes. Beneficial effects:

[0032] The present application adopts the above-mentioned technical solution, especially setting an insulating ink layer in the area directly above the side of the second semiconductor opening area, and the insulating ink layer is in direct contact with the second semiconductor layer, and the insulating ink layer meets the specific surface pencil hardness and resistivity and uses raw materials with a low content of volatile substances, which greatly improves the leakage phenomenon and increases the parallel resistance of the battery; at the same time, compared with the existing technology (such as CN116053331B), the present application adopts a special insulating ink layer, which can ensure sufficiently high insulation performance without setting an insulating film, and can reduce the deposition of the insulating film of the entire battery. After setting the insulating ink layer, there is no need to corrode the insulating film layer outside the insulating ink area, making the process simpler and reducing the damage of the corrosive solution to the first semiconductor layer and the second semiconductor layer when corroding the insulating film layer; thereby taking into account the improvement of the battery conversion efficiency and battery yield.

[0033] In the prior art, the protective ink commonly used in photovoltaic cells generally needs to be cleaned and removed after completing its specific protective function, and the weather resistance of the protective ink is generally poor. The insulating ink needs to have a certain degree of weather resistance because it needs to remain on the battery cell, and the insulating ink contains organic volatilization. It is generally used after coating. For example, in the back-contact battery, there is a phenomenon of easy short circuit between the crossed metal fine grid electrode and the metal main grid electrode or between the metal main grid electrode and the welding strip. At this time, there is no need to enter the vacuum chamber to deposit a thin film. The insulating ink can be formed after the electrode is formed for insulation. Therefore, the insulating ink is currently only configured to protect the electrode in the battery, that is, the insulating ink is usually set on the outside of the electrode. In terms of composition, protective ink is usually composed of 30-55wt% resin, 25-50wt% filler, 15-25wt% solvent, etc., and insulating ink is usually composed of 60-90wt% resin, 10-25wt% filler, 0%-5% solvent, 0-10wt% photoinitiator or curing agent, etc., which differ in solvent content, resin content and composition.

[0034] The insulating ink layer of the present application is disposed outside the interface region between the first and second semiconductor layers and inside the conductive film layer (correspondingly, formed before the conductive film layer is deposited during fabrication), significantly improving leakage current at the interface region between the first and second semiconductor layers. The present application specifically utilizes an insulating ink layer that meets specific surface pencil hardness and resistivity as insulation at the side edges of the second semiconductor opening region, significantly reducing ink solvent diffusion and its adverse effects on the battery. The raw materials used in the insulating ink layer are essentially free of volatile solvents, further reducing the impact of volatile solvent diffusion on the battery. Under the same conditions, if the surface pencil hardness of the insulating ink layer is lower than 2H, defects may occur in the insulating ink layer due to damage from the conveyor belt, suction cup, etc. before the conductive film layer is deposited, resulting in short circuit leakage between the first and second semiconductor layers. Under the same conditions, if the resistivity of the insulating ink layer is lower than 1e11Ω·cm, leakage current between the first and second semiconductor layers may be more likely to occur due to the low resistivity of the insulating ink layer.

[0035] In the preferred solution of the present application, UV curable insulating ink is used and inkjet printing is adopted at the same time, which can greatly reduce the solvent diffusion of the ink and the damage of the solvent diffusion to the corresponding semiconductor layer, thereby improving the battery conversion efficiency and battery yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without creative work.

[0037] FIG1 is a schematic structural diagram of a combined passivated back contact cell with a first semiconductor opening region and a second semiconductor opening region provided in Example 1 of the present application;

[0038] FIG2 is a schematic structural diagram of forming an insulating ink layer at the edge of the second semiconductor opening region in Example 1 of the present application;

[0039] FIG3 is a schematic structural diagram of depositing a conductive film layer on the back side of a silicon wafer in Example 1 of the present application;

[0040] FIG4 is a schematic structural diagram of etching an opening in the insulating ink layer and forming an isolation groove in Example 1 of the present application;

[0041] FIG5 is a schematic structural diagram of forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back side of the silicon wafer in accordance with the first embodiment of the present application.

[0042] FIG6 is a schematic structural diagram of a conventional back-contact battery in the prior art.

[0043] Description of Reference Numerals

[0044] 1. Silicon wafer, 2. Tunneling oxide layer, 3. N-type doped polysilicon layer, 4. Intrinsic amorphous silicon layer, 5. P-type doped silicon layer, 6. Front film layer, 7. Insulating ink layer, 8. Conductive film layer, 9. Metal electrode, 10. Mask layer; 101. Surface of the silicon wafer in the second semiconductor opening area, 102. Side edge. DETAILED DESCRIPTION

[0045] In this application, unless otherwise specified, directional words such as "up, down, left, right" generally refer to the directions shown in the drawings and actual applications, and "inside and outside" refer to the inside and outside of the outline of the component.

[0046] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means two or more, unless otherwise specifically defined.

[0047] In this application, unless otherwise expressly specified or limited, when a first feature is "above" or "below" a second feature, it may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Furthermore, when a first feature is "above," "above," or "above" a second feature, it may mean that the first feature is directly above or diagonally above the second feature, or simply means that the first feature is at a higher level than the second feature. When a first feature is "below," "below," or "below" a second feature, it may mean that the first feature is directly below or diagonally below the second feature, or simply means that the first feature is at a lower level than the second feature.

[0048] The endpoints and any values ​​of the ranges disclosed herein are not limited to the precise ranges or values, and these ranges or values ​​should be understood to include values ​​close to these ranges or values. For numerical ranges, the endpoint values ​​of each range, the endpoint values ​​of each range and the individual point values, and the individual point values ​​can be combined with each other to obtain one or more new numerical ranges, which should be considered as specifically disclosed herein. Among them, the terms "optional" and "optional" all mean that they may be included or not (or may be present or not).

[0049] The present application provides a back-contact battery, comprising a silicon wafer, a first semiconductor layer having a second semiconductor opening region arranged on the back side of the silicon wafer, a second semiconductor layer arranged on the outer surface of the first semiconductor layer and within the second semiconductor opening region, the second semiconductor layer being provided with a first semiconductor opening region spaced apart from the second semiconductor opening region, and a conductive film layer arranged on the outer surface of the second semiconductor layer and within the first semiconductor opening region, an isolation groove being provided on the conductive film layer; and further comprising: an insulating ink layer, which is in number and all arranged between the second semiconductor layer and the conductive film layer and spaced apart along the X-axis direction of the back side, the insulating ink layer being in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layer spans the side edge of the second semiconductor opening region and extends at both ends.

[0050] The insulating ink layer satisfies the following requirements: surface pencil hardness is not less than 2H, resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in the raw materials of the insulating ink layer is not greater than 5%; the isolation groove is located on the outer surface of the insulating ink layer.

[0051] In some preferred embodiments of the present application, the volatile matter content in the raw materials of the insulating ink layer is no more than 2% by weight. This preferred solution is more conducive to further reducing the impact of solvent diffusion on the battery.

[0052] Preferably, the insulating ink layer meets the following requirements: a surface pencil hardness of 2-7H, more preferably 3-7H, and a resistivity of 1e11Ω·cm-5e14Ω·cm, more preferably 1e13Ω·cm-5e14Ω·cm. This preferred solution further reduces leakage between the first and second semiconductor layers, thereby further improving battery conversion efficiency.

[0053] In some preferred embodiments of the present application, the thickness of the insulating ink layer in the Z-axis direction ranges from 2 to 10 μm, more preferably from 3 to 7 μm. In the present application, the thickness refers to the thickness of the insulating ink layer at any position in the Z-axis direction, which is in the range of 2 to 10 μm.

[0054] On the basis of satisfying the thickness ratio of the insulating ink layer to the second semiconductor layer, those skilled in the art can select the thickness of the second semiconductor layer, as well as the thickness ratio of the intrinsic amorphous silicon layer to the P-type doped silicon layer, and the doping concentration of the P-type doped silicon layer according to actual needs. For example, the thickness of the second semiconductor layer can be 10-20nm, the thickness ratio of the intrinsic amorphous silicon layer to the P-type doped silicon layer can be 1:1-3, and the effective doping concentration of the P-type doped silicon layer is 1e18-1e21cm -3 .

[0055] Those skilled in the art can select the thickness of the first semiconductor layer, the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer, the doping concentration of the N-type doped polysilicon layer, and the thickness of the conductive film layer according to actual needs. For example, the thickness of the first semiconductor layer can be 60-150nm, the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer can be 1:40-100, and the effective doping concentration of the N-type doped polysilicon layer is 1e18-1e21cm -3 For example, the thickness of the conductive film layer may be 40-100 nm.

[0056] In the present application, the insulating ink layer is preferably a UV-curable insulating ink or a thermosetting insulating ink, more preferably a UV-curable insulating ink. Thermosetting insulating inks generally contain a relatively high amount of solvent, which forms a layer of solvent volatiles on the surface of the cell during the curing process. UV-curable insulating inks, on the other hand, contain essentially no volatile solvents (less than 2% by weight of solvent). Therefore, no solvent volatile layer forms on the surface of the cell during the UV curing process. In the present application, UV-curable insulating ink is preferred to further reduce solvent diffusion.

[0057] In the present application, the raw materials of the insulating ink layer can be conventional compositions in the prior art, as long as they meet the required volatile substance mass content, surface pencil hardness, and resistivity. Those skilled in the art can choose according to actual needs. For example, the raw materials of the insulating ink layer may include 60-90wt% resin, 10-25wt% filler, 0%-5% solvent, 0-10wt% photoinitiator or curing agent, etc. Exemplarily, the raw materials may include one or more of acrylic resin and / or acrylate, talc, photoinitiator, filler, etc., and solvent. It is understood that the volatile substance refers to the solvent in the insulating ink layer. The type of solvent may be, for example, ethyl acetate, isophorone, ethanol, acetone, etc. The surface pencil hardness and resistivity of the insulating ink layer can be adjusted by the thickness and / or composition of the insulating ink layer.

[0058] Furthermore, the raw materials of the UV curable insulating ink may include 65-90 wt% of resin, 10-20 wt% of filler material, 0%-5% of solvent, 0-10 wt% of photoinitiator or curing agent, and the like.

[0059] In some preferred embodiments of the present application, the width of the insulating ink layer in the X-axis direction is 40-150 μm, the cross-width W11 of the insulating ink layer on the first semiconductor layer is ≥ 20 μm, and the cross-width W12 of the insulating ink layer on the second semiconductor opening area is ≥ 20 μm. Because the present application uses a special insulating ink layer, its properties are different from those of conventional protective inks. Therefore, the use of suitable cross-widths in different ranges can further reduce short-circuit leakage between the first semiconductor layer and the second semiconductor layer, which is more conducive to improving the parallel resistance and battery conversion efficiency of the battery.

[0060] In some preferred embodiments of the present application, the resistance between the conductive film layers on both sides of the isolation trench is greater than 5 kΩ, preferably not less than 300 kΩ. This preferred solution can reduce short-circuit leakage between the first semiconductor layer and the second semiconductor layer, further improving the parallel resistance and conversion efficiency of the battery.

[0061] Those skilled in the art can select the material of the conductive film layer according to actual needs, for example, it can be an indium oxide-based film doped with tin, zinc, tungsten or titanium, or a zinc oxide-based film doped with aluminum, boron or gallium.

[0062] In some preferred embodiments of the present application, in the X-axis direction, the width of the first semiconductor opening region is 0.1-0.3 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm.

[0063] Preferably, the width of the isolation groove in the X-axis direction is 10-190 μm.

[0064] In some preferred embodiments of the present application, the first semiconductor layer comprises a tunneling oxide layer and an N-type doped polysilicon layer, or an intrinsic silicon layer and an N-type doped polysilicon layer; and the second semiconductor layer comprises an intrinsic amorphous silicon layer and a P-type doped silicon layer. The present application is applicable to both heterojunction passivation structures and combined passivation structures, which pose a greater risk of short circuit leakage, and both structures can address the short circuit leakage issue between the first and second semiconductor layers.

[0065] In some preferred embodiments of the present application, the back-contact battery further comprises: a metal electrode disposed on the outer surface of the conductive film layer and disposed on the first semiconductor opening region and the second semiconductor opening region. It is understood that the metal electrodes are divided into two types of electrodes with different polarities, and the polarity of the metal electrode disposed on the first semiconductor opening region is different from that of the metal electrode disposed on the second semiconductor opening region.

[0066] In some preferred embodiments of the present application, the back-contact cell further comprises: a front film layer, which is arranged on the front side of the silicon wafer.

[0067] Those skilled in the art can select the thickness and film structure of the front film layer according to actual needs. For example, the thickness of the front film layer can be 50-120nm. Exemplarily, the front film layer includes a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer arranged in sequence. Those skilled in the art can select the thickness ratio of the silicon dielectric passivation layer and the silicon dielectric anti-reflection layer according to actual needs. The silicon dielectric passivation layer can be, for example, silicon dioxide, amorphous silicon or microcrystalline silicon layer, and the silicon dielectric anti-reflection layer can be, for example, silicon nitride, silicon oxynitride or silicon dioxide.

[0068] Preferably, the front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening region is a textured surface or a polished surface.

[0069] Those skilled in the art can select the type of silicon wafer according to actual needs. For example, the silicon wafer can be N-type.

[0070] The P-type doped silicon layer in the second semiconductor layer of the present application may be, for example, a P-type doped amorphous silicon layer or a P-type doped microcrystalline silicon layer.

[0071] The present application also provides a method for manufacturing a back-contact battery, wherein the back-contact battery is the back-contact battery described above.

[0072] And the production method includes the following steps:

[0073] S101, forming a first semiconductor layer and a second semiconductor layer on the back side of a silicon wafer, and forming a first semiconductor opening region and a second semiconductor opening region;

[0074] S102, forming an insulating ink layer on the outer surface of the side edge of the second semiconductor opening region on the back side obtained in S101 by inkjet printing or printing;

[0075] S103, depositing a conductive film layer on the back surface obtained in S102;

[0076] S104 , etching an opening on the conductive film layer on the back side obtained in S102 to form an isolation groove.

[0077] In some preferred embodiments of the present application, inkjet printing is used to form the insulating ink layer in S102. This application preferably uses inkjet printing, which is non-contact and further reduces solvent diffusion. Contact printing, on the other hand, often requires wiping the screen with solvent during the printing process. Solvent on the screen surface can transfer to the battery surface, thus affecting battery performance to a certain extent.

[0078] In some preferred embodiments of the present application, the insulating ink layer is a UV curable insulating ink, and the UV curing energy is controlled to be 700-2000 mj / cm 2Appropriate UV curing energy can achieve appropriate surface pencil hardness.

[0079] In some preferred embodiments of the present application, when the insulating ink layer is a thermosetting insulating ink, the thermal curing conditions used include: a temperature of 150-180° C. and a time of 5-30 minutes.

[0080] In the present application, the conductive film layer can be deposited by physical vapor deposition (PVD) or activated plasma deposition (RPD). The isolation groove can be formed by direct laser etching, printing, or inkjet printing of corresponding ink followed by etching. The metal electrode can be formed by printing silver paste to form a silver paste grid electrode, electroplating to form a copper grid electrode, etc.

[0081] The embodiments of the present application are described in detail below. These embodiments are exemplary and are only configured to explain the present application, but should not be construed as limiting the present application.

[0082] Example 1

[0083] A combined passivated back contact cell is manufactured by a method comprising the following steps:

[0084] S101 , as shown in FIG1 , provides an N-type silicon wafer 1 , forms a first semiconductor layer and a second semiconductor layer on the back side, and forms a joint passivated back contact heterojunction cell with a first semiconductor opening region and a second semiconductor opening region.

[0085] The first semiconductor layer comprises a tunnel oxide layer 2 (thickness of 1.7 nm), an N-type doped polysilicon layer 3 (thickness of 100 nm, effective doping concentration of 3e20 cm -3 ), the second semiconductor layer comprises an intrinsic amorphous silicon layer 4 (thickness 6nm), a P-type doped silicon layer 5 (specifically a P-type doped amorphous silicon layer, thickness 12nm, effective doping concentration 5e19cm -3 ), a front film layer 6 is formed on the front surface of the silicon wafer 1. The front film layer 6 comprises a silicon dielectric passivation layer (specifically, an intrinsic amorphous silicon layer with a thickness of 10 nm) and a silicon dielectric anti-reflection layer (specifically, silicon nitride with a thickness of 75 nm). In the X-axis direction, the width W1 of the first semiconductor opening region is 0.1 mm, and the width W2 of the second semiconductor opening region is 0.3 mm. The silicon wafer surface 101 of the second semiconductor opening region is a polished surface.

[0086] S102. As shown in FIG2 , an insulating ink layer 7 is formed at the edge of the second semiconductor opening region. The insulating ink layer 7 spans the side edge 102 of the second semiconductor opening region. After curing, the insulating ink layer 7 has a width of 80 μm in the X-axis direction and a thickness of 4-6 μm in the Z-axis direction. The surface pencil hardness of the insulating ink layer 7 is 3H, and the resistivity is 5×10e13 Ω·cm. The volatile matter (i.e., solvent) content in the insulating ink layer is specifically 0.2% by weight. The insulating ink layer 7 has a width W12 of 40 μm above the second semiconductor opening region and a width W11 of 40 μm on the other side. The insulating ink layer 7 is a UV-curable insulating ink (specifically, composed of 79.8 wt% acrylic resin, 15 wt% talc, 5 wt% photoinitiator, and the balance 0.2 wt% ethanol as solvent). The insulating ink layer 7 is formed by inkjet printing, and the UV curing energy is 1000 mj / cm 2 .

[0087] S103, as shown in FIG3, a transparent conductive film layer 8 with a thickness of 60 nm is deposited on the back of the silicon wafer 1. The conductive film layer 8 is deposited by physical vapor deposition (PVD) technology and is a tin-doped indium oxide-based thin film.

[0088] S104: As shown in FIG4 , a portion of the conductive film layer 8 on the insulating ink layer 7 is etched to form an isolation groove. The width W3 of the isolation groove in the X-axis direction is 20 μm. The isolation groove is formed by direct laser etching. After etching, the resistance between the transparent conductive film layer 8 on both sides of the isolation groove is 500 kΩ.

[0089] S105, as shown in FIG5, forming corresponding metal electrodes 9 at corresponding positions on the back side of the silicon wafer 1. The metal electrodes 9 can be formed into silver paste grid line electrodes by printing silver paste.

[0090] Example 2

[0091] The method of Example 1 is referred to, except that the insulating ink layer in S102 is formed by printing.

[0092] Example 3

[0093] The same method as in Example 1 was used, except that in S102, a thermosetting insulating ink (specifically, 70 wt% acrylic resin, 25 wt% filler, and 5 wt% solvent) was used instead of the UV-curable insulating ink. The surface pencil hardness of the thermosetting insulating ink was 3H and the resistivity was 1e12 Ω·cm. The thermosetting insulating ink was formed by printing, and the thermal curing process conditions were: 180°C for 30 minutes. The resistance between the conductive film layers on both sides of the isolation trench was 300 kΩ.

[0094] Example 4

[0095] The method of Example 1 was followed, except that the solvent content in the raw materials for the insulating ink layer in S102 was specifically 2% by weight. The amounts of acrylate, talc, and photoinitiator remained unchanged, and the amount of acrylic resin was adjusted to provide a total of 100%. The surface pencil hardness of the insulating ink layer was 3H, and the resistivity was 6e12 Ω·cm. The resistance between the conductive film layers on both sides of the isolation trench was 200 kΩ.

[0096] Example 5

[0097] The method of Example 1 is referred to, except that, in S102 , the thickness of the insulating ink layer in the Z-axis direction is in the range of 8-10 μm.

[0098] Example 6

[0099] The method of Example 1 is referred to, except that a conventional heterojunction passivation structure is adopted, the tunneling oxide layer in the first semiconductor layer is replaced by intrinsic amorphous silicon, and the N-type doped polysilicon layer is replaced by an N-type doped amorphous layer. The thickness of the intrinsic amorphous silicon is 8 nm, and the thickness of the N-type doped amorphous layer is 12 nm.

[0100] Comparative Example 1

[0101] The method of Example 1 was followed, except that the insulating ink layer 7 was omitted, the second semiconductor layer was in direct contact with the conductive film layer 8, and a mask layer 10 (specifically, silicon nitride) was provided in the region between the first and second semiconductor openings in the X-axis direction, with the mask layer 10 positioned between the first and second semiconductor layers, as shown in FIG6 . The resistance between the conductive film layers on both sides of the isolation trench was 1 kΩ. The preparation method was similar to that of conventional techniques.

[0102] Comparative Example 2

[0103] The method of Example 1 is referred to, except that the P / N types of the two semiconductor layers are different. Specifically, the doped polysilicon layer in the first semiconductor layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer in the second semiconductor layer is an N-type doped amorphous silicon layer.

[0104] Comparative Example 3

[0105] The same method as in Example 1 was used, except that the insulating ink layer was replaced with a protective ink (hot-melt wax) from CN116053331B. The protective ink was formed by inkjet printing. The raw material of the protective ink had a volatile matter content of 6% by mass, a surface pencil hardness of 2H, and a resistivity of 5e9 Ω·cm. The resistance between the conductive film layers on both sides of the isolation trench was 5 kΩ.

[0106] Comparative Example 4

[0107] The method of Example 1 is referred to, except that the insulating ink layer meets the following requirements: surface pencil hardness of 1H, resistivity of 5e8Ω·cm. To meet these parameters, the width of the insulating ink layer 7 in the X-axis direction after curing needs to be adjusted to 160μm, and the resistance between the conductive film layers on both sides of the isolation groove needs to be 5kΩ.

[0108] Comparative Example 5

[0109] The same method as in Example 1 was used, except that the volatile matter content of the insulating ink layer's raw materials was 10% by weight, the amounts of talc and photoinitiator remained unchanged, and the amount of acrylic resin was adjusted to provide a total of 100%. The resistance between the conductive film layers on both sides of the isolation trench was 100 kΩ.

[0110] Test Case

[0111] The back contact cells obtained in the above examples and comparative examples were subjected to various performance tests, and the results are shown in Table 1. The cell yield refers to the cell qualification rate when the batch production quantity is 1000 cells.

[0112] Table 1

[0113] The above results show that, compared to the comparative example, the embodiment of the present application achieves a higher parallel resistance for the back-contact battery, effectively preventing leakage, while also improving battery conversion efficiency and yield, and with a simpler manufacturing process. Conventional existing technologies or solutions that do not meet the requirements of the present application cannot simultaneously achieve the combined effects of effectively preventing leakage, improving battery conversion efficiency, and improving battery yield.

[0114] Furthermore, according to Example 1 and Example 2, it can be seen that the solution of forming the insulating ink layer by the preferred inkjet printing method of the present application can further improve the battery conversion efficiency and battery yield.

[0115] Furthermore, according to Example 1 and Example 3, the use of the preferred UV-curable insulating ink layer and the method for forming the same can further improve the battery conversion efficiency and battery yield.

[0116] Furthermore, according to Example 1 and Examples 4-5, it can be seen that the use of the insulating ink layer with the preferred composition and thickness of the present application can further improve the battery conversion efficiency and battery yield.

[0117] Furthermore, according to Example 1 and Example 6, it can be seen that the solution of the present application is particularly suitable for the solution of the combined passivation structure, which can further improve the battery conversion efficiency and battery yield.

[0118] The preferred embodiments of the present application are described in detail above, but the present application is not limited thereto. Within the technical concept of the present application, various simple modifications can be made to the technical solution of the present application, including combining the various technical features in any other appropriate manner. These simple modifications and combinations should also be regarded as the contents disclosed in the present application and fall within the scope of protection of the present application. Industrial Applicability

[0119] By adopting the above scheme, the insulating ink layer can ensure sufficiently high insulation performance without setting an insulating film, which can reduce the deposition of the insulating film of the entire battery. After setting the insulating ink layer, there is no need to corrode the insulating film layer outside the insulating ink area, making the process flow simpler and reducing the damage of the corrosive solution to the first semiconductor layer and the second semiconductor layer when corroding the insulating film layer; thereby, it is possible to effectively avoid leakage and improve the battery conversion efficiency and battery yield, and the production process flow is simpler and more practical.

Claims

1. A back contact battery, comprising a silicon wafer, a first semiconductor layer having a second semiconductor opening region disposed on the back side of the silicon wafer, a second semiconductor layer disposed on the outer surface of the first semiconductor layer and in the second semiconductor opening region, a first semiconductor opening region arranged spaced apart from the second semiconductor opening region disposed on the second semiconductor layer, and a conductive film layer disposed on the outer surface of the second semiconductor layer and in the first semiconductor opening region, wherein an isolation groove is provided on the conductive film layer; Among them, it is characterized in that it also includes: several insulating ink layers, which are all arranged between the second semiconductor layer and the conductive film layer and are arranged at intervals along the X-axis direction of the back side, and the insulating ink layer is in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layer spans the side edge of the second semiconductor opening area and extends at both ends respectively; wherein, the insulating ink layer satisfies: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11Ω·cm, and the mass content of volatile substances in the raw materials of the insulating ink layer is not more than 5%; the isolation groove is located on the outer surface of the insulating ink layer.

2. The back contact cell according to claim 1, characterized in that: The mass content of volatile substances in the raw materials of the insulating ink layer is not more than 2%.

3. The back contact battery according to claim 1, characterized in that: The thickness of the insulating ink layer in the Z-axis direction is 2-10 μm.

4. The back contact cell according to claim 1, characterized in that: The insulating ink layer is UV curable insulating ink or thermosetting insulating ink.

5. The back contact cell according to claim 1, characterized in that: The width of the insulating ink layer in the X-axis direction is 40-150 μm, the cross width W11 of the insulating ink layer on the first semiconductor layer is ≥20 μm, and the cross width W12 of the insulating ink layer on the second semiconductor opening region is ≥20 μm.

6. The back contact cell according to claim 1, characterized in that: The resistance between the conductive film layers on both sides of the isolation groove is greater than 5 kΩ; And / or, in the X-axis direction, the width of the first semiconductor opening region is 0.1-0.3 mm, and the width of the second semiconductor opening region is 0.3-0.6 mm; the width of the isolation groove in the X-axis direction is 10-190 μm.

7. The back contact cell according to claim 1, characterized in that: The first semiconductor layer includes a tunneling oxide layer and an N-type doped polysilicon layer, or includes an intrinsic silicon layer and an N-type doped polysilicon layer; the second semiconductor layer includes an intrinsic amorphous silicon layer and a P-type doped silicon layer.

8. The back contact cell according to claim 1, characterized in that: The back contact battery further comprises: A metal electrode, which is arranged on the outer surface of the conductive film layer and on the first semiconductor opening area and the second semiconductor opening area; A front film layer, which is arranged on the front side of the silicon wafer and comprises a silicon dielectric passivation layer and a silicon dielectric anti-reflection layer; The front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening area is a textured surface or a polished surface.

9. A method for manufacturing a back contact battery, characterized in that: The back contact cell is a back contact cell as claimed in any one of claims 1 to 8, and the manufacturing method comprises the following steps: S101, forming a first semiconductor layer and a second semiconductor layer on the back side of the silicon wafer, and forming a first semiconductor opening region and a second semiconductor opening region; S102, forming an insulating ink layer on the outer surface of the side edge of the second semiconductor opening region on the back side obtained in S101 by inkjet printing or printing; S103, depositing a conductive film layer on the back surface obtained in S102; S104, etching an opening on the conductive film layer on the back side obtained in S102 to form an isolation groove.

10. The manufacturing method according to claim 9, characterized in that: In S102, an insulating ink layer is formed by inkjet printing; and / or, When the insulating ink layer is a UV curing insulating ink, the UV curing energy is controlled to be 700-2000 mj / cm 2 ; When the insulating ink layer is a thermosetting insulating ink, the thermal curing conditions used include: a temperature of 150-180° C. and a time of 5-30 minutes.

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