Control method for storage device, and storage device and electronic device

Abstract

Disclosed in the present invention are a control method for a storage device, and a storage device and an electronic device. The control method comprises: in response to data to be written that is sent by a host end, writing said data into a storage unit according to a target mode, wherein the target mode comprises a first mode and a second mode, the first mode comprises first storing data in a storage unit of a first type and then migrating the stored data to a storage unit of a second type, and the second mode comprises directly storing data in the storage unit of the second type; according to the target mode, counting the target number of instances of erasable writing, wherein the target number of instances of erasable writing is less than the sum of the actual number of instances of erasable writing for the storage unit of the first type and the actual number of instances of erasable writing for the storage unit of the second type; and in response to the target number of instances of erasable writing being greater than a threshold value of the number of instances of erasable writing, disabling the first mode. That is, in the present application, data is written by means of a target mode, the corresponding target number of instances of erasable writing is acquired, and a write mode is controlled on the basis of the target number of instances of erasable writing, thereby improving the write performance of a storage device, further effectively reducing erase amplification, and prolonging the service life of the storage device.

Description

Storage device control method, storage device, and electronic device

[0001]

Cross-reference

[0002] This application claims priority to Chinese patent application No. CN202311456710.0 filed on November 2, 2023, the entire contents of which are incorporated herein by reference.

Technical field

[0003] The present invention relates to the technical field of storage devices, and in particular to a storage device control method, a storage device, and an electronic device. [Background Technology]

[0004] In the application process of storage devices, in order to improve the write performance of the storage devices, data is usually written through cache writing.

[0005] During actual operation, the inventors of the present application discovered that writing data by cache writing will result in more erases and writes, thereby generating greater erase amplification and reducing the life of the storage device.

[0006] [Summary of the invention]

[0007] According to various embodiments of the present application, a storage device control method, a storage device, and an electronic device are provided.

[0008] The present application provides a control method for a storage device, comprising: in response to data to be written sent by a host, writing the data to be written into a storage unit according to a target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode including first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode including directly storing in a second type of storage unit; wherein the amount of data that can be stored in each of the first type of storage units is less than the amount of data that can be stored in each of the second type of storage units; counting a target number of erase and write times according to the target mode; wherein the target number of erase and write times is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit; and in response to the target number of erase and write times being greater than an erase and write number threshold, turning off the first mode.

[0009] On the other hand, the present application provides a storage device comprising a processor and a storage unit, wherein the processor is coupled to the storage unit and a host end, and executes instructions during operation to implement the above-mentioned control method.

[0010] On the other hand, the present application provides an electronic device, including a processor and a storage device, wherein the processor is coupled to the storage device and executes instructions during operation to implement the above-mentioned control method.

[0011] The details of one or more embodiments of the invention are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the invention will become apparent from the description, drawings, and claims.

Brief Description of the Drawings

[0012] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without inventive efforts. Among them:

[0013] FIG1 is a flow chart of a first embodiment of a method for controlling a storage device according to the present invention;

[0014] FIG2 is a schematic flow chart of an embodiment of step S11;

[0015] FIG3 is a flow chart of a second embodiment of a method for controlling a storage device in the present application;

[0016] 4 is a diagram showing the relationship between the number of erase and write times and the number of error bits corresponding to the first type of storage cell and the second type of storage cell;

[0017] FIG5 is a flowchart of a third embodiment of a method for controlling a storage device in the present application;

[0018] FIG6 is a schematic diagram of threshold voltages corresponding to first-type memory cells and second-type memory cells in the current technology;

[0019] 7 is a schematic diagram of threshold voltages corresponding to the first type of memory cells in the third embodiment of the present application;

[0020] FIG8 is a flowchart of a fourth embodiment of a method for controlling a storage device in the present application;

[0021] FIG9 is a flowchart of a fifth embodiment of a method for controlling a storage device in the present application;

[0022] FIG10 is a flow chart showing the principle of writing data to be written into a storage unit in the present application;

[0023] FIG11 is a schematic structural diagram of an embodiment of a storage device of the present application;

[0024] FIG12 is a schematic structural diagram of an electronic device according to an embodiment of the present application. [Specific implementation method]

[0025] The following will be combined with the drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0026] In current technology, in order to improve the write performance of storage devices, a cache write method (WB feature) is usually used to write the data to be written to the storage device, that is, the data to be written is first written to the flash memory, and then the corresponding data is moved to other storage units. Because the write rate to the flash memory is fast, the write performance of the storage device is improved; however, for the same amount of data written, the number of flash memory blocks occupied by the write-to-flash method is much larger than the number of flash memory blocks occupied by the direct write method, and after writing to the flash memory, it needs to be moved to other storage units, resulting in a larger number of side writes, and then a larger erase amplification, which reduces the life of the storage device.

[0027] Therefore, the present application provides a control method for a storage device, which writes the data to be written into the storage unit through a target mode including a first mode and / or a second mode, obtains the corresponding target number of erase and write times, and controls the writing method based on the target number of erase and write times. While improving the write performance of the storage device, it can also effectively reduce erase amplification and extend the life of the storage device.

[0028] Please refer to FIG. 1 , which is a flowchart of a first embodiment of a method for controlling a storage device of the present application.

[0029] As shown in FIG1 , the control method of the storage device of the present application includes the following steps:

[0030] S11. In response to the data to be written sent by the host side, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit.

[0031] Among them, the host end can be a communication device that can send commands, such as a mobile phone, tablet, computer, etc.; the data to be written can be various types of data that need to be stored, such as text, numbers, images, audio, video, etc.

[0032] In some embodiments, the storage device may include multiple storage units, and a portion of the storage units may be storage units of the first type, and another portion of the storage units may be storage units of the second type; or a single storage unit may be a storage unit of the first type in one time period and a storage unit of the second type in another time period. The setting can be made according to actual conditions.

[0033] The first type of storage unit serves as a buffer area, and the second type of storage unit serves as a normal storage area.

[0034] In some embodiments, the target mode may include the first mode alone, the second mode alone, or both the first mode and the second mode.

[0035] Please refer to FIG. 2 , which is a flow chart of an embodiment of step S11 .

[0036] As shown in Figure 2, it includes:

[0037] S111. Obtain available space of a storage device.

[0038] The available space of the storage device includes the available space of the desired storage unit, and the available space corresponding to each storage unit is determined.

[0039] S112 : In response to the available space of the storage device being greater than or equal to the preset space, write the data to be written into the storage device according to the first mode.

[0040] In order to ensure the normal operation of the first mode, a threshold needs to be set, that is, a preset space is set so that when the data to be written is written to the storage unit using the first mode, sufficient available space is used for caching and transfer.

[0041] Specifically, when it is detected that the available space of the storage device is greater than or equal to the set preset space, the data to be written can be written to the storage device in accordance with the first mode, that is, the target mode can include the first mode alone. In the case of the first mode, the host side sends the data to be written to the storage device. After the storage device receives the data to be written, in response to the action, the storage device stores the data to be written in a first type of storage unit. When the device is idle or the available bandwidth is sufficient, the data cached in the first type of storage unit is moved to the second type of storage unit. The move can be done by directly writing to refresh the data cached in the first type of storage unit to the second type of storage unit. The relevant data of the first type of storage unit becomes invalid, so that the storage unit releases more space.

[0042] S113 . In response to the available space of the storage device being smaller than the preset space, write the data to be written into the storage device according to the second mode.

[0043] Specifically, when it is detected that the available space of the storage device is less than the set preset space, the data to be written can be written to the storage device in accordance with the second mode, that is, the target mode can include the second mode alone. In the case of the second mode, the host side sends the data to be written to the storage device. After the storage device receives the data to be written, in response to the action, the storage device stores the data to be written in the second type of storage unit, that is, directly stores the data to be written in the normal storage area.

[0044] In some embodiments, the target mode may include a first mode and a second mode. For example, in the early stage of the storage process, the available space of the storage device is greater than or equal to the preset space, while in the later stage of the storage process, the available space of the storage device is less than the preset space, that is, when a large amount of data needs to be stored in one storage process, a hybrid mode of the first mode and the second mode is adopted. In this case, based on the comparison between the available space of the storage device obtained in real time and the preset space, when the available space of the storage device is greater than or equal to the preset space, the first mode is adopted to write the data to be written to the storage device, and when the available space of the storage device is less than the preset space, the second mode is adopted to write the data to be written to the storage device.

[0045] S12. Counting target erase / write times according to the target mode; wherein the target erase / write times is less than the sum of actual erase / write times of the first type of memory cells and actual erase / write times of the second type of memory cells.

[0046] Among them, the number of erase and write times is the number of times the data to be written is erased and written when it is written into the storage unit, and the target number of erase and write times is the number of erase and write times corresponding to writing the data to be written into the storage unit according to the target mode; the actual number of erase and write times of the first type of storage unit is the number of erase and write times when the data to be written is stored using the first type of storage unit, and the actual number of erase and write times of the second type of storage unit is the number of erase and write times when the data to be written is stored using the second type of storage unit.

[0047] Specifically, after the data to be written is written into the storage unit according to the target mode, the target erase and write times corresponding to the target mode are counted, as well as the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit. Because the target erase and write times are less than the sum of the actual erase and write times of the two types of storage units, the erase amplification is effectively reduced and the life of the storage device is extended.

[0048] For example, a first type of storage cell has a capacity of 1 GB, and a second type of storage cell has a capacity of 3 GB. When writing 3 GB of data to be written to the storage cell using the second mode, a direct write method is used to write the 3 GB of data to be written directly to the second type of storage cell. During the write process, the second type of storage cell needs to be erased once, and its erase amplification factor is 1 / 1=1. When writing 3 GB of data to be written to the storage cell using the first mode, the 3 GB of data to be written needs to be written to three first type of storage cells with a capacity of 1 GB, and then quickly replied to the host. When the system is idle or has sufficient bandwidth, the 3 GB of data stored in the three first type of storage cells is moved to the second type of storage cell with a capacity of 3 GB. Storing data in the first type of storage cell can improve storage efficiency. When writing data, each 1 GB first type of storage cell is erased once, and when the data is moved to the second type of storage cell, the second type of storage cell is erased once again. Therefore, the first mode has four erases and writes, and the erase amplification factor is 4 / 1=4.

[0049] That is, the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit is: 3+1=4, and the target erase and write times currently counted is less than 4, thus effectively reducing the erase amplification and extending the life of the storage device.

[0050] S13: In response to the target erasure count being greater than the erasure count threshold, shutting down the first mode.

[0051] In order to determine whether the life of the memory cell is exhausted, it is necessary to set an erase and write count threshold.

[0052] Specifically, the erasure count threshold is determined based on the erasable number of times a storage unit in the storage device can be erased. After the data to be written is written into the storage unit according to the target mode and the corresponding target erasure count is counted, the target erasure count is compared with the erasure count threshold. When the target erasure count is greater than the erasure count threshold, it indicates that the life of the storage unit is exhausted. Therefore, it is necessary to turn off the first mode to end the erasure of the storage unit.

[0053] In this embodiment, the data to be written is written into the storage unit through a target mode including the first mode and / or the second mode, the corresponding target erase and write times are obtained, and the target erase and write times are set to be smaller than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit, so as to reduce the erase amplification. That is, the writing mode is controlled based on the target erase and write times, which can improve the write performance of the storage device while effectively reducing the erase amplification and extending the life of the storage device.

[0054] In order to further reduce the erase magnification, it can also be set according to the wear coefficient.

[0055] Please refer to FIG3 , which is a flowchart of a second embodiment of a method for controlling a storage device in the present application.

[0056] As shown in Figure 3, the following steps are included:

[0057] S21. In response to the data to be written sent by the host side, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit.

[0058] The same parts as those in the first embodiment will not be described in detail.

[0059] S22. Obtain a first wear coefficient, wherein the first wear coefficient is determined by a first number of error bits corresponding to the first type of storage unit and a second number of error bits corresponding to the second type of storage unit; wherein the first wear coefficient is a positive number less than 1.

[0060] Among them, the first wear coefficient is an internal operating parameter corresponding to the erasure and programming of the first type of storage unit, which is used to manage the life of the storage device and can adjust the erase amplification; under the same erasure and programming conditions, the number of error bits (Fail bit count, FBC) caused by the first type of storage unit is less than the number of error bits caused by the second type of storage unit.

[0061] In some embodiments, the first wear coefficient may be obtained in advance in the following manner.

[0062] Specifically, the first type of storage cell and the second type of storage cell are erased and written the same number of times, and a first error bit number corresponding to the first type of storage cell and a second error bit number corresponding to the second type of storage cell are obtained respectively, and then a first wear coefficient is determined based on the first error bit number and the second error bit number.

[0063] As shown in FIG. 4 , FIG. 4 is a relationship diagram of the number of erasures and programming and the number of error bits corresponding to the first type of memory cell and the second type of memory cell.

[0064] As shown in FIG4 , when the number of erasures and writes is the same, the second error bit number corresponding to the second type of storage unit is twice the first error bit number corresponding to the first type of storage unit. Therefore, the first wear coefficient is 1 / 2=0.5.

[0065] S23: Determine the product of the first wear coefficient and the actual erasure count of the first type of storage unit, and determine the sum of the product and the actual erasure count of the second type of storage unit as the target erasure count.

[0066] The first wear coefficient needs to be brought into the calculation of the target number of erase and write times.

[0067] Specifically, the first wear coefficient and the actual erasure times of the first type of storage unit are multiplied to obtain a product, and the product is added to the actual erasure times of the second type of storage unit, and the obtained sum is the target erasure times.

[0068] Then, the first wear coefficient is 0.5, the actual number of erase and write times of the first type of storage unit is k, the actual number of erase and write times of the second type of storage unit is m, and the target number of erase and write times is n, then: n=k*0.5+m; for example, the capacity of the first type of storage unit is 1GB, the capacity of the second type of storage unit is 3GB, the data to be written is 3GB, and when the first mode is used to write data, the actual number of erase and write times of the first type of storage unit is 3, and the actual number of erase and write times of the second type of storage unit is 1, then the target number of erase and write times n=3*0.5+1=2.5, which is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit, which is 4; that is, the erase amplification is corrected from 4 to 2.5, which is a 37.5% reduction compared with the original 4 times erase amplification.

[0069] S24: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0070] The same parts as those in the first embodiment will not be described in detail.

[0071] In this embodiment, the data to be written is written into the storage unit through a target pattern including the first pattern and / or the second pattern, the corresponding target number of erase and write times is obtained, and the first wear coefficient affecting the target number of erase and write times is obtained, so that the target number of erase and write times is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit, so as to reduce the erase amplification, that is, the writing mode is controlled based on the target number of erase and write times, which can improve the write performance of the storage device while effectively reducing the erase amplification and extending the life of the storage device.

[0072] In order to further reduce the erase amplification, the wear coefficient may be set according to the erased state threshold voltage and the programmed state threshold voltage, thereby reducing the erase amplification.

[0073] Please refer to FIG5 , which is a flowchart of a third embodiment of a method for controlling a storage device in the present application.

[0074] As shown in Figure 5, the following steps are included:

[0075] S31. In response to the data to be written sent by the host end, the data to be written is written into the storage unit with a first erase state threshold voltage and / or a first programming state threshold voltage according to a first mode; wherein the first erase state threshold voltage is greater than the second erase state threshold voltage corresponding to the first wear coefficient, and the first programming state threshold voltage is less than the second programming state threshold voltage corresponding to the first wear coefficient.

[0076] Among them, when determining the first wear coefficient, there is a corresponding second erased state threshold voltage and a second programmed state threshold voltage. The second erased state threshold voltage is the voltage of the erased state corresponding to the first wear coefficient, and the second programmed state threshold voltage is the voltage of the programmed state corresponding to the first wear coefficient.

[0077] The reason why the number of error bits increases with the increase in the number of erase and write cycles is because of electron tunneling, which in turn causes the tunneling oxide layer of the storage unit to degrade. The degree of degradation depends on the electron tunneling rate.

[0078] 6 and 7 , FIG. 6 is a schematic diagram of threshold voltages corresponding to first-type memory cells and second-type memory cells in the current technology; FIG. 7 is a schematic diagram of threshold voltages corresponding to first-type memory cells in the third embodiment of the present application.

[0079] As shown in FIG6 , the threshold voltage of the programming state (L1 to L7) of the first type of memory cell is relatively high, and the threshold voltage of the erased state (L0) is relatively low, so the amount of electron tunneling is high, and the loss caused to the memory cell is also relatively high. As shown in FIG7 , the threshold voltage corresponding to the first type of memory cell in the current technology is SLC, and the threshold voltage corresponding to the first type of memory cell corresponding to the third embodiment is the optimized SLC. As can be seen from FIG7 , the read window corresponding to the optimized SLC is smaller than the read window of the SLC.

[0080] In some embodiments, the first erased state threshold voltage is 0.2-0.3V higher than the second erased state threshold voltage, and the first programmed state threshold voltage is 0.2-0.3V lower than the second programmed state threshold voltage. For example, the range of the second erased state threshold voltage is 0-0.5V, the range of the second programmed state threshold voltage is 2.0-2.5V, the range of the first erased state threshold voltage is 0.2-0.8V, and the range of the first programmed state threshold voltage is 1.8-2.2V.

[0081] S32. Obtain a second wear coefficient, wherein the second wear coefficient is determined by the first erased state threshold voltage and / or the first programmed state threshold voltage, and wherein the second wear coefficient is smaller than the first wear coefficient.

[0082] Among them, the erased state threshold voltage is negatively correlated with the wear coefficient, and the programmed state threshold voltage is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage cell and the second error bit number corresponding to the second type of storage cell; the first wear coefficient is a positive number less than 1.

[0083] Specifically, by providing a first erased state threshold voltage greater than the second erased state threshold voltage and / or a first programmed state threshold voltage less than the second programmed state threshold voltage, the goal of a lower electron tunneling amount can be achieved, so that the second wear coefficient corresponding to the first erased state threshold voltage and / or the first programmed state threshold voltage is less than the first wear coefficient, that is, the second wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0084] S33: Determine the product of the second wear coefficient and the actual erasure count of the first type of storage unit, and determine the sum of the product and the actual erasure count of the second type of storage unit as the target erasure count.

[0085] S34: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0086] The same parts as those in the first and second embodiments are not described in detail.

[0087] In this embodiment, by increasing the erased state threshold voltage and / or decreasing the programmed state threshold voltage, the electron tunneling amount is reduced, and the corresponding second wear coefficient is also smaller than the first wear coefficient, further reducing the erase amplification and increasing the life of the storage device.

[0088] In order to further reduce the erase amplification, the wear coefficient can be set according to the erase start voltage and the program start voltage, thereby reducing the erase amplification.

[0089] Please refer to FIG8 , which is a flowchart of a fourth embodiment of a method for controlling a storage device in the present application.

[0090] As shown in Figure 8, the following steps are included:

[0091] S41. In response to the data to be written sent by the host, the data to be written is written into the storage unit according to the first mode and based on the first erase start voltage and / or the first programming start voltage; wherein the first erase start voltage is less than the second erase start voltage corresponding to the first wear coefficient, and the first programming start voltage is less than the second programming start voltage corresponding to the first wear coefficient.

[0092] Among them, multiple pulses are required during the conversion process between the programming state and the erased state; when determining the first wear coefficient, there are corresponding second erased state threshold voltage, second programming state threshold voltage, second erase start voltage and second programming start voltage. The second erase start voltage is the starting voltage for converting from the programming state to the erased state corresponding to the first wear coefficient, and the second programming start voltage is the starting voltage for converting from the erased state to the programming state corresponding to the first wear coefficient.

[0093] A lower erase start voltage and / or program start voltage can reduce the degradation rate of the memory cell tunneling oxide layer. The degradation rate depends on the electron tunneling rate. The higher the erase start voltage and program start voltage, the higher the electron tunneling rate and the higher the damage to the memory cell.

[0094] S42. Obtain a third wear coefficient, wherein the third wear coefficient is determined by the first erase start voltage and / or the first program start voltage, and wherein the third wear coefficient is smaller than the first wear coefficient.

[0095] Among them, the erase start voltage is positively correlated with the wear coefficient, and the programming start voltage is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage cell and the second error bit number corresponding to the second type of storage cell; the first wear coefficient is a positive number less than 1.

[0096] Therefore, by giving a first erase start voltage that is lower than the second erase start voltage and / or a first programming start voltage that is lower than the second programming start voltage, the goal of lower electron tunneling amount can be achieved, so that the third wear coefficient corresponding to the first erase start voltage and / or the first programming start voltage is lower than the first wear coefficient, that is, the third wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0097] S43: Determine the product of the third wear coefficient and the actual erasure count of the first type of storage unit, and determine the sum of the product and the actual erasure count of the second type of storage unit as the target erasure count.

[0098] S44: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0099] The same parts as those in the first and second embodiments are not described in detail.

[0100] In some embodiments, while using the first erase start voltage and the first programming start voltage, the first erase state threshold voltage and the first programming state threshold voltage can also be used, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0101] In this embodiment, by lowering the erase start voltage and / or the program start voltage, the electron tunneling amount is reduced, and the corresponding third wear coefficient is also smaller than the first wear coefficient, further reducing the erase amplification and improving the life of the storage device.

[0102] In order to further reduce the erase amplification, the wear coefficient can be set according to the erase step value and the programming step value to further reduce the erase amplification.

[0103] Please refer to FIG9 , which is a flowchart of a fifth embodiment of a method for controlling a storage device in the present application.

[0104] As shown in Figure 9, the following steps are included:

[0105] S51. In response to the data to be written sent by the host end, the data to be written is written into the storage unit according to the first mode with a first erase step value and / or a first programming step value; wherein the first erase step value is smaller than the second erase step value corresponding to the first wear coefficient, and the first programming step value is smaller than the second programming step value corresponding to the first wear coefficient.

[0106] Among them, multiple pulses are required during the conversion process between the programming state and the erased state; when determining the first wear coefficient, there are corresponding second erased state threshold voltage, second programming state threshold voltage, second erase start voltage, second programming start voltage, second erase step value and second programming step value. The second erase step value is the voltage difference between adjacent pulses corresponding to the first wear coefficient for converting from the programming state to the erased state, and the second programming step value is the voltage difference between adjacent pulses corresponding to the first wear coefficient for converting from the erased state to the programming state.

[0107] The degradation rate depends on the electron tunneling rate. When the erase step value and programming step value are high, the electron tunneling amount is high and the damage to the memory cell is also high. Lower erase step value and / or programming step value can reduce the degradation rate of the memory cell tunneling oxide layer.

[0108] S52: Obtain a fourth wear coefficient, wherein the fourth wear coefficient is determined by the first erase step value and / or the first program step value, and wherein the fourth wear coefficient is smaller than the first wear coefficient.

[0109] Among them, the erase step value is positively correlated with the wear coefficient, and the programming step value is positively correlated with the wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; the first wear coefficient is a positive number less than 1.

[0110] Therefore, by giving a first erase step value that is smaller than the second erase step value and / or a first programming step value that is smaller than the second programming step value, the goal of a lower electron tunneling amount can be achieved, so that the fourth wear coefficient corresponding to the first erase step value and / or the first programming step value is smaller than the first wear coefficient, that is, the fourth wear coefficient is less than 0.5, thereby further reducing the erase amplification and improving the life of the storage device.

[0111] S53: Determine the product of the fourth wear coefficient and the actual erasure count of the first type of storage unit, and determine the sum of the product and the actual erasure count of the second type of storage unit as the target erasure count.

[0112] S54: In response to the target erasure count being greater than the erasure count threshold, shut down the first mode.

[0113] The same parts as those in the first and second embodiments are not described in detail.

[0114] In some embodiments, while adopting the first erase step value and the first programming step value, the first erase state threshold voltage and the first programming state threshold voltage can also be adopted, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0115] In other embodiments, the first erase start voltage and the first programming start voltage may be used at the same time as the first erase step value and the first programming step value, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and increasing the life of the storage device.

[0116] In some further embodiments, while adopting the first erase step value and the first programming step value, the first erase start voltage, the first programming start voltage, the first erase state threshold voltage and the first programming state threshold voltage can also be adopted, so that the corresponding wear coefficient is further reduced, thereby further reducing the erase amplification and improving the life of the storage device.

[0117] In this embodiment, by reducing the erase step value and / or the program step value, the electron tunneling amount is reduced, and the corresponding fourth wear coefficient is also smaller than the first wear coefficient, further reducing the erase amplification and improving the life of the storage device.

[0118] In order to illustrate the entire writing process, FIG10 is shown.

[0119] FIG10 is a flow chart showing the principle of writing data to be written into a storage unit in the present application.

[0120] As shown in Figure 10, the target number of erase and write times is set to n, the total number of erase and write times of the storage device is N, the number of erase and write times of the first type of storage unit is k, the number of erase and write times of the second type of storage unit is m, and the wear coefficient is a; when starting to write data, Cycle n=0, SLC cycle k=0, TLC cycle m=0, and data is written to the entire disk of the storage device once. If the first mode is used for writing, that is, the SLC mode is used for writing, then k=K+1, m=m, and the target number of erase and write times is: n=k*a+m. When n is greater than N, the life of the flash memory block corresponding to the storage unit is exhausted, and the WriteBooster function is turned off, that is, the first mode is turned off; if the second mode is used for writing, then k=k, m=m+1, and the target number of erase and write times is: n=k*a+m.

[0121] Please refer to FIG11 , which is a schematic structural diagram of an embodiment of a storage device of the present application.

[0122] As shown in Figure 11, the storage device 600 includes a processor 610 and a storage unit 620. The processor 610 is coupled to the storage unit 620 and the host end, and executes instructions during operation to implement the above-mentioned storage device control method.

[0123] Please refer to FIG12 , which is a schematic structural diagram of an electronic device according to an embodiment of the present application.

[0124] As shown in FIG12 , the electronic device 70 includes a processing device 71 and a storage device 600 . The processor is coupled to the storage device 600 and executes instructions during operation to implement the above-mentioned storage device control method.

[0125] The above technical solution provides a control method for a storage device, which responds to the data to be written sent by the host end, writes the data to be written into the storage unit according to the target mode; wherein the target mode includes at least a first mode and / or a second mode, the first mode includes first storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in a second type of storage unit; wherein the amount of data that can be stored in each first type of storage unit is less than the amount of data that can be stored in each second type of storage unit; according to the target mode, the target number of erase and write times is counted; wherein the target number of erase and write times is less than the sum of the actual number of erase and write times of the first type of storage unit and the actual number of erase and write times of the second type of storage unit; in response to the target number of erase and write times being greater than the erase and write number threshold, the first mode is turned off. That is, in the present application, the data to be written is written into the storage unit through a target mode including the first mode and / or the second mode, the corresponding target erase and write times are obtained, and the target erase and write times are set to be less than the sum of the actual erase and write times of the first type of storage unit and the actual erase and write times of the second type of storage unit, so as to reduce the erase amplification, that is, the writing mode is controlled based on the target erase and write times, which can improve the write performance of the storage device while effectively reducing the erase amplification and extending the life of the storage device.

[0126] The above description is only an embodiment of the present invention and does not limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made by using the contents of the description and drawings of the present invention, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for controlling a storage device, characterized in that: include: In response to the data to be written sent by the host, the data to be written is written into the storage unit according to the target mode; wherein the target mode includes a first mode and a second mode, the first mode includes firstly storing in a first type of storage unit, and then migrating the data stored in the first type of storage unit to a second type of storage unit; the second mode includes directly storing in the second type of storage unit; wherein the amount of data that can be stored in each of the first type of storage units is less than the amount of data that can be stored in each of the second type of storage units; Counting target erasure times according to the target mode; wherein the target erasure times are less than the sum of the actual erasure times of the first type of storage unit and the actual erasure times of the second type of storage unit; In response to the target erasure count being greater than an erasure count threshold, the first mode is turned off.

2. The control method according to claim 1, characterized in that: The counting of target erasing and writing times according to the target mode comprises: Obtaining a first wear coefficient, wherein the first wear coefficient is determined by a first number of error bits corresponding to a first type of storage unit and a second number of error bits corresponding to a second type of storage unit; wherein the first wear coefficient is a positive number less than 1; The product of the first wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

3. The control method according to claim 2, characterized in that: The first wear coefficient is obtained by: Erasing and writing the first type of storage unit and the second type of storage unit the same number of times to obtain a first number of error bits corresponding to the first type of storage unit and a second number of error bits corresponding to the second type of storage unit; The first wear coefficient is determined according to the first number of error bits and the second number of error bits.

4. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit with a first erased state threshold voltage and / or a first programmed state threshold voltage; wherein the first erased state threshold voltage is greater than a second erased state threshold voltage corresponding to a first wear coefficient, and the first programmed state threshold voltage is less than a second programmed state threshold voltage corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtain a second wear coefficient, wherein the second wear coefficient is determined by the first erased state threshold voltage and / or or the first programming state threshold voltage; wherein the second wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by the first error bit number corresponding to the first type of storage unit and the second error bit number corresponding to the second type of storage unit; the first wear coefficient is a positive number less than 1; The product of the second wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

5. The control method according to claim 4, characterized in that: The first erased state threshold voltage is 0.2-0.3V higher than the second erased state threshold voltage, and the first programmed state threshold voltage is 0.2-0.3V lower than the second programmed state threshold voltage.

6. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit based on a first erase start voltage and / or a first programming start voltage; wherein the first erase start voltage is less than a second erase start voltage corresponding to a first wear coefficient, and the first programming start voltage is less than a second programming start voltage corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtaining a third wear coefficient, wherein the third wear coefficient is determined by the first erase start voltage and / or the first programming start voltage; wherein the third wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first error bit number corresponding to a first type of storage cell and a second error bit number corresponding to a second type of storage cell; and the first wear coefficient is a positive number less than 1; The product of the third wear coefficient and the actual number of erasures of the first type of storage unit is determined, and the sum of the product and the actual number of erasures of the second type of storage unit is determined as the target number of erasures.

7. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: According to a first mode, the data to be written is written into a storage unit with a first erase step value and / or a first programming step value; wherein the first erase step value is smaller than a second erase step value corresponding to a first wear coefficient, and the first programming step value is smaller than a second programming step value corresponding to the first wear coefficient; The counting of target erasing and writing times according to the target mode comprises: Obtaining a fourth wear coefficient, wherein the fourth wear coefficient is determined by the first erase step value and / or the first programming step value; wherein the fourth wear coefficient is less than the first wear coefficient; the first wear coefficient is determined by a first error bit number corresponding to a first type of storage unit and a second error bit number corresponding to a second type of storage unit; the first wear coefficient is a positive number less than 1; determining a product of the fourth wear coefficient and an actual number of erase and write times of the first type of storage unit, and The sum of the product and the actual erasure count of the second type of memory cells is determined as the target erasure count.

8. The control method according to claim 1, characterized in that: Writing the data to be written into the storage unit according to the target mode includes: Acquire available space of the storage device, wherein the storage device includes a plurality of storage units; In response to the available space of the storage device being greater than or equal to the preset space, writing the data to be written into the storage device according to the first mode; or, In response to the available space of the storage device being less than the preset space, the data to be written is written into the storage device according to the second mode.

9. A storage device, characterized in that: The storage device includes a processor and a storage unit. The processor is coupled to the storage unit and a host end, and executes instructions when working to implement the control method described in any one of claims 1 to 8.

10. An electronic device, characterized in that: It comprises a processing device and a storage device, wherein the processing device is coupled to the storage device and executes instructions when working to implement the control method described in any one of claims 1 to 8.

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