Driving backplane, epitaxial wafer, preparation method, display module and electronic device

Abstract

The present application relates to the technical field of electronics, and provides a driving backplane, an epitaxial wafer, a preparation method, a display module and an electronic device, used for improving the efficiency of a light-emitting device in a display module. The driving backplane comprises a substrate, a driving circuit layer, a reflective layer and a first bonding layer, and the driving circuit layer, the reflective layer and the first bonding layer are sequentially arranged on the same side of the substrate. The reflective layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the refractive indexes of the first dielectric layer and the second dielectric layer are different; and the thickness, material and number of first dielectric layers and second dielectric layers comprised in reflective layers of different driving backplanes can be different. The first bonding layer is connected to the driving circuit layer and is used for realizing bonding between the driving backplane and the epitaxial wafer. When the driving backplane is applied to the display module, the structure of the reflective layer can be adjusted on the basis of the light-emitting wavelength of a light-emitting device, so that the reflectivity of the reflective layer to red light, green light and blue light can reach 90% or above, thereby improving the efficiency of the light-emitting device.

Description

Driving backplane, epitaxial wafer and preparation method, display module, electronic equipment

[0001] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office on October 30, 2023, with application number 202311435450.9 and application name “Driving backplane, epitaxial wafer and preparation method, display module, electronic device”, all contents of which are incorporated by reference into this application. Technical Field

[0002] The present application relates to the field of electronic technology, and in particular to a driving backplane, an epitaxial wafer and a preparation method thereof, a display module, and an electronic device. Background Art

[0003] A micro light emitting diode (Micro LED) refers to an LED with a size of less than 100 μm. Micro LED is the core light-emitting device of micro displays. Due to its advantages such as fast response, autonomous illumination, high brightness, low power consumption, high resolution and color saturation, Micro LED has become a research hotspot in the current display field.

[0004] Currently, display modules including Micro LEDs are manufactured by bonding a driver backplane to a Micro LED epitaxial wafer. However, Micro LED display modules manufactured using the current mainstream bonding process suffer from low efficiency.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a driving backplane, an epitaxial wafer and a preparation method, a display module, and an electronic device for improving the efficiency of light-emitting devices in a display module.

[0007] To achieve the above objectives, this application adopts the following technical solutions:

[0008] In a first aspect of an embodiment of the present application, a driver backplane is provided, comprising a substrate, a driver circuit layer, a reflective layer, and a first bonding layer, wherein the driver circuit layer, the reflective layer, and the first bonding layer are sequentially arranged on the same side of the substrate. The reflective layer comprises a first dielectric layer and a second dielectric layer stacked together, wherein the first dielectric layer and the second dielectric layer have different refractive indices. The thickness, material, and number of layers of the first dielectric layer and the second dielectric layer included in the reflective layer may vary in different driver backplanes. The first bonding layer is connected to the driver circuit layer via conductive pillars, thereby achieving bonding between the driver backplane and the epitaxial wafer.

[0009] The reflective layer of the driver backplane includes one or more first dielectric layers and one or more second dielectric layers stacked together. The number, thickness, and material of the first and second dielectric layers can be adjusted according to the needs. When the driver backplane is applied to the display module, the structure of the first and second dielectric layers can be adjusted according to the light-emitting wavelength of the light-emitting device in the display module, so that the reflectivity of the reflective layer for red light, green light, and blue light can reach more than 90%, thereby improving the efficiency of the light-emitting device in the display module. In addition, the material of the reflective layer is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard production line process of the driver backplane, the processing technology is simple, and low-cost mass production can be achieved.

[0010] In one possible implementation, the material of the first bonding layer includes a transparent conductive material. The material of the first bonding layer in the driver backplane includes a transparent conductive material, which has high light transmittance, further improving the transmittance of the reflected light in the reflective layer. Furthermore, the first bonding layer does not include metals such as gold, eliminating metal contamination issues. It is compatible with standard driver backplane production lines, offers simple processing, and enables low-cost mass production.

[0011] In one possible implementation, there are multiple first dielectric layers and multiple second dielectric layers, which are arranged alternately. The structure of the reflective layer can be flexibly modified to optimize the reflectivity of the reflective layer for visible light of different wavelengths.

[0012] In a possible implementation, the first bonding layer covers the reflective layer. The driving backplane provided in the embodiment of the present application is suitable for scenarios where non-aligned bonding is required.

[0013] In one possible implementation, the first bonding layer includes a first patterned bonding area and a first dielectric area; the first patterned bonding area is disposed within the first dielectric area and extends through the first dielectric area along its thickness; the driver circuit layer includes a back-end metal interconnect pad, and the first patterned bonding area is connected to the back-end metal interconnect pad via a conductive pillar. The driver backplane provided in this embodiment of the application is suitable for use in scenarios requiring alignment and bonding.

[0014] In one possible implementation, the materials of the first dielectric layer and the second dielectric layer include silicon oxide, titanium dioxide, tantalum pentoxide, or niobium pentoxide, which are technically mature materials and do not require the development of new dielectric materials.

[0015] In one possible implementation, the material of the first dielectric region includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide, or niobium pentoxide. These are technically mature materials, and there is no need to develop new dielectric materials.

[0016] In one possible implementation, the material of the first patterned bonding region includes indium tin oxide, aluminum zinc oxide, or transparent conductive oxide, which is a mature material, eliminating the need to develop new transparent conductive materials.

[0017] A second aspect of the present application provides an epitaxial wafer comprising: a substrate, an epitaxial stack, and a second bonding layer; the epitaxial stack and the second bonding layer are sequentially disposed on the same side of the substrate; the second bonding layer is used to bond the epitaxial wafer to a driver backplane; the second bonding layer is made of a transparent conductive material.

[0018] The second bonding layer in the epitaxial wafer consists of a transparent conductive material. Transparent conductive materials have higher light transmittance than metal materials, further improving the efficiency of light-emitting devices. Furthermore, the second bonding layer does not contain metals such as gold, eliminating metal contamination and enabling low-cost mass production. Furthermore, the second bonding layer can be directly reused as an electrode layer, simplifying the epitaxial wafer's film structure and fabrication process.

[0019] In a possible implementation, the second bonding layer covers the epitaxial stack. The driving backplane provided in the embodiment of the present application is suitable for scenarios where non-aligned bonding is required.

[0020] In one possible implementation, the second bonding layer includes a second patterned bonding region and a second dielectric region; the second patterned bonding region is disposed within the second dielectric region and extends through the second dielectric region along the thickness direction of the second dielectric region. The driver backplane provided in this embodiment of the application is suitable for use in scenarios requiring alignment and bonding.

[0021] In one possible implementation, the material of the second dielectric region includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide, or niobium pentoxide. These are technically mature materials, eliminating the need to develop new dielectric materials.

[0022] In one possible implementation, the material of the second patterned bonding region includes indium tin oxide, aluminum zinc oxide, or transparent conductive oxide, which is a mature material, eliminating the need to develop new transparent conductive materials.

[0023] In one possible implementation, the epitaxial stack includes a second semiconductor layer, an active layer, and a first semiconductor layer stacked sequentially on one side of a substrate. In one possible implementation, the first semiconductor layer includes multiple emitters, one of which is an N-type semiconductor layer and the other is a P-type semiconductor layer. This light-emitting structure is simple and has a wide range of applications.

[0024] In a possible implementation, the epitaxial wafer further includes a first electrode layer, which is disposed between the second bonding layer and the epitaxial stack. In this structure, the material of the first electrode layer and the material of the second bonding layer can be different materials.

[0025] A third aspect of the present application provides a display module comprising a substrate, a driving circuit layer, a reflective layer, a bonding layer, and a plurality of light-emitting devices, sequentially arranged on one side of the substrate. The reflective layer comprises a first dielectric layer and a second dielectric layer stacked together, the first and second dielectric layers having different refractive indices. The bonding layer is connected to the light-emitting devices and to the driving circuit layer via conductive pillars.

[0026] In the display module provided in the embodiment of the present application, the reflective layer includes one or more first dielectric layers and one or more second dielectric layers stacked together. The number of layers, thickness, and material of the first and second dielectric layers can be adjusted to match the needs. The structure of the first and second dielectric layers can be adjusted according to the light emission wavelength of the light-emitting device in the display module, so that the reflectivity of the reflective layer for red light, green light, and blue light can reach more than 90%, thereby improving the light emission efficiency of the display module. In addition, the material of the reflective layer is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard production line process, the processing technology is simple, and low-cost mass production can be achieved.

[0027] In one possible implementation, the bonding layer comprises a transparent conductive material. Transparent conductive materials have high light transmittance, further improving the light extraction efficiency of the display module. Furthermore, the bonding layer does not contain metals such as gold, eliminating metal contamination issues. This material is compatible with standard production line processes, simplifies processing, and enables low-cost mass production.

[0028] In one possible implementation, the bonding layer includes a patterned bonding region and a dielectric region. The patterned bonding region is disposed within the dielectric region and extends through the dielectric region along its thickness. Both the patterned bonding region and the dielectric region are made of transparent materials, further improving the efficiency of the light-emitting device.

[0029] In one possible implementation, the sum of the thickness of the bonding layer and the reflective layer ranges from 100 nm to 2000 nm. Based on the characteristics of the bonding layer provided in this application, the thickness of the bonding layer can be less than 2000 nm, making subsequent etching processes easier to perform.

[0030] In one possible implementation, the light-emitting device includes a first semiconductor layer, an active layer, a second semiconductor layer, and a second electrode, which are arranged in sequence in a direction away from the bonding layer; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

[0031] In one possible implementation, the light-emitting device further includes a first electrode disposed between the first semiconductor layer and the bonding layer. In this structure, the first electrode is an independent film layer, and the bonding layer is not reused as the first electrode, which can reduce restrictions on the bonding layer material.

[0032] According to a fourth aspect of an embodiment of the present application, an electronic device is provided, comprising a display module and a processor, wherein the processor is configured to control the display module to display an image; the display module comprises the display module of any one of the third aspects.

[0033] A fifth aspect of the embodiments of the present application provides a method for manufacturing a driver backplane, comprising: forming a driver circuit layer on a substrate; forming a reflective layer on a side of the driver circuit layer away from the substrate; the reflective layer comprising a first dielectric layer and a second dielectric layer stacked together, the first dielectric layer and the second dielectric layer having different refractive indices; forming a first bonding layer on a side of the reflective layer away from the substrate; and connecting the first bonding layer to the driver circuit layer via conductive pillars. The beneficial effects of the driver backplane obtained by the manufacturing method provided by the embodiments of the present application are the same as those of the driver backplane provided by the first aspect and are not further described here.

[0034] In a possible implementation, forming a first bonding layer on a side of the reflective layer away from the substrate includes: depositing the first bonding layer covering the reflective layer on a side of the reflective layer away from the substrate, wherein the material of the first bonding layer includes a transparent conductive material.

[0035] In one possible implementation, the first bonding layer includes a first patterned bonding area and a first dielectric area. The first bonding layer is formed on the side of the reflective layer away from the substrate, including: depositing a first bonding film covering the reflective layer on the side of the reflective layer away from the substrate, the material of the first bonding film including a transparent conductive material; patterning the first bonding film to form a first patterned bonding area; coupling the first patterned bonding area to the back-end metal interconnect pad of the driving circuit layer; and forming a first dielectric area on the side of the reflective layer away from the substrate, the first dielectric area wrapping the side first dielectric area of ​​the first patterned bonding area.

[0036] A sixth aspect of the present application provides a method for preparing an epitaxial wafer, comprising: forming an epitaxial stack on a substrate; forming a second bonding layer on a side of the epitaxial stack away from the substrate; wherein the second bonding layer comprises a transparent conductive material. The beneficial effects of the epitaxial wafer obtained by the preparation method provided by this embodiment of the present application are the same as those of the epitaxial wafer provided by the second aspect and are not further elaborated here.

[0037] In one possible implementation, forming a second bonding layer on the side of the epitaxial stack facing away from the substrate includes depositing the second bonding layer overlying the epitaxial stack on the side facing away from the substrate. In this structure, the second bonding layer can be reused as the first electrode layer, simplifying the epitaxial wafer fabrication process.

[0038] In one possible implementation, the second bonding layer includes a second patterned bonding region and a second dielectric region. Forming the second bonding layer on the side of the epitaxial stack away from the substrate involves: forming a second bonding film on the side of the epitaxial stack away from the substrate, wherein the second bonding film is made of a transparent conductive material; patterning the second bonding film to form multiple second patterned bonding regions; and forming a second dielectric region on the side of the first electrode layer away from the substrate, wherein the second dielectric region wraps around the side of the second patterned bonding region. In this structure, a portion of the second patterned bonding region can be reused as the first electrode layer, simplifying the epitaxial wafer fabrication process.

[0039] In one possible implementation, before forming the second bonding layer on the side of the epitaxial stack facing away from the substrate, the fabrication method further includes forming a first electrode layer on the side of the epitaxial stack facing away from the substrate. In this structure, the epitaxial wafer includes the first electrode layer, which reduces restrictions on the material of the second bonding layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application;

[0041] FIG2A is a schematic diagram of a manufacturing process of a display module according to an embodiment of the present application;

[0042] FIG2B is a schematic diagram of a manufacturing process of a display module according to an embodiment of the present application;

[0043] FIG3A is a schematic structural diagram of a driving backplane provided in an embodiment of the present application;

[0044] FIG3B is a schematic structural diagram of an epitaxial wafer provided in an embodiment of the present application;

[0045] FIG3C is a schematic structural diagram of a bonded wafer provided in an embodiment of the present application;

[0046] FIG4 is a schematic diagram of a process for preparing a driver backplane according to an embodiment of the present application;

[0047] 5 to 9 are schematic diagrams of a process for preparing a driver backplane according to an embodiment of the present application;

[0048] FIG10 is a schematic diagram of a process for preparing an epitaxial wafer according to an embodiment of the present application;

[0049] Figures 11 to 13 are schematic diagrams of a process for preparing a sheet according to an embodiment of the present application;

[0050] 14A and 14B are schematic structural diagrams of a bonded wafer provided in an embodiment of the present application;

[0051] FIG15 is a schematic diagram of a manufacturing process of another driving backplane provided in an embodiment of the present application;

[0052] FIG16 is a schematic diagram of another process for preparing an epitaxial wafer according to an embodiment of the present application;

[0053] Figures 17 to 22 are schematic diagrams of another process for preparing a stretched sheet according to an embodiment of the present application;

[0054] 23A and 23B are schematic structural diagrams of another bonded wafer provided in an embodiment of the present application;

[0055] 24A and 24B are schematic structural diagrams of a display module provided in an embodiment of the present application. DETAILED DESCRIPTION

[0056] The technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments.

[0057] Hereinafter, the terms "second," "first," etc., are used for descriptive convenience only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature qualified as "second," "first," etc. may explicitly or implicitly include one or more of such features. In the description of this application, unless otherwise specified, "plurality" means two or more.

[0058] In the embodiments of the present application, directional terms such as "up", "down", "left" and "right" may be defined including but not limited to the orientation relative to the components schematically placed in the drawings. It should be understood that these directional terms may be relative concepts, which are used for relative description and clarification, and may change accordingly according to changes in the orientation of the components in the drawings.

[0059] In the embodiments of the present application, unless otherwise clearly specified and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integrated connection; it can be a direct connection or an indirect connection through an intermediate medium.

[0060] In the embodiments of the present application, "and / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can represent: A exists alone, A and B exist simultaneously, and B exists alone. A and B can be singular or plural. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0061] The embodiments of the present application provide an electronic device, which may be, for example, a consumer electronic product with a display module, a home electronic product, a vehicle-mounted electronic product, or a financial terminal product. Consumer electronic products include virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, mixed reality (MR) electronic devices, mobile phones, tablet computers, notebooks, personal digital assistants (PDAs), etc. Home electronic products include smart door locks, rechargeable small household appliances (such as soymilk machines, sweeping robots), etc. Vehicle-mounted electronic products include vehicle-mounted navigation systems, vehicle-mounted computers, etc. The embodiments of the present application do not impose any special restrictions on the specific forms of the above-mentioned electronic devices.

[0062] FIG1 is a structural diagram of an electronic device provided in an embodiment of the present application.

[0063] AR electronic devices are wearable devices that can be worn on the human head for display. They use computer technology to superimpose virtual information onto the real world, allowing the real environment and virtual objects to be superimposed on the same screen in real time, achieving mutual complementation of the two types of information, and interacting with visual, auditory and other information. They also display images in front of the user through helmets, glasses and other devices, enhancing the user's sense of reality.

[0064] Taking the electronic device as AR glasses as an example, as shown in FIG1 , the AR glasses include a display module 1 , a frame 2 , and lenses 3 .

[0065] The frame 2 includes temples 21, on which the display module 1 can be mounted, i.e., the display module 1 is positioned sideways. A lens 3 is also mounted on the frame 2, for example, the frame 2 and the lens 3 are fixed. Alternatively, the frame 2 also includes a frame 22, in which the lens 3 is mounted.

[0066] In some embodiments, the AR glasses also incorporate an optical waveguide structure, which comprises three components: an incident light coupling, a waveguide, and an outgoing light coupling. For example, the optical waveguide structure is integrated into the lens 3. The optical signal emitted by the display module 1 is coupled into the waveguide via the incident coupling component. The light coupled into the waveguide adjusts its transmission direction and enters the human eye via the outgoing light coupling component, thereby achieving transmission of the optical signal from the display module 1 to the entrance pupil of the human eye.

[0067] The display module 1 included in the AR glasses may be one or more. In the embodiment of the present application, the AR glasses are illustrated by taking the example of including one display module 1 .

[0068] In some embodiments, the AR glasses further include a processor, which is used to control the display module 1 to display images.

[0069] Micro LEDs (micro light-emitting diodes) are widely used as light-emitting chips in miniature display modules due to their fast response, autonomous illumination, high brightness, low power consumption, high resolution, and excellent color saturation. Large-scale, low-cost manufacturing of display modules is a key factor in the penetration of Micro LED technology. Currently, display modules containing Micro LEDs are fabricated by bonding a driver backplane to an epitaxial wafer.

[0070] In one implementation, bonding layers are respectively formed on the driving backplane and the epitaxial wafer, and then a bonding process is performed to connect the driving backplane and the epitaxial wafer. Finally, the bonded wafer is processed to form the display module 1 .

[0071] FIG. 2A is a schematic diagram illustrating a process for preparing a display module according to an embodiment of the present application.

[0072] In some embodiments, as shown in FIG2A , the process of preparing the display module 1 includes: forming a driving backplane 30, the driving backplane 30 includes a substrate 31, a driving circuit layer 32, a reflective layer 34 (the material is a metal with a high reflectivity, such as silver (Ag)), and a first bonding layer 33 covering the surface of the reflective layer 34, the material of the first bonding layer 33 includes a gold / tin (Au / Sn) alloy. Forming an epitaxial wafer 40, the epitaxial wafer 40 includes a base 41, an epitaxial stack 42′, and a second bonding layer 44, the material of the second bonding layer 44 includes a gold / tin alloy. Bonding the first bonding layer 33 of the driving backplane 30 to the second bonding layer 44 of the epitaxial wafer 40 to form a bonded wafer. The bonded wafer is then processed to form the display module 1 (this step is not shown in FIG2A ).

[0073] In the above process, the materials of the first bonding layer 33 and the second bonding layer 44 include a gold / tin alloy. The reflectivity of the gold material in the visible light wavelength range is approximately 40%-90%, and the reflectivity varies greatly in the red, green, and blue light wavelength ranges, with the reflectivity in the blue light wavelength range being approximately 30%-40%, the reflectivity in the green light wavelength range being approximately 70%, and the reflectivity in the red light wavelength range being greater than 80%. In order to improve the efficiency of the light-emitting device, a reflective layer 34 is required to increase the reflectivity, thereby improving the efficiency of the light-emitting device. However, after the reflective layer 34 is provided, the improvement in the reflectivity of the stack of the reflective layer 34, the first bonding layer 33, and the second bonding layer 44 in the visible light wavelength range is not ideal.

[0074] FIG. 2B is a schematic diagram illustrating a process for preparing a display module according to an embodiment of the present application.

[0075] In some embodiments, as shown in FIG2B , the process of preparing a display module 1 includes: forming a driving backplane 30, which includes a substrate 31, a driving circuit layer 32, a reflective layer 34 (made of a metal with a high reflectivity, such as silver), and a first bonding layer 33. The first bonding layer 33 includes a first patterned bonding area 331 and a first dielectric area 332 surrounding the first patterned bonding area 331, and the material of the first patterned bonding area 331 includes copper (Cu). Forming an epitaxial wafer 40, which includes a base 41, a light-emitting structure 42, and a second bonding layer 44. The second bonding layer 44 includes a second patterned bonding area 441 and a second dielectric area 442 surrounding the second patterned bonding area 441, and the material of the second patterned bonding area 441 includes copper. The first bonding layer 33 of the driving backplane 30 is bonded to the second bonding layer 44 of the epitaxial wafer 40, and the first patterned bonding area 331 and the second patterned bonding area 441 are aligned and bonded to form a bonded wafer. The bonded wafers are then processed to form a display module 1 (this step is not shown in FIG. 2B ).

[0076] In the above process, the material of the first patterned bonding area 331 and the second patterned bonding area 441 includes copper. The reflectivity of copper material in the visible light wavelength range is approximately 60%-90%, and the reflectivity varies greatly among the red, green, and blue light wavelength ranges, with the reflectivity in the blue light wavelength range being approximately 60%-70%, the reflectivity in the green light wavelength range being approximately 60%-70%, and the reflectivity in the red light wavelength range being approximately 90%. In order to improve the efficiency of the light-emitting device, a reflective layer 34 is required to increase the reflectivity, thereby improving the efficiency of the light-emitting device. However, after the reflective layer 34 is provided, the improvement in the reflectivity of the stack of reflective layer 34, first bonding layer 33, and second bonding layer 44 in the visible light wavelength range is not ideal.

[0077] The embodiment of the present application provides a new driving backplane 30 and epitaxial wafer 40 for improving the device efficiency of the display module 1 .

[0078] FIG3A is a schematic structural diagram of a driving backplane provided in an embodiment of the present application.

[0079] An embodiment of the present application provides a driving backplane 30 , as shown in FIG3A . The driving backplane 30 includes a substrate 31 , a driving circuit layer 32 , a reflective layer 34 , and a first bonding layer 33 . The driving circuit layer 32 , the reflective layer 34 , and the first bonding layer 33 are sequentially arranged on one side of the substrate 31 .

[0080] In some embodiments, the reflective layer 34 includes a first dielectric layer 341 and a second dielectric layer 342 that are stacked. The first dielectric layer 341 and the second dielectric layer 342 have different refractive indices.

[0081] For example, the first dielectric layer 341 and the second dielectric layer 342 are made of different materials, so that the refractive indices of the first dielectric layer 341 and the second dielectric layer 342 are different.

[0082] Optionally, the materials of the first dielectric layer 341 and the second dielectric layer 342 are both transparent dielectric materials. For example, the materials of the first dielectric layer 341 and the second dielectric layer 342 include inorganic materials such as silicon oxide (SiO2), titanium dioxide (TiO2), tantalum pentoxide (Ta2O5), and niobium pentoxide (Nb2O5). In one possible implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is TiO2. In another possible implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is Ta2O5. In yet another implementation, the material of the first dielectric layer 341 is SiO2, and the material of the second dielectric layer 342 is Nb2O5.

[0083] In some embodiments, the reflective layer 34 only includes a first dielectric layer 341 and a second dielectric layer 342 , and the first dielectric layer 341 and the second dielectric layer 342 are stacked along the thickness direction of the driving backplate 30 .

[0084] In other embodiments, as shown in FIG3A , there are multiple first dielectric layers 341 in the reflective layer 34 , and there are multiple second dielectric layers 342 in the reflective layer 34 . The multiple first dielectric layers 341 and the multiple second dielectric layers 342 are alternately arranged along the thickness direction of the driving backplane 30 .

[0085] Alternatively, one first dielectric layer 341 and one second dielectric layer 342 constitute a repeating period, and multiple first dielectric layers 341 and multiple second dielectric layers 342 are divided into multiple repeating periods, which are stacked along the thickness direction of the driver backplane 30. The thickness of the first dielectric layer 341 in each repeating period can be equal or unequal. The thickness of the second dielectric layer 342 in each repeating period can be equal or unequal.

[0086] For example, the material of the first dielectric layer 341 in each repeating period is the same, and the material of the second dielectric layer 342 in each repeating period is the same.

[0087] In the driving backplane 30 provided in the embodiment of the present application, the reflective layer 34 includes one or more first dielectric layers 341 and one or more second dielectric layers 342 stacked together. The number, thickness, and material of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the requirements. When the driving backplane 30 is applied to the display module 1, the structure of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the light-emitting wavelength of the light-emitting device in the display module 1, so that the reflectivity of the reflective layer 34 to red light, green light, and blue light can reach more than 90%, thereby improving the efficiency of the light-emitting device in the display module 1. In addition, the material of the reflective layer 34 is an inorganic thin film material, which does not need to include heavy metal materials such as silver (Ag), and there is no heavy metal pollution problem. It is compatible with the standard production line process of the driving backplane 30, the processing technology is simple, and low-cost mass production can be achieved.

[0088] In some embodiments, the first bonding layer 33 is connected to the driving circuit layer 32 via a conductive pillar. For example, the driving backplane 30 includes a first conductive pillar 35 that penetrates the reflective layer 34 along the thickness direction of the reflective layer 34. The two ends of the first conductive pillar 35 are respectively connected to the first bonding layer 33 and the driving circuit layer 32 to achieve the connection between the first bonding layer 33 and the driving circuit layer 32.

[0089] Illustratively, the material of the first bonding layer 33 includes metal.

[0090] Alternatively, for example, the material of the first bonding layer 33 includes a transparent conductive material.

[0091] For example, the material of the first bonding layer 33 includes indium tin oxide (ITO), aluminum zinc oxide (AZO), transparent conductive oxide (TCO), etc.

[0092] In the embodiment of the present application, the first bonding layer 33 of the driver backplane 30 comprises a transparent conductive material. Transparent conductive materials have higher light transmittance than metal materials, further improving the efficiency of the light-emitting device. Furthermore, the first bonding layer 33 does not contain metals such as gold (Au), eliminating metal contamination issues. The first bonding layer 33 is compatible with the standard production line process for the driver backplane 30, offering a simple process and enabling low-cost mass production.

[0093] FIG3B is a schematic structural diagram of an epitaxial wafer provided in an embodiment of the present application.

[0094] The present embodiment provides an epitaxial wafer 40, as shown in FIG3B , which includes a substrate 41, an epitaxial stack 42′, a first electrode layer 45, and a second bonding layer 44. The epitaxial stack 42′, the first electrode layer 45, and the second bonding layer 44 are sequentially arranged on one side of the substrate 41.

[0095] The second bonding layer 44 is connected to the first electrode layer 45 , and the material of the second bonding layer 44 includes a transparent conductive material.

[0096] For example, the material of the second bonding layer 44 includes ITO, AZO, TCO, etc. In some embodiments, the material of the first bonding layer 33 is the same as the material of the second bonding layer 44 .

[0097] In some embodiments, the material of the first electrode layer 45 includes a transparent conductive material. For example, the material of the first electrode layer 45 includes ITO, AZO, TCO, etc. For example, the material of the first electrode layer 45 is the same as the material of the second bonding layer 44.

[0098] In some embodiments, the first electrode layer 45 and the second bonding layer 44 are an integrally formed structure, and the two are simultaneously manufactured using the same process.

[0099] For example, the second bonding layer 44 is reused as the first electrode layer 45. Alternatively, a portion of the second bonding layer 44 is used as the first electrode layer 45. With this structure, the film structure of the epitaxial wafer 40 is simple, and the manufacturing process can also be simplified.

[0100] In the embodiment of the present application, the second bonding layer 44 in the epitaxial wafer 40 is made of a transparent conductive material. Transparent conductive materials have a higher light transmittance than metal materials, further improving the efficiency of the light-emitting device. Furthermore, the second bonding layer 44 does not contain metals such as gold (Au), eliminating metal contamination issues and enabling low-cost mass production.

[0101] FIG3C is a schematic structural diagram of a bonded wafer provided in an embodiment of the present application.

[0102] As shown in FIG3C , a first bonding layer 33 is prepared on the driving backplane 30 , and a second bonding layer 44 is prepared on the epitaxial wafer 40 . The first bonding layer 33 and the second bonding layer 44 are bonded to form a bonded wafer to achieve the connection between the driving backplane 30 and the epitaxial wafer 40 .

[0103] In some embodiments, the sum of the thicknesses L3 of the first bonding layer 33, the second bonding layer 44, and the reflective layer 34 after bonding is in the range of 100 nm to 2000 nm. For example, the sum of the thicknesses L3 is 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, or 1900 nm.

[0104] Based on the structure of the first bonding layer 33, the second bonding layer 44 and the reflective layer 34 provided in this application, the sum of the thickness L3 of the first bonding layer 33 and the second bonding layer 44 after bonding and the reflective layer 34 can be less than 2000nm, making the subsequent etching process easy to carry out.

[0105] The following is an illustrative description of the method for preparing the driving backplane 30 and the method for preparing the epitaxial wafer 40 provided in the embodiments of the present application.

[0106] Example 1

[0107] FIG4 is a schematic diagram of a process for preparing a driver backplane according to an embodiment of the present application, and FIG5 to FIG9 are schematic diagrams of a process for preparing a driver backplane according to an embodiment of the present application.

[0108] The present invention provides a method for preparing a driver backplane, as shown in FIG4 , and the method includes:

[0109] S1. As shown in FIG5 , a driving circuit layer 32 is formed on a substrate 31 .

[0110] For example, the substrate 31 is a single crystal silicon (Si) substrate, and a complementary metal oxide semiconductor (CMOS) process is used to form a driving circuit layer 32 on the substrate 31. For example, a front end of line (FEOL) process is used to form a transistor and other structures as the FEOL layer of the driving backplane 30. A back end of line (BEOL) process is used to form a wiring layer, a via, and a back-end metal interconnect pad (pad) and other structures as the BEOL layer of the driving backplane 30. The back-end metal interconnect pads of the driving circuit layer 32 include a plurality of pads, etc.

[0111] S2. As shown in FIG6 , a reflective film 34 ′ is formed on the side of the driving circuit layer 32 away from the substrate 31 .

[0112] The reflective film 34 ′ includes a first dielectric film 341 ′ and a second dielectric film 342 ′ stacked together. When the reflective film 34 ′ includes multiple layers of the first dielectric film 341 ′ and the second dielectric film 342 ′, the multiple layers of the first dielectric film 341 ′ and the multiple layers of the second dielectric film 342 ′ are alternately arranged.

[0113] For example, the first dielectric film 341' and the second dielectric film 342' in the reflective film 34' may be made of different materials or have different thicknesses. The multiple first dielectric films 341' may be made of the same material but may have different thicknesses. The multiple second dielectric films 342' may be made of the same material but may have different thicknesses.

[0114] For example, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is TiO2. Alternatively, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is Ta2O5. Alternatively, the material of the first dielectric film 341' is SiO2, and the material of the second dielectric film 342' is Nb2O5.

[0115] In the embodiment of the present application, there is no limitation on the number of layers, thickness of each layer, and material of each layer of the first dielectric film 341′ and the second dielectric film 342′ in the reflective layer 34. These layers can be adjusted based on the desired reflectivity of the reflective layer 34. FIG6 illustrates an example of a reflective layer 34 including a plurality of stacked first dielectric films 341′ and a plurality of second dielectric films 342′.

[0116] S3 . As shown in FIG. 7 , forming via holes on the reflective film 34 ′ to form a reflective layer 34 .

[0117] The via holes penetrate the reflective film 34' and communicate with the back-end metal interconnect pads of the driving circuit layer 32. For example, the reflective film 34' is patterned by exposure, development, etching and other processes to form the reflective layer 34.

[0118] S4 . As shown in FIG. 8 , a first conductive pillar 35 is formed in the via hole in the reflective layer 34 .

[0119] For example, step S4 includes:

[0120] S41 , depositing a metal film on the reflective layer 34 , wherein the metal film fills the via holes and connects to the back-end metal interconnect pads, and covers the reflective layer 34 .

[0121] For example, the material of the metal film includes aluminum (Al), tungsten (W), and other metals with low resistance and good hole-filling effect.

[0122] S42: Planarize the metal film by etching or chemical mechanical polishing, remove the metal film on the surface of the reflective layer 34, and retain the metal film in the via hole to form a first conductive pillar 35. The first conductive pillar 35 is made of a metal such as aluminum or tungsten.

[0123] S5. As shown in FIG9 , a first bonding layer 33 is formed on the side of the reflective layer 34 away from the substrate 31 .

[0124] For example, step S5 includes: depositing a first bonding layer 33 covering the reflective layer 34 and the first conductive pillar 35 on the side of the reflective layer 34 away from the substrate 31, the first bonding layer 33 is connected to the first conductive pillar 35, and the first bonding layer 33 is connected to the back-end metal interconnection pad of the driving circuit layer 32 through the first conductive pillar 35.

[0125] In some embodiments, the first bonding layer 33 covers the reflective layer 34 and the first conductive pillars 35 , and the first bonding layer 33 is made of a transparent conductive material.

[0126] At this point, the driving backplane 30 provided in the embodiment of the present application is prepared. The first bonding layer 33 in the driving backplane 30 provided in this example is a structure in which the entire layer is made of conductive material. When the driving backplane 30 is subsequently bonded to the epitaxial wafer 40, a non-alignment process can be used for bonding, which can reduce the process difficulty.

[0127] FIG10 is a schematic diagram of a preparation process of an epitaxial wafer provided in an embodiment of the present application, and FIG11 to FIG13 are schematic diagrams of a preparation process of an epitaxial wafer provided in an embodiment of the present application.

[0128] The present embodiment provides a method for preparing an epitaxial wafer 40, as shown in FIG10 , and the preparation method includes:

[0129] S10 , as shown in FIG11 , an epitaxial stack 42 ′ is formed on the substrate 41 .

[0130] The base 41 includes, for example, a sapphire substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, a single crystal silicon substrate, a zinc oxide (ZnO) substrate, or the like.

[0131] In some embodiments, step S10 includes:

[0132] S101 , forming a nucleation film 421 ′ on a substrate 41 .

[0133] For example, the nucleation film 421 ′ may be formed by a metal-organic chemical vapor deposition (MOCVD) growth method or a molecular beam epitaxy (MBE) growth method.

[0134] The material of the nucleation film 421 ′ may include, for example, one or more of GaN, aluminum gallium nitride (AlGaN), and aluminum nitride (AlN).

[0135] S102 , forming a buffer film 422 ′ on a side of the nucleation film 421 ′ away from the substrate 41 .

[0136] For example, an MOCVD process may be used to epitaxially grow an AlGaN graded layer with a gradually decreasing Al (aluminum) composition.

[0137] The buffer film 422 ′ may be a graded buffer layer. The buffer film 422 ′ may be a GaN layer, an AlN / GaN superlattice structure layer, or a combination of the aforementioned structures.

[0138] S103 , forming a second semiconductor film 423 ′ on a side of the buffer film 422 ′ away from the substrate 41 .

[0139] For example, the second semiconductor film 423' is formed by an MOCVD growth method or an MBE growth method.

[0140] S104 , forming an active film 424 ′ on a side of the second semiconductor film 423 ′ away from the substrate 41 .

[0141] The active film 424 ′ is used to emit light of different colors. The material of the active film 424 ′ includes, for example, indium gallium nitride (InGaN). By adjusting the In component in InGaN, light of different colors can be emitted.

[0142] S105 , forming a first semiconductor film 425 ′ on a side of the active film 424 ′ away from the substrate 41 .

[0143] For example, the first semiconductor film 425' is formed by using an MOCVD growth method or an MBE growth method.

[0144] In some embodiments, the second semiconductor film 423 ′ and the first semiconductor film 425 ′ are N-type semiconductor films and P-type semiconductor films, respectively.

[0145] For example, the second semiconductor film 423′ can be an N-type semiconductor film. For example, the N-type semiconductor film can be formed by doping a semiconductor material, such as gallium nitride. In an N-type semiconductor film, free electrons are majority carriers and holes are minority carriers, and electrical conduction is primarily achieved through free electrons. The higher the concentration of free electrons, the stronger the conductivity of the N-type semiconductor film.

[0146] The first semiconductor film 425′ can be a P-type semiconductor film. For example, the P-type semiconductor film can be formed by doping a semiconductor material, such as gallium nitride. In a P-type semiconductor film, holes are majority carriers and free electrons are minority carriers, and electrical conduction is primarily due to holes. The higher the hole concentration, the stronger the conductivity of the P-type semiconductor film.

[0147] In some embodiments, the epitaxial stack 42′ includes a nucleation film 421′, a buffer film 422′, a second semiconductor film 423′, an active film 424′, and a first semiconductor film 425′. The structure of the epitaxial stack 42′ provided in the embodiment of the present application is only a schematic diagram, and film layers can be added or reduced on the basis of the above structure. For example, the epitaxial stack 42′ only includes the first semiconductor film 425′, the active film 424′, and the second semiconductor film 423′. When the epitaxial wafer is bonded to the driving backplane using a non-aligned process, the first semiconductor film 425′, the active film 424′, and the second semiconductor film 423′ serve as the first semiconductor layer 425, the active layer 424, and the second semiconductor layer 423 of the epitaxial stack 42′.

[0148] S20 , as shown in FIG. 12 and FIG. 13 , a first electrode layer 45 and a second bonding layer 44 are formed on a side of the epitaxial stack 42 ′ away from the substrate 41 .

[0149] In some embodiments, as shown in FIG12 , step S20 includes:

[0150] S21 , forming a first electrode layer 45 on a side of the epitaxial stack 42 ′ away from the substrate 41 .

[0151] For example, the material of the first electrode layer 45 includes a transparent conductive material. The first electrode layer 45 is provided on the surface of the first semiconductor film 425′ and is connected to the first semiconductor film 425′. If the first semiconductor film 425′ is a P-type semiconductor layer, the first electrode layer 45 connected to the first semiconductor film 425′ serves as a P-electrode.

[0152] S22 , forming a second bonding layer 44 on a side of the first electrode layer 45 away from the substrate 41 .

[0153] For example, step S22 includes: depositing a second bonding layer 44 covering the first electrode layer 45 on a side of the first electrode layer 45 away from the substrate 41 . In some embodiments, the second bonding layer 44 covers the first electrode layer 45 .

[0154] The second bonding layer 44 is connected to the first electrode layer 45. For example, the second bonding layer 44 is formed on the surface of the first electrode layer 45 and is in contact with the first electrode layer 45. The material of the second bonding layer 44 includes, for example, a transparent conductive material.

[0155] In this structure, the materials of the first electrode layer 45 and the second bonding layer 44 can be different, which reduces the requirement for material consistency.

[0156] In some other embodiments, as shown in FIG13 , step S20 includes:

[0157] A second bonding layer 44 is formed on the side of the epitaxial stack 42' away from the substrate 41, and the second bonding layer 44 is reused as the first electrode layer 45. For example, the material of the second bonding layer 44 includes a transparent conductive material.

[0158] In this structure, the first electrode layer 45 and the second bonding layer 44 can be formed in one process, which can simplify the preparation process of the epitaxial wafer.

[0159] As shown in FIG. 12 and FIG. 13 , in this example, the second bonding layer 44 , the first electrode layer 45 , and the epitaxial stack 42 ′ are not patterned.

[0160] At this point, the epitaxial wafer 40 provided in the embodiment of the present application is prepared. The second bonding layer 44 in the epitaxial wafer 40 provided in this example is a structure in which the entire layer is made of conductive material. As shown in Figures 14A and 14B, when bonding the driving backplane 30 to the epitaxial wafer 40, a non-alignment process can be used to bond the first bonding layer 33 and the second bonding layer 44, which can reduce the process difficulty.

[0161] Example 2

[0162] FIG15 is a schematic diagram of a process for preparing a driving backplane provided in an embodiment of the present application.

[0163] The present invention provides a method for preparing a driver backplane, as shown in FIG4 , and the method includes:

[0164] S1. As shown in FIG5 , a driving circuit layer 32 is formed on a substrate 31 .

[0165] S2. As shown in FIG6 , a reflective film 34 ′ is formed on the side of the driving circuit layer 32 away from the substrate 31 .

[0166] S3 . As shown in FIG. 7 , forming via holes on the reflective film 34 ′ to form a reflective layer 34 .

[0167] S4 . As shown in FIG. 8 , a first conductive pillar 35 is formed in the via hole in the reflective layer 34 .

[0168] Steps S1-S4 are the same as steps S1-S4 in Example 1. Please refer to the above related descriptions and will not be repeated here.

[0169] S5. As shown in FIG. 15 , a first bonding layer 33 is formed on a side of the reflective layer 34 away from the substrate 31 .

[0170] In some embodiments, step S5 includes:

[0171] S51 , depositing a first bonding film 33 ′ covering the reflective layer 34 and the first conductive pillars 35 on a side of the reflective layer 34 away from the substrate 31 . The material of the first bonding film 33 ′ includes a transparent conductive material.

[0172] S52 , patterning the first bonding film 33 ′ to form a first patterned bonding region 331 .

[0173] The first patterned bonding area 331 is connected to the driving circuit layer 32 through the first conductive pillar 35 . The structure of the first patterned bonding area 331 corresponds one-to-one to the back-end metal interconnection pad in the driving circuit layer 32 .

[0174] S53 , forming a first dielectric region 332 on a side of the reflective layer 34 away from the substrate 31 .

[0175] The first dielectric region 332 fills the gap area around the first patterned bonding region 331 and wraps the side surface of the first patterned bonding region 331 to achieve electrical insulation.

[0176] For example, step S53 includes:

[0177] S531 , depositing a third dielectric film 332 ′ covering the first patterned bonding region 331 and the reflective layer 34 on a side of the reflective layer 34 away from the substrate 31 .

[0178] S532 , performing a planarization process on the third dielectric film 332 ′ by using an etching or chemical mechanical polishing process to planarize the surface of the third dielectric film 332 ′ and form the first dielectric region 332 .

[0179] As shown in FIG15 , the driving backplane 30 includes a substrate 31, a driving circuit layer 32, a reflective layer 34, and a first bonding layer 33. The first bonding layer 33 includes a first patterned bonding area 331 and a first dielectric area 332. The first patterned bonding area 331 is disposed within the first dielectric area 332 and penetrates the first dielectric area 332 along the thickness direction of the first dielectric area 332. The first patterned bonding area 331 can be connected to the back-end metal interconnect pad in the driving circuit layer 32 through the first conductive pillar 35.

[0180] For example, the material of the first dielectric region 332 includes inorganic materials such as silicon dioxide (SiO 2 ) and silicon nitride (SiN).

[0181] At this point, the driver backplane 30 provided in the embodiment of the present application is prepared. The first bonding layer 33 in the driver backplane 30 provided in this example is a patterned structure. When the driver backplane 30 is subsequently bonded to the epitaxial wafer 40, an alignment process can be used for bonding.

[0182] Figure 16 is a schematic diagram of the process for preparing an epitaxial wafer according to an embodiment of the present application. Figures 17 to 21 are schematic diagrams of the process for preparing an epitaxial wafer according to an embodiment of the present application.

[0183] The present embodiment provides a method for preparing an epitaxial wafer 40, as shown in FIG16 , and the preparation method includes:

[0184] S10 , as shown in FIG17 , forming an epitaxial stack 42 ′ on the substrate 41 .

[0185] In some embodiments, step S10 includes:

[0186] First, steps S101 to S105 in Example 1 are performed to form a stack of a nucleation film 421 ′, a buffer film 422 ′, a second semiconductor film 423 ′, an active film 424 ′, and a first semiconductor film 425 ′.

[0187] S106 , as shown in FIG. 17 , patterning the second semiconductor film 423 ′, the active film 424 ′ and the first semiconductor film 425 ′ to form a light emitting structure 42 .

[0188] For example, patterning is performed using processes such as exposure, development, and etching, and the light-emitting structure 42 serves as a Micro LED light-emitting pixel (mesa) unit structure.

[0189] Depending on the structure of the epitaxial stack 42′, the film layers patterned for the epitaxial stack 42′ are also different. However, regardless of the structure, the first semiconductor film 425′, the active film 424′, and the second semiconductor film 423′ in the epitaxial stack 42′ need to be patterned. As shown in Figure 17, after the epitaxial stack 42′ is patterned, the light-emitting structure 42 formed includes the first semiconductor layer 425, the active layer 424, and the second semiconductor layer 423. The nucleation film 421′ and the buffer film 422′ in the epitaxial stack 42′ do not need to be patterned. Of course, the nucleation film 421′ and the buffer film 422′ can also be patterned.

[0190] In some embodiments, after executing step 106 , the light emitting structure 42 may be passivated to eliminate etching damage, surface defects, and other issues of the light emitting structure 42 , thereby improving the light emitting efficiency of the light emitting structure 42 .

[0191] S20 , as shown in FIG. 18 , forming a first electrode layer 45 on the side of the epitaxial stack 42 ′ away from the substrate 41 .

[0192] The first electrode layer 45 is located on one side of the first semiconductor layer 425 . The first electrode layer 45 includes a plurality of first electrodes 451 . The first electrodes 451 are correspondingly connected to the first semiconductor layer 425 in the light emitting structure 42 and serve as driving electrodes of the light emitting structure 42 .

[0193] S21 . As shown in FIG. 19 , a planar layer 46 is formed. The planar layer 46 wraps the side surfaces of the first electrode 451 and the light emitting structure 42 .

[0194] For example, step S21 includes:

[0195] S211 , depositing a planar film to fill the gap between the first electrode 451 and the light emitting structure 42 .

[0196] S212: Planarize the planar film by etching or chemical mechanical polishing to expose the first electrode 451, thereby forming a planar layer 46. The material of the planar layer 46 includes, for example, silicon dioxide (SiO2), silicon nitride (SiN), and the like.

[0197] S22 , as shown in FIG. 20 , forming a second conductive column 47 .

[0198] For example, step S22 includes:

[0199] S221 , performing etching on the planar layer 46 by using processes such as exposure, development, and etching to form via holes, the positions of which correspond to the positions of the back-end metal interconnect pads in the driving circuit layer 32 .

[0200] S222 , depositing a conductive film to fill the via hole and cover the planar layer 46 .

[0201] S223 , planarizing the conductive film by etching or chemical mechanical polishing, removing the portion of the conductive film above the planarization layer 46 , and retaining the portion of the conductive film within the via hole as the second conductive pillar 47 .

[0202] S30 , as shown in FIG. 21 , forming a second bonding layer 44 on a side of the first electrode layer 45 away from the substrate 41 .

[0203] In some embodiments, the steps of forming the second bonding layer 44 are the same as the steps of forming the first bonding layer 33 .

[0204] For example, step S30 includes:

[0205] S301 , depositing a second bonding film covering the planar layer 46 , the first electrode layer 45 and the second conductive pillars 47 on a side of the planar layer 46 away from the substrate 41 , wherein the material of the second bonding film includes a transparent conductive material.

[0206] S302 , patterning the second bonding film to form a second patterned bonding region 441 .

[0207] The structure of the second patterned bonding region 441 corresponds to the back-end metal interconnect pad in the driving circuit layer 32 , and the first electrode layer 45 is connected to the second patterned bonding region 441 .

[0208] S303 , forming a second dielectric region 442 on a side of the planar layer 46 away from the substrate 41 .

[0209] The second dielectric region 442 fills the gap area around the second patterned bonding region 441 and wraps the side surface of the second patterned bonding region 441 to achieve electrical insulation.

[0210] For example, step S303 includes:

[0211] S3031 , depositing a fourth dielectric film covering the second patterned bonding region 441 and the planar layer 46 on a side of the planar layer 46 away from the substrate 41 .

[0212] S3032 , performing a planarization process on the fourth dielectric film by using an etching or chemical mechanical polishing process to planarize the surface of the fourth dielectric film and form a second dielectric region 442 .

[0213] In some embodiments, epitaxial wafer 40 includes substrate 41, epitaxial stack 42', first electrode layer 45, and second bonding layer 44. As shown in FIG21, epitaxial stack 42' includes multiple light emitting structures 42, each configured to emit light of the same color.

[0214] The light-emitting structure 42 includes a first semiconductor layer 425, an active layer 424, and a second semiconductor layer 423, which are stacked in sequence in a direction away from the second bonding layer 44. The first electrode layer 45 includes a plurality of first electrodes 451, which are arranged on a side of the first semiconductor layer 425 away from the substrate 41. The first electrodes 451 are in contact with the first semiconductor layer 425 and connected to the second patterned bonding region 441.

[0215] The second bonding layer 44 includes a second patterned bonding region 441 and a second dielectric region 442 . The second patterned bonding region 441 is disposed in the second dielectric region 442 and penetrates the second dielectric region 442 along a thickness direction of the second dielectric region 442 .

[0216] In other embodiments, as shown in Figure 22, the epitaxial wafer 40 does not include the first electrode layer 45, and the second patterned bonding region 441 is reused as the first electrode layer 45. After step S10 is performed, steps S21, S22, and S30 are directly performed.

[0217] The second bonding layer 44 includes a plurality of second patterned bonding regions 441 and a second dielectric region 442. The second patterned bonding regions 441 are disposed within the second dielectric region 442 and extend through the thickness of the second dielectric region 442. Among the plurality of second patterned bonding regions 441, the second patterned bonding regions 441 corresponding to the positions of the light-emitting structures 42 are reused as first electrodes 451 for driving the light-emitting structures 42 to emit light. The epitaxial wafer 40 does not include an independent first electrode layer 45.

[0218] At this point, the epitaxial wafer 40 provided in the embodiment of the present application is prepared. The second bonding layer 44 in the epitaxial wafer 40 provided in this example is a patterned structure, as shown in Figures 23A and 23B. When the driving backplane 30 is subsequently bonded to the epitaxial wafer 40, an alignment process is used to bond the first bonding layer 33 and the second bonding layer 44.

[0219] Example 3

[0220] The driving backplane 30 provided in Example 1 and Example 2 is bonded to the epitaxial wafer 40 to obtain a bonded wafer. After processing the bonded wafer, the display module 1 provided in the embodiment of the present application can be obtained.

[0221] 24A and 24B are schematic structural diagrams of a display module provided in an embodiment of the present application.

[0222] An embodiment of the present application provides a display module 1 , as shown in FIG24A . The display module 1 includes a substrate 31 and a driving circuit layer 32 , a reflective layer 34 , a bonding layer 50 , and a light-emitting device 60 sequentially arranged on one side of the substrate 31 .

[0223] The driving circuit layer 32 includes, for example, a pixel circuit for driving the light-emitting device 60 and a back-end metal interconnect pad corresponding to the pixel circuit.

[0224] The reflective layer 34 includes a first dielectric layer 341 and a second dielectric layer 342 stacked together. The first dielectric layer 341 and the second dielectric layer 342 have different refractive indices. The structure of the reflective layer 34 can refer to the above description of the reflective layer 34 in the driving backplane 30 and will not be repeated here.

[0225] The bonding layer 50 is connected to the light emitting device 60 and is connected to the driving circuit layer 32 via the first conductive pillar 35 , so as to transmit the signal of the driving circuit layer 32 to the light emitting device 60 .

[0226] In the display module 1 provided in the embodiment of the present application, the reflective layer 34 includes one or more first dielectric layers 341 and one or more second dielectric layers 342, which are stacked. The number of layers, thickness, and material of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted to match the needs. The structure of the first dielectric layer 341 and the second dielectric layer 342 can be adjusted according to the light emission wavelength of the light-emitting device in the display module 1, so that the reflectivity of the reflective layer 34 for red light, green light, and blue light can reach more than 90%, thereby improving the efficiency of the light-emitting device in the display module 1. In addition, the material of the reflective layer 34 is an inorganic thin film material, which does not need to include heavy metal materials such as silver, and there is no heavy metal pollution problem. It is compatible with the standard production line process of the driver backplane 30, and the processing technology is simple, which can achieve low-cost mass production.

[0227] In some embodiments, the material of the bonding layer 50 includes a transparent conductive material.

[0228] For example, the bonding layer 50 includes a plurality of patterned bonding regions 51 and a dielectric region 52 . The patterned bonding regions 51 are disposed in the dielectric region 52 and penetrate the dielectric region 52 along a thickness direction of the dielectric region 52 .

[0229] The bonding layer 50 is formed by bonding the first bonding layer 33 in the driver backplane 30 and the second bonding layer 44 in the epitaxial wafer 40. The patterned bonding region 51 is formed by bonding the first patterned bonding region 331 and the second patterned bonding region 441. The patterned bonding region 51 may have a bonding interface or may not have a bonding contact surface. The dielectric region 52 is formed by bonding the first dielectric region 332 in the driver backplane 30 and the second dielectric region 442 in the epitaxial wafer 40.

[0230] The plurality of light emitting devices 60 are disposed corresponding to the plurality of patterned bonding regions 51 .

[0231] In some embodiments, as shown in FIG. 24A , the light emitting device 60 includes a first electrode 451 , a first semiconductor layer 425 , an active layer 424 , a second semiconductor layer 423 , and a second electrode 48 sequentially disposed in a direction away from the bonding layer 50 .

[0232] In other embodiments, as shown in Figure 24B, the light-emitting device 60 includes a first semiconductor layer 425, an active layer 424, a second semiconductor layer 423 and a second electrode 48 arranged in sequence along a direction away from the bonding layer 50, and the patterned bonding area 51 arranged corresponding to the light-emitting structure 42 is reused as the first electrode 451 in the light-emitting device 60.

[0233] The bonding layer 50 is made of a transparent conductive material, which has high light transmittance, further improving the efficiency of the light-emitting device. Furthermore, the bonding layer 50 does not contain metals such as gold, eliminating metal contamination issues. It is compatible with standard production line processes, offering simple processing and enabling low-cost mass production.

[0234] In some embodiments, the sum of the thicknesses L4 of the bonding layer 50 and the reflective layer 34 ranges from 100 nm to 2000 nm. For example, the sum of the thicknesses L4 ranges from 150 nm, 200 nm, 250 nm, 300 nm, 350 nm, 400 nm, 450 nm, 500 nm, 550 nm, 600 nm, 650 nm, 700 nm, 750 nm, 800 nm, 850 nm, 900 nm, 950 nm, 1000 nm, 1100 nm, 1200 nm, 1300 nm, 1400 nm, 1500 nm, 1600 nm, 1700 nm, 1800 nm, or 1900 nm.

[0235] Based on the characteristics of the bonding layer 50 provided in the present application, the thickness of the bonding layer 50 can be less than 2000 nm, making the subsequent etching process easy to perform.

[0236] In some embodiments, as shown in FIG24B , the display module 1 further includes a plurality of device pads located on a side of the planar layer 46 away from the substrate 31. One side of the device pads is connected to the drive circuit layer 32 via the second conductive pillars 47, the patterned bonding area 51, and the first conductive pillars 35. The other side of some of the device pads is connected to the second electrode 48 for transmitting signals from the drive circuit layer 32 to the second electrode 48. The other side of some of the device pads is used to connect to components such as a circuit board to receive external signals and transmit them to the drive circuit layer 32.

[0237] In some embodiments, the light emitting devices 60 in the display module 1 are configured to emit light of the same color.

[0238] The structures of the first dielectric layer 341 and the second dielectric layer 342 included in the reflective layer 34 in the display module 1 are matched and adjusted according to the luminous color of the light-emitting device 60. Therefore, the structure of the reflective layer 34 in the display module 1 for emitting red light, the structure of the reflective layer 34 in the display module 1 for emitting blue light, and the structure of the reflective layer 34 in the display module 1 for emitting green light can be different, so that the reflectivity of the reflective layer 34 in each display module 1 for the light emitted by the light-emitting device 60 included in the display module 1 can reach more than 90%.

[0239] The above is only a specific embodiment of the present application, but the scope of protection of this application is not limited to this. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A driving backplane, characterized in that: include: substrate; A driving circuit layer, arranged on one side of the substrate; A reflective layer is arranged on a side of the driving circuit away from the substrate; the reflective layer comprises a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; The first bonding layer is arranged on a side of the reflective layer away from the substrate; the first bonding layer is connected to the driving circuit layer through a conductive column.

2. The driving backplane according to claim 1, characterized in that: The material of the first bonding layer includes a transparent conductive material.

3. The driving backplane according to claim 1 or 2, characterized in that: There are a plurality of the first dielectric layers and a plurality of the second dielectric layers, and the plurality of the first dielectric layers and the plurality of the second dielectric layers are arranged alternately.

4. The driving backplane according to any one of claims 1 to 3, characterized in that: The first bonding layer covers the reflective layer.

5. The driving backplane according to claim 1, characterized in that: The first bonding layer includes a first patterned bonding region and a first dielectric region; The first patterned bonding area is disposed in the first dielectric area and penetrates the first dielectric area along a thickness direction of the first dielectric area; The driving circuit layer includes a back-end metal interconnect pad, and the first patterned bonding area is connected to the back-end metal interconnect pad through the conductive column.

6. The driving backplane according to any one of claims 1 to 5, characterized in that: The materials of the first dielectric layer, the second dielectric layer and the first dielectric region include silicon oxide, titanium dioxide, tantalum pentoxide or niobium pentoxide.

7. The driving backplane according to claim 5, characterized in that: The material of the first patterned bonding region includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide.

8. An epitaxial wafer, characterized in that: include: substrate; An epitaxial stack is arranged on one side of the substrate; A second bonding layer is arranged on a side of the epitaxial stack away from the substrate; The material of the second bonding layer includes a transparent conductive material.

9. The epitaxial wafer according to claim 8, characterized in that: The second bonding layer covers the epitaxial stack.

10. The epitaxial wafer according to claim 8, characterized in that: The second bonding layer includes a second patterned bonding area and a second dielectric area; the second patterned bonding area is arranged in the second dielectric area and penetrates the second dielectric area along a thickness direction of the second dielectric area.

11. The epitaxial wafer according to claim 10, characterized in that: The epitaxial stack includes a second semiconductor layer, an active layer and a first semiconductor layer which are sequentially stacked on one side of the substrate; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

12. The epitaxial wafer according to any one of claims 8 to 11, characterized in that: The epitaxial wafer further includes a first electrode layer, and the first electrode layer is arranged between the second bonding layer and the epitaxial stack.

13. The epitaxial wafer according to claim 10, characterized in that: The material of the second patterned bonding area includes indium tin oxide, zinc aluminum oxide or transparent conductive oxide; the material of the second dielectric area includes silicon oxide, silicon nitride, titanium dioxide, tantalum pentoxide or niobium pentoxide.

14. A display module, characterized in that: include: substrate; A driving circuit layer, a reflective layer, a bonding layer and a plurality of light-emitting devices are sequentially arranged on one side of the substrate; The reflective layer includes a first dielectric layer and a second dielectric layer which are stacked, and the first dielectric layer and the second dielectric layer have different refractive indices; the bonding layer is connected to the light emitting device and is connected to the driving circuit layer through a conductive column.

15. The display module according to claim 14, characterized in that: The material of the bonding layer includes a transparent conductive material.

16. The display module according to claim 14 or 15, characterized in that: The bonding layer includes a plurality of patterned bonding areas and a dielectric area; the plurality of patterned bonding areas are arranged in the dielectric area and penetrate the dielectric area along the thickness direction of the dielectric area; the light emitting device is arranged corresponding to some of the patterned bonding areas among the plurality of patterned bonding areas.

17. The display module according to any one of claims 14 to 16, characterized in that: The sum of the thickness of the bonding layer and the reflective layer ranges from 100 nm to 2000 nm.

18. The display module according to any one of claims 14 to 17, characterized in that: The light emitting device comprises a first semiconductor layer, an active layer, a second semiconductor layer and a second electrode which are sequentially arranged in a direction away from the bonding layer; one of the first semiconductor layer and the second semiconductor layer is an N-type semiconductor layer, and the other is a P-type semiconductor layer.

19. An electronic device, characterized in that: It comprises a display module and a processor, wherein the processor is used to control the display module to display an image; the display module comprises the display module described in any one of claims 14-18.

20. A method for preparing a driving backplane, characterized in that: include: forming a driving circuit layer on the substrate; A reflective layer is formed on a side of the driving circuit layer away from the substrate; the reflective layer comprises a first dielectric layer and a second dielectric layer stacked in layers, and the first dielectric layer and the second dielectric layer have different refractive indices; A first bonding layer is formed on a side of the reflective layer away from the substrate; the first bonding layer is connected to the driving circuit layer through a conductive column.

21. The preparation method according to claim 20, characterized in that: Forming a first bonding layer on a side of the reflective layer away from the substrate, comprising: A first bonding layer covering the reflective layer is deposited on a side of the reflective layer away from the substrate, wherein the material of the first bonding layer includes a transparent conductive material.

22. The preparation method according to claim 20, characterized in that: The first bonding layer includes a first patterned bonding area and a first dielectric area, and the first bonding layer is formed on a side of the reflective layer away from the substrate, including: Depositing a first bonding film covering the reflective layer on a side of the reflective layer away from the substrate, wherein the material of the first bonding film includes a transparent conductive material; Patterning the first bonding film to form a first patterned bonding area; the first patterned bonding area is connected to the driving circuit layer; A first dielectric region is formed on a side of the reflective layer away from the substrate, and the first dielectric region wraps a side surface of the first patterned bonding region.

23. A method for preparing an epitaxial wafer, characterized in that: include: forming an epitaxial stack on a substrate; forming a second bonding layer on a side of the epitaxial stack away from the substrate; The material of the second bonding layer includes a transparent conductive material.

24. The preparation method according to claim 23, characterized in that: Forming a second bonding layer on a side of the epitaxial stack away from the substrate, comprising: A second bonding layer covering the epitaxial stack is deposited on a side of the epitaxial stack away from the substrate.

25. The preparation method according to claim 23, characterized in that: The second bonding layer includes a second patterned bonding area and a second dielectric area, and the second bonding layer is formed on a side of the epitaxial stack away from the substrate, including: forming a second bonding film on a side of the epitaxial stack away from the substrate, wherein the material of the second bonding film is a transparent conductive material; patterning the second bonding film to form a plurality of second patterned bonding regions; A second dielectric region is formed on a side of the epitaxial stack away from the substrate, and the second dielectric region wraps around a side surface of the second patterned bonding region.

26. The preparation method according to any one of claims 23 to 25, characterized in that: Before forming a second bonding layer on a side of the epitaxial stack away from the substrate, the preparation method further comprises: A first electrode layer is formed on a side of the epitaxial stack away from the substrate.

Images