IIR filter device and filtering method thereof

Abstract

Disclosed in the present application are an IIR filter device and a filtering method thereof. The IIR filter device comprises: a head data module, which stores current input data and two pieces of input historical data; a filtering module, which stores output data of each stage via an intermediate data module first position corresponding to each stage of filtering, switches the addresses of the first position and a second position and, via a calculation module, reads the current input data and the two pieces of input historical data from a designated position, reads two pieces of output historical data from an intermediate data module and stores said data in a tail data module, and after filtering, outputs data and triggers the next stage of filtering; and the tail data module, which is used, when any stage of filtering is complete, for storing the output data of said stage of filtering as input data for the next stage of filtering, the designated position of a first stage of filtering being the head data module, and the designated position of the other stages of filtering being the tail data module. The application reduces data read and write times, avoids interruption of the calculation pipeline, reduces the required data storage by half, and reduces the required clock frequency.

Description

IIR filter device and filtering method thereof

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to the Chinese patent application filed with the State Intellectual Property Office of the People's Republic of China on October 30, 2023, with application number 202311425949.1 and invention name "A IIR filter device and filtering method thereof", the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the field of filter technology, and in particular to an IIR filter device and a filtering method thereof. Background Art

[0004] An IIR filter device and filtering method thereof (Infinite Impulse Response Filter) is a digital filter whose output signal is composed of a weighted sum of past input signals and output signals.

[0005] IIRs with too high an order are unstable. Generally speaking, high-order IIRs are converted into a cascade of multiple biquad IIRs, where each biquad IIR is called a section.

[0006] For a biquad IIR filter, each section needs to store and read the current input data, two historical input data points, and two historical output data points. Thus, a traditional implementation of an N-section cascaded biquad IIR filter operating in serial computing mode requires a random access memory (RAM) size of 5*N words. Because intermediate stages need to read and write historical input and output values, the total computation time requires 10*N clock cycles. This requires a clock frequency greater than 10*N times the sampling rate. Given a fixed sampling rate, this higher clock frequency increases cost and power consumption.

[0007] Summary of the Invention

[0008] The purpose of this application is to provide an IIR filter device and a filtering method thereof, which are used to solve the problems that the existing IIR filter requires a large RAM space, a long read and write time, and a relatively high clock frequency.

[0009] In a first aspect, an embodiment of the present application provides an IIR filter device, comprising:

[0010] The header data module receives the current input data, latches it by overwriting the earliest input historical data, and keeps storing the current input data and two input historical data;

[0011] A filtering module, for performing multi-stage filtering calculations, including an intermediate data module and a calculation module, wherein the intermediate data module includes a first position and a second position corresponding to each stage of filtering, uses the first position corresponding to each stage of filtering to store output data of the filtering at that stage, and swaps the addresses of the first position and the second position. When the calculation module determines that the current stage of filtering is triggered, it reads the current input data and two input historical data from a specified position, reads the data at the first position and the second position corresponding to the current stage of filtering from the intermediate data module as two output historical data, stores the two output historical data in the tail data module as two input historical data for the next stage of filtering, obtains the current output data after filtering, and triggers the next stage of filtering;

[0012] a tail data module, configured to store the two output history data read by the calculation module as two input history data, and when any level of filtering is completed, store the output data of the filtering at that level as current input data for the next level of filtering;

[0013] The designated position of the first level filtering is the head data module, and the designated positions of the other levels of filtering are the tail data modules.

[0014] In some possible embodiments, the header data module includes:

[0015] Header data registers, including a first header register, a second header register, and a third header register;

[0016] The header data manager is used to receive current input data, latch the input history data of the first header register to the second header register / third header register where the earliest input history data is located, and latch the current input data to the first header register.

[0017] In some possible embodiments, the header data register further includes a status register;

[0018] The header data manager is used to trigger a change in the status value of the status register after the first level of filtering is completed;

[0019] When the state value is the first state value, the input historical data of the first register is latched into the second register; when the state value is the second state value, the input historical data of the first register is latched into the third register.

[0020] In some possible embodiments, the intermediate data module includes:

[0021] An intermediate data manager stores output data of each level of filtering in a first location and exchanges addresses of the first location and a second location;

[0022] The intermediate data memory includes a first address and a second address corresponding to each level of filtering, and the first address and the second address are used to store corresponding data.

[0023] In some possible embodiments, the calculation module includes:

[0024] A data selector is used to read the current input data and two input historical data from a specified position when triggering the current level of filtering, read the data at the first position and the second position corresponding to the current level of filtering from the intermediate data module as two output historical data, read the coefficients corresponding to the current input data, the two input historical data, and the two output historical data from the coefficient memory, and output them to the multiplier-accumulator;

[0025] A coefficient memory is used to store the coefficients corresponding to the current input data, two input historical data and two output historical data of each level of filtering;

[0026] The multiplier-accumulator is used to perform multiplication and accumulation operations based on the current input data, two input historical data, two output historical data and corresponding coefficients to obtain the current output data.

[0027] In some possible embodiments, the calculation module further includes:

[0028] The output latch is connected to the multiplier-accumulator and is used to latch the current output data.

[0029] In some possible embodiments, the tail data module includes:

[0030] The tail data manager is configured to latch, during the current level filter calculation, the output history data read by the calculation module from the first position corresponding to the current level filter in the intermediate data module into the second tail register, latch the output history data read from the second position corresponding to the current level filter in the intermediate data module into the third tail register, and latch the output data of the current level filter into the first tail register when the current level filter is completed;

[0031] The tail data registers include a first tail register, a second tail register, and a third tail register.

[0032] In some possible embodiments, the device further includes:

[0033] A beat counter is used to start counting when any level of filtering is triggered. Each time the beat count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients. The beat count value is cleared when the current level of filtering is completed.

[0034] The section counter is used to add one to the section count value when any level of filtering is completed. When the section count value reaches the set number of sections, it is determined that all levels of filtering are completed and the section count value is cleared.

[0035] In a second aspect, an embodiment of the present application further provides a filtering method of an IIR filter device, comprising:

[0036] The header data module is used to receive the current input data, and latches the data by overwriting the earliest input history data, thereby keeping the current input data and two input history data;

[0037] Trigger the first level of filtering, read the current input data and two input historical data from the header data module, and read two output historical data from the first position and second position corresponding to the first level of filtering in the intermediate data module for filtering;

[0038] Determine to trigger other level filtering, read current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the level filtering in the intermediate data module for filtering, and store the two output historical data in the tail storage module as two input historical data for the next level filtering;

[0039] When it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level filtering; and the next level filtering is triggered until the filtering is completed.

[0040] In some possible embodiments, the method further includes:

[0041] When any level of filtering is triggered, counting begins. Each time the count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients.

[0042] Determine that the beat count value is cleared when the current level filtering is completed;

[0043] When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

[0044] In some possible embodiments, a parameter group is read in the following order:

[0045] Second input historical data and corresponding coefficients, current input data and corresponding coefficients, first output historical data and corresponding coefficients, first input historical data and corresponding coefficients, second output historical data and corresponding coefficients;

[0046] The first input historical data is earlier than the second input historical data, and the first output historical data is earlier than the second output historical data.

[0047] The IIR filter device provided in the embodiment of the present application introduces a header data module, an intermediate data module, and a tail data module, and uses exchange addresses instead of multiple data reading and writing, so that the calculation results of the intermediate sections are propagated section by section in the register, and the intermediate results are not stored in the RAM, which reduces the time for reading and writing the RAM and avoids interrupting the calculation pipeline. Compared with the traditional serial calculation direct I-type IIR filter, the RAM required for data storage is reduced by half, and the required clock frequency is reduced by more than 40%.

[0048] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments of the present application. Obviously, the drawings introduced below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0050] Figure 1 is a schematic diagram of the grid structure of a direct type IIR filter;

[0051] Figure 2 is a schematic diagram of a multi-stage biquad IIR filter cascade;

[0052] FIG3 is a schematic diagram of the grid structure of a direct type I biquad IIR;

[0053] FIG4 is a schematic structural diagram of an IIR filter device provided in an embodiment of the present application;

[0054] FIG5a is a schematic diagram of the structure of the first-stage filter performing filtering calculation in an embodiment of the present application;

[0055] FIG5 b is a schematic diagram of the structure of filtering calculations performed by other filters in an embodiment of the present application;

[0056] FIG6 is a schematic diagram of the operation of the header data manager in an embodiment of the present application;

[0057] FIG7 is a schematic diagram of an intermediate data memory exchanging addresses and storing data in an embodiment of the present application;

[0058] FIG8 is a schematic diagram of the filtering calculation process of other stage filters in an embodiment of the present application;

[0059] FIG9 is a flowchart showing the overall operation of the beat calculator and the beat counter according to an embodiment of the present application;

[0060] FIG10 is a flow chart of a filtering method of an IIR filter device in an embodiment of the present application;

[0061] FIG11 is a schematic diagram of a filtering calculation process performed by other stage filters in another embodiment of the present application;

[0062] FIG12 is a flowchart showing the overall operation of the beat calculator and the beat counter in another embodiment of the present application. DETAILED DESCRIPTION

[0063] To further illustrate the technical solutions provided by the embodiments of the present application, this is described in detail below in conjunction with the accompanying drawings and specific implementation methods. Although the embodiments of the present application provide the method operation steps as shown in the following embodiments or drawings, more or fewer operation steps may be included in the method based on routine or no creative labor. In steps where there is no necessary causal relationship logically, the execution order of these steps is not limited to the execution order provided by the embodiments of the present application. During the actual processing process or when the control device is executed, the method may be executed in the order of the methods shown in the embodiments or drawings or in parallel.

[0064] The time domain expression of IIR is as follows:

[0065] The direct type IIR filter grid structure is shown in Figure 1.

[0066] IIR filters with too high an order are unstable. Generally speaking, high-order IIR filters are converted into a cascade of multiple biquad IIR filters, as shown in Figure 2.

[0067] Each stage of the biquad IIR filter is called a section, and the grid structure of a section of direct I-type biquad IIR filter is shown in FIG3 .

[0068] For a biquad IIR filter, each section needs to store and read the current input data, two historical input data points, and two historical output data points. Thus, a traditional implementation of an N-section cascaded biquad IIR filter operating in serial computing mode requires a RAM size of 5*N words. Because the intermediate stages need to read and write the input and output historical data of their own stages, the total computation time requires 10*N clock cycles. The required clock frequency must be at least 10*N times the sampling rate. Given a fixed sampling rate, a high clock frequency increases cost and power consumption.

[0069] In view of this, the present application provides an IIR filter device, which, although still a cascaded biquad IIR direct type I, reduces RAM usage and lowers the required clock frequency by optimizing data access methods and adjusting calculation steps.

[0070] Other features and advantages of the present application will be described in the following description, and in part will become apparent from the description, or will be understood by practicing the present application. The purposes and other advantages of the present application can be realized and obtained by the structures particularly pointed out in the written description, claims, and drawings.

[0071] The IIR filter device and filtering method thereof in the embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0072] An embodiment of the present application provides an IIR filter device, as shown in FIG4 , comprising:

[0073] The header data module 10 receives the current input data, latches it in a way that overwrites the earliest input historical data, and keeps storing the current input data and two input historical data;

[0074] That is, the header data module uses three storage locations. Every time a new data is input, if any of the three storage locations are free, the data can be stored in the free location. If all three locations have data, the oldest historical data can be overwritten. The header data module always stores the current input data and the two most recent input historical data.

[0075] The filtering module 20 is used to perform multi-stage filtering calculations. Each filter stage includes an intermediate data module 201 and a calculation module 202. The intermediate data module 201 includes a first position and a second position corresponding to each stage of filtering. The first position corresponding to each stage of filtering is used to store the output data of the filtering stage, and the addresses of the first position and the second position are swapped. When the calculation module determines that the current stage of filtering is triggered, it reads the current input data and two input historical data from the specified position, reads the data at the first position and the second position corresponding to the current stage of filtering from the intermediate data module as two output historical data, stores the two output historical data in the tail data module as two input historical data for the next stage of filtering, obtains the current output data after filtering, and triggers the next stage of filtering. The calculation module 202 is used to implement the function of a multi-stage cascaded filter. The cascaded filter is a direct I-type biquad IIR filter. After completing the first stage of filtering, the newly calculated output data is stored in the first position corresponding to the filtering stage. However, after being stored in the first position, the addresses of the first position and the second position are swapped, and the output data is alternately stored in the two addresses. In this way, when the filtering calculation is triggered, the two addresses store the two most recent output historical data.

[0076] The calculation module 202 triggers the first-stage filtering calculation after a new data input. Then, in a cascaded order, after each stage of filtering calculation is completed, the next stage of filtering calculation is triggered. After the last stage of filtering calculation is completed, new data is input to the first stage of filtering to start the next serial filtering calculation. The calculation module 202 requires the current input data, two input historical data, and two output historical data to perform filtering calculations at each level. In this embodiment of the application, the current input data is identified as x0, the previous input historical data is identified as x1, the previous input historical data is identified as x2, the previous output historical data is identified as y1, and the previous output historical data is identified as y2.

[0077] The tail data module 30 is used to store the two output historical data read by the calculation module as two input historical data, and when any level of filtering is completed, store the output data of the filtering at that level as the current input data of the next level of filtering;

[0078] In the embodiment of the present application, the data that the tail data module always stores are: two input history data and current input data of the lower-level filter. For the specific storage method, please refer to the above description.

[0079] The designated position of the first level filtering is the head data module, and the designated positions of the other levels of filtering are the tail data modules.

[0080] The embodiment of the present application introduces a header data module, an intermediate data module, and a tail data module. The intermediate data module uses an exchange address instead of multiple data reading and writing. The tail data module always stores the current output data and two historical output data of the current calculation, and uses them as the input of the next section of filtering calculation, so that the calculation results of the intermediate section are propagated in the register by section, and the intermediate results are not stored in the RAM, which reduces the time for reading and writing RAM and avoids interrupting the calculation pipeline. Compared with the traditional serial calculation direct I type IIR, the required data RAM is reduced by half and the required clock frequency is reduced by more than 40%.

[0081] The head data module 10 is used to provide x0, x1 and x2 for the first stage of filtering, and the tail data module 30 is used to provide x0, x1 and x2 for the next stage of filtering after the filtering is completed.

[0082] The header data module 10 is used to store and manage the current input data x0 and two input historical data x1 and x2 of the first stage filtering. As shown in FIG5a , the header data module 10 includes:

[0083] The header data manager 101 is configured to receive the current input data x0, latch the input history data of the first header register rx0 into the second header register rx1 / third header register rx2, where the earliest input history data is located, and latch the current input data x0 into the first header register rx0. Thus, when x0 arrives, the data previously latched into rx0 is moved to rx1 or rx2 as x1, overwriting the earliest input history data. The data latched into rx2 or rx1 is then used as x2, and x0, x1, and x2 remain latched.

[0084] The header data register 102 includes a first header register rx0, a second header register rx1 and a third header register rx2.

[0085] In this embodiment, the header data register 102 also includes a status register z1_addr;

[0086] The header data manager 101 is used to trigger the change of the status value of the status register z1_addr after the first level of filtering is completed;

[0087] Among them, when the state value is the first state value, the input historical data of the first register rx0 is latched to the second register rx1, and when the state value is the second state value, the input historical data of the first register rx0 is latched to the third register rx2. The above-mentioned first state value is 0 and the second state value is 1, or the first state value is 1 and the second state value is 0.

[0088] Figure 6 shows the data storage process of the header data management module. When data x0 is input, if z1_addr is 0, the value of rx0 is latched into rx1. If z1_addr is 1, the value of rx0 is latched into rx2, and then x0 is latched into rx0, and the status value of z1_addr is flipped.

[0089] The intermediate data module 201 is used to store and manage intermediate historical data. As shown in FIG5 a and FIG5 b , in the embodiment of the present application, the intermediate data module 201 includes:

[0090] The intermediate data manager 2011 stores the output data of each level of filtering into the first position (y1 position) corresponding to the filtering level, and swaps the addresses of the first position (y1 position) and the second position (y2 position);

[0091] The intermediate data memory 2012 includes first addresses and second addresses corresponding to each level of filtering, and the first addresses and second addresses are used to store corresponding data.

[0092] In the embodiment of the present application, the calculation module implements the function of an IIR filter. The IIR filter is composed of N sections of biquad IIR filters connected in series. Each stage of the biquad IIR filter corresponds to an intermediate data memory in the intermediate data module, where N is the number of cascaded sections of the IIR filter. As shown in Figure 7, the N intermediate data memories are a RAM with a depth of 2*N. After each stage of the biquad IIR filter completes the filtering calculation, the current output data y_next is stored in the y1 position of the intermediate data memory of this section. After the storage is completed, the addresses of the y1 position and the y2 position of this section are swapped.

[0093] The tail data module 30 is used to store and manage the current output data and its two output historical data of each section, and use them as the current input data and its two input historical data of the next section. This allows the historical data to be propagated in each section, saving RAM and RAM read and write clock cycles. As shown in Figures 5a and 5b, the tail data module 30 includes:

[0094] The tail data manager 301 is configured to, during the current level filter calculation, latch the output history data y1 read by the calculation module 202 from the first position corresponding to the current level filter in the intermediate data module 201 into the second tail register ry1, latch the output history data y2 read from the second position corresponding to the current level filter in the intermediate data module 201 into the third tail register ry2, and latch the output data y_next of the current level filter into the first tail register ry0 when the current level filter is completed;

[0095] The tail data register 302 includes a first tail register ry0, a second tail register ry1 and a third tail register ry2.

[0096] When each section of calculation is completed, the output result y_next of this section is stored in register ry0, which is the input data x0 to be used in the next section of calculation.

[0097] During each calculation, the historical data y1 and y2 are read back from the intermediate data memory. While these two data are used for calculation, they are latched into ry1 and ry2 respectively. These two data are x1 and x2 to be used in the next calculation.

[0098] Through the tail data manager 301 and the tail data register 302, the historical data x0, x1, and x2 that originally needed to be stored in each section no longer need to be stored separately, but are instead transmitted sequentially between each section through the tail data register 302, thereby saving RAM and the clock cycles required to read and write RAM.

[0099] The calculation module 202 in the embodiment of the present application is used to perform multi-stage filtering calculations. As shown in FIG5a and FIG5b , the calculation module 202 includes:

[0100] The data selector 2021 is used to read the current input data x0 and two input historical data x1 and x2 from the specified position when triggering the current stage of filtering, read the two output historical data y1 and y2 from the first and second positions corresponding to the current stage of filtering from the intermediate data module, read the coefficients b0, b1, b2, a1, and a2 corresponding to the current input data x0, the two input historical data x1 and x2, and the two output historical data y1 and y2 from the coefficient memory 2022, and output them to the multiplier accumulator 2023;

[0101] FIG5a is a structural diagram corresponding to the first-stage filtering calculation. The data selector 2021 reads x0, x1, and x2 from registers rx0, rx1, and rx2. The intermediate data manager 2011 reads y1 and y2 from the intermediate data memory 2012 and sends them to the data selector 2021.

[0102] FIG5 b is a structural diagram of the filtering calculations at all stages except the first stage. The tail manager 301 reads data from ry0, ry1, and ry2 in the tail data register 302, obtains x0, x1, and x2, and sends them to the data selector 2021. The intermediate data manager 2011 reads y1 and y2 from the intermediate data memory 2012 and sends them to the data selector 2021.

[0103] The coefficient memory 2022 is used to store the coefficients b0, b1, b2, a1, and a2 corresponding to the current input data x0, the two input historical data x1 and x2, and the two output historical data y1 and y2 of each level of filtering;

[0104] The multiplication and accumulation unit 2023 is used to perform multiplication and accumulation operations based on the current input data x0, the two input historical data x1, x2, the two output historical data y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2, respectively, to obtain the current output data. The specific calculation formula is as follows: ACC=ACC+C*D (2)

[0105] Among them, ACC is the accumulated value of the multiplier-accumulator, D is the current input data x0, the two input historical data x1, x2, and the two output historical data y1, y2, C is the coefficient, and the C coefficients corresponding to D are b0, b1, b2, a1, and a2, respectively. The multiplier-accumulator 2023 uses the coefficient sequence (b0, b1, b2, a1, a2) to multiply the corresponding data sequence (x0, x1, x2, y1, y2) based on the original accumulated value for accumulation.

[0106] Optionally, the calculation module 202 further includes: an output latch 2024 connected to the multiplier-accumulator, and configured to latch current output data y_next.

[0107] In this way, when a section of calculation is completed, the tail data manager 301 reads the current output data from the output latch 2024 to y_next, and interacts with the intermediate data management 2011 to read y1 and y2 from the intermediate data storage 2012 to ry1 and ry2.

[0108] As shown in Figure 8, for the calculation module, when the calculation of section M begins, x0, x1, and x2 of this section are read in the above manner, that is, y_next, y1, and y2 of the previous section are stored in ry0, ry1, and ry2, and y1 and y2 of this section are read in the above manner; y1 is latched to ry1, and y2 is latched to ry2; the multiplication and accumulator starts calculation; when the calculation ends, y_next is latched to ry0; and the calculation of section M+1 is triggered. The calculation process is the same as above and will not be repeated here.

[0109] Figure 11 is a schematic diagram of the filtering calculation process of other levels of filters in another embodiment of the present application; compared with the calculation process shown in Figure 8, the accumulator is further initialized at the beginning of the calculation of section M; when the calculation of section M+1 is triggered, the multiplication accumulator is further initialized. The remaining calculation process is the same as the calculation process shown in Figure 8 and will not be repeated here.

[0110] As shown in FIG5a and FIG5b, the IIR filter device further includes:

[0111] The beat counter 50 is used to start counting when filtering. Each time the beat count value increases by one, a parameter group is read. The parameter group includes: current input data x0 and corresponding coefficients, first input historical data x1 and corresponding coefficients, second input historical data x2 and corresponding coefficients, first output historical data y1 and corresponding coefficients, second output historical data y2 and corresponding coefficients. When the current level filtering is completed, the beat count value is cleared. The beat count of the beat counter is set to 5. In this way, the beat count value of the beat counter is counted from 0, 1, 2, 3, and 4 to achieve 5 beat counts. The data selector 2021 can read one data and corresponding coefficient for each beat according to the beat count, completing the data reading of x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, and a2;

[0112] The section counter 40 increments the section count value upon completion of any filtering stage. When the section count value reaches the set number of sections, all filtering stages are considered complete and the section count value is reset to zero. The beat counter increments the section count value as it counts the set number of beats and resets it to zero when it reaches the set number of sections. The set number of sections is N. That is, every five beats, the ACC outputs the current section's result, y_next. When all sections have completed the operation, the output latch latches the result and outputs it as the final result.

[0113] The section counter 40 and the beat counter 50 can be used to control the calculation process. The head data manager, the middle data manager, and the tail data manager read and latch data according to the count values ​​of the beat counter and the section counter. The specific process is shown in Figure 9:

[0114] Input a batch of data;

[0115] Start the section counter and initialize the section counter;

[0116] Start the beat counter and initialize the beat counter;

[0117] Other components work according to the count values ​​of the beat counter and the beat counter;

[0118] The beat count value is increased by 1, and one of the data among x0, x1, x2, y1, y2 and its coefficient is read;

[0119] Determine whether the beat count is greater than or equal to 5 according to the beat count value;

[0120] If the beat count reaches 5, it means that x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2 have been read. Multiplication and accumulation operations are performed using x0, x1, x2, y1, y2 and the corresponding coefficients b0, b1, b2, a1, a2. After the calculation is completed, the section count value is increased by 1. If the beat count does not reach 5, the other components return to work according to the count values ​​of the section counter and the beat count value;

[0121] Determine whether the node count value is greater than or equal to N;

[0122] If the beat count value reaches N, it means that the N-level filtering is completed and the current filtering calculation ends. If the beat count value does not reach N, the beat counter is started, the beat counter is initialized, and the next level of filtering calculation begins.

[0123] As shown in FIG12 , in another embodiment, according to the overall working process of the beat calculator and the section counter, compared with the process shown in FIG9 , when the section counter is started and initialized, the multiplier accumulator is further initialized. The rest of the process is the same and will not be repeated here.

[0124] The present application also provides a filtering method of an IIR filter device, as shown in FIG10 , including:

[0125] Step 101: Receive current input data using the header data module and latch it by overwriting the earliest input history data, so as to keep storing the current input data and two input history data;

[0126] Step 102: trigger the first level of filtering, read the current input data and two input historical data from the header data module, and read two output historical data from the first position and the second position corresponding to the first level of filtering in the intermediate data module for filtering;

[0127] Step 103: Determine whether to trigger other level filtering, read the current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the filter at this level in the intermediate data module for filtering, and store the two input historical data in the tail storage module as two input historical data for the next level filtering;

[0128] Step 104: When it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level of filtering; and the next level of filtering is triggered until the filtering is completed.

[0129] As an optional implementation, counting starts when any level of filtering is triggered, and each time the count value increases by one, a parameter group is read, and the parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients;

[0130] Determine that the beat count value is cleared when the current level filtering is completed;

[0131] When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

[0132] In this embodiment of the application, a parameter group is read in the following order:

[0133] The second input historical data x2 and coefficient b2, the current input data x0 and coefficient b0, the first output historical data y1 and coefficient a1, the first input historical data x1 and coefficient b1, the second output historical data y2 and coefficient a2.

[0134] The specific rules for selecting data by the data selector are shown in Table 1:

[0135] Table 1

[0136] The coefficient memory stores all the IIR coefficients and outputs the coefficients according to the value of the beat counter as shown in Table 2:

[0137] Table 2

[0138] Only by following the data reading arrangements in Tables 1 and 2 can conflicts between data reading and writing and coefficient reading be avoided, and all data reading and writing can be completed within 5 clock cycles, avoiding the idle cycles of the data storage and computing modules during data reading and writing, and reducing the clock speed requirements.

[0139] Although the preferred embodiments of the present application have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present application.

[0140] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. An IIR filter device, characterized in that: include: The head data module receives the current input data, latches it in a way of overwriting the earliest input historical data, and keeps storing the current input data and two input historical data; A filtering module, used for performing multi-stage filtering calculations, including an intermediate data module and a calculation module, wherein the intermediate data module includes a first position and a second position corresponding to each stage of filtering, and uses the first position corresponding to each stage of filtering to store output data of the filtering at the stage, and exchanges the addresses of the first position and the second position, and when the calculation module determines to trigger the current stage of filtering, reads the current input data and two input historical data from the specified position, reads the data of the first position and the second position corresponding to the current stage of filtering from the intermediate data module as two output historical data, stores the two output historical data in the tail data module as two input historical data of the next stage of filtering, obtains the current output data after filtering, and triggers the next stage of filtering; A tail data module, used to store the two output historical data read by the calculation module as two input historical data, and when any level of filtering is completed, store the output data of the filtering at that level as the current input data of the next level of filtering; Among them, the designated position of the first level of filtering is the head data module, and the designated position of other levels of filtering is the tail data module.

2. The device according to claim 1, characterized in that The header data module includes: Header data registers, including a first header register, a second header register and a third header register; The header data manager is used to receive current input data, latch the input history data of the first header register to the second header register / third header register where the earliest input history data is located, and latch the current input data to the first header register.

3. The device according to claim 2, characterized in that The header data register also includes a status register; The header data manager is used to trigger the change of the state value of the state register after the first level of filtering is completed; When the state value is a first state value, the input historical data of the first register is latched into the second register, and when the state value is a second state value, the input historical data of the first register is latched into the third register.

4. The device according to claim 1, characterized in that The intermediate data module includes: An intermediate data manager stores output data of each level of filtering in a first location and exchanges addresses of the first location and a second location; The intermediate data storage device includes a first address and a second address corresponding to each level of filtering, wherein the first address and the second address are used to store corresponding data.

5. The device according to claim 1, characterized in that The calculation module comprises: The data selector is used to read the current input data and two input historical data from the specified position when triggering the current level filtering, read the data of the first position and the second position corresponding to the current level filtering from the intermediate data module as two output historical data, and read the current input data, two input historical data from the coefficient memory. Input historical data and coefficients corresponding to two output historical data, and output to the multiplier-accumulator; A coefficient memory, used to store coefficients corresponding to current input data, two input historical data and two output historical data of each level of filtering; The multiplier-accumulator is used to perform multiplication-accumulation operations according to current input data, two input historical data, two output historical data and corresponding coefficients to obtain current output data.

6. The device according to claim 5, characterized in that The calculation module also includes: The output latch is connected to the multiplier-accumulator and is used to latch the current output data.

7. The device according to claim 1, characterized in that The tail data module includes: The tail data manager is used to latch the output history data read by the calculation module from the first position corresponding to the current level filter in the intermediate data module into the second tail register when the current level filter is calculated, latch the output history data read from the second position corresponding to the current level filter in the intermediate data module into the third tail register, and latch the output data of the current level filter into the first tail register when the current level filter is completed; The tail data registers include a first tail register, a second tail register and a third tail register.

8. The device according to claim 1, characterized in that Also includes: A beat counter is used to start counting when any level of filtering is triggered. Each time the beat count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, second output historical data and corresponding coefficients. When the current level of filtering is completed, the beat count value is cleared; The node counter is used to increase the node count value by one when any level of filtering is completed. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

9. A filtering method of an IIR filter device, characterized in that: include: The head data module is used to receive the current input data, and latches the data in a manner of overwriting the earliest input historical data, so as to keep storing the current input data and two input historical data; Trigger the first level of filtering, read the current input data and two input historical data from the head data module, and read two output historical data from the first position and the second position corresponding to the first level of filtering in the intermediate data module for filtering; Determine to trigger other level filtering, read current input data and two input historical data from the tail data module, read two output historical data from the first position and the second position of the level filtering in the intermediate data module for filtering, and store the two output historical data in the tail storage module as two input historical data for the next level filtering; When it is determined that any level of filtering is completed, the tail data module is used to store the output data of the filtering at that level as the current input data of the next level of filtering; And trigger the next level filtering until the filtering is completed.

10. The method according to claim 9, characterized in that Also includes: When any level of filtering is triggered, counting starts. Each time the count value increases by one, a corresponding parameter group is read. The parameter group includes: current input data and corresponding coefficients, first input historical data and corresponding coefficients, second input historical data and corresponding coefficients, first output historical data and corresponding coefficients, and second output historical data and corresponding coefficients; Determine that the beat count value is cleared when the current level filtering is completed; When any level of filtering is completed, the node count value is increased by one. When the node count value reaches the set number of nodes, it is determined that all levels of filtering are completed and the node count value is cleared.

11. The method according to claim 9, characterized in that Read a parameter group in the following order: The second input historical data and corresponding coefficients, the current input data and corresponding coefficients, the first output historical data and corresponding coefficients, the first input historical data and corresponding coefficients, the second output historical data and corresponding coefficients; The first input historical data is earlier than the second input historical data, and the first output historical data is earlier than the second output historical data.

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