Pixel driving circuit, display panel and driving method

Abstract

A pixel driving circuit (PDC), a display panel (NPL) and a driving method, which relate to the technical field of display. The pixel driving circuit (PDC) comprises a drive transistor (T3), and a switch sub-circuit (SW), which is electrically connected to a control end of the drive transistor (T3), wherein the switch sub-circuit (SW) comprises a control unit (CT) and a switch unit (ST), a second electrode of the switch unit (ST) being electrically connected to the control end of the drive transistor (T3), and a control end of the switch unit (ST) being electrically connected to a control node (Nx); a control end of the control unit (CT) is electrically connected to a control signal end, and a first electrode of the control unit (CT) is electrically connected to a corresponding scanning signal end; the control unit (CT) is configured to load the voltage of the corresponding scanning signal end to the control node (Nx) in response to a turn-on level of the control signal end; the switch unit (ST) is configured to cut off the switch unit (ST) in response to a cut-off level on the control node (Nx); and the drive transistor (T3) is configured to be capable of outputting a driving current under the control of the voltage on the control end of the drive transistor (T3). The effect of reducing the power consumption of a product is achieved.

Description

Pixel driving circuit, display panel and driving method

[0001] Cross-references

[0002] This disclosure claims priority to Chinese patent application number 202311423073.7, filed on October 30, 2023, entitled “Pixel driving circuit, display panel and driving method”, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present disclosure relates to the field of display technology, and in particular to a pixel driving circuit, a display panel, and a driving method. Background Art

[0004] With the continuous development and progress of touch display technology, in order to present an immersive aesthetic experience to the audience, AMOLED (active-drive organic light-emitting diode) display has become the mainstream of the world's display products with its excellent color reproduction and contrast effects. The matching of AMOLED display technology in the mobile phone field is booming.

[0005] Due to the superior physical properties of AMOLED and its diverse display refresh rates, multi-frequency display products continue to develop. Furthermore, considering product power consumption, display technology continues to evolve. However, in actual use, OLED products currently experience high screen power consumption, MIP (Mobile Industry Processor Interface) transmission power consumption, and terminal GPU (Graphics Processor) power consumption for image rendering. There is an urgent need to reduce power consumption in these areas to increase standby time.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field.

[0007] Summary of the Invention

[0008] The purpose of the present disclosure is to overcome the above-mentioned deficiencies of the prior art and provide a pixel driving circuit, a display panel and a driving method to reduce product power consumption.

[0009] According to one aspect of the present disclosure, there is provided a pixel driving circuit for driving a display panel, the pixel driving circuit comprising a driving transistor and a switch subcircuit electrically connected to a control terminal of the driving transistor;

[0010] The switch subcircuit includes a control unit and a switch unit;

[0011] The second electrode of the switch unit is electrically connected to the control terminal of the driving transistor, and the control terminal of the switch unit is electrically connected to the control node;

[0012] The control terminal of the control unit is electrically connected to the control signal terminal, and the first terminal of the control unit is electrically connected to the corresponding scan signal terminal;

[0013] The control unit is configured to, in response to the on-level of the control signal terminal, load the corresponding voltage of the scan signal terminal to the control node;

[0014] The switch unit is configured to turn off the switch unit in response to a cut-off level on the control node;

[0015] The driving transistor is configured to output a driving current under the control of a voltage on a control terminal of the driving transistor.

[0016] According to an embodiment of the present disclosure, the switch subcircuit includes a reset switch subcircuit for resetting the control terminal of the drive transistor;

[0017] The reset switch subcircuit includes a reset switch unit and a reset control unit;

[0018] The second electrode of the reset switch unit is electrically connected to the control terminal of the driving transistor, the control terminal of the reset switch unit is electrically connected to the first control node, and the reset switch unit is configured to turn off the reset switch unit in response to the cut-off level on the first control node;

[0019] The first electrode of the reset control unit is electrically connected to the reset scan signal end, the control end of the reset control unit is electrically connected to the first control signal end, and the reset control unit is configured to respond to the conduction level of the first control signal end so that the voltage of the reset scan signal end is loaded to the first control node.

[0020] According to one embodiment of the present disclosure, the reset switch unit includes a first transistor, wherein a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor, and a first node are electrically connected to each other, and the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to be turned off in response to a cut-off level on the first control node;

[0021] The reset control unit includes a ninth transistor; the first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, the second electrode of the ninth transistor, the control terminal of the first transistor and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to respond to the conduction level of the first control signal terminal so that the voltage of the reset scan signal terminal is loaded to the first control node.

[0022] According to one embodiment of the present disclosure, the switch subcircuit includes a threshold compensation switch subcircuit;

[0023] The threshold compensation switch subcircuit includes a compensation switch unit and a compensation control unit;

[0024] The first electrode of the compensation switch unit is electrically connected to the second electrode of the driving transistor, the control terminal of the compensation switch unit is electrically connected to the second control node, and the compensation switch unit is configured to turn off the compensation switch unit in response to a cut-off level on the second control node;

[0025] The first electrode of the compensation control unit is electrically connected to the compensation scanning signal end, the control end of the compensation control unit is electrically connected to the second control signal end, and the compensation control unit is configured to respond to the conduction level of the second control signal end so that the voltage of the compensation scanning signal end is loaded to the second control node.

[0026] According to one embodiment of the present disclosure, the compensation switch unit includes a second transistor, wherein a first electrode of the second transistor, a second electrode of the driving transistor, and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor, and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to be turned off in response to a cut-off level on the second control node;

[0027] The compensation control unit includes a tenth transistor; the first electrode of the tenth transistor is electrically connected to the compensation scan signal terminal, the second electrode of the tenth transistor, the control terminal of the second transistor and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to respond to the conduction level of the second control signal terminal so that the voltage of the compensation scan signal terminal is loaded to the second control node.

[0028] According to an embodiment of the present disclosure, the switch subcircuit includes a reset switch subcircuit and a threshold compensation switch subcircuit;

[0029] The reset switch subcircuit includes a reset switch unit and a reset control unit;

[0030] The reset switch unit includes a first transistor, wherein a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor, and a first node are electrically connected to each other, and the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to be turned off in response to a cut-off level on the first control node;

[0031] The reset control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to, in response to a conduction level of the first control signal terminal, cause a voltage of the reset scan signal terminal to be applied to the first control node;

[0032] The threshold compensation switch subcircuit includes a compensation switch unit and a compensation control unit;

[0033] The compensation switch unit includes a second transistor, wherein a first electrode of the second transistor, a second electrode of the driving transistor, and a third node are electrically connected to each other, a second electrode of the second transistor, a control terminal of the driving transistor, a second electrode of the first transistor, and the first node are electrically connected to each other, and the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to be turned off in response to a cut-off level on the second control node;

[0034] The compensation control unit includes a tenth transistor; the first electrode of the tenth transistor is electrically connected to the compensation scan signal terminal, the second electrode of the tenth transistor, the control terminal of the second transistor and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to respond to the conduction level of the second control signal terminal so that the voltage of the compensation scan signal terminal is loaded to the second control node.

[0035] According to one embodiment of the present disclosure, the pixel driving circuit further includes:

[0036] a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the data signal terminal, and a control terminal of the fourth transistor is electrically connected to the data scan signal terminal;

[0037] a fifth transistor, wherein a second electrode of the fifth transistor, a second electrode of the fourth transistor, a first electrode of the driving transistor, and the second node are electrically connected to each other, and a control terminal of the fifth transistor is electrically connected to a light emitting control signal terminal;

[0038] a sixth transistor, wherein a first electrode of the sixth transistor, a second electrode of the driving transistor, and a third node are electrically connected to each other, and a control terminal of the sixth transistor is electrically connected to the light emitting control signal terminal;

[0039] a seventh transistor, wherein a first electrode of the seventh transistor is electrically connected to the second initialization signal terminal, a second electrode of the seventh transistor, the second electrode of the sixth transistor, the pixel electrode, and the fourth node are electrically connected to each other, and a control terminal of the seventh transistor is electrically connected to the reset signal terminal;

[0040] a storage capacitor, wherein a first electrode plate of the storage capacitor, a first electrode of the fifth transistor, and a first driving power supply voltage terminal are electrically connected to each other, and a second electrode plate of the storage capacitor, a control terminal of the driving transistor, and a first node are electrically connected to each other;

[0041] The fourth transistor is configured to, in response to the conduction level of the data scanning signal terminal, load the data voltage of the data signal terminal to the second node;

[0042] The fifth transistor is configured to, in response to the on-level of the light emitting control signal terminal, load the voltage of the first driving power supply voltage terminal to the second node;

[0043] The sixth transistor is configured to, in response to the on-level of the light emitting control signal terminal, load the voltage of the third node to the fourth node;

[0044] The seventh transistor is configured to load the voltage of the second initialization signal terminal to the fourth node in response to the on-level of the reset signal terminal.

[0045] According to an embodiment of the present disclosure, the pixel driving circuit further includes an eighth transistor;

[0046] The first electrode of the eighth transistor is electrically connected to the third initialization signal terminal;

[0047] The second electrode of the eighth transistor, the second electrode of the fifth transistor, the second electrode of the fourth transistor, the first electrode of the driving transistor, and the second node are electrically connected to each other;

[0048] The control terminal of the eighth transistor is electrically connected to the reset signal terminal;

[0049] The eighth transistor is configured to load the voltage of the third initialization signal terminal to the second node in response to the on-level of the reset signal terminal.

[0050] According to a second aspect of the present disclosure, a display panel is provided, comprising the above-mentioned pixel driving circuit arranged in an array, the display panel comprising switch sub-circuit traces corresponding one-to-one to each pixel driving circuit column, and the control end of the control unit of the pixel driving circuit column is electrically connected to the switch sub-circuit trace.

[0051] According to one embodiment of the present disclosure, the switching unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor, and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to be turned off in response to a cut-off level on the first control node;

[0052] The control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to, in response to a conduction level of the first control signal terminal, cause a voltage of the reset scan signal terminal to be applied to the first control node;

[0053] The control end of the ninth transistor of the pixel driving circuit column is electrically connected to the first control signal wiring.

[0054] According to one embodiment of the present disclosure, the switching unit includes a second transistor, wherein a first electrode of the second transistor, a second electrode of the driving transistor, and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor, and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to be turned off in response to a cut-off level on the second control node;

[0055] The control unit includes a tenth transistor; a first electrode of the tenth transistor is electrically connected to the compensation scan signal terminal, a second electrode of the tenth transistor, a control terminal of the second transistor, and the second control node are electrically connected to each other, and the control terminal of the tenth transistor is electrically connected to the second control signal terminal. The tenth transistor is configured to, in response to a conduction level of the second control signal terminal, load a voltage of the compensation scan signal terminal to the second control node;

[0056] The control terminal of the tenth transistor of the pixel driving circuit column is electrically connected to the second control signal wiring.

[0057] According to a third aspect of the present disclosure, a method for driving a display panel is provided, which is applied to the above-mentioned display panel. The method for driving a display panel includes:

[0058] Drive each sub-pixel row by row;

[0059] When driving any row of sub-pixels, determine whether each sub-pixel needs to be refreshed; when a sub-pixel does not need to be refreshed, when the scanning signal end corresponding to the switch sub-circuit of the pixel driving circuit corresponding to the sub-pixel is loaded with a conduction level, the switch sub-circuit wiring electrically connected to the pixel driving circuit corresponding to the sub-pixel is loaded with a cutoff level of the control signal end.

[0060] According to one embodiment of the present disclosure, the switching unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor, and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to be turned off in response to a cut-off level on the first control node;

[0061] The control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to, in response to a conduction level of the first control signal terminal, cause a voltage of the reset scan signal terminal to be applied to the first control node;

[0062] The control terminal of the ninth transistor of the pixel driving circuit column is electrically connected to the first control signal wiring;

[0063] Applying the cutoff level of the first control signal end to the switch sub-circuit wiring electrically connected to the pixel driving circuit corresponding to the sub-pixel includes:

[0064] The cutoff level of the first control signal end is applied to the first control signal wiring.

[0065] According to one embodiment of the present disclosure, the switching unit includes a second transistor, wherein a first electrode of the second transistor, a second electrode of the driving transistor, and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor, and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to be turned off in response to a cut-off level on the second control node;

[0066] The control unit includes a tenth transistor; a first electrode of the tenth transistor is electrically connected to the compensation scan signal terminal, a second electrode of the tenth transistor, a control terminal of the second transistor, and the second control node are electrically connected to each other, and the control terminal of the tenth transistor is electrically connected to the second control signal terminal. The tenth transistor is configured to, in response to a conduction level of the second control signal terminal, load a voltage of the compensation scan signal terminal to the second control node;

[0067] The control terminal of the tenth transistor of the pixel driving circuit column is electrically connected to the second control signal wiring;

[0068] Applying a cutoff level of a second control signal end to a switch sub-circuit trace electrically connected to the pixel driving circuit corresponding to the sub-pixel includes:

[0069] The cutoff level of the second control signal end is applied to the second control signal wiring.

[0070] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0071] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0072] FIG1 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0073] FIG2 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0074] FIG3 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0075] FIG4 is a schematic diagram of a pixel driving circuit in one embodiment of the present disclosure.

[0076] FIG. 5 is a timing diagram illustrating the operation of the pixel driving circuit in FIG. 4 during refreshing in one embodiment of the present disclosure.

[0077] 6-1 to 6-5 are equivalent circuit diagrams of the pixel driving circuit in FIG. 5 at different stages when refreshing, in one embodiment of the present disclosure.

[0078] FIG. 7 is an operation timing diagram of the pixel driving circuit in FIG. 4 when not refreshing (ie, maintaining) in one embodiment of the present disclosure.

[0079] 8-1 to 8-5 are equivalent circuit diagrams of the pixel driving circuit in FIG. 7 at different stages when the pixel driving circuit is not refreshed (ie, maintained) in one embodiment of the present disclosure.

[0080] FIG9 is a schematic diagram of a display panel in one embodiment of the present disclosure.

[0081] FIG10 is a signal diagram of a data signal, a first control signal, and a second control signal of a certain pixel driving circuit column.

[0082] Description of reference numerals:

[0083] PNL, display panel; AA, display area; BB, peripheral area; DIC, driver chip; DH, row direction; DL, data line; DV, column direction; GL, scan line; GS, strobe signal;

[0084] GOAS, gate drive circuit group; GOA, gate drive circuit; GOA1, first gate drive circuit; GOA2, second gate drive circuit; GOA3, third gate drive circuit; GOA4, fourth gate drive circuit; GOA5, fifth gate drive circuit; SR, shift register;

[0085] UU, display unit; PIX, sub-pixel;

[0086] PDC, pixel driving circuit; SW, switch subcircuit; SW1, reset switch subcircuit; SW2, threshold compensation switch subcircuit; CT, control unit; CT1, reset control unit; CT2, compensation control unit; ST, switch unit; ST1, reset switch unit; ST2, compensation switch unit; T1, first transistor; T2, second transistor; T3, driving transistor; T4, fourth transistor; T5, fifth transistor; T6, sixth transistor; T7, seventh transistor; T8, eighth transistor; T9, ninth transistor; T10, tenth transistor; CST, storage capacitor; N1, first node; N2, second node; N3, first transistor; Three nodes; N4, the fourth node; Nx, the control node; Nx1, the first control node; Nx2, the second control node; V1, the first driving power supply voltage; V2, the second driving power supply voltage; EM, the light-emitting control signal; RSTG, the reset scan signal; CG, the compensation scan signal; RST, the reset signal; DG, the data scan signal; Data, the data signal; CP, the control signal; CP1, the first control signal; CP2, the second control signal; Vint1, the first initialization signal; Vint2, the second initialization signal; Vint3, the third initialization signal; CP1L, the first control signal routing; CP2L, the second control signal routing;

[0087] VPDC, pixel driving circuit column. DETAILED DESCRIPTION

[0088] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0089] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0090] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first", "second" and "third" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0091] In the embodiment of the present disclosure, a transistor refers to an element comprising at least three terminals: a gate, a source, and a drain. The transistor has a channel region between the drain (drain electrode terminal, drain region, or drain electrode) and the source (source electrode terminal, source region, or source electrode), and current can flow through the source, the channel region, and the drain. The channel region refers to the region through which current mainly flows. In the embodiment of the present disclosure, in the case of using transistors with opposite polarities or in the case of a change in the direction of current during circuit operation, the functions of the "source" and the "drain" are sometimes interchanged, that is, the "source" and the "drain" can be interchanged. In the embodiment of the present disclosure, for any transistor, one of the "source" and the "drain" is referred to as the first pole of the transistor, and the other is referred to as the second pole of the transistor, and the gate is referred to as the control terminal of the transistor. In an embodiment of the present disclosure, at least part of the signal has a high level and a low level; one of the high level and the low level can be used as the on-level of the signal, and the on-level of the signal can turn on the controlled transistor; the other of the high level and the low level can be used as the off-level of the signal, and the off-level of the signal can turn off the controlled transistor. For example, for a signal that controls a P-type transistor (the signal can be loaded to the control terminal of the P-type transistor), its on-level is a low level, and its off-level is a high level. For another example, for a signal that controls an N-type transistor (the signal can be loaded to the control terminal of the N-type transistor), its on-level is a high level, and its off-level is a low level.

[0092] An embodiment of the present disclosure provides a display panel PNL, as shown in FIG1 , comprising display units UU arranged in an array. The display units UU include sub-pixels PIX and pixel drive circuits PDC that drive the sub-pixels PIX. The display panel PNL is provided with a plurality of scan lines GL arranged along the row direction DH in the display area AA, each scan line GL being arranged in a one-to-one correspondence with each row of display units UU; the scan lines GL are connected to the pixel drive circuits PDC of the corresponding rows of display units UU. The display panel PNL is provided with a plurality of data lines DL arranged along the column direction DV in the display area AA, each data line DL being arranged in a one-to-one correspondence with each column of display units UU; the data lines DL are connected to the pixel drive circuits PDC of the corresponding columns of display units UU. Thus, the pixel drive circuit PDC of each display unit UU is connected to one scan line GL and one data line DL. When a selection signal is applied to the scan line GL, the data voltage applied to the data line DL can be applied to the pixel drive circuit PDC.

[0093] In one embodiment of the present disclosure, the sub-pixel PIX may be a current-driven light-emitting element such as an OLED, a QLED, a Micro LED, or a MiNi LED. In one example, the sub-pixel PIX is an OLED. In another example, the sub-pixel PIX is a QLED.

[0094] In an embodiment of the present disclosure, referring to FIG. 2 , a gate drive circuit GOA may be provided in the peripheral area BB of the display panel PNL. The gate drive circuit GOA may include a plurality of shift registers SR connected in cascade. The scan lines GL are connected to at least some of the shift registers SR in a one-to-one correspondence, so that the strobe signals generated by the shift registers SR are applied to the corresponding scan lines GL.

[0095] In one embodiment of the present disclosure, as shown in Figure 3, the pixel driving circuit PDC includes a driving transistor T3 and a switching sub-circuit SW electrically connected to the control end of the driving transistor T3; the switching sub-circuit SW includes a control unit CT and a switching unit ST; the second electrode of the switching unit ST is electrically connected to the control end of the driving transistor T3, and the control end of the switching unit ST is electrically connected to the control node Nx; the control end of the control unit CT is electrically connected to the control signal end, and the first electrode of the control unit CT is electrically connected to the corresponding scan signal end; the control unit CT is configured to respond to the on-level of the control signal end so that the voltage of the corresponding scan signal end is loaded to the control node Nx; the switch unit ST is configured to respond to the off-level on the control node Nx so that the switch unit ST is turned off; the driving transistor T3 is configured to be able to output a driving current under the control of the voltage on the control end of the driving transistor T3.

[0096] When the sub-pixel PIX does not need to be refreshed, the control terminal of the control unit CT of the switch sub-circuit SW of the pixel driving circuit PDC is applied with the cut-off level of the control signal terminal to turn off the control unit CT. At this time, the conduction level of the scanning signal of the corresponding scanning signal terminal electrically connected to the first electrode of the control unit CT cannot be transmitted to the control node Nx through the control unit CT, so that the switch unit ST cannot be turned on, so that the driving transistor T3 cannot generate the driving current, and the sub-pixel PIX cannot be refreshed (that is, the state of the previous frame is maintained); when the sub-pixel PIX needs to be refreshed, the pixel driving circuit PDC is turned on. The control terminal of the control unit CT of the switching sub-circuit SW applies the conduction level of the control signal terminal to turn on the control unit CT, and at the same time, the conduction level of the switch unit ST is applied through the corresponding scan signal terminal, so that the conduction level of the corresponding scan signal is transmitted to the control node Nx through the control unit CT, thereby turning on the switch unit ST, and the driving transistor T3 generates a driving current, so that the sub-pixel PIX is refreshed; compared with the traditional pixel driving circuit PDC, the pixel driving circuit PDC can refresh and maintain the sub-pixel PIX, which provides the possibility of refreshing and maintaining any area of ​​the display panel.

[0097] For example, when a certain area of ​​the display panel needs to be partially refreshed, the corresponding sub-pixel PIX is refreshed through the above-mentioned pixel circuit, and the remaining areas of the display panel are not refreshed, thereby reducing the power consumption of the product and increasing the standby time and service life of the product.

[0098] For another example, when the entire screen of the display panel needs to be refreshed, all corresponding sub-pixels PIX are refreshed through the pixel driving circuit PDC, thereby achieving the refresh of the entire display panel to retain the full-screen refresh function of the existing pixel driving circuit PDC.

[0099] In one embodiment of the present disclosure, as shown in Figure 4, the switch sub-circuit SW includes a reset switch sub-circuit SW1 for resetting the control end of the driving transistor T3; the reset switch sub-circuit SW1 includes a reset switch unit ST1 and a reset control unit CT1; the second electrode of the reset switch unit ST1 is electrically connected to the control end of the driving transistor T3, the control end of the reset switch unit ST1 is electrically connected to the first control node Nx1, and the reset switch unit ST1 is configured to cut off the reset switch unit ST1 in response to the cut-off level on the first control node Nx1; the first electrode of the reset control unit CT1 is electrically connected to the reset scan signal end, the control end of the reset control unit CT1 is electrically connected to the first control signal end, and the reset control unit CT1 is configured to load the voltage of the reset scan signal end to the first control node Nx1 in response to the on-level of the first control signal end.

[0100] By loading the on-level of the first control signal CP1 on the control end of the reset control unit CT1, the reset control unit CT1 is turned on, so that the on-level of the reset scan signal RSTG is transmitted to the first control node Nx1 through the reset control unit CT1, so that the reset switch unit ST1 is turned on, which helps to reset the control end of the driving transistor T3; by loading the off-level of the first control signal CP1 on the control end of the reset control unit CT1, the reset control unit CT1 is turned off, so that the on-level of the reset scan signal RSTG cannot be transmitted to the first control node Nx1 through the reset control unit CT1, so that the reset switch unit ST1 is turned off, which helps to not reset the control end of the driving transistor T3.

[0101] In one embodiment of the present disclosure, as shown in FIG4 , the reset switch unit ST1 includes a first transistor T1, wherein a first electrode of the first transistor T1 is electrically connected to a first initialization signal terminal, a second electrode of the first transistor T1, a control terminal of the driving transistor T3, and a first node N1 are electrically connected to each other, and the control terminal of the first transistor T1 is electrically connected to a first control node Nx1. The first transistor T1 is configured to turn off the first transistor T1 in response to a cutoff voltage at the first control node Nx1. In other embodiments of the present disclosure, the reset switch unit ST1 may further include multiple first transistors T1 connected in series or in parallel.

[0102] In one embodiment of the present disclosure, as shown in FIG4 , the reset control unit CT1 includes a ninth transistor T9; a first electrode of the ninth transistor T9 is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor T9, the control terminal of the first transistor T1, and the first control node Nx1 are electrically connected to each other, and the control terminal of the ninth transistor T9 is electrically connected to the first control signal terminal. The ninth transistor T9 is configured to, in response to a conduction level at the first control signal terminal, apply a voltage at the reset scan signal terminal to the first control node Nx1. In other embodiments of the present disclosure, the reset control unit CT1 may further include a plurality of ninth transistors T9 connected in series or in parallel.

[0103] By loading the on-level of the first control signal CP1 on the control terminal of the ninth transistor T9, the ninth transistor T9 is turned on, so that the on-level of the reset scan signal RSTG is transmitted to the first control node Nx1 through the ninth transistor T9, so that the first transistor T1 is turned on, and the first initialization signal Vint1 is transmitted to the control terminal of the driving transistor T3 through the first transistor T1, so as to reset the control terminal of the driving transistor T3; by loading the off-level of the first control signal CP1 on the control terminal of the ninth transistor T9, the ninth transistor T9 is turned off, so that the on-level of the reset scan signal RSTG cannot be transmitted to the first control node Nx1 through the ninth transistor T9, so that the first transistor T1 is turned off, and the first initialization signal Vint1 cannot be transmitted to the control terminal of the driving transistor T3 through the first transistor T1, so as to not reset the control terminal of the driving transistor T3.

[0104] In some embodiments of the present disclosure, as shown in Figure 4, the switch sub-circuit SW includes a threshold compensation switch sub-circuit SW2; the threshold compensation switch sub-circuit SW2 includes a compensation switch unit ST2 and a compensation control unit CT2; the first electrode of the compensation switch unit ST2 is electrically connected to the second electrode of the driving transistor T3, the control end of the compensation switch unit ST2 is electrically connected to the second control node Nx2, and the compensation switch unit ST2 is configured to respond to the cut-off level on the second control node Nx2 to turn off the compensation switch unit ST2; the first electrode of the compensation control unit CT2 is electrically connected to the compensation scan signal end, the control end of the compensation control unit CT2 is electrically connected to the second control signal end, and the compensation control unit CT2 is configured to respond to the on-level of the second control signal end to load the voltage of the compensation scan signal end to the second control node Nx2.

[0105] By loading the on-level of the second control signal CP2 on the control end of the compensation control unit CT2, the compensation control unit CT2 is turned on, so that the on-level of the compensation scanning signal CG is transmitted to the second control node Nx2 through the compensation control unit CT2, so that the compensation switch unit ST2 is turned on, which helps to compensate for the threshold voltage of the driving transistor T3.

[0106] In one embodiment of the present disclosure, as shown in Figure 4, the compensation switch unit ST2 includes a second transistor T2, the first electrode of the second transistor T2, the second electrode of the driving transistor T3, and the third node N3 are electrically connected to each other, the second electrode of the second transistor T2, the control end of the driving transistor T3 and the first node N1 are electrically connected to each other, the control end of the second transistor T2 is electrically connected to the second control node Nx2, and the second transistor T2 is configured to turn off the second transistor T2 in response to the cut-off level on the second control node Nx2; in other embodiments of the present disclosure, the compensation switch unit ST2 may further include a plurality of second transistors T2 connected in series or in parallel.

[0107] In one embodiment of the present disclosure, as shown in FIG4 , the compensation control unit CT2 includes a tenth transistor T10; a first electrode of the tenth transistor T10 is electrically connected to the compensation scan signal terminal, a second electrode of the tenth transistor T10, a control terminal of the second transistor T2, and a second control node Nx2 are electrically connected to each other, and the control terminal of the tenth transistor T10 is electrically connected to the second control signal terminal. The tenth transistor T10 is configured to, in response to a conduction level at the second control signal terminal, apply a voltage at the compensation scan signal terminal to the second control node Nx2. In other embodiments of the present disclosure, the compensation control unit CT2 may further include a plurality of tenth transistors T10 connected in series or in parallel.

[0108] By loading the on-level of the second control signal CP2 on the control terminal of the tenth transistor T10, the tenth transistor T10 is turned on, so that the on-level of the compensation scan signal CG is transmitted to the second control node Nx2 through the tenth transistor T10, so that the second transistor T2 is turned on, and the threshold voltage of the driving transistor T3 is transmitted to the first node N1 through the second transistor T2, so as to compensate for the threshold voltage of the driving transistor T3.

[0109] In some embodiments of the present disclosure, as shown in FIG4 , the switch sub-circuit SW includes a reset switch sub-circuit SW1 and a threshold compensation switch sub-circuit SW2; the reset switch sub-circuit SW1 includes a reset switch unit ST1 and a reset control unit CT1; the reset switch unit ST1 includes a first transistor T1, wherein a first electrode of the first transistor T1 is electrically connected to the first initialization signal terminal, a second electrode of the first transistor T1, a control terminal of the driving transistor T3, and a first node N1 are electrically connected to each other, and the control terminal of the first transistor T1 is electrically connected to the first control node Nx1; the first transistor T1 is configured to turn off the first transistor T1 in response to a cut-off level on the first control node Nx1; the reset control unit CT1 includes a ninth transistor T9; a first electrode of the ninth transistor T9 is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor T9, the control terminal of the first transistor T1, and the first control node Nx1 are electrically connected to each other, and the control terminal of the ninth transistor T9 is electrically connected to the first control signal terminal; the ninth transistor T9 is configured to load the voltage of the reset scan signal terminal to the ninth transistor T9 in response to the on-level of the first control signal terminal. a control node Nx1; the threshold compensation switch sub-circuit SW2 includes a compensation switch unit ST2 and a compensation control unit CT2; the compensation switch unit ST2 includes a second transistor T2, wherein a first electrode of the second transistor T2, a second electrode of the driving transistor T3, and a third node N3 are electrically connected to each other, a second electrode of the second transistor T2, a control terminal of the driving transistor T3, a second electrode of the first transistor T1, and the first node N1 are electrically connected to each other, and a control terminal of the second transistor T2 is electrically connected to the second control node Nx2; the second transistor T2 is configured to turn off the second transistor T2 in response to a turn-off level on the second control node Nx2; the compensation control unit CT2 includes a tenth transistor T10; a first electrode of the tenth transistor T10 is electrically connected to the compensation scan signal terminal, a second electrode of the tenth transistor T10, the control terminal of the second transistor T2, and the second control node Nx2 are electrically connected to each other, and the control terminal of the tenth transistor T10 is electrically connected to the second control signal terminal; the tenth transistor T10 is configured to load a voltage of the compensation scan signal terminal to the second control node Nx2 in response to a turn-on level of the second control signal terminal. In other embodiments of the present disclosure, the reset switch unit ST1 may further include a plurality of first transistors T1 connected in series or in parallel, the reset control unit CT1 may further include a plurality of ninth transistors T9 connected in series or in parallel, the compensation switch unit ST2 may further include a plurality of second transistors T2 connected in series or in parallel, and the compensation control unit CT2 may further include a plurality of tenth transistors T10 connected in series or in parallel. It should be noted that the control node Nx includes a first control node Nx1 and a second control node Nx2.

[0110] In one embodiment of the present disclosure, as shown in FIG4 , the pixel driving circuit PDC further includes:

[0111] a fourth transistor T4, wherein a first electrode of the fourth transistor T4 is electrically connected to the data signal terminal, and a control terminal of the fourth transistor T4 is electrically connected to the data scan signal terminal;

[0112] a fifth transistor T5, wherein a second electrode of the fifth transistor T5, a second electrode of the fourth transistor T4, a first electrode of the driving transistor T3, and a second node N2 are electrically connected to each other, and a control terminal of the fifth transistor T5 is electrically connected to the light emitting control signal terminal;

[0113] a sixth transistor T6, wherein a first electrode of the sixth transistor T6, a second electrode of the driving transistor T3, and a third node N3 are electrically connected to each other, and a control terminal of the sixth transistor T6 is electrically connected to the light emitting control signal terminal;

[0114] a seventh transistor T7, wherein a first electrode of the seventh transistor T7 is electrically connected to the second initialization signal terminal, a second electrode of the seventh transistor T7, a second electrode of the sixth transistor T6, the pixel electrode, and the fourth node N4 are electrically connected to each other, and a control terminal of the seventh transistor T7 is electrically connected to the reset signal terminal;

[0115] a storage capacitor CST, a first electrode plate of the storage capacitor CST, a first electrode of the fifth transistor T5, and a first driving power supply voltage terminal electrically connected to each other, and a second electrode plate of the storage capacitor CST, a control terminal of the driving transistor T3, and a first node N1 electrically connected to each other;

[0116] The fourth transistor T4 is configured to, in response to the on-level of the data scanning signal terminal, load the data voltage of the data signal terminal to the second node N2;

[0117] The fifth transistor T5 is configured to, in response to the on-level of the light emitting control signal terminal, load the voltage of the first driving power supply voltage terminal to the second node N2;

[0118] The sixth transistor T6 is configured to load the voltage of the third node N3 to the fourth node N4 in response to the on-level of the light emitting control signal terminal;

[0119] The seventh transistor T7 is configured to, in response to the on-level of the reset signal terminal, load the voltage of the second initialization signal terminal to the fourth node N4;

[0120] The storage capacitor CST is configured to store the data voltage of the data signal terminal and the threshold voltage of the driving transistor T3 .

[0121] It should be noted that one end of the light emitting element is electrically connected to the fourth node N4, and the other end is electrically connected to the second driving power supply voltage terminal.

[0122] In one embodiment of the present disclosure, as shown in FIG4 , the pixel driving circuit PDC further includes an eighth transistor T8 ; a first electrode of the eighth transistor T8 is electrically connected to the third initialization signal terminal; a second electrode of the eighth transistor T8 , a second electrode of the fifth transistor T5 , a second electrode of the fourth transistor T4 , a first electrode of the driving transistor T3 , and a second node N2 are electrically connected to each other; a control terminal of the eighth transistor T8 is electrically connected to the reset signal terminal; and the eighth transistor T8 is configured to, in response to a conduction level at the reset signal terminal, load the voltage of the third initialization signal terminal to the second node N2 . By applying a conduction level of the reset signal RST to the control terminal of the eighth transistor T8 , the eighth transistor T8 is turned on, and the third initialization signal Vint3 is transmitted to the second node N2 through the eighth transistor T8 , thereby resetting the first electrode of the driving transistor T3 and reducing the residual voltage of the previous frame on the second node N2.

[0123] It should be noted that in the present disclosure, the first transistor T1, the second transistor T2, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, the ninth transistor T9, and the tenth transistor T10 can be P-type transistors or N-type transistors, respectively. In one embodiment of the present disclosure, corresponding to different types of transistors, one of a high level and a low level is used as the on-level of each signal, and the other is used as the off-level of each signal. For example, the on-level of a P-type transistor is a low level, and its off-level is a high level. For another example, the on-level of an N-type transistor is a high level, and its off-level is a low level.

[0124] The following describes the operation of the pixel driver circuit PDC in FIG4 in detail in conjunction with the operation timing diagram of the pixel driver circuit PDC shown in FIG5 . FIG5 shows an operation timing diagram of the pixel driver circuit PDC during refresh. This operation timing diagram illustrates the level states of the light-emitting control signal EM, the reset scan signal RSTG, the compensation scan signal CG, the data scan signal DG, the reset signal RST, the first control signal CP1, and the second control signal CP2 during four time periods. The first transistor T1 and the second transistor T2 are N-type transistors, and the remaining transistors are P-type transistors. The first drive power supply voltage V1 is VDD, and the second drive power supply voltage V2 is VSS. The light-emitting element is an organic light-emitting diode, and the first terminal of the light-emitting element is the anode, and the second terminal of the light-emitting element is the cathode.

[0125] First time period t1: as shown in Figure 5 and Figure 6-1, the first control signal CP1 and the compensation scan signal CG are at a low level, the light-emitting control signal EM, the reset scan signal RSTG, the data scan signal DG, the reset signal RST and the second control signal CP2 are at a high level, then the first transistor T1 and the ninth transistor T9 are turned on, the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8 and the tenth transistor T10 are turned off, and the first initialization signal Vint1 is transmitted to the first node N1 through the first transistor T1 to reset the control end of the driving transistor T3 and the storage capacitor CST.

[0126] Second time period t2: As shown in Figure 5 and Figure 6-2, the second control signal CP2, the data scan signal DG and the reset scan signal RSTG are at a low level, the light-emitting control signal EM, the compensation scan signal CG, the reset signal RST and the first control signal CP1 are at a high level, then the second transistor T2, the driving transistor T3, the fourth transistor T4 and the tenth transistor T10 are turned on, and the remaining transistors are turned off, and the voltage of the data signal Data is transmitted to the first node N1 through the fourth transistor T4, the second node N2, the third transistor, the third node N3, and the second transistor T2 in sequence, and the storage capacitor CST stores the voltage of the data signal Data and the threshold voltage of the driving transistor T3, so as to write the voltage of the data signal Data into the storage capacitor CST.

[0127] The third time period t3: as shown in Figure 5 and Figure 6-3, the reset scan signal RSTG, the compensation scan signal CG and the reset signal RST are at a low level, the light-emitting control signal EM, the data scan signal DG, the first control signal CP1 and the second control signal CP2 are at a high level, then the seventh transistor T7 and the eighth transistor T8 are turned on, and the remaining transistors are turned off, the second initialization signal Vint2 is transmitted to the fourth node N4 through the seventh transistor T7 to reset the pixel electrode; the third initialization signal Vint3 is transmitted to the second node N2 through the eighth transistor T8 to reset the first electrode of the driving transistor T3.

[0128] The fourth time period t4: as shown in Figure 5 and Figure 6-4, the reset scan signal RSTG and the compensation scan signal CG are at a low level, the light-emitting control signal EM, the reset signal RST, the data scan signal DG, the first control signal CP1 and the second control signal CP2 are at a high level, and all transistors are turned off to wait for the response of the above-mentioned signals and transistors.

[0129] Fifth time period t5: As shown in Figure 5 and Figure 6-5, the reset scan signal RSTG, the compensation scan signal CG and the light-emitting control signal EM are at a low level, the reset signal RST, the data scan signal DG, the first control signal CP1 and the second control signal CP2 are at a high level, then the fifth transistor T5, the sixth transistor T6 and the driving transistor T3 are turned on, and the remaining transistors are turned off, and the storage capacitor CST uses the stored voltage signal to make the driving transistor T3 generate a driving current, and the driving current drives the light-emitting element to emit light.

[0130] The following describes the working process of the pixel driving circuit PDC in FIG4 in detail in conjunction with the working timing diagram of the pixel driving circuit PDC shown in FIG7 . FIG7 shows the working timing diagram of the pixel driving circuit PDC when it is maintained (i.e., not refreshed). The working timing diagram illustrates the level states of the light emitting control signal EM, the reset scan signal RSTG, the compensation scan signal CG, the data scan signal DG, the reset signal RST, the first control signal CP1, and the second control signal CP2 in four time periods; wherein the first transistor T1 and the second transistor T2 are N-type transistors, and the remaining transistors are P-type transistors. The first driving power supply voltage V1 is VDD, and the second driving power supply voltage V2 is VSS; wherein the light emitting element is an organic light emitting diode, the first end of the light emitting element is the anode, and the second end of the light emitting element is the cathode.

[0131] The first period H1: as shown in Figure 7 and Figure 8-1, the compensation scan signal CG and the second control signal CP2 are at a low level, the light-emitting control signal EM, the reset scan signal RSTG, the data scan signal DG, the reset signal RST and the first control signal CP1 are at a high level, then all transistors are cut off, and the first initialization signal Vint1 cannot be transmitted to the first node N1 through the first transistor T1, thereby failing to reset the control end of the driving transistor T3 and the storage capacitor CST.

[0132] Second period H2: As shown in Figure 7 and Figure 8-2, the data scan signal DG, the first control signal CP1 and the reset scan signal RSTG are at a low level, the light emitting control signal EM, the compensation scan signal CG, the reset signal RST and the second control signal CP2 are at a high level, then the driving transistor T3 and the fourth transistor T4 are turned on, and the remaining transistors are turned off. Since the second transistor T2 is turned off, the voltage of the data signal Data and the threshold voltage of the driving transistor T3 cannot be written into the storage capacitor CST.

[0133] The third period H3: as shown in Figures 7 and 8-3, the first control signal CP1, the second control signal CP2, the reset scan signal RSTG, the compensation scan signal CG and the reset signal RST are at a low level, the light-emitting control signal EM and the data scan signal DG are at a high level, the seventh transistor T7 and the eighth transistor T8 are turned on, and the remaining transistors are turned off, the second initialization signal Vint2 is transmitted to the fourth node N4 through the seventh transistor T7 to reset the pixel electrode; the third initialization signal Vint3 is transmitted to the second node N2 through the eighth transistor T8 to reset the first electrode of the driving transistor T3.

[0134] The fourth period H4: as shown in Figures 7 and 8-4, the first control signal CP1, the second control signal CP2, the reset scan signal RSTG and the compensation scan signal CG are at a low level, the light-emitting control signal EM, the reset signal RST and the data scan signal DG are at a high level, and all transistors are turned off to wait for the response of the above-mentioned signals and transistors.

[0135] Fifth period H5: As shown in Figures 7 and 8-5, the first control signal CP1, the second control signal CP2, the reset scan signal RSTG, the compensation scan signal CG and the light-emitting control signal EM are at a low level, the reset signal RST and the data scan signal DG are at a high level, then the fifth transistor T5 and the sixth transistor T6 are turned on, and the remaining transistors are turned off. Since the voltage of the data signal Data is not written into the storage capacitor CST, the light-emitting element is not refreshed.

[0136] In some embodiments of the present disclosure, the ninth transistor T9 and the tenth transistor T10 may also be N-type transistors, and the phases of the timing diagrams of the corresponding first control signal CP1 and the second control signal CP2 are opposite. For example, when the ninth transistor T9 and the tenth transistor T10 are P-type transistors, the on-level of the corresponding first control signal CP1 and the second control signal CP2 is a low level, and the off-level is a high level; when the ninth transistor T9 and the tenth transistor T10 are N-type transistors, the on-level of the corresponding first control signal CP1 and the second control signal CP2 is a high level, and the off-level is a low level.

[0137] In one embodiment of the present disclosure, as shown in FIG9 , the display panel PNL includes switch sub-circuit traces corresponding to respective pixel drive circuit columns VPDC, and the control end of the control unit CT of the pixel drive circuit column VPDC is electrically connected to the switch sub-circuit traces.

[0138] When any area of ​​the display panel PNL does not need to be refreshed, the control unit CT is turned off by applying the cut-off level of the control signal end to the control end of the switch sub-circuit SW of the pixel driving circuit PDC corresponding to the sub-pixel PIX in the area of ​​the display panel PNL that does not need to be refreshed. At this time, the conduction level of the scan signal of the corresponding scan signal end electrically connected to the first pole of the control unit CT cannot be transmitted to the control node Nx through the control unit CT, so that the switch unit ST cannot be turned on, so that the driving transistor T3 cannot generate a driving current, and the sub-pixel PIX cannot be refreshed, thereby achieving refresh of any area of ​​the display panel PNL. Compared with the traditional display panel PNL that can only achieve full-surface refresh, the display panel PNL provided in this embodiment can control the refresh and maintenance of any different areas of the screen, and achieve refresh display of any part of the screen and non-refresh display of any part (any part maintains the previous frame display), thereby achieving the purpose of extreme power saving.

[0139] In one embodiment of the present disclosure, the switch unit ST includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first initialization signal terminal, a second electrode of the first transistor T1, a control terminal of the driving transistor T3, and a first node N1 are electrically connected to each other, the control terminal of the first transistor T1 is electrically connected to the first control node Nx1, and the first transistor T1 is configured to turn off the first transistor T1 in response to the cut-off level on the first control node Nx1; the control unit CT includes a ninth transistor T9; a first electrode of the ninth transistor T9 is electrically connected to the reset scan signal terminal, and a second electrode of the ninth transistor T9 is electrically connected to the reset scan signal terminal. The control terminal of the ninth transistor T9 is electrically connected to the first control signal terminal, and the ninth transistor T9 is configured to load the voltage of the reset scan signal terminal to the first control node Nx1 in response to the conduction level of the first control signal terminal; the control terminal of the ninth transistor T9 of the pixel driving circuit column VPDC is electrically connected to the first control signal line CP1L, and the control terminal of the ninth transistor T9 of each pixel driving circuit PDC of the pixel driving circuit column VPDC is electrically connected to the same first control signal line CP1L. In other embodiments of the present disclosure, the switch unit ST may include a plurality of first transistors T1 connected in series or in parallel, and the control unit CT may include a plurality of ninth transistors T9 connected in series or in parallel. The control terminal of the ninth transistor T9 of each pixel driving circuit PDC of the pixel driving circuit column VPDC may also be electrically connected to a first control signal line CP1L.

[0140] In one embodiment of the present disclosure, the switch unit ST includes a second transistor T2, wherein a first electrode of the second transistor T2, a second electrode of the driving transistor T3, and a third node N3 are electrically connected to each other, a second electrode of the second transistor T2, a control terminal of the driving transistor T3, and a first node N1 are electrically connected to each other, and a control terminal of the second transistor T2 is electrically connected to a second control node Nx2. The second transistor T2 is configured to turn off the second transistor T2 in response to a cut-off level on the second control node Nx2. The control unit CT includes a tenth transistor T10. A first electrode of the tenth transistor T10 is electrically connected to the compensation scan signal terminal. The tenth transistor T10 is electrically connected to the compensation scan signal terminal. The second electrode of the transistor T10, the control terminal of the second transistor T2, and the second control node Nx2 are electrically connected to each other. The control terminal of the tenth transistor T10 is electrically connected to the second control signal terminal. The tenth transistor T10 is configured to load the voltage of the compensation scanning signal terminal to the second control node Nx2 in response to the conduction level of the second control signal terminal. The control terminal of the tenth transistor T10 of the pixel driving circuit column VPDC is electrically connected to the second control signal line CP2L, and the control terminal of the tenth transistor T10 of each pixel driving circuit PDC of the pixel driving circuit column VPDC is electrically connected to the same second control signal line CP2L. In other embodiments of the present disclosure, the switch unit ST may include a plurality of second transistors T2 connected in series or in parallel, and the control unit CT may include a plurality of tenth transistors T10 connected in series or in parallel. The control terminal of the tenth transistor T10 of each pixel driving circuit PDC of the pixel driving circuit column VPDC may also be electrically connected to a second control signal line CP2L.

[0141] By applying the on-level and off-level of the first control signal CP1 to the first control signal line CP1L and applying the on-level and off-level of the second control signal CP2 to the second control signal line CP2L, the ninth transistor T9 and the tenth transistor T10 are turned on and off.

[0142] In an embodiment of the present disclosure, as shown in FIG9 , the control terminal of the ninth transistor T9 of each pixel driver circuit PDC of a pixel driver circuit column VPDC is electrically connected to the same first control signal trace CP1L, and the control terminal of the tenth transistor T10 of each pixel driver circuit PDC of a pixel driver circuit column VPDC is electrically connected to the same second control signal trace CP2L. This reduces the number of first control signal traces CP1L and second control signal traces CP2L, thereby reducing the number of signal interfaces on the corresponding driver chip DIC.

[0143] In an embodiment of the present disclosure, as shown in FIG9 , a pixel driving circuit PDC corresponding to each row of sub-pixels PIX is correspondingly provided with a gate driving circuit group GOAS, and several gate driving circuit groups GOAS are cascaded in sequence; each gate driving circuit group GOAS includes a first gate driving circuit GOA1, a second gate driving circuit GOA2, a third gate driving circuit GOA3, a fourth gate driving circuit GOA4 and a fifth gate driving circuit GOA5, the first gate driving circuit GOA1 is used to output a light emitting control signal EM, the second gate driving circuit GOA2 is used to output a reset scanning signal RSTG, the third gate driving circuit GOA3 is used to output a compensation scanning signal CG, the fourth gate driving circuit GOA4 is used to output a data scanning signal DG, and the fifth gate driving circuit GOA5 is used to output a reset signal RST; the first gate driving circuit GOA1 of the previous level The output end is electrically connected to the input end of the first gate drive circuit GOA1 of the next level, the output end of the second gate drive circuit GOA2 of the previous level is electrically connected to the input end of the second gate drive circuit GOA2 of the next level, the output end of the third gate drive circuit GOA3 of the previous level is electrically connected to the input end of the third gate drive circuit GOA3 of the next level, the output end of the fourth gate drive circuit GOA4 of the previous level is electrically connected to the input end of the fourth gate drive circuit GOA4 of the next level, and the output end of the fifth gate drive circuit GOA5 of the previous level is electrically connected to the input end of the fifth gate drive circuit GOA5 of the next level; the first gate drive circuit GOA1 of the first level, the second gate drive circuit GOA2 of the first level, the third gate drive circuit GOA3 of the first level, the fourth gate drive circuit GOA4 of the first level and the fifth gate drive circuit GOA5 of the first level are respectively electrically connected to a start signal end.

[0144] In an embodiment of the present disclosure, a driver chip DIC is further provided on the display panel PNL, which provides a plurality of first control signal lines CP1L and second control signal lines CP2L. The first control signal lines CP1L, the second control signal lines CP2L, the scan signal lines and the data signal lines are all electrically connected to the driver chip DIC.

[0145] In some embodiments of the present disclosure, as shown in FIG10 , the driver chip DIC is configured such that: in the hold region of the display panel PNL (i.e., the sub-pixels PIX that do not need to be refreshed), the first control signal trace CP1L is loaded with the cutoff level of the first control signal CP1, and the second control signal trace CP2L is loaded with the cutoff level of the second control signal CP2; thus, the voltage of the data signal Data on the data signal trace cannot be written into the pixel driver circuit PDC. The driver chip DIC is further configured such that, when driving the refresh region of the display panel PNL (i.e., the sub-pixels PIX that need to be refreshed), the data signal trace is loaded with the voltage of the data signal Data, the first control signal trace CP1L is loaded with the on-level of the first control signal CP1, and the second control signal trace CP2L is loaded with the on-level of the second control signal CP2; however, in terms of time sequence, the on-level of the first control signal CP1 is earlier than the on-level of the second control signal CP2 to ensure that the pixel driver circuit PDC is driven in a timely manner to operate.

[0146] The present disclosure also provides a method for driving a display panel PNL, which is applied to the above-mentioned display panel PNL. The method for driving the display panel PNL includes:

[0147] Step S110, driving each sub-pixel PIX row by row;

[0148] In step S120, when driving any row of sub-pixels PIX, it is determined whether each sub-pixel PIX needs to be refreshed; when a sub-pixel PIX does not need to be refreshed, when a conduction level is loaded on the scanning signal terminal corresponding to the switch sub-circuit SW of the pixel driving circuit PDC corresponding to the sub-pixel PIX, a cut-off level of the control signal terminal is loaded on the switch sub-circuit wiring electrically connected to the pixel driving circuit PDC corresponding to the sub-pixel PIX.

[0149] In some embodiments of the present disclosure, in step S120, the switch unit ST includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first initialization signal terminal, a second electrode of the first transistor T1, a control terminal of the driving transistor T3, and a first node N1 are electrically connected to each other, the control terminal of the first transistor T1 is electrically connected to the first control node Nx1, and the first transistor T1 is configured to turn off the first transistor T1 in response to the cut-off level on the first control node Nx1; the control unit CT includes a ninth transistor T9; a first electrode of the ninth transistor T9 is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor T9, a first ... A control terminal of a transistor T1 and a first control node Nx1 are electrically connected to each other, a control terminal of a ninth transistor T9 is electrically connected to the first control signal terminal, and the ninth transistor T9 is configured to load a voltage of a reset scan signal terminal to the first control node Nx1 in response to a conduction level of the first control signal terminal; a control terminal of the ninth transistor T9 of the pixel driving circuit column VPDC is electrically connected to a first control signal trace CP1L; and loading an off-level voltage of the first control signal terminal to a switch sub-circuit trace electrically connected to a pixel driving circuit PDC corresponding to a sub-pixel PIX includes loading the off-level voltage of the first control signal terminal to the first control signal trace CP1L.

[0150] In some embodiments of the present disclosure, in step S120, the switch unit ST includes a second transistor T2, a first electrode of the second transistor T2, a second electrode of the driving transistor T3, and a third node N3 are electrically connected to each other, the second electrode of the second transistor T2, a control terminal of the driving transistor T3, and the first node N1 are electrically connected to each other, the control terminal of the second transistor T2 is electrically connected to the second control node Nx2, and the second transistor T2 is configured to turn off the second transistor T2 in response to a cut-off level on the second control node Nx2; the control unit CT includes a tenth transistor T10; the first electrode of the tenth transistor T10 is electrically connected to the compensation scan signal terminal, and the tenth transistor T10 is electrically connected to the compensation scan signal terminal. 0, the control terminal of the second transistor T2, and the second control node Nx2 are electrically connected to each other, the control terminal of the tenth transistor T10 is electrically connected to the second control signal terminal, and the tenth transistor T10 is configured to, in response to the on-level of the second control signal terminal, load the voltage of the compensation scanning signal terminal to the second control node Nx2; the control terminal of the tenth transistor T10 of the pixel driving circuit column VPDC is electrically connected to the second control signal wiring CP2L; and loading the cut-off level of the second control signal terminal to the switch sub-circuit wiring electrically connected to the pixel driving circuit PDC corresponding to the sub-pixel PIX includes: loading the cut-off level of the second control signal terminal to the second control signal wiring CP2L.

[0151] For example, as shown in Figures 9 and 10, within one frame time, when only the sub-pixels PIX in the nth row and the mth column need to be refreshed (that is, the sub-pixels PIX in the remaining rows and columns are not refreshed), the driving chip DIC controls the gate driving circuit group GOAS in the nth row to load the on-level of the corresponding scanning signal, and the gate driving circuit groups GOAS in the n+1th row and the n-1th row load the on-level of the corresponding scanning signal. At the same time, the driving chip DIC loads the on-level of the first control signal CP1 to the first control signal wiring CP1L in the mth column, the on-level of the second control signal CP2 to the second control signal wiring CP2L in the mth column, the off-level of the first control signal CP1 to the m+1th column and the m-1th column, and the off-level of the second control signal CP2 to the m+1th column and the m-1th column, thereby achieving the refresh of the sub-pixels PIX in the nth row and the mth column, and the sub-pixels PIX in the remaining rows and columns are not refreshed. It should be noted that the scan signals include a light emitting control signal EM, a reset scan signal RSTG, a compensation scan signal CG, a reset signal RST and a data scan signal DG.

[0152] It should be noted that although the steps of the method for driving the display panel PNL in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps shown must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0153] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A pixel driving circuit for driving a display panel, wherein: The pixel driving circuit includes a driving transistor and a switch subcircuit electrically connected to a control terminal of the driving transistor; The switch subcircuit comprises a control unit and a switch unit; The second electrode of the switch unit is electrically connected to the control terminal of the driving transistor, and the control terminal of the switch unit is electrically connected to the control node; The control terminal of the control unit is electrically connected to the control signal terminal, and the first electrode of the control unit is electrically connected to the corresponding scan signal terminal; The control unit is configured to, in response to the conduction level of the control signal terminal, load the corresponding voltage of the scan signal terminal to the control node; The switch unit is configured to turn off the switch unit in response to a cut-off level on the control node; The driving transistor is configured to be capable of outputting a driving current under the control of a voltage on a control terminal of the driving transistor.

2. The pixel driving circuit according to claim 1, wherein: The switch subcircuit includes a reset switch subcircuit for resetting the control terminal of the drive transistor; The reset switch subcircuit comprises a reset switch unit and a reset control unit; The second electrode of the reset switch unit is electrically connected to the control terminal of the driving transistor, the control terminal of the reset switch unit is electrically connected to the first control node, and the reset switch unit is configured to turn off the reset switch unit in response to a cut-off level on the first control node; The first electrode of the reset control unit is electrically connected to the reset scan signal terminal, the control terminal of the reset control unit is electrically connected to the first control signal terminal, and the reset control unit is configured to load the voltage of the reset scan signal terminal to the first control node in response to the conduction level of the first control signal terminal.

3. The pixel driving circuit according to claim 2, wherein: The reset switch unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to turn off the first transistor in response to a cut-off level on the first control node; The reset control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to respond to a conduction level of the first control signal terminal so that the voltage of the reset scan signal terminal is loaded to the first control node.

4. The pixel driving circuit according to claim 1, wherein: The switch subcircuit includes a threshold compensation switch subcircuit; The threshold compensation switch subcircuit includes a compensation switch unit and a compensation control unit; The first electrode of the compensation switch unit is electrically connected to the second electrode of the driving transistor, the control end of the compensation switch unit is electrically connected to the second control node, and the compensation switch unit is configured to turn off the compensation switch unit in response to a cut-off level on the second control node; The first electrode of the compensation control unit is electrically connected to the compensation scanning signal terminal, the control terminal of the compensation control unit is electrically connected to the second control signal terminal, and the compensation control unit is configured to load the voltage of the compensation scanning signal terminal to the second control node in response to the conduction level of the second control signal terminal.

5. The pixel driving circuit according to claim 4, wherein: The compensation switch unit includes a second transistor, a first electrode of the second transistor, a second electrode of the driving transistor and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to turn off the second transistor in response to a cut-off level on the second control node; The compensation control unit includes a tenth transistor; the first electrode of the tenth transistor is electrically connected to the compensation scanning signal terminal, the second electrode of the tenth transistor, the control terminal of the second transistor and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to respond to the conduction level of the second control signal terminal so that the voltage of the compensation scanning signal terminal is loaded to the second control node.

6. The pixel driving circuit according to claim 1, wherein: The switch subcircuit includes a reset switch subcircuit and a threshold compensation switch subcircuit; The reset switch subcircuit comprises a reset switch unit and a reset control unit; The reset switch unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to turn off the first transistor in response to a cut-off level on the first control node; The reset control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to the reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to, in response to a conduction level of the first control signal terminal, load a voltage of the reset scan signal terminal to the first control node; The threshold compensation switch subcircuit includes a compensation switch unit and a compensation control unit; The compensation switch unit includes a second transistor, a first electrode of the second transistor, a second electrode of the driving transistor and a third node are electrically connected to each other, a second electrode of the second transistor, a control terminal of the driving transistor, a second electrode of the first transistor and a first node are electrically connected to each other, a control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to turn off the second transistor in response to a cut-off level on the second control node; The compensation control unit includes a tenth transistor; the first electrode of the tenth transistor is electrically connected to the compensation scanning signal terminal, the second electrode of the tenth transistor, the control terminal of the second transistor and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to respond to the conduction level of the second control signal terminal so that the voltage of the compensation scanning signal terminal is loaded to the second control node.

7. The pixel driving circuit according to claim 1, wherein: The pixel driving circuit further includes: a fourth transistor, wherein a first electrode of the fourth transistor is electrically connected to the data signal terminal, The control terminal of the fourth transistor is electrically connected to the data scanning signal terminal; a fifth transistor, wherein a second electrode of the fifth transistor, a second electrode of the fourth transistor, a first electrode of the driving transistor and a second node are electrically connected to each other, and a control terminal of the fifth transistor is electrically connected to a light emitting control signal terminal; a sixth transistor, wherein a first electrode of the sixth transistor, a second electrode of the driving transistor and a third node are electrically connected to each other, and a control terminal of the sixth transistor is electrically connected to the light emitting control signal terminal; a seventh transistor, wherein a first electrode of the seventh transistor is electrically connected to the second initialization signal terminal, a second electrode of the seventh transistor, a second electrode of the sixth transistor, a pixel electrode and a fourth node are electrically connected to each other, and a control terminal of the seventh transistor is electrically connected to the reset signal terminal; a storage capacitor, wherein a first electrode plate of the storage capacitor, a first electrode of the fifth transistor, and a first driving power supply voltage terminal are electrically connected to each other, and a second electrode plate of the storage capacitor, a control terminal of the driving transistor, and a first node are electrically connected to each other; The fourth transistor is configured to, in response to the conduction level of the data scanning signal terminal, load the data voltage of the data signal terminal to the second node; The fifth transistor is configured to load the voltage of the first driving power supply voltage terminal to the second node in response to the conduction level of the light emitting control signal terminal; The sixth transistor is configured to load the voltage of the third node to the fourth node in response to the conduction level of the light emitting control signal terminal; The seventh transistor is configured to load the voltage of the second initialization signal terminal to the fourth node in response to the on-level of the reset signal terminal.

8. The pixel driving circuit according to claim 7, wherein: The pixel driving circuit further includes an eighth transistor; The first electrode of the eighth transistor is electrically connected to the third initialization signal terminal; The second electrode of the eighth transistor, the second electrode of the fifth transistor, the second electrode of the fourth transistor, the first electrode of the driving transistor and the second node are electrically connected to each other; The control terminal of the eighth transistor is electrically connected to the reset signal terminal; The eighth transistor is configured to load the voltage of the third initialization signal terminal to the second node in response to the on-level of the reset signal terminal.

9. A display panel comprising the pixel driving circuit as claimed in claim 1 arranged in an array, wherein: The display panel includes switch sub-circuit wirings corresponding to each pixel driving circuit column one by one, and the control end of the control unit of the pixel driving circuit column is electrically connected to the switch sub-circuit wirings.

10. The display panel according to claim 9, wherein: The switch unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to turn off the first transistor in response to a cut-off level on the first control node; The control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to a reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to, in response to a conduction level of the first control signal terminal, load a voltage of the reset scan signal terminal to the first control node; The control end of the ninth transistor of the pixel driving circuit column is electrically connected to the first control signal wiring.

11. The display panel according to claim 9, wherein: The switch unit includes a second transistor, a first electrode of the second transistor, a second electrode of the driving transistor and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to turn off the second transistor in response to a cut-off level on the second control node; The control unit includes a tenth transistor; a first electrode of the tenth transistor is electrically connected to the compensation scanning signal terminal, a second electrode of the tenth transistor, a control terminal of the second transistor, and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to load the voltage of the compensation scanning signal terminal to the second control node in response to the conduction level of the second control signal terminal; The control terminal of the tenth transistor of the pixel driving circuit column is connected to the second control signal path. Electrical connection.

12. A method for driving a display panel, applied to the display panel according to claim 9; wherein: The driving method of the display panel includes: Driving each sub-pixel row by row; When driving any row of the sub-pixels, determine whether each of the sub-pixels needs to be refreshed; when one of the sub-pixels does not need to be refreshed, when the scan signal end corresponding to the switch sub-circuit of the pixel driving circuit corresponding to the sub-pixel is loaded with a conduction level, the switch sub-circuit wiring electrically connected to the pixel driving circuit corresponding to the sub-pixel is loaded with a cutoff level of the control signal end.

13. The method for driving a display panel according to claim 12, wherein: The switch unit includes a first transistor, a first electrode of the first transistor is electrically connected to a first initialization signal terminal, a second electrode of the first transistor, a control terminal of the driving transistor and a first node are electrically connected to each other, the control terminal of the first transistor is electrically connected to a first control node, and the first transistor is configured to turn off the first transistor in response to a cut-off level on the first control node; The control unit includes a ninth transistor; a first electrode of the ninth transistor is electrically connected to a reset scan signal terminal, a second electrode of the ninth transistor, a control terminal of the first transistor, and the first control node are electrically connected to each other, the control terminal of the ninth transistor is electrically connected to the first control signal terminal, and the ninth transistor is configured to load a voltage of the reset scan signal terminal to the first control node in response to a conduction level of the first control signal terminal; The control end of the ninth transistor of the pixel driving circuit column is electrically connected to the first control signal wiring; Loading the cutoff level of the first control signal end to the switch sub-circuit wiring electrically connected to the pixel driving circuit corresponding to the sub-pixel includes: The cutoff level of the first control signal terminal is applied to the first control signal wiring.

14. The method for driving a display panel according to claim 12, wherein: The switch unit includes a second transistor, a first electrode of the second transistor, a second electrode of the driving transistor and a third node are electrically connected to each other, the second electrode of the second transistor, a control terminal of the driving transistor and the first node are electrically connected to each other, the control terminal of the second transistor is electrically connected to a second control node, and the second transistor is configured to turn off the second transistor in response to a cut-off level on the second control node; The control unit includes a tenth transistor; a first electrode of the tenth transistor is electrically connected to the compensation scanning signal terminal, a second electrode of the tenth transistor, a control terminal of the second transistor, and the second control node are electrically connected to each other, the control terminal of the tenth transistor is electrically connected to the second control signal terminal, and the tenth transistor is configured to load the voltage of the compensation scanning signal terminal to the second control node in response to the conduction level of the second control signal terminal; The control end of the tenth transistor of the pixel driving circuit column is electrically connected to the second control signal wiring; Loading the cutoff level of the second control signal end to the switch sub-circuit wiring electrically connected to the pixel driving circuit corresponding to the sub-pixel includes: The cutoff level of the second control signal terminal is applied to the second control signal wiring.

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